stats.txt revision 11606
17934SN/A 27934SN/A---------- Begin Simulation Statistics ---------- 311336Sandreas.hansson@arm.comsim_seconds 2.783855 # Number of seconds simulated 411606Sandreas.sandberg@arm.comsim_ticks 2783854715000 # Number of ticks simulated 511606Sandreas.sandberg@arm.comfinal_tick 2783854715000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67934SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711606Sandreas.sandberg@arm.comhost_inst_rate 812904 # Simulator instruction rate (inst/s) 811606Sandreas.sandberg@arm.comhost_op_rate 989581 # Simulator op (including micro ops) rate (op/s) 911606Sandreas.sandberg@arm.comhost_tick_rate 15850589349 # Simulator tick rate (ticks/s) 1011606Sandreas.sandberg@arm.comhost_mem_usage 583016 # Number of bytes of host memory used 1111606Sandreas.sandberg@arm.comhost_seconds 175.63 # Real time elapsed on the host 1211606Sandreas.sandberg@arm.comsim_insts 142771202 # Number of instructions simulated 1311606Sandreas.sandberg@arm.comsim_ops 173801044 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611606Sandreas.sandberg@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 1710513SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 1810513SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 1910892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 1207012 # Number of bytes read from this memory 2011606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu.data 10324772 # Number of bytes read from this memory 2110535Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 2211606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::total 11533320 # Number of bytes read from this memory 2310892Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 1207012 # Number of instructions bytes read from this memory 2410892Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory 2511606Sandreas.sandberg@arm.comsystem.physmem.bytes_written::writebacks 8840896 # Number of bytes written to this memory 2610535Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory 2711606Sandreas.sandberg@arm.comsystem.physmem.bytes_written::total 8858420 # Number of bytes written to this memory 2810513SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory 2910513SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 3010892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 27313 # Number of read requests responded to by this memory 3111606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu.data 161844 # Number of read requests responded to by this memory 3210535Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 3311606Sandreas.sandberg@arm.comsystem.physmem.num_reads::total 189181 # Number of read requests responded to by this memory 3411606Sandreas.sandberg@arm.comsystem.physmem.num_writes::writebacks 138139 # Number of write requests responded to by this memory 3510535Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory 3611606Sandreas.sandberg@arm.comsystem.physmem.num_writes::total 142520 # Number of write requests responded to by this memory 3710513SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) 3810513SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) 3911336Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 433576 # Total read bandwidth from this memory (bytes/s) 4011606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu.data 3708804 # Total read bandwidth from this memory (bytes/s) 4110535Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) 4211606Sandreas.sandberg@arm.comsystem.physmem.bw_read::total 4142932 # Total read bandwidth from this memory (bytes/s) 4311336Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 433576 # Instruction read bandwidth from this memory (bytes/s) 4411336Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s) 4511606Sandreas.sandberg@arm.comsystem.physmem.bw_write::writebacks 3175775 # Write bandwidth from this memory (bytes/s) 4610535Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) 4711606Sandreas.sandberg@arm.comsystem.physmem.bw_write::total 3182070 # Write bandwidth from this memory (bytes/s) 4811606Sandreas.sandberg@arm.comsystem.physmem.bw_total::writebacks 3175775 # Total bandwidth to/from this memory (bytes/s) 4910513SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) 5010513SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 5111336Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 433576 # Total bandwidth to/from this memory (bytes/s) 5211606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu.data 3715099 # Total bandwidth to/from this memory (bytes/s) 5310585Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) 5411606Sandreas.sandberg@arm.comsystem.physmem.bw_total::total 7325002 # Total bandwidth to/from this memory (bytes/s) 5511606Sandreas.sandberg@arm.comsystem.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 5610517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 5710517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 5810517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 5910517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 6010517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 6110517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 6210517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 6310517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) 6410517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 6510517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 6610517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 6710517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) 6811606Sandreas.sandberg@arm.comsystem.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 6911606Sandreas.sandberg@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 7011606Sandreas.sandberg@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 7110535Sandreas.hansson@arm.comsystem.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 7210535Sandreas.hansson@arm.comsystem.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 7310535Sandreas.hansson@arm.comsystem.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 7410535Sandreas.hansson@arm.comsystem.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 7510535Sandreas.hansson@arm.comsystem.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 7610535Sandreas.hansson@arm.comsystem.cf0.dma_write_txs 631 # Number of DMA write transactions. 7710535Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 7811606Sandreas.sandberg@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 7910628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 8010628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 8110628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 8210628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 8310628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 8410628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 8510628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 8610628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 8710535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 8810535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 8910535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 9010535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 9110535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 9210535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 9310535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 9410535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 9510535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 9610535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 9710535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 9810535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 9910535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 10010535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 10110535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 10210535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 10310535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 10410535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 10510535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 10610535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 10710535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 10811606Sandreas.sandberg@arm.comsystem.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 10911336Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walks 10028 # Table walker walks requested 11011336Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksShort 10028 # Table walker walks initiated with short descriptors 11111336Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::samples 10028 # Table walker wait (enqueue to first request) latency 11211336Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::0 10028 100.00% 100.00% # Table walker wait (enqueue to first request) latency 11311336Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::total 10028 # Table walker wait (enqueue to first request) latency 11410628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution 11510628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution 11610628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution 11711336Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::4K 6353 80.79% 80.79% # Table walker page sizes translated 11810628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::1M 1511 19.21% 100.00% # Table walker page sizes translated 11911336Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::total 7864 # Table walker page sizes translated 12011336Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10028 # Table walker requests started/completed, data/inst 12110628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 12211336Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 10028 # Table walker requests started/completed, data/inst 12311336Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7864 # Table walker requests started/completed, data/inst 12410628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 12511336Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864 # Table walker requests started/completed, data/inst 12611336Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst 12710535Sandreas.hansson@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 12810535Sandreas.hansson@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 12911606Sandreas.sandberg@arm.comsystem.cpu.dtb.read_hits 31525882 # DTB read hits 13011336Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 8580 # DTB read misses 13111606Sandreas.sandberg@arm.comsystem.cpu.dtb.write_hits 23124079 # DTB write hits 13210535Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 1448 # DTB write misses 13310535Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 13410535Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 13510535Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 13610535Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 13711547Sandreas.sandberg@arm.comsystem.cpu.dtb.flush_entries 4285 # Number of entries that have been flushed from TLB 13810535Sandreas.hansson@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 13910535Sandreas.hansson@arm.comsystem.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch 14010535Sandreas.hansson@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 14110535Sandreas.hansson@arm.comsystem.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions 14211606Sandreas.sandberg@arm.comsystem.cpu.dtb.read_accesses 31534462 # DTB read accesses 14311606Sandreas.sandberg@arm.comsystem.cpu.dtb.write_accesses 23125527 # DTB write accesses 14410535Sandreas.hansson@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 14511606Sandreas.sandberg@arm.comsystem.cpu.dtb.hits 54649961 # DTB hits 14611336Sandreas.hansson@arm.comsystem.cpu.dtb.misses 10028 # DTB misses 14711606Sandreas.sandberg@arm.comsystem.cpu.dtb.accesses 54659989 # DTB accesses 14811606Sandreas.sandberg@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 14910628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 15010628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 15110628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 15210628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 15310628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 15410628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 15510628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 15610628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 15710535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 15810535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 15910535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 16010535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 16110535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 16210535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 16310535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 16410535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 16510535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 16610535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 16710535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 16810535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 16910535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 17010535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 17110535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 17210535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 17310535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 17410535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 17510535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 17610535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 17710535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 17811606Sandreas.sandberg@arm.comsystem.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 17910628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walks 4762 # Table walker walks requested 18010628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors 18110628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency 18210628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency 18310628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency 18410628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution 18510628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution 18610628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution 18710628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated 18810628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated 18910628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated 19010628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 19110628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst 19210628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst 19310628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 19410628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst 19510628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst 19610628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst 19711606Sandreas.sandberg@arm.comsystem.cpu.itb.inst_hits 147037694 # ITB inst hits 19810535Sandreas.hansson@arm.comsystem.cpu.itb.inst_misses 4762 # ITB inst misses 19910535Sandreas.hansson@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 20010535Sandreas.hansson@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 20110535Sandreas.hansson@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 20210535Sandreas.hansson@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 20310535Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 20410535Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 20510535Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 20610535Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 20711547Sandreas.sandberg@arm.comsystem.cpu.itb.flush_entries 2849 # Number of entries that have been flushed from TLB 20810535Sandreas.hansson@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 20910535Sandreas.hansson@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 21010535Sandreas.hansson@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 21110535Sandreas.hansson@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 21210535Sandreas.hansson@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 21310535Sandreas.hansson@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 21411606Sandreas.sandberg@arm.comsystem.cpu.itb.inst_accesses 147042456 # ITB inst accesses 21511606Sandreas.sandberg@arm.comsystem.cpu.itb.hits 147037694 # DTB hits 21610535Sandreas.hansson@arm.comsystem.cpu.itb.misses 4762 # DTB misses 21711606Sandreas.sandberg@arm.comsystem.cpu.itb.accesses 147042456 # DTB accesses 21811530Sandreas.sandberg@arm.comsystem.cpu.numPwrStateTransitions 6160 # Number of power state transitions 21911530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::samples 3080 # Distribution of time spent in the clock gated state 22011606Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::mean 874939633.669805 # Distribution of time spent in the clock gated state 22111606Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::stdev 17329944405.377167 # Distribution of time spent in the clock gated state 22211530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::underflows 3002 97.47% 97.47% # Distribution of time spent in the clock gated state 22311530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::1000-5e+10 72 2.34% 99.81% # Distribution of time spent in the clock gated state 22411530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state 22511530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state 22611530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state 22711530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state 22811570SCurtis.Dunham@arm.comsystem.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 22911530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::max_value 499984036900 # Distribution of time spent in the clock gated state 23011530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::total 3080 # Distribution of time spent in the clock gated state 23111606Sandreas.sandberg@arm.comsystem.cpu.pwrStateResidencyTicks::ON 89040643297 # Cumulative time (in ticks) in various power states 23211606Sandreas.sandberg@arm.comsystem.cpu.pwrStateResidencyTicks::CLK_GATED 2694814071703 # Cumulative time (in ticks) in various power states 23311606Sandreas.sandberg@arm.comsystem.cpu.numCycles 5567712511 # number of cpu cycles simulated 23410535Sandreas.hansson@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 23510535Sandreas.hansson@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 23611201Sandreas.hansson@arm.comsystem.cpu.kern.inst.arm 0 # number of arm instructions executed 23711336Sandreas.hansson@arm.comsystem.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed 23811606Sandreas.sandberg@arm.comsystem.cpu.committedInsts 142771202 # Number of instructions committed 23911606Sandreas.sandberg@arm.comsystem.cpu.committedOps 173801044 # Number of ops (including micro ops) committed 24011606Sandreas.sandberg@arm.comsystem.cpu.num_int_alu_accesses 153160791 # Number of integer alu accesses 24110535Sandreas.hansson@arm.comsystem.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses 24211606Sandreas.sandberg@arm.comsystem.cpu.num_func_calls 16873864 # number of times a function call or return occured 24311606Sandreas.sandberg@arm.comsystem.cpu.num_conditional_control_insts 18730220 # number of instructions that are conditional controls 24411606Sandreas.sandberg@arm.comsystem.cpu.num_int_insts 153160791 # number of integer instructions 24510535Sandreas.hansson@arm.comsystem.cpu.num_fp_insts 11484 # number of float instructions 24611606Sandreas.sandberg@arm.comsystem.cpu.num_int_register_reads 285043206 # number of times the integer registers were read 24711606Sandreas.sandberg@arm.comsystem.cpu.num_int_register_writes 107178068 # number of times the integer registers were written 24810535Sandreas.hansson@arm.comsystem.cpu.num_fp_register_reads 8772 # number of times the floating registers were read 24910535Sandreas.hansson@arm.comsystem.cpu.num_fp_register_writes 2716 # number of times the floating registers were written 25011606Sandreas.sandberg@arm.comsystem.cpu.num_cc_register_reads 530847827 # number of times the CC registers were read 25111606Sandreas.sandberg@arm.comsystem.cpu.num_cc_register_writes 62363707 # number of times the CC registers were written 25211606Sandreas.sandberg@arm.comsystem.cpu.num_mem_refs 55938510 # number of memory refs 25311606Sandreas.sandberg@arm.comsystem.cpu.num_load_insts 31855508 # Number of load instructions 25411606Sandreas.sandberg@arm.comsystem.cpu.num_store_insts 24083002 # Number of store instructions 25511606Sandreas.sandberg@arm.comsystem.cpu.num_idle_cycles 5389631125.859330 # Number of idle cycles 25611606Sandreas.sandberg@arm.comsystem.cpu.num_busy_cycles 178081385.140670 # Number of busy cycles 25710535Sandreas.hansson@arm.comsystem.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles 25810535Sandreas.hansson@arm.comsystem.cpu.idle_fraction 0.968015 # Percentage of idle cycles 25911606Sandreas.sandberg@arm.comsystem.cpu.Branches 36396820 # Number of branches fetched 26010535Sandreas.hansson@arm.comsystem.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction 26111606Sandreas.sandberg@arm.comsystem.cpu.op_class::IntAlu 121151571 68.36% 68.36% # Class of executed instruction 26211606Sandreas.sandberg@arm.comsystem.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction 26310535Sandreas.hansson@arm.comsystem.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction 26410535Sandreas.hansson@arm.comsystem.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction 26510535Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction 26610535Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCvt 0 0.00% 68.43% # Class of executed instruction 26710535Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMult 0 0.00% 68.43% # Class of executed instruction 26810535Sandreas.hansson@arm.comsystem.cpu.op_class::FloatDiv 0 0.00% 68.43% # Class of executed instruction 26910535Sandreas.hansson@arm.comsystem.cpu.op_class::FloatSqrt 0 0.00% 68.43% # Class of executed instruction 27010535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAdd 0 0.00% 68.43% # Class of executed instruction 27110535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 68.43% # Class of executed instruction 27210535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAlu 0 0.00% 68.43% # Class of executed instruction 27310535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCmp 0 0.00% 68.43% # Class of executed instruction 27410535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCvt 0 0.00% 68.43% # Class of executed instruction 27510535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMisc 0 0.00% 68.43% # Class of executed instruction 27610535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMult 0 0.00% 68.43% # Class of executed instruction 27710535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 68.43% # Class of executed instruction 27810535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShift 0 0.00% 68.43% # Class of executed instruction 27910535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 68.43% # Class of executed instruction 28010535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdSqrt 0 0.00% 68.43% # Class of executed instruction 28110535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 68.43% # Class of executed instruction 28210535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 68.43% # Class of executed instruction 28310535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 68.43% # Class of executed instruction 28410535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 68.43% # Class of executed instruction 28510535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 68.43% # Class of executed instruction 28610535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Class of executed instruction 28710535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction 28810535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction 28910535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction 29011606Sandreas.sandberg@arm.comsystem.cpu.op_class::MemRead 31855508 17.98% 86.41% # Class of executed instruction 29111606Sandreas.sandberg@arm.comsystem.cpu.op_class::MemWrite 24083002 13.59% 100.00% # Class of executed instruction 29210535Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 29310535Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 29411606Sandreas.sandberg@arm.comsystem.cpu.op_class::total 177217860 # Class of executed instruction 29511606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 29611606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.replacements 819387 # number of replacements 29710535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use 29811606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.total_refs 53783783 # Total number of references to valid blocks. 29911606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.sampled_refs 819899 # Sample count of references to valid blocks. 30011606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.avg_refs 65.598059 # Average number of references to valid blocks. 30110535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. 30210535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor 30310535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 30410535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 30510535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 30610535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id 30710535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id 30810535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 30910535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 31011606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.tag_accesses 219234707 # Number of tag accesses 31111606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.data_accesses 219234707 # Number of data accesses 31211606Sandreas.sandberg@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 31311606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 30128737 # number of ReadReq hits 31411606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_hits::total 30128737 # number of ReadReq hits 31511606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 22339767 # number of WriteReq hits 31611606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_hits::total 22339767 # number of WriteReq hits 31711570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 395067 # number of SoftPFReq hits 31811570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 395067 # number of SoftPFReq hits 31911570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 457333 # number of LoadLockedReq hits 32011570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 457333 # number of LoadLockedReq hits 32111336Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits 32211336Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits 32311606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_hits::cpu.data 52468504 # number of demand (read+write) hits 32411606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_hits::total 52468504 # number of demand (read+write) hits 32511606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_hits::cpu.data 52863571 # number of overall hits 32611606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_hits::total 52863571 # number of overall hits 32711606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 396277 # number of ReadReq misses 32811606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_misses::total 396277 # number of ReadReq misses 32911606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 301662 # number of WriteReq misses 33011606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_misses::total 301662 # number of WriteReq misses 33111570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 116119 # number of SoftPFReq misses 33211570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 116119 # number of SoftPFReq misses 33311570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses 33411570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses 33510535Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 33610535Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 33711606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_misses::cpu.data 697939 # number of demand (read+write) misses 33811606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_misses::total 697939 # number of demand (read+write) misses 33911606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_misses::cpu.data 814058 # number of overall misses 34011606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_misses::total 814058 # number of overall misses 34111606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 30525014 # number of ReadReq accesses(hits+misses) 34211606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_accesses::total 30525014 # number of ReadReq accesses(hits+misses) 34311606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 22641429 # number of WriteReq accesses(hits+misses) 34411606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_accesses::total 22641429 # number of WriteReq accesses(hits+misses) 34511336Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) 34611336Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) 34711336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) 34811336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) 34911336Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) 35011336Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) 35111606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 53166443 # number of demand (read+write) accesses 35211606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_accesses::total 53166443 # number of demand (read+write) accesses 35311606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 53677629 # number of overall (read+write) accesses 35411606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_accesses::total 53677629 # number of overall (read+write) accesses 35510535Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses 35610535Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses 35711336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013323 # miss rate for WriteReq accesses 35811336Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.013323 # miss rate for WriteReq accesses 35911570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227156 # miss rate for SoftPFReq accesses 36011570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.227156 # miss rate for SoftPFReq accesses 36111570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018483 # miss rate for LoadLockedReq accesses 36211570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.018483 # miss rate for LoadLockedReq accesses 36310535Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 36410535Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses 36511570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.013127 # miss rate for demand accesses 36611570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.013127 # miss rate for demand accesses 36710535Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.015166 # miss rate for overall accesses 36810535Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses 36910535Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 37010535Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 37110535Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 37210535Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 37310535Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 37410535Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 37511606Sandreas.sandberg@arm.comsystem.cpu.dcache.writebacks::writebacks 682138 # number of writebacks 37611606Sandreas.sandberg@arm.comsystem.cpu.dcache.writebacks::total 682138 # number of writebacks 37711606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 37811606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.replacements 1698988 # number of replacements 37911336Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use 38011606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.total_refs 145341295 # Total number of references to valid blocks. 38111606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.sampled_refs 1699500 # Sample count of references to valid blocks. 38211606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.avg_refs 85.520032 # Average number of references to valid blocks. 38311570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.warmup_cycle 7831497000 # Cycle when the warmup percentage was hit. 38411336Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor 38510535Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy 38610535Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy 38710535Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 38810535Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id 38910535Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id 39010535Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id 39110535Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id 39210535Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 39311606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.tag_accesses 148740307 # Number of tag accesses 39411606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.data_accesses 148740307 # Number of data accesses 39511606Sandreas.sandberg@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 39611606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 145341295 # number of ReadReq hits 39711606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_hits::total 145341295 # number of ReadReq hits 39811606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_hits::cpu.inst 145341295 # number of demand (read+write) hits 39911606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_hits::total 145341295 # number of demand (read+write) hits 40011606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_hits::cpu.inst 145341295 # number of overall hits 40111606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_hits::total 145341295 # number of overall hits 40211606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 1699506 # number of ReadReq misses 40311606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_misses::total 1699506 # number of ReadReq misses 40411606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_misses::cpu.inst 1699506 # number of demand (read+write) misses 40511606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_misses::total 1699506 # number of demand (read+write) misses 40611606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_misses::cpu.inst 1699506 # number of overall misses 40711606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_misses::total 1699506 # number of overall misses 40811606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 147040801 # number of ReadReq accesses(hits+misses) 40911606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_accesses::total 147040801 # number of ReadReq accesses(hits+misses) 41011606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 147040801 # number of demand (read+write) accesses 41111606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_accesses::total 147040801 # number of demand (read+write) accesses 41211606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 147040801 # number of overall (read+write) accesses 41311606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_accesses::total 147040801 # number of overall (read+write) accesses 41411336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses 41511336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses 41611336Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses 41711336Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses 41811336Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.011558 # miss rate for overall accesses 41911336Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses 42010535Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 42110535Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 42210535Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 42310535Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 42410535Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 42510535Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 42611606Sandreas.sandberg@arm.comsystem.cpu.icache.writebacks::writebacks 1698988 # number of writebacks 42711606Sandreas.sandberg@arm.comsystem.cpu.icache.writebacks::total 1698988 # number of writebacks 42811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 42911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.replacements 109912 # number of replacements 43011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.tagsinuse 65246.862245 # Cycle average of tags in use 43111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.total_refs 4827688 # Total number of references to valid blocks. 43211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.sampled_refs 175338 # Sample count of references to valid blocks. 43311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.avg_refs 27.533609 # Average number of references to valid blocks. 43411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.warmup_cycle 71491095000 # Cycle when the warmup percentage was hit. 43511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.971735 # Average occupied blocks per requestor 43611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.023390 # Average occupied blocks per requestor 43711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 9170.132693 # Average occupied blocks per requestor 43811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 56073.734427 # Average occupied blocks per requestor 43910535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy 44010535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 44111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.139925 # Average percentage of cache occupancy 44211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.855617 # Average percentage of cache occupancy 44311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.995588 # Average percentage of cache occupancy 44410535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 44511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 65421 # Occupied blocks per task id 44610535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 44711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 44811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id 44911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 9745 # Occupied blocks per task id 45011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 55480 # Occupied blocks per task id 45110535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 45211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.998245 # Percentage of cache occupancy per task id 45311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.tag_accesses 40257223 # Number of tag accesses 45411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.data_accesses 40257223 # Number of data accesses 45511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 45611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 5671 # number of ReadReq hits 45711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2714 # number of ReadReq hits 45811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadReq_hits::total 8385 # number of ReadReq hits 45911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 682138 # number of WritebackDirty hits 46011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 682138 # number of WritebackDirty hits 46111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 1666989 # number of WritebackClean hits 46211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 1666989 # number of WritebackClean hits 46311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 2746 # number of UpgradeReq hits 46411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 2746 # number of UpgradeReq hits 46511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 152790 # number of ReadExReq hits 46611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 152790 # number of ReadExReq hits 46711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681191 # number of ReadCleanReq hits 46811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 1681191 # number of ReadCleanReq hits 46911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 505440 # number of ReadSharedReq hits 47011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 505440 # number of ReadSharedReq hits 47111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_hits::cpu.dtb.walker 5671 # number of demand (read+write) hits 47211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_hits::cpu.itb.walker 2714 # number of demand (read+write) hits 47311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 1681191 # number of demand (read+write) hits 47411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 658230 # number of demand (read+write) hits 47511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_hits::total 2347806 # number of demand (read+write) hits 47611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_hits::cpu.dtb.walker 5671 # number of overall hits 47711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_hits::cpu.itb.walker 2714 # number of overall hits 47811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 1681191 # number of overall hits 47911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 658230 # number of overall hits 48011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_hits::total 2347806 # number of overall hits 48110535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses 48210535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 48310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses 48411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses 48511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses 48610535Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 48710535Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 48811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 146117 # number of ReadExReq misses 48911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 146117 # number of ReadExReq misses 49010892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 18298 # number of ReadCleanReq misses 49110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 18298 # number of ReadCleanReq misses 49210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 15568 # number of ReadSharedReq misses 49310892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 15568 # number of ReadSharedReq misses 49410535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses 49510535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 49610892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 18298 # number of demand (read+write) misses 49711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 161685 # number of demand (read+write) misses 49811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_misses::total 179992 # number of demand (read+write) misses 49910535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses 50010535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 50110892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 18298 # number of overall misses 50211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 161685 # number of overall misses 50311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_misses::total 179992 # number of overall misses 50411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 5678 # number of ReadReq accesses(hits+misses) 50511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2716 # number of ReadReq accesses(hits+misses) 50611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 8394 # number of ReadReq accesses(hits+misses) 50711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 682138 # number of WritebackDirty accesses(hits+misses) 50811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 682138 # number of WritebackDirty accesses(hits+misses) 50911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 1666989 # number of WritebackClean accesses(hits+misses) 51011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 1666989 # number of WritebackClean accesses(hits+misses) 51111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 2755 # number of UpgradeReq accesses(hits+misses) 51211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 2755 # number of UpgradeReq accesses(hits+misses) 51310535Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 51410535Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 51511336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 298907 # number of ReadExReq accesses(hits+misses) 51611336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses) 51711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699489 # number of ReadCleanReq accesses(hits+misses) 51811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 1699489 # number of ReadCleanReq accesses(hits+misses) 51911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521008 # number of ReadSharedReq accesses(hits+misses) 52011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 521008 # number of ReadSharedReq accesses(hits+misses) 52111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_accesses::cpu.dtb.walker 5678 # number of demand (read+write) accesses 52211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_accesses::cpu.itb.walker 2716 # number of demand (read+write) accesses 52311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 1699489 # number of demand (read+write) accesses 52411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 819915 # number of demand (read+write) accesses 52511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_accesses::total 2527798 # number of demand (read+write) accesses 52611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_accesses::cpu.dtb.walker 5678 # number of overall (read+write) accesses 52711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_accesses::cpu.itb.walker 2716 # number of overall (read+write) accesses 52811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 1699489 # number of overall (read+write) accesses 52911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 819915 # number of overall (read+write) accesses 53011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_accesses::total 2527798 # number of overall (read+write) accesses 53111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001233 # miss rate for ReadReq accesses 53211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000736 # miss rate for ReadReq accesses 53311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.001072 # miss rate for ReadReq accesses 53411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.003267 # miss rate for UpgradeReq accesses 53511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.003267 # miss rate for UpgradeReq accesses 53610535Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 53710535Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 53811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.488838 # miss rate for ReadExReq accesses 53911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.488838 # miss rate for ReadExReq accesses 54011336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010767 # miss rate for ReadCleanReq accesses 54111336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses 54211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029881 # miss rate for ReadSharedReq accesses 54311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029881 # miss rate for ReadSharedReq accesses 54411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001233 # miss rate for demand accesses 54511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000736 # miss rate for demand accesses 54611336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.010767 # miss rate for demand accesses 54711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.197197 # miss rate for demand accesses 54811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.071205 # miss rate for demand accesses 54911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001233 # miss rate for overall accesses 55011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000736 # miss rate for overall accesses 55111336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.010767 # miss rate for overall accesses 55211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.197197 # miss rate for overall accesses 55311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.071205 # miss rate for overall accesses 55410535Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 55510535Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 55610535Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 55710535Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 55810535Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 55910535Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 56011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks 56111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.writebacks::total 101949 # number of writebacks 56211606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 5059872 # Total number of requests made to the snoop filter. 56311606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 2540470 # Number of requests hitting in the snoop filter with a single holder of the requested data. 56411606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 39261 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 56511336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 422 # Total number of snoops made to the snoop filter. 56611336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 422 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 56711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 56811606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 56911336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 67800 # Transaction distribution 57011606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 2288314 # Transaction distribution 57110726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution 57210726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution 57311606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 682138 # Transaction distribution 57411606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 1698988 # Transaction distribution 57511606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 137249 # Transaction distribution 57611606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 2755 # Transaction distribution 57710535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 57811606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 2757 # Transaction distribution 57911336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution 58011336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution 58111606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 1699506 # Transaction distribution 58211606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 521008 # Transaction distribution 58311606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116044 # Packet count per connected master and slave (bytes) 58411606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581953 # Packet count per connected master and slave (bytes) 58510535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) 58611336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes) 58711606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_count::total 7753423 # Packet count per connected master and slave (bytes) 58811606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217539704 # Cumulative packet size per connected master and slave (bytes) 58911606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96314145 # Cumulative packet size per connected master and slave (bytes) 59010535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) 59111336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes) 59211606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_size::total 313964701 # Cumulative packet size per connected master and slave (bytes) 59311606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoops 115326 # Total snoops (count) 59411606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoopTraffic 6541312 # Total snoop traffic (bytes) 59511606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 5251057 # Request fanout histogram 59611606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.018717 # Request fanout histogram 59711606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.135522 # Request fanout histogram 59810535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 59911606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 5152775 98.13% 98.13% # Request fanout histogram 60011606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 98282 1.87% 100.00% # Request fanout histogram 60111138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 60210535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 60311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 60411138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 60511606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 5251057 # Request fanout histogram 60611606Sandreas.sandberg@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 60710726Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 30164 # Transaction distribution 60810726Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 30164 # Transaction distribution 60910726Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 59002 # Transaction distribution 61010892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 59002 # Transaction distribution 61110726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes) 61210535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 61311245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 61410535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 61510535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 61610535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) 61710535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) 61810535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 61910535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 62010535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 62110535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 62210535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 62310535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 62410535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 62510535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 62610535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 62710535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 62810535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 62910535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 63010726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 105404 # Packet count per connected master and slave (bytes) 63110535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes) 63210535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes) 63310726Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 178332 # Packet count per connected master and slave (bytes) 63410726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67833 # Cumulative packet size per connected master and slave (bytes) 63510535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 63611245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 63710535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 63810535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 63910535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) 64010535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) 64110535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 64210535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 64310535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 64410535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 64510535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 64610535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 64710535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 64810535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 64910535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 65010535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 65110535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 65210535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 65310726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes) 65410535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) 65510535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) 65610726Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) 65711606Sandreas.sandberg@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 65810535Sandreas.hansson@arm.comsystem.iocache.tags.replacements 36430 # number of replacements 65911606Sandreas.sandberg@arm.comsystem.iocache.tags.tagsinuse 0.909890 # Cycle average of tags in use 66010535Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 66110535Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. 66210535Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 66311606Sandreas.sandberg@arm.comsystem.iocache.tags.warmup_cycle 227410176509 # Cycle when the warmup percentage was hit. 66411606Sandreas.sandberg@arm.comsystem.iocache.tags.occ_blocks::realview.ide 0.909890 # Average occupied blocks per requestor 66511336Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy 66611336Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy 66710535Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 66810535Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 66910535Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 67010535Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 328176 # Number of tag accesses 67110535Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 328176 # Number of data accesses 67211606Sandreas.sandberg@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 67310535Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses 67410535Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 240 # number of ReadReq misses 67510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 67610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 67711456Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 36464 # number of demand (read+write) misses 67811456Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 36464 # number of demand (read+write) misses 67911456Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 36464 # number of overall misses 68011456Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 36464 # number of overall misses 68110535Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses) 68210535Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses) 68310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 68410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 68511456Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 36464 # number of demand (read+write) accesses 68611456Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 36464 # number of demand (read+write) accesses 68711456Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 36464 # number of overall (read+write) accesses 68811456Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 36464 # number of overall (read+write) accesses 68910535Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 69010535Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 69110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 69210892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 69310535Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 69410535Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 69510535Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 69610535Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 69710535Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 69810535Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 69910535Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 70010535Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 70110535Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 70210535Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 70310585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 36190 # number of writebacks 70410585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 36190 # number of writebacks 70511606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_requests 362809 # Total number of requests made to the snoop filter. 70611606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_requests 151023 # Number of requests hitting in the snoop filter with a single holder of the requested data. 70711606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_requests 488 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 70811606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 70911606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 71011606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 71111606Sandreas.sandberg@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 71210892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 40087 # Transaction distribution 71310892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 74202 # Transaction distribution 71410726Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 27546 # Transaction distribution 71510726Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 27546 # Transaction distribution 71611606Sandreas.sandberg@arm.comsystem.membus.trans_dist::WritebackDirty 138139 # Transaction distribution 71711606Sandreas.sandberg@arm.comsystem.membus.trans_dist::CleanEvict 8203 # Transaction distribution 71811606Sandreas.sandberg@arm.comsystem.membus.trans_dist::UpgradeReq 130 # Transaction distribution 71910513SAli.Saidi@ARM.comsystem.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 72011606Sandreas.sandberg@arm.comsystem.membus.trans_dist::UpgradeResp 132 # Transaction distribution 72111606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadExReq 145996 # Transaction distribution 72211606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadExResp 145996 # Transaction distribution 72310892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 34115 # Transaction distribution 72410892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 72510892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 72610726Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes) 72710517SAli.Saidi@ARM.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) 72810513SAli.Saidi@ARM.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) 72911606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 497824 # Packet count per connected master and slave (bytes) 73011606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 605184 # Packet count per connected master and slave (bytes) 73111336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) 73211336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) 73311606Sandreas.sandberg@arm.comsystem.membus.pkt_count::total 714542 # Packet count per connected master and slave (bytes) 73410726Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) 73510517SAli.Saidi@ARM.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) 73610513SAli.Saidi@ARM.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) 73711606Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092348 # Cumulative packet size per connected master and slave (bytes) 73811606Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255321 # Cumulative packet size per connected master and slave (bytes) 73910892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes) 74010892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes) 74111606Sandreas.sandberg@arm.comsystem.membus.pkt_size::total 20586841 # Cumulative packet size per connected master and slave (bytes) 74210409Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 74311570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 74411606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::samples 430442 # Request fanout histogram 74511606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::mean 0.012836 # Request fanout histogram 74611606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::stdev 0.112565 # Request fanout histogram 74710409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 74811606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::0 424917 98.72% 98.72% # Request fanout histogram 74911606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::1 5525 1.28% 100.00% # Request fanout histogram 75010409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 75110409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 75211606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 75310409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 75411606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::total 430442 # Request fanout histogram 75511606Sandreas.sandberg@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 75611606Sandreas.sandberg@arm.comsystem.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 75711606Sandreas.sandberg@arm.comsystem.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 75811606Sandreas.sandberg@arm.comsystem.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 75911606Sandreas.sandberg@arm.comsystem.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 76011606Sandreas.sandberg@arm.comsystem.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 76111606Sandreas.sandberg@arm.comsystem.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 76211239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 76311239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 76411239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 76511239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 76611239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 76711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 76811606Sandreas.sandberg@arm.comsystem.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 76911606Sandreas.sandberg@arm.comsystem.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 77010513SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 77110513SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 77210513SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 77310513SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 77410513SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 77510513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 77610513SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 77710513SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 77810513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 77910513SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 78010513SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 78110513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 78210513SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 78310513SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 78410513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 78510513SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 78610513SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 78710513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 78810513SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 78910513SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 79010513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 79110513SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 79210513SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 79310513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 79410513SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 79510513SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 79610513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 79710513SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 79810513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 79910513SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 0 # number of posts to CPU 80010513SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 80111606Sandreas.sandberg@arm.comsystem.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 80211606Sandreas.sandberg@arm.comsystem.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 80311606Sandreas.sandberg@arm.comsystem.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 80411606Sandreas.sandberg@arm.comsystem.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 80511606Sandreas.sandberg@arm.comsystem.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 80611606Sandreas.sandberg@arm.comsystem.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 80711606Sandreas.sandberg@arm.comsystem.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 80811239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 80911239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 81011239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 81111239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 81211606Sandreas.sandberg@arm.comsystem.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 81311606Sandreas.sandberg@arm.comsystem.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 81411606Sandreas.sandberg@arm.comsystem.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 81511606Sandreas.sandberg@arm.comsystem.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 81611606Sandreas.sandberg@arm.comsystem.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 81711606Sandreas.sandberg@arm.comsystem.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 81811606Sandreas.sandberg@arm.comsystem.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 81911606Sandreas.sandberg@arm.comsystem.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 82011606Sandreas.sandberg@arm.comsystem.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 82111606Sandreas.sandberg@arm.comsystem.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 82211606Sandreas.sandberg@arm.comsystem.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 82311606Sandreas.sandberg@arm.comsystem.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783854715000 # Cumulative time (in ticks) in various power states 8247934SN/A 8257934SN/A---------- End Simulation Statistics ---------- 826