stats.txt revision 10726
17934SN/A 27934SN/A---------- Begin Simulation Statistics ---------- 310585Sandreas.hansson@arm.comsim_seconds 2.783867 # Number of seconds simulated 410726Sandreas.hansson@arm.comsim_ticks 2783867052000 # Number of ticks simulated 510726Sandreas.hansson@arm.comfinal_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67934SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710726Sandreas.hansson@arm.comhost_inst_rate 1378466 # Simulator instruction rate (inst/s) 810726Sandreas.hansson@arm.comhost_op_rate 1678062 # Simulator op (including micro ops) rate (op/s) 910726Sandreas.hansson@arm.comhost_tick_rate 26878113924 # Simulator tick rate (ticks/s) 1010726Sandreas.hansson@arm.comhost_mem_usage 614624 # Number of bytes of host memory used 1110726Sandreas.hansson@arm.comhost_seconds 103.57 # Real time elapsed on the host 1210726Sandreas.hansson@arm.comsim_insts 142772879 # Number of instructions simulated 1310726Sandreas.hansson@arm.comsim_ops 173803124 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610513SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 1710513SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 1810726Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 1210788 # Number of bytes read from this memory 1910585Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 10328292 # Number of bytes read from this memory 2010535Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 2110726Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 11540616 # Number of bytes read from this memory 2210726Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 1210788 # Number of instructions bytes read from this memory 2310726Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 1210788 # Number of instructions bytes read from this memory 2410726Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 8837568 # Number of bytes written to this memory 2510535Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory 2610726Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 8855092 # Number of bytes written to this memory 2710513SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory 2810513SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 2910726Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 27372 # Number of read requests responded to by this memory 3010585Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 161899 # Number of read requests responded to by this memory 3110535Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 3210726Sandreas.hansson@arm.comsystem.physmem.num_reads::total 189295 # Number of read requests responded to by this memory 3310726Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 138087 # Number of write requests responded to by this memory 3410535Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory 3510726Sandreas.hansson@arm.comsystem.physmem.num_writes::total 142468 # Number of write requests responded to by this memory 3610513SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) 3710513SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) 3810726Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 434930 # Total read bandwidth from this memory (bytes/s) 3910585Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 3710052 # Total read bandwidth from this memory (bytes/s) 4010535Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) 4110726Sandreas.hansson@arm.comsystem.physmem.bw_read::total 4145534 # Total read bandwidth from this memory (bytes/s) 4210726Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 434930 # Instruction read bandwidth from this memory (bytes/s) 4310726Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 434930 # Instruction read bandwidth from this memory (bytes/s) 4410726Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 3174565 # Write bandwidth from this memory (bytes/s) 4510535Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) 4610726Sandreas.hansson@arm.comsystem.physmem.bw_write::total 3180860 # Write bandwidth from this memory (bytes/s) 4710726Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 3174565 # Total bandwidth to/from this memory (bytes/s) 4810513SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) 4910513SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 5010726Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 434930 # Total bandwidth to/from this memory (bytes/s) 5110585Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 3716347 # Total bandwidth to/from this memory (bytes/s) 5210585Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) 5310726Sandreas.hansson@arm.comsystem.physmem.bw_total::total 7326394 # Total bandwidth to/from this memory (bytes/s) 5410517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 5510517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 5610517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 5710517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 5810517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 5910517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 6010517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 6110517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) 6210517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 6310517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 6410517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 6510517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) 6610535Sandreas.hansson@arm.comsystem.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 6710535Sandreas.hansson@arm.comsystem.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 6810535Sandreas.hansson@arm.comsystem.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 6910535Sandreas.hansson@arm.comsystem.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 7010535Sandreas.hansson@arm.comsystem.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 7110535Sandreas.hansson@arm.comsystem.cf0.dma_write_txs 631 # Number of DMA write transactions. 7210535Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 7310628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 7410628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 7510628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 7610628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 7710628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 7810628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 7910628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 8010628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 8110535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 8210535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 8310535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 8410535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 8510535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 8610535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 8710535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 8810535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 8910535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 9010535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 9110535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 9210535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 9310535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 9410535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 9510535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 9610535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 9710535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 9810535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 9910535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 10010535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 10110535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 10210628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walks 10029 # Table walker walks requested 10310628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksShort 10029 # Table walker walks initiated with short descriptors 10410628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::samples 10029 # Table walker wait (enqueue to first request) latency 10510628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::0 10029 100.00% 100.00% # Table walker wait (enqueue to first request) latency 10610628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::total 10029 # Table walker wait (enqueue to first request) latency 10710628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution 10810628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution 10910628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution 11010628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::4K 6354 80.79% 80.79% # Table walker page sizes translated 11110628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::1M 1511 19.21% 100.00% # Table walker page sizes translated 11210628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::total 7865 # Table walker page sizes translated 11310628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10029 # Table walker requests started/completed, data/inst 11410628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 11510628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 10029 # Table walker requests started/completed, data/inst 11610628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7865 # Table walker requests started/completed, data/inst 11710628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 11810628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 7865 # Table walker requests started/completed, data/inst 11910628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 17894 # Table walker requests started/completed, data/inst 12010535Sandreas.hansson@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 12110535Sandreas.hansson@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 12210726Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 31526223 # DTB read hits 12310585Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 8581 # DTB read misses 12410726Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 23124452 # DTB write hits 12510535Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 1448 # DTB write misses 12610535Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 12710535Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 12810535Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 12910535Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 13010535Sandreas.hansson@arm.comsystem.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB 13110535Sandreas.hansson@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 13210535Sandreas.hansson@arm.comsystem.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch 13310535Sandreas.hansson@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 13410535Sandreas.hansson@arm.comsystem.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions 13510726Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 31534804 # DTB read accesses 13610726Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 23125900 # DTB write accesses 13710535Sandreas.hansson@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 13810726Sandreas.hansson@arm.comsystem.cpu.dtb.hits 54650675 # DTB hits 13910585Sandreas.hansson@arm.comsystem.cpu.dtb.misses 10029 # DTB misses 14010726Sandreas.hansson@arm.comsystem.cpu.dtb.accesses 54660704 # DTB accesses 14110628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 14210628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 14310628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 14410628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 14510628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 14610628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 14710628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 14810628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 14910535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 15010535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 15110535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 15210535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 15310535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 15410535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 15510535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 15610535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 15710535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 15810535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 15910535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 16010535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 16110535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 16210535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 16310535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 16410535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 16510535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 16610535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 16710535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 16810535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 16910535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 17010628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walks 4762 # Table walker walks requested 17110628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors 17210628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency 17310628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency 17410628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency 17510628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution 17610628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution 17710628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution 17810628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated 17910628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated 18010628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated 18110628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 18210628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst 18310628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst 18410628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 18510628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst 18610628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst 18710628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst 18810726Sandreas.hansson@arm.comsystem.cpu.itb.inst_hits 147039346 # ITB inst hits 18910535Sandreas.hansson@arm.comsystem.cpu.itb.inst_misses 4762 # ITB inst misses 19010535Sandreas.hansson@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 19110535Sandreas.hansson@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 19210535Sandreas.hansson@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 19310535Sandreas.hansson@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 19410535Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 19510535Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 19610535Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 19710535Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 19810535Sandreas.hansson@arm.comsystem.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB 19910535Sandreas.hansson@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 20010535Sandreas.hansson@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 20110535Sandreas.hansson@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 20210535Sandreas.hansson@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 20310535Sandreas.hansson@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 20410535Sandreas.hansson@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 20510726Sandreas.hansson@arm.comsystem.cpu.itb.inst_accesses 147044108 # ITB inst accesses 20610726Sandreas.hansson@arm.comsystem.cpu.itb.hits 147039346 # DTB hits 20710535Sandreas.hansson@arm.comsystem.cpu.itb.misses 4762 # DTB misses 20810726Sandreas.hansson@arm.comsystem.cpu.itb.accesses 147044108 # DTB accesses 20910726Sandreas.hansson@arm.comsystem.cpu.numCycles 5567737188 # number of cpu cycles simulated 21010535Sandreas.hansson@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 21110535Sandreas.hansson@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 21210726Sandreas.hansson@arm.comsystem.cpu.committedInsts 142772879 # Number of instructions committed 21310726Sandreas.hansson@arm.comsystem.cpu.committedOps 173803124 # Number of ops (including micro ops) committed 21410726Sandreas.hansson@arm.comsystem.cpu.num_int_alu_accesses 153162683 # Number of integer alu accesses 21510535Sandreas.hansson@arm.comsystem.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses 21610726Sandreas.hansson@arm.comsystem.cpu.num_func_calls 16873899 # number of times a function call or return occured 21710726Sandreas.hansson@arm.comsystem.cpu.num_conditional_control_insts 18730330 # number of instructions that are conditional controls 21810726Sandreas.hansson@arm.comsystem.cpu.num_int_insts 153162683 # number of integer instructions 21910535Sandreas.hansson@arm.comsystem.cpu.num_fp_insts 11484 # number of float instructions 22010726Sandreas.hansson@arm.comsystem.cpu.num_int_register_reads 285059803 # number of times the integer registers were read 22110726Sandreas.hansson@arm.comsystem.cpu.num_int_register_writes 107179480 # number of times the integer registers were written 22210535Sandreas.hansson@arm.comsystem.cpu.num_fp_register_reads 8772 # number of times the floating registers were read 22310535Sandreas.hansson@arm.comsystem.cpu.num_fp_register_writes 2716 # number of times the floating registers were written 22410726Sandreas.hansson@arm.comsystem.cpu.num_cc_register_reads 530854003 # number of times the CC registers were read 22510726Sandreas.hansson@arm.comsystem.cpu.num_cc_register_writes 62364299 # number of times the CC registers were written 22610726Sandreas.hansson@arm.comsystem.cpu.num_mem_refs 55939276 # number of memory refs 22710726Sandreas.hansson@arm.comsystem.cpu.num_load_insts 31855884 # Number of load instructions 22810726Sandreas.hansson@arm.comsystem.cpu.num_store_insts 24083392 # Number of store instructions 22910726Sandreas.hansson@arm.comsystem.cpu.num_idle_cycles 5389653746.932674 # Number of idle cycles 23010726Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 178083441.067325 # Number of busy cycles 23110535Sandreas.hansson@arm.comsystem.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles 23210535Sandreas.hansson@arm.comsystem.cpu.idle_fraction 0.968015 # Percentage of idle cycles 23310726Sandreas.hansson@arm.comsystem.cpu.Branches 36396981 # Number of branches fetched 23410535Sandreas.hansson@arm.comsystem.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction 23510726Sandreas.hansson@arm.comsystem.cpu.op_class::IntAlu 121152838 68.36% 68.36% # Class of executed instruction 23610585Sandreas.hansson@arm.comsystem.cpu.op_class::IntMult 116892 0.07% 68.43% # Class of executed instruction 23710535Sandreas.hansson@arm.comsystem.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction 23810535Sandreas.hansson@arm.comsystem.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction 23910535Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction 24010535Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCvt 0 0.00% 68.43% # Class of executed instruction 24110535Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMult 0 0.00% 68.43% # Class of executed instruction 24210535Sandreas.hansson@arm.comsystem.cpu.op_class::FloatDiv 0 0.00% 68.43% # Class of executed instruction 24310535Sandreas.hansson@arm.comsystem.cpu.op_class::FloatSqrt 0 0.00% 68.43% # Class of executed instruction 24410535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAdd 0 0.00% 68.43% # Class of executed instruction 24510535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 68.43% # Class of executed instruction 24610535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAlu 0 0.00% 68.43% # Class of executed instruction 24710535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCmp 0 0.00% 68.43% # Class of executed instruction 24810535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCvt 0 0.00% 68.43% # Class of executed instruction 24910535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMisc 0 0.00% 68.43% # Class of executed instruction 25010535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMult 0 0.00% 68.43% # Class of executed instruction 25110535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 68.43% # Class of executed instruction 25210535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShift 0 0.00% 68.43% # Class of executed instruction 25310535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 68.43% # Class of executed instruction 25410535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdSqrt 0 0.00% 68.43% # Class of executed instruction 25510535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 68.43% # Class of executed instruction 25610535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 68.43% # Class of executed instruction 25710535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 68.43% # Class of executed instruction 25810535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 68.43% # Class of executed instruction 25910535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 68.43% # Class of executed instruction 26010535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Class of executed instruction 26110535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction 26210535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction 26310535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction 26410726Sandreas.hansson@arm.comsystem.cpu.op_class::MemRead 31855884 17.98% 86.41% # Class of executed instruction 26510726Sandreas.hansson@arm.comsystem.cpu.op_class::MemWrite 24083392 13.59% 100.00% # Class of executed instruction 26610535Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 26710535Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 26810726Sandreas.hansson@arm.comsystem.cpu.op_class::total 177219912 # Class of executed instruction 26910535Sandreas.hansson@arm.comsystem.cpu.kern.inst.arm 0 # number of arm instructions executed 27010585Sandreas.hansson@arm.comsystem.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed 27110726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 819402 # number of replacements 27210535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use 27310726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks. 27410726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks. 27510726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 65.597713 # Average number of references to valid blocks. 27610535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. 27710535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor 27810535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 27910535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 28010535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 28110535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id 28210535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id 28310535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 28410535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 28510726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 219237582 # Number of tag accesses 28610726Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 219237582 # Number of data accesses 28710726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 30129052 # number of ReadReq hits 28810726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 30129052 # number of ReadReq hits 28910726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 22340110 # number of WriteReq hits 29010726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 22340110 # number of WriteReq hits 29110585Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 395080 # number of SoftPFReq hits 29210585Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 395080 # number of SoftPFReq hits 29310585Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 457347 # number of LoadLockedReq hits 29410585Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 457347 # number of LoadLockedReq hits 29510585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 460136 # number of StoreCondReq hits 29610585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits 29710726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 52469162 # number of demand (read+write) hits 29810726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 52469162 # number of demand (read+write) hits 29910726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 52864242 # number of overall hits 30010726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 52864242 # number of overall hits 30110726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 396276 # number of ReadReq misses 30210726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 396276 # number of ReadReq misses 30310585Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 301678 # number of WriteReq misses 30410585Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 301678 # number of WriteReq misses 30510585Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 116120 # number of SoftPFReq misses 30610585Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 116120 # number of SoftPFReq misses 30710585Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses 30810585Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses 30910535Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 31010535Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 31110726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 697954 # number of demand (read+write) misses 31210726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 697954 # number of demand (read+write) misses 31310726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 814074 # number of overall misses 31410726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 814074 # number of overall misses 31510726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 30525328 # number of ReadReq accesses(hits+misses) 31610726Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 30525328 # number of ReadReq accesses(hits+misses) 31710726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 22641788 # number of WriteReq accesses(hits+misses) 31810726Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 22641788 # number of WriteReq accesses(hits+misses) 31910585Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 511200 # number of SoftPFReq accesses(hits+misses) 32010585Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 511200 # number of SoftPFReq accesses(hits+misses) 32110585Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 465959 # number of LoadLockedReq accesses(hits+misses) 32210585Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses) 32310585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 460138 # number of StoreCondReq accesses(hits+misses) 32410585Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses) 32510726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 53167116 # number of demand (read+write) accesses 32610726Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 53167116 # number of demand (read+write) accesses 32710726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 53678316 # number of overall (read+write) accesses 32810726Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 53678316 # number of overall (read+write) accesses 32910535Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses 33010535Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses 33110535Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses 33210535Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses 33310585Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227152 # miss rate for SoftPFReq accesses 33410585Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.227152 # miss rate for SoftPFReq accesses 33510585Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018482 # miss rate for LoadLockedReq accesses 33610585Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.018482 # miss rate for LoadLockedReq accesses 33710535Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 33810535Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses 33910535Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses 34010535Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses 34110535Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.015166 # miss rate for overall accesses 34210535Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses 34310535Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 34410535Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 34510535Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 34610535Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 34710535Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 34810535Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 34910535Sandreas.hansson@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 35010535Sandreas.hansson@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 35110726Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 682059 # number of writebacks 35210726Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 682059 # number of writebacks 35310535Sandreas.hansson@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 35410726Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 1699214 # number of replacements 35510585Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use 35610726Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 145342721 # Total number of references to valid blocks. 35710726Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 1699726 # Sample count of references to valid blocks. 35810726Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 85.509500 # Average number of references to valid blocks. 35910535Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. 36010585Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 511.663681 # Average occupied blocks per requestor 36110535Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy 36210535Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy 36310535Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 36410535Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id 36510535Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id 36610535Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id 36710535Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id 36810535Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 36910726Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 148742185 # Number of tag accesses 37010726Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 148742185 # Number of data accesses 37110726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 145342721 # number of ReadReq hits 37210726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 145342721 # number of ReadReq hits 37310726Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 145342721 # number of demand (read+write) hits 37410726Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 145342721 # number of demand (read+write) hits 37510726Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 145342721 # number of overall hits 37610726Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 145342721 # number of overall hits 37710726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 1699732 # number of ReadReq misses 37810726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 1699732 # number of ReadReq misses 37910726Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 1699732 # number of demand (read+write) misses 38010726Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 1699732 # number of demand (read+write) misses 38110726Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 1699732 # number of overall misses 38210726Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 1699732 # number of overall misses 38310726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 147042453 # number of ReadReq accesses(hits+misses) 38410726Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 147042453 # number of ReadReq accesses(hits+misses) 38510726Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 147042453 # number of demand (read+write) accesses 38610726Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 147042453 # number of demand (read+write) accesses 38710726Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 147042453 # number of overall (read+write) accesses 38810726Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 147042453 # number of overall (read+write) accesses 38910585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011559 # miss rate for ReadReq accesses 39010585Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses 39110585Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.011559 # miss rate for demand accesses 39210585Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.011559 # miss rate for demand accesses 39310585Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.011559 # miss rate for overall accesses 39410585Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.011559 # miss rate for overall accesses 39510535Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 39610535Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 39710535Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 39810535Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 39910535Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 40010535Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 40110535Sandreas.hansson@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 40210535Sandreas.hansson@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 40310535Sandreas.hansson@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 40410726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 110026 # number of replacements 40510726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 65155.309107 # Cycle average of tags in use 40610726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 2727887 # Total number of references to valid blocks. 40710726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 175307 # Sample count of references to valid blocks. 40810726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 15.560628 # Average number of references to valid blocks. 40910535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 41010726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 48893.401643 # Average occupied blocks per requestor 41110585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor 41210585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004345 # Average occupied blocks per requestor 41310726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654943 # Average occupied blocks per requestor 41410726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 7194.316179 # Average occupied blocks per requestor 41510535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.746054 # Average percentage of cache occupancy 41610535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy 41710535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 41810535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.138316 # Average percentage of cache occupancy 41910585Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.109777 # Average percentage of cache occupancy 42010535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy 42110535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 42210535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 65276 # Occupied blocks per task id 42310535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 42410535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id 42510535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id 42610535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id 42710535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 10700 # Occupied blocks per task id 42810535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 50640 # Occupied blocks per task id 42910535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 43010535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id 43110726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 26204344 # Number of tag accesses 43210726Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 26204344 # Number of data accesses 43310585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits 43410535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits 43510726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 1681357 # number of ReadReq hits 43610726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 505474 # number of ReadReq hits 43710726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 2198053 # number of ReadReq hits 43810726Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 682059 # number of Writeback hits 43910726Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 682059 # number of Writeback hits 44010535Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits 44110535Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits 44210585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 151058 # number of ReadExReq hits 44310585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 151058 # number of ReadExReq hits 44410585Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.dtb.walker 7601 # number of demand (read+write) hits 44510535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits 44610726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 1681357 # number of demand (read+write) hits 44710726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 656532 # number of demand (read+write) hits 44810726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2349111 # number of demand (read+write) hits 44910585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.dtb.walker 7601 # number of overall hits 45010535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits 45110726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 1681357 # number of overall hits 45210726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 656532 # number of overall hits 45310726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2349111 # number of overall hits 45410535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses 45510535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 45610726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 18357 # number of ReadReq misses 45710535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 15534 # number of ReadReq misses 45810726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 33900 # number of ReadReq misses 45910535Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 2728 # number of UpgradeReq misses 46010535Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 2728 # number of UpgradeReq misses 46110535Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 46210535Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 46310535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 147864 # number of ReadExReq misses 46410535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 147864 # number of ReadExReq misses 46510535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses 46610535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 46710726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 18357 # number of demand (read+write) misses 46810535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 163398 # number of demand (read+write) misses 46910726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 181764 # number of demand (read+write) misses 47010535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses 47110535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 47210726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 18357 # number of overall misses 47310535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 163398 # number of overall misses 47410726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 181764 # number of overall misses 47510585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses) 47610535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) 47710726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 1699714 # number of ReadReq accesses(hits+misses) 47810726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 521008 # number of ReadReq accesses(hits+misses) 47910726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 2231953 # number of ReadReq accesses(hits+misses) 48010726Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 682059 # number of Writeback accesses(hits+misses) 48110726Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 682059 # number of Writeback accesses(hits+misses) 48210535Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) 48310535Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) 48410535Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 48510535Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 48610585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 298922 # number of ReadExReq accesses(hits+misses) 48710585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses) 48810585Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.dtb.walker 7608 # number of demand (read+write) accesses 48910535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses 49010726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 1699714 # number of demand (read+write) accesses 49110726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 819930 # number of demand (read+write) accesses 49210726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2530875 # number of demand (read+write) accesses 49310585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.dtb.walker 7608 # number of overall (read+write) accesses 49410535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses 49510726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 1699714 # number of overall (read+write) accesses 49610726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 819930 # number of overall (read+write) accesses 49710726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2530875 # number of overall (read+write) accesses 49810585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000920 # miss rate for ReadReq accesses 49910535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses 50010726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010800 # miss rate for ReadReq accesses 50110535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029815 # miss rate for ReadReq accesses 50210726Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.015188 # miss rate for ReadReq accesses 50310535Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses 50410535Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses 50510535Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 50610535Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 50710585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494657 # miss rate for ReadExReq accesses 50810585Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.494657 # miss rate for ReadExReq accesses 50910585Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000920 # miss rate for demand accesses 51010535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses 51110726Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.010800 # miss rate for demand accesses 51210585Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.199283 # miss rate for demand accesses 51310585Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.071819 # miss rate for demand accesses 51410585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000920 # miss rate for overall accesses 51510535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses 51610726Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.010800 # miss rate for overall accesses 51710585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.199283 # miss rate for overall accesses 51810585Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.071819 # miss rate for overall accesses 51910535Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 52010535Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 52110535Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 52210535Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 52310535Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 52410535Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 52510535Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 52610535Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 52710726Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 101897 # number of writebacks 52810726Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 101897 # number of writebacks 52910535Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 53010726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 2288542 # Transaction distribution 53110726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution 53210726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution 53310726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution 53410726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::Writeback 682059 # Transaction distribution 53510535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution 53610535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 53710535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution 53810585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution 53910585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution 54010726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417508 # Packet count per connected master and slave (bytes) 54110726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444657 # Packet count per connected master and slave (bytes) 54210535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) 54310585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes) 54410726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 5917595 # Packet count per connected master and slave (bytes) 54510726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) 54610726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96310049 # Cumulative packet size per connected master and slave (bytes) 54710535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) 54810585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) 54910726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 205239845 # Cumulative packet size per connected master and slave (bytes) 55010585Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 36631 # Total snoops (count) 55110726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 3268658 # Request fanout histogram 55210726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 3.011156 # Request fanout histogram 55310726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.105030 # Request fanout histogram 55410535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 55510535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 55610535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 55710535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 55810726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::3 3232194 98.88% 98.88% # Request fanout histogram 55910726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::4 36464 1.12% 100.00% # Request fanout histogram 56010535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 56110726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 56210726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 56310726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 3268658 # Request fanout histogram 56410726Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 30164 # Transaction distribution 56510726Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 30164 # Transaction distribution 56610726Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 59002 # Transaction distribution 56710726Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 22778 # Transaction distribution 56810535Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 56910726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes) 57010535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 57110535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 57210535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 57310535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) 57410535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) 57510535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 57610535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 57710535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 57810535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 57910535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 58010535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 58110535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 58210535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 58310535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 58410535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 58510535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 58610535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 58710535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 58810535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 58910535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 59010726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 105404 # Packet count per connected master and slave (bytes) 59110535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes) 59210535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes) 59310726Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 178332 # Packet count per connected master and slave (bytes) 59410726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67833 # Cumulative packet size per connected master and slave (bytes) 59510535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 59610535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 59710535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 59810535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) 59910535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) 60010535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 60110535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 60210535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 60310535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 60410535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 60510535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 60610535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 60710535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 60810535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 60910535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 61010535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 61110535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 61210535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 61310535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 61410535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 61510726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes) 61610535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) 61710535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) 61810726Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) 61910535Sandreas.hansson@arm.comsystem.iocache.tags.replacements 36430 # number of replacements 62010726Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 0.909961 # Cycle average of tags in use 62110535Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 62210535Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. 62310535Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 62410535Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. 62510726Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 0.909961 # Average occupied blocks per requestor 62610585Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.056873 # Average percentage of cache occupancy 62710585Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.056873 # Average percentage of cache occupancy 62810535Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 62910535Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 63010535Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 63110535Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 328176 # Number of tag accesses 63210535Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 328176 # Number of data accesses 63310535Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses 63410535Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 240 # number of ReadReq misses 63510585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses 63610585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses 63710535Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses 63810535Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 240 # number of demand (read+write) misses 63910535Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 240 # number of overall misses 64010535Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 240 # number of overall misses 64110535Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses) 64210535Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses) 64310535Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 64410535Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 64510535Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 240 # number of demand (read+write) accesses 64610535Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 240 # number of demand (read+write) accesses 64710535Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 240 # number of overall (read+write) accesses 64810535Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 240 # number of overall (read+write) accesses 64910535Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 65010535Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 65110585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 65210585Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 65310535Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 65410535Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 65510535Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 65610535Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 65710535Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 65810535Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 65910535Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 66010535Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 66110535Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 66210535Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 66310585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 66410535Sandreas.hansson@arm.comsystem.iocache.cache_copies 0 # number of cache copies performed 66510585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 36190 # number of writebacks 66610585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 36190 # number of writebacks 66710535Sandreas.hansson@arm.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 66810726Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 74227 # Transaction distribution 66910726Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 74227 # Transaction distribution 67010726Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 27546 # Transaction distribution 67110726Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 27546 # Transaction distribution 67210726Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 138087 # Transaction distribution 67310513SAli.Saidi@ARM.comsystem.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 67410513SAli.Saidi@ARM.comsystem.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 67510513SAli.Saidi@ARM.comsystem.membus.trans_dist::UpgradeReq 4507 # Transaction distribution 67610513SAli.Saidi@ARM.comsystem.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 67710513SAli.Saidi@ARM.comsystem.membus.trans_dist::UpgradeResp 4509 # Transaction distribution 67810513SAli.Saidi@ARM.comsystem.membus.trans_dist::ReadExReq 146085 # Transaction distribution 67910513SAli.Saidi@ARM.comsystem.membus.trans_dist::ReadExResp 146085 # Transaction distribution 68010726Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes) 68110517SAli.Saidi@ARM.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) 68210513SAli.Saidi@ARM.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) 68310726Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498791 # Packet count per connected master and slave (bytes) 68410726Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 606151 # Packet count per connected master and slave (bytes) 68510585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109118 # Packet count per connected master and slave (bytes) 68610585Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 109118 # Packet count per connected master and slave (bytes) 68710726Sandreas.hansson@arm.comsystem.membus.pkt_count::total 715269 # Packet count per connected master and slave (bytes) 68810726Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) 68910517SAli.Saidi@ARM.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) 69010513SAli.Saidi@ARM.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) 69110726Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096316 # Cumulative packet size per connected master and slave (bytes) 69210726Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259289 # Cumulative packet size per connected master and slave (bytes) 69310585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856 # Cumulative packet size per connected master and slave (bytes) 69410585Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes) 69510726Sandreas.hansson@arm.comsystem.membus.pkt_size::total 22909145 # Cumulative packet size per connected master and slave (bytes) 69610409Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 69710726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 359045 # Request fanout histogram 69810409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 69910409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 70010409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 70110409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 70210726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 359045 100.00% 100.00% # Request fanout histogram 70310409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 70410409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 70510409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 70610409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 70710726Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 359045 # Request fanout histogram 70810513SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 70910513SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 71010513SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 71110513SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 71210513SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 71310513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 71410513SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 71510513SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 71610513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 71710513SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 71810513SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 71910513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 72010513SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 72110513SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 72210513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 72310513SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 72410513SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 72510513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 72610513SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 72710513SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 72810513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 72910513SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 73010513SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 73110513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 73210513SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 73310513SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 73410513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 73510513SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 73610513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 73710513SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 0 # number of posts to CPU 73810513SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 7397934SN/A 7407934SN/A---------- End Simulation Statistics ---------- 741