stats.txt revision 10535
17934SN/A 27934SN/A---------- Begin Simulation Statistics ---------- 310517SAli.Saidi@ARM.comsim_seconds 2.783854 # Number of seconds simulated 410535Sandreas.hansson@arm.comsim_ticks 2783854461500 # Number of ticks simulated 510535Sandreas.hansson@arm.comfinal_tick 2783854461500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67934SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710535Sandreas.hansson@arm.comhost_inst_rate 1414038 # Simulator instruction rate (inst/s) 810535Sandreas.hansson@arm.comhost_op_rate 1721363 # Simulator op (including micro ops) rate (op/s) 910535Sandreas.hansson@arm.comhost_tick_rate 27571822204 # Simulator tick rate (ticks/s) 1010535Sandreas.hansson@arm.comhost_mem_usage 560116 # Number of bytes of host memory used 1110535Sandreas.hansson@arm.comhost_seconds 100.97 # Real time elapsed on the host 1210535Sandreas.hansson@arm.comsim_insts 142771592 # Number of instructions simulated 1310535Sandreas.hansson@arm.comsim_ops 173801445 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610513SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 1710513SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 1810513SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.inst 1210980 # Number of bytes read from this memory 1910513SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.data 10345892 # Number of bytes read from this memory 2010535Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 2110513SAli.Saidi@ARM.comsystem.physmem.bytes_read::total 11558408 # Number of bytes read from this memory 2210513SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::cpu.inst 1210980 # Number of instructions bytes read from this memory 2310513SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::total 1210980 # Number of instructions bytes read from this memory 2410517SAli.Saidi@ARM.comsystem.physmem.bytes_written::writebacks 6521536 # Number of bytes written to this memory 2510535Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory 2610513SAli.Saidi@ARM.comsystem.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 2710517SAli.Saidi@ARM.comsystem.physmem.bytes_written::total 8857396 # Number of bytes written to this memory 2810513SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory 2910513SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 3010513SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.inst 27375 # Number of read requests responded to by this memory 3110513SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.data 162174 # Number of read requests responded to by this memory 3210535Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 3310513SAli.Saidi@ARM.comsystem.physmem.num_reads::total 189573 # Number of read requests responded to by this memory 3410517SAli.Saidi@ARM.comsystem.physmem.num_writes::writebacks 101899 # Number of write requests responded to by this memory 3510535Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory 3610513SAli.Saidi@ARM.comsystem.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 3710517SAli.Saidi@ARM.comsystem.physmem.num_writes::total 142504 # Number of write requests responded to by this memory 3810513SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) 3910513SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) 4010513SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.inst 435001 # Total read bandwidth from this memory (bytes/s) 4110517SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.data 3716391 # Total read bandwidth from this memory (bytes/s) 4210535Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) 4310517SAli.Saidi@ARM.comsystem.physmem.bw_read::total 4151944 # Total read bandwidth from this memory (bytes/s) 4410513SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::cpu.inst 435001 # Instruction read bandwidth from this memory (bytes/s) 4510513SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::total 435001 # Instruction read bandwidth from this memory (bytes/s) 4610517SAli.Saidi@ARM.comsystem.physmem.bw_write::writebacks 2342628 # Write bandwidth from this memory (bytes/s) 4710535Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) 4810513SAli.Saidi@ARM.comsystem.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s) 4910535Sandreas.hansson@arm.comsystem.physmem.bw_write::total 3181702 # Write bandwidth from this memory (bytes/s) 5010517SAli.Saidi@ARM.comsystem.physmem.bw_total::writebacks 2342628 # Total bandwidth to/from this memory (bytes/s) 5110513SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) 5210513SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 5310513SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.inst 435001 # Total bandwidth to/from this memory (bytes/s) 5410517SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.data 3722686 # Total bandwidth to/from this memory (bytes/s) 5510535Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s) 5610535Sandreas.hansson@arm.comsystem.physmem.bw_total::total 7333646 # Total bandwidth to/from this memory (bytes/s) 5710517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 5810517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 5910517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 6010517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 6110517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 6210517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 6310517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 6410517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) 6510517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 6610517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 6710517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 6810517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) 6910535Sandreas.hansson@arm.comsystem.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 7010535Sandreas.hansson@arm.comsystem.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 7110535Sandreas.hansson@arm.comsystem.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 7210535Sandreas.hansson@arm.comsystem.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 7310535Sandreas.hansson@arm.comsystem.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 7410535Sandreas.hansson@arm.comsystem.cf0.dma_write_txs 631 # Number of DMA write transactions. 7510535Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 7610535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 7710535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 7810535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 7910535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 8010535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 8110535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 8210535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 8310535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 8410535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 8510535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 8610535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 8710535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 8810535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 8910535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 9010535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 9110535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 9210535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 9310535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 9410535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 9510535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 9610535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 9710535Sandreas.hansson@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 9810535Sandreas.hansson@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 9910535Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 31525959 # DTB read hits 10010535Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 8580 # DTB read misses 10110535Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 23124081 # DTB write hits 10210535Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 1448 # DTB write misses 10310535Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 10410535Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 10510535Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 10610535Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 10710535Sandreas.hansson@arm.comsystem.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB 10810535Sandreas.hansson@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 10910535Sandreas.hansson@arm.comsystem.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch 11010535Sandreas.hansson@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 11110535Sandreas.hansson@arm.comsystem.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions 11210535Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 31534539 # DTB read accesses 11310535Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 23125529 # DTB write accesses 11410535Sandreas.hansson@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 11510535Sandreas.hansson@arm.comsystem.cpu.dtb.hits 54650040 # DTB hits 11610535Sandreas.hansson@arm.comsystem.cpu.dtb.misses 10028 # DTB misses 11710535Sandreas.hansson@arm.comsystem.cpu.dtb.accesses 54660068 # DTB accesses 11810535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 11910535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 12010535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 12110535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 12210535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 12310535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 12410535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 12510535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 12610535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 12710535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 12810535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 12910535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 13010535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 13110535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 13210535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 13310535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 13410535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 13510535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 13610535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 13710535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 13810535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 13910535Sandreas.hansson@arm.comsystem.cpu.itb.inst_hits 147038107 # ITB inst hits 14010535Sandreas.hansson@arm.comsystem.cpu.itb.inst_misses 4762 # ITB inst misses 14110535Sandreas.hansson@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 14210535Sandreas.hansson@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 14310535Sandreas.hansson@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 14410535Sandreas.hansson@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 14510535Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 14610535Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 14710535Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 14810535Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 14910535Sandreas.hansson@arm.comsystem.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB 15010535Sandreas.hansson@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 15110535Sandreas.hansson@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 15210535Sandreas.hansson@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 15310535Sandreas.hansson@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 15410535Sandreas.hansson@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 15510535Sandreas.hansson@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 15610535Sandreas.hansson@arm.comsystem.cpu.itb.inst_accesses 147042869 # ITB inst accesses 15710535Sandreas.hansson@arm.comsystem.cpu.itb.hits 147038107 # DTB hits 15810535Sandreas.hansson@arm.comsystem.cpu.itb.misses 4762 # DTB misses 15910535Sandreas.hansson@arm.comsystem.cpu.itb.accesses 147042869 # DTB accesses 16010535Sandreas.hansson@arm.comsystem.cpu.numCycles 5567712004 # number of cpu cycles simulated 16110535Sandreas.hansson@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 16210535Sandreas.hansson@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 16310535Sandreas.hansson@arm.comsystem.cpu.committedInsts 142771592 # Number of instructions committed 16410535Sandreas.hansson@arm.comsystem.cpu.committedOps 173801445 # Number of ops (including micro ops) committed 16510535Sandreas.hansson@arm.comsystem.cpu.num_int_alu_accesses 153161099 # Number of integer alu accesses 16610535Sandreas.hansson@arm.comsystem.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses 16710535Sandreas.hansson@arm.comsystem.cpu.num_func_calls 16873874 # number of times a function call or return occured 16810535Sandreas.hansson@arm.comsystem.cpu.num_conditional_control_insts 18730301 # number of instructions that are conditional controls 16910535Sandreas.hansson@arm.comsystem.cpu.num_int_insts 153161099 # number of integer instructions 17010535Sandreas.hansson@arm.comsystem.cpu.num_fp_insts 11484 # number of float instructions 17110535Sandreas.hansson@arm.comsystem.cpu.num_int_register_reads 285057250 # number of times the integer registers were read 17210535Sandreas.hansson@arm.comsystem.cpu.num_int_register_writes 107178308 # number of times the integer registers were written 17310535Sandreas.hansson@arm.comsystem.cpu.num_fp_register_reads 8772 # number of times the floating registers were read 17410535Sandreas.hansson@arm.comsystem.cpu.num_fp_register_writes 2716 # number of times the floating registers were written 17510535Sandreas.hansson@arm.comsystem.cpu.num_cc_register_reads 530849099 # number of times the CC registers were read 17610535Sandreas.hansson@arm.comsystem.cpu.num_cc_register_writes 62363961 # number of times the CC registers were written 17710535Sandreas.hansson@arm.comsystem.cpu.num_mem_refs 55938603 # number of memory refs 17810535Sandreas.hansson@arm.comsystem.cpu.num_load_insts 31855595 # Number of load instructions 17910535Sandreas.hansson@arm.comsystem.cpu.num_store_insts 24083008 # Number of store instructions 18010535Sandreas.hansson@arm.comsystem.cpu.num_idle_cycles 5389630193.939086 # Number of idle cycles 18110535Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 178081810.060914 # Number of busy cycles 18210535Sandreas.hansson@arm.comsystem.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles 18310535Sandreas.hansson@arm.comsystem.cpu.idle_fraction 0.968015 # Percentage of idle cycles 18410535Sandreas.hansson@arm.comsystem.cpu.Branches 36396923 # Number of branches fetched 18510535Sandreas.hansson@arm.comsystem.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction 18610535Sandreas.hansson@arm.comsystem.cpu.op_class::IntAlu 121151902 68.36% 68.36% # Class of executed instruction 18710535Sandreas.hansson@arm.comsystem.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction 18810535Sandreas.hansson@arm.comsystem.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction 18910535Sandreas.hansson@arm.comsystem.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction 19010535Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction 19110535Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCvt 0 0.00% 68.43% # Class of executed instruction 19210535Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMult 0 0.00% 68.43% # Class of executed instruction 19310535Sandreas.hansson@arm.comsystem.cpu.op_class::FloatDiv 0 0.00% 68.43% # Class of executed instruction 19410535Sandreas.hansson@arm.comsystem.cpu.op_class::FloatSqrt 0 0.00% 68.43% # Class of executed instruction 19510535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAdd 0 0.00% 68.43% # Class of executed instruction 19610535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 68.43% # Class of executed instruction 19710535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAlu 0 0.00% 68.43% # Class of executed instruction 19810535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCmp 0 0.00% 68.43% # Class of executed instruction 19910535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCvt 0 0.00% 68.43% # Class of executed instruction 20010535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMisc 0 0.00% 68.43% # Class of executed instruction 20110535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMult 0 0.00% 68.43% # Class of executed instruction 20210535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 68.43% # Class of executed instruction 20310535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShift 0 0.00% 68.43% # Class of executed instruction 20410535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 68.43% # Class of executed instruction 20510535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdSqrt 0 0.00% 68.43% # Class of executed instruction 20610535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 68.43% # Class of executed instruction 20710535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 68.43% # Class of executed instruction 20810535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 68.43% # Class of executed instruction 20910535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 68.43% # Class of executed instruction 21010535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 68.43% # Class of executed instruction 21110535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Class of executed instruction 21210535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction 21310535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction 21410535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction 21510535Sandreas.hansson@arm.comsystem.cpu.op_class::MemRead 31855595 17.98% 86.41% # Class of executed instruction 21610535Sandreas.hansson@arm.comsystem.cpu.op_class::MemWrite 24083008 13.59% 100.00% # Class of executed instruction 21710535Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 21810535Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 21910535Sandreas.hansson@arm.comsystem.cpu.op_class::total 177218284 # Class of executed instruction 22010535Sandreas.hansson@arm.comsystem.cpu.kern.inst.arm 0 # number of arm instructions executed 22110535Sandreas.hansson@arm.comsystem.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed 22210535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 819396 # number of replacements 22310535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use 22410535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 53783832 # Total number of references to valid blocks. 22510535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 819908 # Sample count of references to valid blocks. 22610535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 65.597399 # Average number of references to valid blocks. 22710535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. 22810535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor 22910535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 23010535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 23110535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 23210535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id 23310535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id 23410535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 23510535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 23610535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 219234948 # Number of tag accesses 23710535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 219234948 # Number of data accesses 23810535Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 30128799 # number of ReadReq hits 23910535Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 30128799 # number of ReadReq hits 24010535Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 22339754 # number of WriteReq hits 24110535Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 22339754 # number of WriteReq hits 24210535Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits 24310535Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits 24410535Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits 24510535Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits 24610535Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits 24710535Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits 24810535Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 52468553 # number of demand (read+write) hits 24910535Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 52468553 # number of demand (read+write) hits 25010535Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 52863618 # number of overall hits 25110535Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 52863618 # number of overall hits 25210535Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 396285 # number of ReadReq misses 25310535Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 396285 # number of ReadReq misses 25410535Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses 25510535Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses 25610535Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses 25710535Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses 25810535Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses 25910535Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses 26010535Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 26110535Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 26210535Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 697948 # number of demand (read+write) misses 26310535Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 697948 # number of demand (read+write) misses 26410535Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 814069 # number of overall misses 26510535Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 814069 # number of overall misses 26610535Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 30525084 # number of ReadReq accesses(hits+misses) 26710535Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 30525084 # number of ReadReq accesses(hits+misses) 26810535Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 22641417 # number of WriteReq accesses(hits+misses) 26910535Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 22641417 # number of WriteReq accesses(hits+misses) 27010535Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) 27110535Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) 27210535Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) 27310535Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) 27410535Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) 27510535Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) 27610535Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 53166501 # number of demand (read+write) accesses 27710535Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 53166501 # number of demand (read+write) accesses 27810535Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 53677687 # number of overall (read+write) accesses 27910535Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 53677687 # number of overall (read+write) accesses 28010535Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses 28110535Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses 28210535Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses 28310535Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses 28410535Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses 28510535Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses 28610535Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses 28710535Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses 28810535Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 28910535Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses 29010535Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses 29110535Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses 29210535Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.015166 # miss rate for overall accesses 29310535Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses 29410535Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 29510535Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 29610535Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 29710535Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 29810535Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 29910535Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 30010535Sandreas.hansson@arm.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 30110535Sandreas.hansson@arm.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 30210535Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 682037 # number of writebacks 30310535Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 682037 # number of writebacks 30410535Sandreas.hansson@arm.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 30510535Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 1699006 # number of replacements 30610535Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use 30710535Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 145341690 # Total number of references to valid blocks. 30810535Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 1699518 # Sample count of references to valid blocks. 30910535Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 85.519359 # Average number of references to valid blocks. 31010535Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. 31110535Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor 31210535Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy 31310535Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy 31410535Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 31510535Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id 31610535Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id 31710535Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id 31810535Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id 31910535Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 32010535Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 148740738 # Number of tag accesses 32110535Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 148740738 # Number of data accesses 32210535Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 145341690 # number of ReadReq hits 32310535Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 145341690 # number of ReadReq hits 32410535Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 145341690 # number of demand (read+write) hits 32510535Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 145341690 # number of demand (read+write) hits 32610535Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 145341690 # number of overall hits 32710535Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 145341690 # number of overall hits 32810535Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 1699524 # number of ReadReq misses 32910535Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 1699524 # number of ReadReq misses 33010535Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 1699524 # number of demand (read+write) misses 33110535Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 1699524 # number of demand (read+write) misses 33210535Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 1699524 # number of overall misses 33310535Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 1699524 # number of overall misses 33410535Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 147041214 # number of ReadReq accesses(hits+misses) 33510535Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 147041214 # number of ReadReq accesses(hits+misses) 33610535Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 147041214 # number of demand (read+write) accesses 33710535Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 147041214 # number of demand (read+write) accesses 33810535Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 147041214 # number of overall (read+write) accesses 33910535Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 147041214 # number of overall (read+write) accesses 34010535Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses 34110535Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses 34210535Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses 34310535Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses 34410535Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.011558 # miss rate for overall accesses 34510535Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses 34610535Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 34710535Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 34810535Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 34910535Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 35010535Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 35110535Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 35210535Sandreas.hansson@arm.comsystem.cpu.icache.fast_writes 0 # number of fast writes performed 35310535Sandreas.hansson@arm.comsystem.cpu.icache.cache_copies 0 # number of cache copies performed 35410535Sandreas.hansson@arm.comsystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 35510535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 110027 # number of replacements 35610535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 65155.314992 # Cycle average of tags in use 35710535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 2727662 # Total number of references to valid blocks. 35810535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 175308 # Sample count of references to valid blocks. 35910535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 15.559256 # Average number of references to valid blocks. 36010535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 36110535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 48893.413815 # Average occupied blocks per requestor 36210535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931995 # Average occupied blocks per requestor 36310535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor 36410535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654834 # Average occupied blocks per requestor 36510535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 7194.310003 # Average occupied blocks per requestor 36610535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.746054 # Average percentage of cache occupancy 36710535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy 36810535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 36910535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.138316 # Average percentage of cache occupancy 37010535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.109776 # Average percentage of cache occupancy 37110535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy 37210535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 37310535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 65276 # Occupied blocks per task id 37410535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 37510535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id 37610535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id 37710535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id 37810535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 10700 # Occupied blocks per task id 37910535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 50640 # Occupied blocks per task id 38010535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 38110535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id 38210535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 26202418 # Number of tag accesses 38310535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 26202418 # Number of data accesses 38410535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits 38510535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits 38610535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 1681149 # number of ReadReq hits 38710535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 505483 # number of ReadReq hits 38810535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 2197850 # number of ReadReq hits 38910535Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 682037 # number of Writeback hits 39010535Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 682037 # number of Writeback hits 39110535Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits 39210535Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits 39310535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 151043 # number of ReadExReq hits 39410535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 151043 # number of ReadExReq hits 39510535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits 39610535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits 39710535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 1681149 # number of demand (read+write) hits 39810535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 656526 # number of demand (read+write) hits 39910535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2348893 # number of demand (read+write) hits 40010535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits 40110535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits 40210535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 1681149 # number of overall hits 40310535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 656526 # number of overall hits 40410535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2348893 # number of overall hits 40510535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses 40610535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 40710535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 18358 # number of ReadReq misses 40810535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 15534 # number of ReadReq misses 40910535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 33901 # number of ReadReq misses 41010535Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 2728 # number of UpgradeReq misses 41110535Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 2728 # number of UpgradeReq misses 41210535Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 41310535Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 41410535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 147864 # number of ReadExReq misses 41510535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 147864 # number of ReadExReq misses 41610535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses 41710535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 41810535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 18358 # number of demand (read+write) misses 41910535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 163398 # number of demand (read+write) misses 42010535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 181765 # number of demand (read+write) misses 42110535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses 42210535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 42310535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 18358 # number of overall misses 42410535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 163398 # number of overall misses 42510535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 181765 # number of overall misses 42610535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses) 42710535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) 42810535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 1699507 # number of ReadReq accesses(hits+misses) 42910535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 521017 # number of ReadReq accesses(hits+misses) 43010535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 2231751 # number of ReadReq accesses(hits+misses) 43110535Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 682037 # number of Writeback accesses(hits+misses) 43210535Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 682037 # number of Writeback accesses(hits+misses) 43310535Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) 43410535Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) 43510535Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 43610535Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 43710535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 298907 # number of ReadExReq accesses(hits+misses) 43810535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses) 43910535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses 44010535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses 44110535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 1699507 # number of demand (read+write) accesses 44210535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 819924 # number of demand (read+write) accesses 44310535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2530658 # number of demand (read+write) accesses 44410535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses 44510535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses 44610535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 1699507 # number of overall (read+write) accesses 44710535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 819924 # number of overall (read+write) accesses 44810535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2530658 # number of overall (read+write) accesses 44910535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses 45010535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses 45110535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010802 # miss rate for ReadReq accesses 45210535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029815 # miss rate for ReadReq accesses 45310535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.015190 # miss rate for ReadReq accesses 45410535Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses 45510535Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses 45610535Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 45710535Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 45810535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494682 # miss rate for ReadExReq accesses 45910535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.494682 # miss rate for ReadExReq accesses 46010535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses 46110535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses 46210535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.010802 # miss rate for demand accesses 46310535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.199284 # miss rate for demand accesses 46410535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.071825 # miss rate for demand accesses 46510535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses 46610535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses 46710535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.010802 # miss rate for overall accesses 46810535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.199284 # miss rate for overall accesses 46910535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.071825 # miss rate for overall accesses 47010535Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 47110535Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 47210535Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 47310535Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 47410535Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 47510535Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 47610535Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 47710535Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 47810535Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 101899 # number of writebacks 47910535Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 101899 # number of writebacks 48010535Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 48110535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 2288348 # Transaction distribution 48210535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 2288348 # Transaction distribution 48310535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution 48410535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution 48510535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::Writeback 682037 # Transaction distribution 48610535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution 48710535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 48810535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution 48910535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution 49010535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution 49110535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417092 # Packet count per connected master and slave (bytes) 49210535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444665 # Packet count per connected master and slave (bytes) 49310535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) 49410535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes) 49510535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 5917183 # Packet count per connected master and slave (bytes) 49610535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108805624 # Cumulative packet size per connected master and slave (bytes) 49710535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308299 # Cumulative packet size per connected master and slave (bytes) 49810535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) 49910535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes) 50010535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 205224775 # Cumulative packet size per connected master and slave (bytes) 50110535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 36632 # Total snoops (count) 50210535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 3268420 # Request fanout histogram 50310535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 5.011156 # Request fanout histogram 50410535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.105033 # Request fanout histogram 50510535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 50610535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 50710535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 50810535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 50910535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 51010535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 51110535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::5 3231956 98.88% 98.88% # Request fanout histogram 51210535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::6 36464 1.12% 100.00% # Request fanout histogram 51310535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 51410535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 51510535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 51610535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 3268420 # Request fanout histogram 51710535Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 30171 # Transaction distribution 51810535Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 30171 # Transaction distribution 51910535Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 59016 # Transaction distribution 52010535Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 22792 # Transaction distribution 52110535Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 52210535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54158 # Packet count per connected master and slave (bytes) 52310535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 52410535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 52510535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 52610535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) 52710535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) 52810535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 52910535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 53010535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 53110535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 53210535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 53310535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 53410535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 53510535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 53610535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 53710535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 53810535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 53910535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 54010535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 54110535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 54210535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 54310535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes) 54410535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes) 54510535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes) 54610535Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes) 54710535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes) 54810535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 54910535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 55010535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 55110535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) 55210535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) 55310535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 55410535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 55510535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 55610535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 55710535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 55810535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 55910535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 56010535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 56110535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 56210535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 56310535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 56410535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 56510535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 56610535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 56710535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 56810535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes) 56910535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) 57010535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) 57110535Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes) 57210535Sandreas.hansson@arm.comsystem.iocache.tags.replacements 36430 # number of replacements 57310535Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use 57410535Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 57510535Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. 57610535Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 57710535Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. 57810535Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 0.909893 # Average occupied blocks per requestor 57910535Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy 58010535Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy 58110535Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 58210535Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 58310535Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 58410535Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 328176 # Number of tag accesses 58510535Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 328176 # Number of data accesses 58610535Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 58710535Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits 58810535Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses 58910535Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 240 # number of ReadReq misses 59010535Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses 59110535Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 240 # number of demand (read+write) misses 59210535Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 240 # number of overall misses 59310535Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 240 # number of overall misses 59410535Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses) 59510535Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses) 59610535Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 59710535Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 59810535Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 240 # number of demand (read+write) accesses 59910535Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 240 # number of demand (read+write) accesses 60010535Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 240 # number of overall (read+write) accesses 60110535Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 240 # number of overall (read+write) accesses 60210535Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 60310535Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 60410535Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 60510535Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 60610535Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 60710535Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 60810535Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 60910535Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 61010535Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 61110535Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 61210535Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 61310535Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 61410535Sandreas.hansson@arm.comsystem.iocache.fast_writes 36224 # number of fast writes performed 61510535Sandreas.hansson@arm.comsystem.iocache.cache_copies 0 # number of cache copies performed 61610535Sandreas.hansson@arm.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 61710517SAli.Saidi@ARM.comsystem.membus.trans_dist::ReadReq 74235 # Transaction distribution 61810517SAli.Saidi@ARM.comsystem.membus.trans_dist::ReadResp 74235 # Transaction distribution 61910513SAli.Saidi@ARM.comsystem.membus.trans_dist::WriteReq 27560 # Transaction distribution 62010513SAli.Saidi@ARM.comsystem.membus.trans_dist::WriteResp 27560 # Transaction distribution 62110517SAli.Saidi@ARM.comsystem.membus.trans_dist::Writeback 101899 # Transaction distribution 62210513SAli.Saidi@ARM.comsystem.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 62310513SAli.Saidi@ARM.comsystem.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 62410513SAli.Saidi@ARM.comsystem.membus.trans_dist::UpgradeReq 4507 # Transaction distribution 62510513SAli.Saidi@ARM.comsystem.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 62610513SAli.Saidi@ARM.comsystem.membus.trans_dist::UpgradeResp 4509 # Transaction distribution 62710513SAli.Saidi@ARM.comsystem.membus.trans_dist::ReadExReq 146085 # Transaction distribution 62810513SAli.Saidi@ARM.comsystem.membus.trans_dist::ReadExResp 146085 # Transaction distribution 62910513SAli.Saidi@ARM.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes) 63010517SAli.Saidi@ARM.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) 63110513SAli.Saidi@ARM.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) 63210517SAli.Saidi@ARM.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498795 # Packet count per connected master and slave (bytes) 63310517SAli.Saidi@ARM.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 606197 # Packet count per connected master and slave (bytes) 63410513SAli.Saidi@ARM.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes) 63510513SAli.Saidi@ARM.comsystem.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes) 63610517SAli.Saidi@ARM.comsystem.membus.pkt_count::total 679125 # Packet count per connected master and slave (bytes) 63710513SAli.Saidi@ARM.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes) 63810517SAli.Saidi@ARM.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) 63910513SAli.Saidi@ARM.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) 64010517SAli.Saidi@ARM.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096508 # Cumulative packet size per connected master and slave (bytes) 64110517SAli.Saidi@ARM.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259523 # Cumulative packet size per connected master and slave (bytes) 64210513SAli.Saidi@ARM.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes) 64310513SAli.Saidi@ARM.comsystem.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes) 64410517SAli.Saidi@ARM.comsystem.membus.pkt_size::total 20593219 # Cumulative packet size per connected master and slave (bytes) 64510409Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 64610517SAli.Saidi@ARM.comsystem.membus.snoop_fanout::samples 322858 # Request fanout histogram 64710409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 64810409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 64910409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 65010409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 65110517SAli.Saidi@ARM.comsystem.membus.snoop_fanout::1 322858 100.00% 100.00% # Request fanout histogram 65210409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 65310409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 65410409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 65510409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 65610517SAli.Saidi@ARM.comsystem.membus.snoop_fanout::total 322858 # Request fanout histogram 65710513SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 65810513SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 65910513SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 66010513SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 66110513SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 66210513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 66310513SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 66410513SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 66510513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 66610513SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 66710513SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 66810513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 66910513SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 67010513SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 67110513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 67210513SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 67310513SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 67410513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 67510513SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 67610513SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 67710513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 67810513SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 67910513SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 68010513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 68110513SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 68210513SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 68310513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 68410513SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 68510513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 68610513SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 0 # number of posts to CPU 68710513SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 6887934SN/A 6897934SN/A---------- End Simulation Statistics ---------- 690