stats.txt revision 10513
17934SN/A 27934SN/A---------- Begin Simulation Statistics ---------- 310513SAli.Saidi@ARM.comsim_seconds 2.783853 # Number of seconds simulated 410513SAli.Saidi@ARM.comsim_ticks 2783853461500 # Number of ticks simulated 510513SAli.Saidi@ARM.comfinal_tick 2783853461500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67934SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710513SAli.Saidi@ARM.comhost_inst_rate 1369296 # Simulator instruction rate (inst/s) 810513SAli.Saidi@ARM.comhost_op_rate 1666897 # Simulator op (including micro ops) rate (op/s) 910513SAli.Saidi@ARM.comhost_tick_rate 26699855189 # Simulator tick rate (ticks/s) 1010513SAli.Saidi@ARM.comhost_mem_usage 553552 # Number of bytes of host memory used 1110513SAli.Saidi@ARM.comhost_seconds 104.26 # Real time elapsed on the host 1210513SAli.Saidi@ARM.comsim_insts 142769281 # Number of instructions simulated 1310513SAli.Saidi@ARM.comsim_ops 173798567 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1610513SAli.Saidi@ARM.comsystem.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 1710513SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 1810513SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 1910513SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.inst 1210980 # Number of bytes read from this memory 2010513SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.data 10345892 # Number of bytes read from this memory 2110513SAli.Saidi@ARM.comsystem.physmem.bytes_read::total 11558408 # Number of bytes read from this memory 2210513SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::cpu.inst 1210980 # Number of instructions bytes read from this memory 2310513SAli.Saidi@ARM.comsystem.physmem.bytes_inst_read::total 1210980 # Number of instructions bytes read from this memory 2410513SAli.Saidi@ARM.comsystem.physmem.bytes_written::writebacks 6521472 # Number of bytes written to this memory 2510513SAli.Saidi@ARM.comsystem.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory 2610513SAli.Saidi@ARM.comsystem.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory 2710513SAli.Saidi@ARM.comsystem.physmem.bytes_written::total 8857332 # Number of bytes written to this memory 2810513SAli.Saidi@ARM.comsystem.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 2910513SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory 3010513SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 3110513SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.inst 27375 # Number of read requests responded to by this memory 3210513SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.data 162174 # Number of read requests responded to by this memory 3310513SAli.Saidi@ARM.comsystem.physmem.num_reads::total 189573 # Number of read requests responded to by this memory 3410513SAli.Saidi@ARM.comsystem.physmem.num_writes::writebacks 101898 # Number of write requests responded to by this memory 3510513SAli.Saidi@ARM.comsystem.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory 3610513SAli.Saidi@ARM.comsystem.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory 3710513SAli.Saidi@ARM.comsystem.physmem.num_writes::total 142503 # Number of write requests responded to by this memory 3810513SAli.Saidi@ARM.comsystem.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) 3910513SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) 4010513SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) 4110513SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.inst 435001 # Total read bandwidth from this memory (bytes/s) 4210513SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.data 3716392 # Total read bandwidth from this memory (bytes/s) 4310513SAli.Saidi@ARM.comsystem.physmem.bw_read::total 4151946 # Total read bandwidth from this memory (bytes/s) 4410513SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::cpu.inst 435001 # Instruction read bandwidth from this memory (bytes/s) 4510513SAli.Saidi@ARM.comsystem.physmem.bw_inst_read::total 435001 # Instruction read bandwidth from this memory (bytes/s) 4610513SAli.Saidi@ARM.comsystem.physmem.bw_write::writebacks 2342606 # Write bandwidth from this memory (bytes/s) 4710513SAli.Saidi@ARM.comsystem.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s) 4810513SAli.Saidi@ARM.comsystem.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) 4910513SAli.Saidi@ARM.comsystem.physmem.bw_write::total 3181680 # Write bandwidth from this memory (bytes/s) 5010513SAli.Saidi@ARM.comsystem.physmem.bw_total::writebacks 2342606 # Total bandwidth to/from this memory (bytes/s) 5110513SAli.Saidi@ARM.comsystem.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s) 5210513SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) 5310513SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 5410513SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.inst 435001 # Total bandwidth to/from this memory (bytes/s) 5510513SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.data 3722687 # Total bandwidth to/from this memory (bytes/s) 5610513SAli.Saidi@ARM.comsystem.physmem.bw_total::total 7333626 # Total bandwidth to/from this memory (bytes/s) 5710513SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu.inst 24 # Number of bytes read from this memory 5810513SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::total 24 # Number of bytes read from this memory 5910513SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu.inst 24 # Number of instructions bytes read from this memory 6010513SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::total 24 # Number of instructions bytes read from this memory 6110513SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu.inst 6 # Number of read requests responded to by this memory 6210513SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::total 6 # Number of read requests responded to by this memory 6310409Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::cpu.inst 9 # Total read bandwidth from this memory (bytes/s) 6410409Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::total 9 # Total read bandwidth from this memory (bytes/s) 6510409Sandreas.hansson@arm.comsystem.realview.nvmem.bw_inst_read::cpu.inst 9 # Instruction read bandwidth from this memory (bytes/s) 6610409Sandreas.hansson@arm.comsystem.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) 6710409Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) 6810409Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) 6910513SAli.Saidi@ARM.comsystem.membus.trans_dist::ReadReq 74236 # Transaction distribution 7010513SAli.Saidi@ARM.comsystem.membus.trans_dist::ReadResp 74236 # Transaction distribution 7110513SAli.Saidi@ARM.comsystem.membus.trans_dist::WriteReq 27560 # Transaction distribution 7210513SAli.Saidi@ARM.comsystem.membus.trans_dist::WriteResp 27560 # Transaction distribution 7310513SAli.Saidi@ARM.comsystem.membus.trans_dist::Writeback 101898 # Transaction distribution 7410513SAli.Saidi@ARM.comsystem.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution 7510513SAli.Saidi@ARM.comsystem.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 7610513SAli.Saidi@ARM.comsystem.membus.trans_dist::UpgradeReq 4507 # Transaction distribution 7710513SAli.Saidi@ARM.comsystem.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 7810513SAli.Saidi@ARM.comsystem.membus.trans_dist::UpgradeResp 4509 # Transaction distribution 7910513SAli.Saidi@ARM.comsystem.membus.trans_dist::ReadExReq 146085 # Transaction distribution 8010513SAli.Saidi@ARM.comsystem.membus.trans_dist::ReadExResp 146085 # Transaction distribution 8110513SAli.Saidi@ARM.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes) 8210513SAli.Saidi@ARM.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 12 # Packet count per connected master and slave (bytes) 8310513SAli.Saidi@ARM.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) 8410513SAli.Saidi@ARM.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498794 # Packet count per connected master and slave (bytes) 8510513SAli.Saidi@ARM.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 606198 # Packet count per connected master and slave (bytes) 8610513SAli.Saidi@ARM.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes) 8710513SAli.Saidi@ARM.comsystem.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes) 8810513SAli.Saidi@ARM.comsystem.membus.pkt_count::total 679126 # Packet count per connected master and slave (bytes) 8910513SAli.Saidi@ARM.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes) 9010513SAli.Saidi@ARM.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 24 # Cumulative packet size per connected master and slave (bytes) 9110513SAli.Saidi@ARM.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) 9210513SAli.Saidi@ARM.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096444 # Cumulative packet size per connected master and slave (bytes) 9310513SAli.Saidi@ARM.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259463 # Cumulative packet size per connected master and slave (bytes) 9410513SAli.Saidi@ARM.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes) 9510513SAli.Saidi@ARM.comsystem.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes) 9610513SAli.Saidi@ARM.comsystem.membus.pkt_size::total 20593159 # Cumulative packet size per connected master and slave (bytes) 9710409Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 9810513SAli.Saidi@ARM.comsystem.membus.snoop_fanout::samples 322857 # Request fanout histogram 9910409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 10010409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 10110409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 10210409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 10310513SAli.Saidi@ARM.comsystem.membus.snoop_fanout::1 322857 100.00% 100.00% # Request fanout histogram 10410409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 10510409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 10610409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 10710409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 10810513SAli.Saidi@ARM.comsystem.membus.snoop_fanout::total 322857 # Request fanout histogram 10910513SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 11010513SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 11110513SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 11210513SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 11310513SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 11410513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 11510513SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 11610513SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 11710513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 11810513SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 11910513SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 12010513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 12110513SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 12210513SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 12310513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 12410513SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 12510513SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 12610513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 12710513SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 12810513SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 12910513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 13010513SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 13110513SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 13210513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 13310513SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 13410513SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 13510513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 13610513SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 13710513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 13810513SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 0 # number of posts to CPU 13910513SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 1408528SN/Asystem.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 14110513SAli.Saidi@ARM.comsystem.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 14210513SAli.Saidi@ARM.comsystem.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 14310513SAli.Saidi@ARM.comsystem.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 14410513SAli.Saidi@ARM.comsystem.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 14510513SAli.Saidi@ARM.comsystem.cf0.dma_write_txs 631 # Number of DMA write transactions. 14610513SAli.Saidi@ARM.comsystem.iobus.trans_dist::ReadReq 30171 # Transaction distribution 14710513SAli.Saidi@ARM.comsystem.iobus.trans_dist::ReadResp 30171 # Transaction distribution 14810513SAli.Saidi@ARM.comsystem.iobus.trans_dist::WriteReq 59016 # Transaction distribution 14910513SAli.Saidi@ARM.comsystem.iobus.trans_dist::WriteResp 22792 # Transaction distribution 15010513SAli.Saidi@ARM.comsystem.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution 15110513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54158 # Packet count per connected master and slave (bytes) 15210513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 15310513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 15410513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 15510409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) 15610513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) 15710513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 15810409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 15910409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 16010409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 16110513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 16210409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 16310409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 16410513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 16510513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 16610409Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 16710513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 16810513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 16910513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 17010513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 17110513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 17210513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes) 17310513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes) 17410513SAli.Saidi@ARM.comsystem.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes) 17510513SAli.Saidi@ARM.comsystem.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes) 17610513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes) 17710513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 17810513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 17910513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 18010409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) 18110513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) 18210513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 18310409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 18410409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 18510409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 18610513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 18710409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 18810409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 18910513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 19010513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 19110409Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 19210513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 19310513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) 19410513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 19510513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) 19610513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 19710513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes) 19810513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) 19910513SAli.Saidi@ARM.comsystem.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) 20010513SAli.Saidi@ARM.comsystem.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes) 20110036SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 20210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 20310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 20410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 20510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 20610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 20710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 20810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 20910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 21010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 21110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 21210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 21310038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 21410038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 21510038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 21610038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 21710038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 21810038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 21910038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 22010038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 22110038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 22210038SAli.Saidi@ARM.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 2238528SN/Asystem.cpu.dtb.inst_hits 0 # ITB inst hits 2248528SN/Asystem.cpu.dtb.inst_misses 0 # ITB inst misses 22510513SAli.Saidi@ARM.comsystem.cpu.dtb.read_hits 31525428 # DTB read hits 22610513SAli.Saidi@ARM.comsystem.cpu.dtb.read_misses 8580 # DTB read misses 22710513SAli.Saidi@ARM.comsystem.cpu.dtb.write_hits 23123837 # DTB write hits 22810513SAli.Saidi@ARM.comsystem.cpu.dtb.write_misses 1448 # DTB write misses 22910513SAli.Saidi@ARM.comsystem.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 23010513SAli.Saidi@ARM.comsystem.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 23110513SAli.Saidi@ARM.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 23210513SAli.Saidi@ARM.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 23310513SAli.Saidi@ARM.comsystem.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB 2348528SN/Asystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 23510513SAli.Saidi@ARM.comsystem.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch 2368528SN/Asystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 23710513SAli.Saidi@ARM.comsystem.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions 23810513SAli.Saidi@ARM.comsystem.cpu.dtb.read_accesses 31534008 # DTB read accesses 23910513SAli.Saidi@ARM.comsystem.cpu.dtb.write_accesses 23125285 # DTB write accesses 2408528SN/Asystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 24110513SAli.Saidi@ARM.comsystem.cpu.dtb.hits 54649265 # DTB hits 24210513SAli.Saidi@ARM.comsystem.cpu.dtb.misses 10028 # DTB misses 24310513SAli.Saidi@ARM.comsystem.cpu.dtb.accesses 54659293 # DTB accesses 24410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 24510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 24610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 24710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 24810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 24910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 25010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 25110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 25210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 25310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 25410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 25510038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 25610038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 25710038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 25810038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 25910038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 26010038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 26110038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 26210038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 26310038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 26410038SAli.Saidi@ARM.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 26510513SAli.Saidi@ARM.comsystem.cpu.itb.inst_hits 147035651 # ITB inst hits 26610513SAli.Saidi@ARM.comsystem.cpu.itb.inst_misses 4762 # ITB inst misses 2678528SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 2688528SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 2698528SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 2708528SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 27110513SAli.Saidi@ARM.comsystem.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 27210513SAli.Saidi@ARM.comsystem.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 27310513SAli.Saidi@ARM.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 27410513SAli.Saidi@ARM.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 27510513SAli.Saidi@ARM.comsystem.cpu.itb.flush_entries 2913 # Number of entries that have been flushed from TLB 2768528SN/Asystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 2778528SN/Asystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 2788528SN/Asystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 2798528SN/Asystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 2808528SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 2818528SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 28210513SAli.Saidi@ARM.comsystem.cpu.itb.inst_accesses 147040413 # ITB inst accesses 28310513SAli.Saidi@ARM.comsystem.cpu.itb.hits 147035651 # DTB hits 28410513SAli.Saidi@ARM.comsystem.cpu.itb.misses 4762 # DTB misses 28510513SAli.Saidi@ARM.comsystem.cpu.itb.accesses 147040413 # DTB accesses 28610513SAli.Saidi@ARM.comsystem.cpu.numCycles 5567710004 # number of cpu cycles simulated 2878528SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 2888528SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 28910513SAli.Saidi@ARM.comsystem.cpu.committedInsts 142769281 # Number of instructions committed 29010513SAli.Saidi@ARM.comsystem.cpu.committedOps 173798567 # Number of ops (including micro ops) committed 29110513SAli.Saidi@ARM.comsystem.cpu.num_int_alu_accesses 153158502 # Number of integer alu accesses 29210513SAli.Saidi@ARM.comsystem.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses 29310513SAli.Saidi@ARM.comsystem.cpu.num_func_calls 16873305 # number of times a function call or return occured 29410513SAli.Saidi@ARM.comsystem.cpu.num_conditional_control_insts 18730015 # number of instructions that are conditional controls 29510513SAli.Saidi@ARM.comsystem.cpu.num_int_insts 153158502 # number of integer instructions 29610513SAli.Saidi@ARM.comsystem.cpu.num_fp_insts 11484 # number of float instructions 29710513SAli.Saidi@ARM.comsystem.cpu.num_int_register_reads 285052059 # number of times the integer registers were read 29810513SAli.Saidi@ARM.comsystem.cpu.num_int_register_writes 107176408 # number of times the integer registers were written 29910513SAli.Saidi@ARM.comsystem.cpu.num_fp_register_reads 8772 # number of times the floating registers were read 30010513SAli.Saidi@ARM.comsystem.cpu.num_fp_register_writes 2716 # number of times the floating registers were written 30110513SAli.Saidi@ARM.comsystem.cpu.num_cc_register_reads 530840054 # number of times the CC registers were read 30210513SAli.Saidi@ARM.comsystem.cpu.num_cc_register_writes 62363143 # number of times the CC registers were written 30310513SAli.Saidi@ARM.comsystem.cpu.num_mem_refs 55937812 # number of memory refs 30410513SAli.Saidi@ARM.comsystem.cpu.num_load_insts 31855061 # Number of load instructions 30510513SAli.Saidi@ARM.comsystem.cpu.num_store_insts 24082751 # Number of store instructions 30610513SAli.Saidi@ARM.comsystem.cpu.num_idle_cycles 5389631214.604722 # Number of idle cycles 30710513SAli.Saidi@ARM.comsystem.cpu.num_busy_cycles 178078789.395278 # Number of busy cycles 30810513SAli.Saidi@ARM.comsystem.cpu.not_idle_fraction 0.031984 # Percentage of non-idle cycles 30910513SAli.Saidi@ARM.comsystem.cpu.idle_fraction 0.968016 # Percentage of idle cycles 31010513SAli.Saidi@ARM.comsystem.cpu.Branches 36396067 # Number of branches fetched 31110513SAli.Saidi@ARM.comsystem.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction 31210513SAli.Saidi@ARM.comsystem.cpu.op_class::IntAlu 121149664 68.36% 68.36% # Class of executed instruction 31310513SAli.Saidi@ARM.comsystem.cpu.op_class::IntMult 116881 0.07% 68.43% # Class of executed instruction 31410513SAli.Saidi@ARM.comsystem.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction 31510513SAli.Saidi@ARM.comsystem.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction 31610513SAli.Saidi@ARM.comsystem.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction 31710513SAli.Saidi@ARM.comsystem.cpu.op_class::FloatCvt 0 0.00% 68.43% # Class of executed instruction 31810513SAli.Saidi@ARM.comsystem.cpu.op_class::FloatMult 0 0.00% 68.43% # Class of executed instruction 31910513SAli.Saidi@ARM.comsystem.cpu.op_class::FloatDiv 0 0.00% 68.43% # Class of executed instruction 32010513SAli.Saidi@ARM.comsystem.cpu.op_class::FloatSqrt 0 0.00% 68.43% # Class of executed instruction 32110513SAli.Saidi@ARM.comsystem.cpu.op_class::SimdAdd 0 0.00% 68.43% # Class of executed instruction 32210513SAli.Saidi@ARM.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 68.43% # Class of executed instruction 32310513SAli.Saidi@ARM.comsystem.cpu.op_class::SimdAlu 0 0.00% 68.43% # Class of executed instruction 32410513SAli.Saidi@ARM.comsystem.cpu.op_class::SimdCmp 0 0.00% 68.43% # Class of executed instruction 32510513SAli.Saidi@ARM.comsystem.cpu.op_class::SimdCvt 0 0.00% 68.43% # Class of executed instruction 32610513SAli.Saidi@ARM.comsystem.cpu.op_class::SimdMisc 0 0.00% 68.43% # Class of executed instruction 32710513SAli.Saidi@ARM.comsystem.cpu.op_class::SimdMult 0 0.00% 68.43% # Class of executed instruction 32810513SAli.Saidi@ARM.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 68.43% # Class of executed instruction 32910513SAli.Saidi@ARM.comsystem.cpu.op_class::SimdShift 0 0.00% 68.43% # Class of executed instruction 33010513SAli.Saidi@ARM.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 68.43% # Class of executed instruction 33110513SAli.Saidi@ARM.comsystem.cpu.op_class::SimdSqrt 0 0.00% 68.43% # Class of executed instruction 33210513SAli.Saidi@ARM.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 68.43% # Class of executed instruction 33310513SAli.Saidi@ARM.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 68.43% # Class of executed instruction 33410513SAli.Saidi@ARM.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 68.43% # Class of executed instruction 33510513SAli.Saidi@ARM.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 68.43% # Class of executed instruction 33610513SAli.Saidi@ARM.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 68.43% # Class of executed instruction 33710513SAli.Saidi@ARM.comsystem.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Class of executed instruction 33810513SAli.Saidi@ARM.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction 33910513SAli.Saidi@ARM.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction 34010513SAli.Saidi@ARM.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction 34110513SAli.Saidi@ARM.comsystem.cpu.op_class::MemRead 31855061 17.98% 86.41% # Class of executed instruction 34210513SAli.Saidi@ARM.comsystem.cpu.op_class::MemWrite 24082751 13.59% 100.00% # Class of executed instruction 34310220Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 34410220Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 34510513SAli.Saidi@ARM.comsystem.cpu.op_class::total 177215263 # Class of executed instruction 3468528SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 34710513SAli.Saidi@ARM.comsystem.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed 34810513SAli.Saidi@ARM.comsystem.cpu.icache.tags.replacements 1698994 # number of replacements 34910513SAli.Saidi@ARM.comsystem.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use 35010513SAli.Saidi@ARM.comsystem.cpu.icache.tags.total_refs 145339246 # Total number of references to valid blocks. 35110513SAli.Saidi@ARM.comsystem.cpu.icache.tags.sampled_refs 1699506 # Sample count of references to valid blocks. 35210513SAli.Saidi@ARM.comsystem.cpu.icache.tags.avg_refs 85.518525 # Average number of references to valid blocks. 35310513SAli.Saidi@ARM.comsystem.cpu.icache.tags.warmup_cycle 7831492000 # Cycle when the warmup percentage was hit. 35410513SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor 35510513SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy 35610513SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy 35710036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 35810513SAli.Saidi@ARM.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id 35910513SAli.Saidi@ARM.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id 36010513SAli.Saidi@ARM.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id 36110513SAli.Saidi@ARM.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id 36210036SAli.Saidi@ARM.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 36310513SAli.Saidi@ARM.comsystem.cpu.icache.tags.tag_accesses 148738270 # Number of tag accesses 36410513SAli.Saidi@ARM.comsystem.cpu.icache.tags.data_accesses 148738270 # Number of data accesses 36510513SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::cpu.inst 145339246 # number of ReadReq hits 36610513SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_hits::total 145339246 # number of ReadReq hits 36710513SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::cpu.inst 145339246 # number of demand (read+write) hits 36810513SAli.Saidi@ARM.comsystem.cpu.icache.demand_hits::total 145339246 # number of demand (read+write) hits 36910513SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::cpu.inst 145339246 # number of overall hits 37010513SAli.Saidi@ARM.comsystem.cpu.icache.overall_hits::total 145339246 # number of overall hits 37110513SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::cpu.inst 1699512 # number of ReadReq misses 37210513SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_misses::total 1699512 # number of ReadReq misses 37310513SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::cpu.inst 1699512 # number of demand (read+write) misses 37410513SAli.Saidi@ARM.comsystem.cpu.icache.demand_misses::total 1699512 # number of demand (read+write) misses 37510513SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::cpu.inst 1699512 # number of overall misses 37610513SAli.Saidi@ARM.comsystem.cpu.icache.overall_misses::total 1699512 # number of overall misses 37710513SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 147038758 # number of ReadReq accesses(hits+misses) 37810513SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_accesses::total 147038758 # number of ReadReq accesses(hits+misses) 37910513SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::cpu.inst 147038758 # number of demand (read+write) accesses 38010513SAli.Saidi@ARM.comsystem.cpu.icache.demand_accesses::total 147038758 # number of demand (read+write) accesses 38110513SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::cpu.inst 147038758 # number of overall (read+write) accesses 38210513SAli.Saidi@ARM.comsystem.cpu.icache.overall_accesses::total 147038758 # number of overall (read+write) accesses 38310513SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses 38410513SAli.Saidi@ARM.comsystem.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses 38510513SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses 38610513SAli.Saidi@ARM.comsystem.cpu.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses 38710513SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.011558 # miss rate for overall accesses 38810513SAli.Saidi@ARM.comsystem.cpu.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses 3898528SN/Asystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 3908528SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3918528SN/Asystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 3928528SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 3938983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 3948983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3958528SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 3968528SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 3978528SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 39810513SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.replacements 110027 # number of replacements 39910513SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.tagsinuse 65155.315266 # Cycle average of tags in use 40010513SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.total_refs 2727659 # Total number of references to valid blocks. 40110513SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.sampled_refs 175308 # Sample count of references to valid blocks. 40210513SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.avg_refs 15.559239 # Average number of references to valid blocks. 40310513SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 40410513SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 48893.414938 # Average occupied blocks per requestor 40510513SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931995 # Average occupied blocks per requestor 40610513SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004344 # Average occupied blocks per requestor 40710513SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.653997 # Average occupied blocks per requestor 40810513SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 7194.309992 # Average occupied blocks per requestor 40910513SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.746054 # Average percentage of cache occupancy 4109797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy 41110513SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 41210513SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.138316 # Average percentage of cache occupancy 41310513SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.109776 # Average percentage of cache occupancy 41410513SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy 41510036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 41610513SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 65276 # Occupied blocks per task id 41710036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 41810036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id 41910513SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id 42010513SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id 42110513SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 10700 # Occupied blocks per task id 42210513SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 50640 # Occupied blocks per task id 42310036SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 42410513SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id 42510513SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.tag_accesses 26202376 # Number of tag accesses 42610513SAli.Saidi@ARM.comsystem.cpu.l2cache.tags.data_accesses 26202376 # Number of data accesses 42710513SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7597 # number of ReadReq hits 42810513SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits 42910513SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 1681137 # number of ReadReq hits 43010513SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 505491 # number of ReadReq hits 43110513SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_hits::total 2197846 # number of ReadReq hits 43210513SAli.Saidi@ARM.comsystem.cpu.l2cache.Writeback_hits::writebacks 682038 # number of Writeback hits 43310513SAli.Saidi@ARM.comsystem.cpu.l2cache.Writeback_hits::total 682038 # number of Writeback hits 43410513SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits 43510513SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits 43610513SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 151041 # number of ReadExReq hits 43710513SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_hits::total 151041 # number of ReadExReq hits 43810513SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.dtb.walker 7597 # number of demand (read+write) hits 43910513SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits 44010513SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 1681137 # number of demand (read+write) hits 44110513SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.data 656532 # number of demand (read+write) hits 44210513SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 2348887 # number of demand (read+write) hits 44310513SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.dtb.walker 7597 # number of overall hits 44410513SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits 44510513SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 1681137 # number of overall hits 44610513SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.data 656532 # number of overall hits 44710513SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 2348887 # number of overall hits 44810513SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses 44910513SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 45010513SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 18358 # number of ReadReq misses 45110513SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 15534 # number of ReadReq misses 45210513SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_misses::total 33901 # number of ReadReq misses 45310513SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 2728 # number of UpgradeReq misses 45410513SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_misses::total 2728 # number of UpgradeReq misses 45510513SAli.Saidi@ARM.comsystem.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 45610513SAli.Saidi@ARM.comsystem.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 45710513SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 147864 # number of ReadExReq misses 45810513SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_misses::total 147864 # number of ReadExReq misses 45910513SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses 46010513SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 46110513SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.inst 18358 # number of demand (read+write) misses 46210513SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::cpu.data 163398 # number of demand (read+write) misses 46310513SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_misses::total 181765 # number of demand (read+write) misses 46410513SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses 46510513SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 46610513SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.inst 18358 # number of overall misses 46710513SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::cpu.data 163398 # number of overall misses 46810513SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_misses::total 181765 # number of overall misses 46910513SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7604 # number of ReadReq accesses(hits+misses) 47010513SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) 47110513SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 1699495 # number of ReadReq accesses(hits+misses) 47210513SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 521025 # number of ReadReq accesses(hits+misses) 47310513SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_accesses::total 2231747 # number of ReadReq accesses(hits+misses) 47410513SAli.Saidi@ARM.comsystem.cpu.l2cache.Writeback_accesses::writebacks 682038 # number of Writeback accesses(hits+misses) 47510513SAli.Saidi@ARM.comsystem.cpu.l2cache.Writeback_accesses::total 682038 # number of Writeback accesses(hits+misses) 47610513SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) 47710513SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) 47810513SAli.Saidi@ARM.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 47910513SAli.Saidi@ARM.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 48010513SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 298905 # number of ReadExReq accesses(hits+misses) 48110513SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_accesses::total 298905 # number of ReadExReq accesses(hits+misses) 48210513SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.dtb.walker 7604 # number of demand (read+write) accesses 48310513SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses 48410513SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.inst 1699495 # number of demand (read+write) accesses 48510513SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::cpu.data 819930 # number of demand (read+write) accesses 48610513SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_accesses::total 2530652 # number of demand (read+write) accesses 48710513SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.dtb.walker 7604 # number of overall (read+write) accesses 48810513SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses 48910513SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.inst 1699495 # number of overall (read+write) accesses 49010513SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::cpu.data 819930 # number of overall (read+write) accesses 49110513SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_accesses::total 2530652 # number of overall (read+write) accesses 49210513SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000921 # miss rate for ReadReq accesses 49310513SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses 49410513SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010802 # miss rate for ReadReq accesses 49510513SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029814 # miss rate for ReadReq accesses 49610513SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.015190 # miss rate for ReadReq accesses 49710513SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses 49810513SAli.Saidi@ARM.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses 49910513SAli.Saidi@ARM.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 50010513SAli.Saidi@ARM.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 50110513SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494686 # miss rate for ReadExReq accesses 50210513SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.494686 # miss rate for ReadExReq accesses 50310513SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000921 # miss rate for demand accesses 50410513SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses 50510513SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.010802 # miss rate for demand accesses 50610513SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.199283 # miss rate for demand accesses 50710513SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::total 0.071825 # miss rate for demand accesses 50810513SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000921 # miss rate for overall accesses 50910513SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses 51010513SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.010802 # miss rate for overall accesses 51110513SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.199283 # miss rate for overall accesses 51210513SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::total 0.071825 # miss rate for overall accesses 5139312Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5149312Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5159312Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 5169312Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 5179312Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 5189312Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 5199312Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 5209312Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 52110513SAli.Saidi@ARM.comsystem.cpu.l2cache.writebacks::writebacks 101898 # number of writebacks 52210513SAli.Saidi@ARM.comsystem.cpu.l2cache.writebacks::total 101898 # number of writebacks 5239312Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 52410513SAli.Saidi@ARM.comsystem.cpu.dcache.tags.replacements 819402 # number of replacements 52510513SAli.Saidi@ARM.comsystem.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use 52610513SAli.Saidi@ARM.comsystem.cpu.dcache.tags.total_refs 53783051 # Total number of references to valid blocks. 52710513SAli.Saidi@ARM.comsystem.cpu.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks. 52810513SAli.Saidi@ARM.comsystem.cpu.dcache.tags.avg_refs 65.595966 # Average number of references to valid blocks. 52910513SAli.Saidi@ARM.comsystem.cpu.dcache.tags.warmup_cycle 23054000 # Cycle when the warmup percentage was hit. 53010513SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor 5319885Sstever@gmail.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 5329885Sstever@gmail.comsystem.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 53310036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 53410513SAli.Saidi@ARM.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id 53510513SAli.Saidi@ARM.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id 53610513SAli.Saidi@ARM.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 53710036SAli.Saidi@ARM.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 53810513SAli.Saidi@ARM.comsystem.cpu.dcache.tags.tag_accesses 219231854 # Number of tag accesses 53910513SAli.Saidi@ARM.comsystem.cpu.dcache.tags.data_accesses 219231854 # Number of data accesses 54010513SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::cpu.data 30128262 # number of ReadReq hits 54110513SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_hits::total 30128262 # number of ReadReq hits 54210513SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::cpu.data 22339512 # number of WriteReq hits 54310513SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_hits::total 22339512 # number of WriteReq hits 54410513SAli.Saidi@ARM.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 395063 # number of SoftPFReq hits 54510513SAli.Saidi@ARM.comsystem.cpu.dcache.SoftPFReq_hits::total 395063 # number of SoftPFReq hits 54610513SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits 54710513SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits 54810513SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits 54910513SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits 55010513SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::cpu.data 52467774 # number of demand (read+write) hits 55110513SAli.Saidi@ARM.comsystem.cpu.dcache.demand_hits::total 52467774 # number of demand (read+write) hits 55210513SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::cpu.data 52862837 # number of overall hits 55310513SAli.Saidi@ARM.comsystem.cpu.dcache.overall_hits::total 52862837 # number of overall hits 55410513SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::cpu.data 396291 # number of ReadReq misses 55510513SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_misses::total 396291 # number of ReadReq misses 55610513SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::cpu.data 301661 # number of WriteReq misses 55710513SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_misses::total 301661 # number of WriteReq misses 55810513SAli.Saidi@ARM.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 116123 # number of SoftPFReq misses 55910513SAli.Saidi@ARM.comsystem.cpu.dcache.SoftPFReq_misses::total 116123 # number of SoftPFReq misses 56010513SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses 56110513SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses 56210513SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 56310513SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 56410513SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::cpu.data 697952 # number of demand (read+write) misses 56510513SAli.Saidi@ARM.comsystem.cpu.dcache.demand_misses::total 697952 # number of demand (read+write) misses 56610513SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::cpu.data 814075 # number of overall misses 56710513SAli.Saidi@ARM.comsystem.cpu.dcache.overall_misses::total 814075 # number of overall misses 56810513SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 30524553 # number of ReadReq accesses(hits+misses) 56910513SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_accesses::total 30524553 # number of ReadReq accesses(hits+misses) 57010513SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 22641173 # number of WriteReq accesses(hits+misses) 57110513SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_accesses::total 22641173 # number of WriteReq accesses(hits+misses) 57210513SAli.Saidi@ARM.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) 57310513SAli.Saidi@ARM.comsystem.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) 57410513SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) 57510513SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) 57610513SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) 57710513SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) 57810513SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::cpu.data 53165726 # number of demand (read+write) accesses 57910513SAli.Saidi@ARM.comsystem.cpu.dcache.demand_accesses::total 53165726 # number of demand (read+write) accesses 58010513SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::cpu.data 53676912 # number of overall (read+write) accesses 58110513SAli.Saidi@ARM.comsystem.cpu.dcache.overall_accesses::total 53676912 # number of overall (read+write) accesses 58210513SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012983 # miss rate for ReadReq accesses 58310513SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.012983 # miss rate for ReadReq accesses 58410513SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses 58510513SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses 58610513SAli.Saidi@ARM.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227164 # miss rate for SoftPFReq accesses 58710513SAli.Saidi@ARM.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.227164 # miss rate for SoftPFReq accesses 58810513SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses 58910513SAli.Saidi@ARM.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses 59010513SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 59110513SAli.Saidi@ARM.comsystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses 59210513SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses 59310513SAli.Saidi@ARM.comsystem.cpu.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses 59410513SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.015166 # miss rate for overall accesses 59510513SAli.Saidi@ARM.comsystem.cpu.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses 5969481Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 5979481Snilay@cs.wisc.edusystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 5989481Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 5999481Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 6009481Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6019481Snilay@cs.wisc.edusystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 6029481Snilay@cs.wisc.edusystem.cpu.dcache.fast_writes 0 # number of fast writes performed 6039481Snilay@cs.wisc.edusystem.cpu.dcache.cache_copies 0 # number of cache copies performed 60410513SAli.Saidi@ARM.comsystem.cpu.dcache.writebacks::writebacks 682038 # number of writebacks 60510513SAli.Saidi@ARM.comsystem.cpu.dcache.writebacks::total 682038 # number of writebacks 6069481Snilay@cs.wisc.edusystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 60710513SAli.Saidi@ARM.comsystem.cpu.toL2Bus.trans_dist::ReadReq 2288345 # Transaction distribution 60810513SAli.Saidi@ARM.comsystem.cpu.toL2Bus.trans_dist::ReadResp 2288345 # Transaction distribution 60910513SAli.Saidi@ARM.comsystem.cpu.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution 61010513SAli.Saidi@ARM.comsystem.cpu.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution 61110513SAli.Saidi@ARM.comsystem.cpu.toL2Bus.trans_dist::Writeback 682038 # Transaction distribution 61210513SAli.Saidi@ARM.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution 61310513SAli.Saidi@ARM.comsystem.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 61410513SAli.Saidi@ARM.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution 61510513SAli.Saidi@ARM.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 298905 # Transaction distribution 61610513SAli.Saidi@ARM.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 298905 # Transaction distribution 61710513SAli.Saidi@ARM.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417070 # Packet count per connected master and slave (bytes) 61810513SAli.Saidi@ARM.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444678 # Packet count per connected master and slave (bytes) 61910513SAli.Saidi@ARM.comsystem.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) 62010513SAli.Saidi@ARM.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes) 62110513SAli.Saidi@ARM.comsystem.cpu.toL2Bus.pkt_count::total 5917174 # Packet count per connected master and slave (bytes) 62210513SAli.Saidi@ARM.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108804860 # Cumulative packet size per connected master and slave (bytes) 62310513SAli.Saidi@ARM.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96308747 # Cumulative packet size per connected master and slave (bytes) 62410513SAli.Saidi@ARM.comsystem.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) 62510513SAli.Saidi@ARM.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes) 62610513SAli.Saidi@ARM.comsystem.cpu.toL2Bus.pkt_size::total 205224459 # Cumulative packet size per connected master and slave (bytes) 62710513SAli.Saidi@ARM.comsystem.cpu.toL2Bus.snoops 36632 # Total snoops (count) 62810513SAli.Saidi@ARM.comsystem.cpu.toL2Bus.snoop_fanout::samples 3268415 # Request fanout histogram 62910513SAli.Saidi@ARM.comsystem.cpu.toL2Bus.snoop_fanout::mean 5.011156 # Request fanout histogram 63010513SAli.Saidi@ARM.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.105033 # Request fanout histogram 63110409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 63210409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 63310409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 63410409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 63510409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 63610409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 63710513SAli.Saidi@ARM.comsystem.cpu.toL2Bus.snoop_fanout::5 3231951 98.88% 98.88% # Request fanout histogram 63810513SAli.Saidi@ARM.comsystem.cpu.toL2Bus.snoop_fanout::6 36464 1.12% 100.00% # Request fanout histogram 63910409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 64010409Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 64110513SAli.Saidi@ARM.comsystem.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 64210513SAli.Saidi@ARM.comsystem.cpu.toL2Bus.snoop_fanout::total 3268415 # Request fanout histogram 64310513SAli.Saidi@ARM.comsystem.iocache.tags.replacements 36430 # number of replacements 64410513SAli.Saidi@ARM.comsystem.iocache.tags.tagsinuse 0.909886 # Cycle average of tags in use 6459885Sstever@gmail.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 64610513SAli.Saidi@ARM.comsystem.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. 64710513SAli.Saidi@ARM.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 64810513SAli.Saidi@ARM.comsystem.iocache.tags.warmup_cycle 227409698009 # Cycle when the warmup percentage was hit. 64910513SAli.Saidi@ARM.comsystem.iocache.tags.occ_blocks::realview.ide 0.909886 # Average occupied blocks per requestor 65010513SAli.Saidi@ARM.comsystem.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy 65110513SAli.Saidi@ARM.comsystem.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy 65210513SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 65310513SAli.Saidi@ARM.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 65410513SAli.Saidi@ARM.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 65510513SAli.Saidi@ARM.comsystem.iocache.tags.tag_accesses 328176 # Number of tag accesses 65610513SAli.Saidi@ARM.comsystem.iocache.tags.data_accesses 328176 # Number of data accesses 65710513SAli.Saidi@ARM.comsystem.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits 65810513SAli.Saidi@ARM.comsystem.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits 65910513SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses 66010513SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::total 240 # number of ReadReq misses 66110513SAli.Saidi@ARM.comsystem.iocache.demand_misses::realview.ide 240 # number of demand (read+write) misses 66210513SAli.Saidi@ARM.comsystem.iocache.demand_misses::total 240 # number of demand (read+write) misses 66310513SAli.Saidi@ARM.comsystem.iocache.overall_misses::realview.ide 240 # number of overall misses 66410513SAli.Saidi@ARM.comsystem.iocache.overall_misses::total 240 # number of overall misses 66510513SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses) 66610513SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses) 66710513SAli.Saidi@ARM.comsystem.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) 66810513SAli.Saidi@ARM.comsystem.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) 66910513SAli.Saidi@ARM.comsystem.iocache.demand_accesses::realview.ide 240 # number of demand (read+write) accesses 67010513SAli.Saidi@ARM.comsystem.iocache.demand_accesses::total 240 # number of demand (read+write) accesses 67110513SAli.Saidi@ARM.comsystem.iocache.overall_accesses::realview.ide 240 # number of overall (read+write) accesses 67210513SAli.Saidi@ARM.comsystem.iocache.overall_accesses::total 240 # number of overall (read+write) accesses 67310513SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 67410513SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 67510513SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 67610513SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 67710513SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 67810513SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 6798528SN/Asystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 6808528SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 6818528SN/Asystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 6828528SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 6838983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 6848983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 68510513SAli.Saidi@ARM.comsystem.iocache.fast_writes 36224 # number of fast writes performed 6868528SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 6878528SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 6887934SN/A 6897934SN/A---------- End Simulation Statistics ---------- 690