17934SN/A 27934SN/A---------- Begin Simulation Statistics ---------- 311754Sandreas.hansson@arm.comsim_seconds 2.783856 # Number of seconds simulated 411754Sandreas.hansson@arm.comsim_ticks 2783855588000 # Number of ticks simulated 511754Sandreas.hansson@arm.comfinal_tick 2783855588000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 67934SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711754Sandreas.hansson@arm.comhost_inst_rate 1539062 # Simulator instruction rate (inst/s) 811754Sandreas.hansson@arm.comhost_op_rate 1873561 # Simulator op (including micro ops) rate (op/s) 911754Sandreas.hansson@arm.comhost_tick_rate 30009675812 # Simulator tick rate (ticks/s) 1011754Sandreas.hansson@arm.comhost_mem_usage 581968 # Number of bytes of host memory used 1111754Sandreas.hansson@arm.comhost_seconds 92.77 # Real time elapsed on the host 1211754Sandreas.hansson@arm.comsim_insts 142771499 # Number of instructions simulated 1311754Sandreas.hansson@arm.comsim_ops 173801409 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611754Sandreas.hansson@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 1710513SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory 1810513SAli.Saidi@ARM.comsystem.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory 1910892Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 1207012 # Number of bytes read from this memory 2011754Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 10324900 # Number of bytes read from this memory 2110535Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory 2211754Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 11533448 # Number of bytes read from this memory 2310892Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 1207012 # Number of instructions bytes read from this memory 2410892Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 1207012 # Number of instructions bytes read from this memory 2511606Sandreas.sandberg@arm.comsystem.physmem.bytes_written::writebacks 8840896 # Number of bytes written to this memory 2610535Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory 2711606Sandreas.sandberg@arm.comsystem.physmem.bytes_written::total 8858420 # Number of bytes written to this memory 2810513SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory 2910513SAli.Saidi@ARM.comsystem.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory 3010892Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 27313 # Number of read requests responded to by this memory 3111754Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 161846 # Number of read requests responded to by this memory 3210535Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory 3311754Sandreas.hansson@arm.comsystem.physmem.num_reads::total 189183 # Number of read requests responded to by this memory 3411606Sandreas.sandberg@arm.comsystem.physmem.num_writes::writebacks 138139 # Number of write requests responded to by this memory 3510535Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory 3611606Sandreas.sandberg@arm.comsystem.physmem.num_writes::total 142520 # Number of write requests responded to by this memory 3710513SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) 3810513SAli.Saidi@ARM.comsystem.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) 3911336Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 433576 # Total read bandwidth from this memory (bytes/s) 4011754Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 3708849 # Total read bandwidth from this memory (bytes/s) 4110535Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) 4211754Sandreas.hansson@arm.comsystem.physmem.bw_read::total 4142976 # Total read bandwidth from this memory (bytes/s) 4311336Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 433576 # Instruction read bandwidth from this memory (bytes/s) 4411336Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 433576 # Instruction read bandwidth from this memory (bytes/s) 4511754Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 3175774 # Write bandwidth from this memory (bytes/s) 4610535Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) 4711754Sandreas.hansson@arm.comsystem.physmem.bw_write::total 3182069 # Write bandwidth from this memory (bytes/s) 4811754Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 3175774 # Total bandwidth to/from this memory (bytes/s) 4910513SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) 5010513SAli.Saidi@ARM.comsystem.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) 5111336Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 433576 # Total bandwidth to/from this memory (bytes/s) 5211754Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 3715144 # Total bandwidth to/from this memory (bytes/s) 5310585Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) 5411754Sandreas.hansson@arm.comsystem.physmem.bw_total::total 7325045 # Total bandwidth to/from this memory (bytes/s) 5511754Sandreas.hansson@arm.comsystem.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 5610517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory 5710517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory 5810517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory 5910517SAli.Saidi@ARM.comsystem.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory 6010517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory 6110517SAli.Saidi@ARM.comsystem.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory 6210517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 6310517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) 6410517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 6510517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 6610517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 6710517SAli.Saidi@ARM.comsystem.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) 6811754Sandreas.hansson@arm.comsystem.realview.vram.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 6911754Sandreas.hansson@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 7011754Sandreas.hansson@arm.comsystem.bridge.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 7110535Sandreas.hansson@arm.comsystem.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 7210535Sandreas.hansson@arm.comsystem.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 7310535Sandreas.hansson@arm.comsystem.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 7410535Sandreas.hansson@arm.comsystem.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. 7510535Sandreas.hansson@arm.comsystem.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. 7610535Sandreas.hansson@arm.comsystem.cf0.dma_write_txs 631 # Number of DMA write transactions. 7710535Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 7811754Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 7910628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 8010628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 8110628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 8210628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 8310628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 8410628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 8510628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 8610628Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 8710535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 8810535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 8910535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 9010535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 9110535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 9210535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 9310535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 9410535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 9510535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 9610535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 9710535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 9810535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 9910535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 10010535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 10110535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 10210535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 10310535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 10410535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 10510535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 10610535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 10710535Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 10811754Sandreas.hansson@arm.comsystem.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 10911336Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walks 10028 # Table walker walks requested 11011336Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksShort 10028 # Table walker walks initiated with short descriptors 11111336Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::samples 10028 # Table walker wait (enqueue to first request) latency 11211336Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::0 10028 100.00% 100.00% # Table walker wait (enqueue to first request) latency 11311336Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkWaitTime::total 10028 # Table walker wait (enqueue to first request) latency 11410628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution 11510628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution 11610628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution 11711336Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::4K 6353 80.79% 80.79% # Table walker page sizes translated 11810628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::1M 1511 19.21% 100.00% # Table walker page sizes translated 11911336Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkPageSizes::total 7864 # Table walker page sizes translated 12011336Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 10028 # Table walker requests started/completed, data/inst 12110628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 12211336Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 10028 # Table walker requests started/completed, data/inst 12311336Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7864 # Table walker requests started/completed, data/inst 12410628Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 12511336Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 7864 # Table walker requests started/completed, data/inst 12611336Sandreas.hansson@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 17892 # Table walker requests started/completed, data/inst 12710535Sandreas.hansson@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 12810535Sandreas.hansson@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 12911754Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 31525952 # DTB read hits 13011336Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 8580 # DTB read misses 13111754Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 23124113 # DTB write hits 13210535Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 1448 # DTB write misses 13310535Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed 13410535Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 13510535Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 13610535Sandreas.hansson@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 13711547Sandreas.sandberg@arm.comsystem.cpu.dtb.flush_entries 4285 # Number of entries that have been flushed from TLB 13810535Sandreas.hansson@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 13910535Sandreas.hansson@arm.comsystem.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch 14010535Sandreas.hansson@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 14110535Sandreas.hansson@arm.comsystem.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions 14211754Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 31534532 # DTB read accesses 14311754Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 23125561 # DTB write accesses 14410535Sandreas.hansson@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 14511754Sandreas.hansson@arm.comsystem.cpu.dtb.hits 54650065 # DTB hits 14611336Sandreas.hansson@arm.comsystem.cpu.dtb.misses 10028 # DTB misses 14711754Sandreas.hansson@arm.comsystem.cpu.dtb.accesses 54660093 # DTB accesses 14811754Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 14910628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 15010628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 15110628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 15210628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 15310628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 15410628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 15510628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 15610628Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 15710535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 15810535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 15910535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 16010535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 16110535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 16210535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 16310535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 16410535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 16510535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 16610535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 16710535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 16810535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 16910535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 17010535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 17110535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 17210535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 17310535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 17410535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 17510535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 17610535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 17710535Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 17811754Sandreas.hansson@arm.comsystem.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 17910628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walks 4762 # Table walker walks requested 18010628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksShort 4762 # Table walker walks initiated with short descriptors 18110628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::samples 4762 # Table walker wait (enqueue to first request) latency 18210628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency 18310628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency 18410628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::samples 6702500 # Table walker pending requests distribution 18510628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::0 6702500 100.00% 100.00% # Table walker pending requests distribution 18610628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walksPending::total 6702500 # Table walker pending requests distribution 18710628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated 18810628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated 18910628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated 19010628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 19110628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 4762 # Table walker requests started/completed, data/inst 19210628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 4762 # Table walker requests started/completed, data/inst 19310628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 19410628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst 19510628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst 19610628Sandreas.hansson@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst 19711754Sandreas.hansson@arm.comsystem.cpu.itb.inst_hits 147038008 # ITB inst hits 19810535Sandreas.hansson@arm.comsystem.cpu.itb.inst_misses 4762 # ITB inst misses 19910535Sandreas.hansson@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 20010535Sandreas.hansson@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 20110535Sandreas.hansson@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 20210535Sandreas.hansson@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 20310535Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb 64 # Number of times complete TLB was flushed 20410535Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA 20510535Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 20610535Sandreas.hansson@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 20711547Sandreas.sandberg@arm.comsystem.cpu.itb.flush_entries 2849 # Number of entries that have been flushed from TLB 20810535Sandreas.hansson@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 20910535Sandreas.hansson@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 21010535Sandreas.hansson@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 21110535Sandreas.hansson@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 21210535Sandreas.hansson@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 21310535Sandreas.hansson@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 21411754Sandreas.hansson@arm.comsystem.cpu.itb.inst_accesses 147042770 # ITB inst accesses 21511754Sandreas.hansson@arm.comsystem.cpu.itb.hits 147038008 # DTB hits 21610535Sandreas.hansson@arm.comsystem.cpu.itb.misses 4762 # DTB misses 21711754Sandreas.hansson@arm.comsystem.cpu.itb.accesses 147042770 # DTB accesses 21811530Sandreas.sandberg@arm.comsystem.cpu.numPwrStateTransitions 6160 # Number of power state transitions 21911530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::samples 3080 # Distribution of time spent in the clock gated state 22011754Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::mean 874939855.098377 # Distribution of time spent in the clock gated state 22111754Sandreas.hansson@arm.comsystem.cpu.pwrStateClkGateDist::stdev 17329944394.226795 # Distribution of time spent in the clock gated state 22211530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::underflows 3002 97.47% 97.47% # Distribution of time spent in the clock gated state 22311530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::1000-5e+10 72 2.34% 99.81% # Distribution of time spent in the clock gated state 22411530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.03% 99.84% # Distribution of time spent in the clock gated state 22511530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::2e+11-2.5e+11 1 0.03% 99.87% # Distribution of time spent in the clock gated state 22611530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::2.5e+11-3e+11 1 0.03% 99.90% # Distribution of time spent in the clock gated state 22711530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::4.5e+11-5e+11 3 0.10% 100.00% # Distribution of time spent in the clock gated state 22811570SCurtis.Dunham@arm.comsystem.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 22911530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::max_value 499984036900 # Distribution of time spent in the clock gated state 23011530Sandreas.sandberg@arm.comsystem.cpu.pwrStateClkGateDist::total 3080 # Distribution of time spent in the clock gated state 23111754Sandreas.hansson@arm.comsystem.cpu.pwrStateResidencyTicks::ON 89040834297 # Cumulative time (in ticks) in various power states 23211754Sandreas.hansson@arm.comsystem.cpu.pwrStateResidencyTicks::CLK_GATED 2694814753703 # Cumulative time (in ticks) in various power states 23311754Sandreas.hansson@arm.comsystem.cpu.numCycles 5567714257 # number of cpu cycles simulated 23410535Sandreas.hansson@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 23510535Sandreas.hansson@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 23611201Sandreas.hansson@arm.comsystem.cpu.kern.inst.arm 0 # number of arm instructions executed 23711336Sandreas.hansson@arm.comsystem.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed 23811754Sandreas.hansson@arm.comsystem.cpu.committedInsts 142771499 # Number of instructions committed 23911754Sandreas.hansson@arm.comsystem.cpu.committedOps 173801409 # Number of ops (including micro ops) committed 24011754Sandreas.hansson@arm.comsystem.cpu.num_int_alu_accesses 153161120 # Number of integer alu accesses 24110535Sandreas.hansson@arm.comsystem.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses 24211754Sandreas.hansson@arm.comsystem.cpu.num_func_calls 16873932 # number of times a function call or return occured 24311754Sandreas.hansson@arm.comsystem.cpu.num_conditional_control_insts 18730256 # number of instructions that are conditional controls 24411754Sandreas.hansson@arm.comsystem.cpu.num_int_insts 153161120 # number of integer instructions 24510535Sandreas.hansson@arm.comsystem.cpu.num_fp_insts 11484 # number of float instructions 24611754Sandreas.hansson@arm.comsystem.cpu.num_int_register_reads 285043874 # number of times the integer registers were read 24711754Sandreas.hansson@arm.comsystem.cpu.num_int_register_writes 107178310 # number of times the integer registers were written 24810535Sandreas.hansson@arm.comsystem.cpu.num_fp_register_reads 8772 # number of times the floating registers were read 24910535Sandreas.hansson@arm.comsystem.cpu.num_fp_register_writes 2716 # number of times the floating registers were written 25011754Sandreas.hansson@arm.comsystem.cpu.num_cc_register_reads 530848973 # number of times the CC registers were read 25111754Sandreas.hansson@arm.comsystem.cpu.num_cc_register_writes 62363815 # number of times the CC registers were written 25211754Sandreas.hansson@arm.comsystem.cpu.num_mem_refs 55938612 # number of memory refs 25311754Sandreas.hansson@arm.comsystem.cpu.num_load_insts 31855576 # Number of load instructions 25411754Sandreas.hansson@arm.comsystem.cpu.num_store_insts 24083036 # Number of store instructions 25511754Sandreas.hansson@arm.comsystem.cpu.num_idle_cycles 5389632489.859149 # Number of idle cycles 25611754Sandreas.hansson@arm.comsystem.cpu.num_busy_cycles 178081767.140850 # Number of busy cycles 25710535Sandreas.hansson@arm.comsystem.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles 25810535Sandreas.hansson@arm.comsystem.cpu.idle_fraction 0.968015 # Percentage of idle cycles 25911754Sandreas.hansson@arm.comsystem.cpu.Branches 36396926 # Number of branches fetched 26010535Sandreas.hansson@arm.comsystem.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction 26111754Sandreas.hansson@arm.comsystem.cpu.op_class::IntAlu 121151851 68.36% 68.36% # Class of executed instruction 26211606Sandreas.sandberg@arm.comsystem.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction 26310535Sandreas.hansson@arm.comsystem.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction 26410535Sandreas.hansson@arm.comsystem.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction 26510535Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction 26610535Sandreas.hansson@arm.comsystem.cpu.op_class::FloatCvt 0 0.00% 68.43% # Class of executed instruction 26710535Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMult 0 0.00% 68.43% # Class of executed instruction 26811687Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMultAcc 0 0.00% 68.43% # Class of executed instruction 26910535Sandreas.hansson@arm.comsystem.cpu.op_class::FloatDiv 0 0.00% 68.43% # Class of executed instruction 27011687Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMisc 0 0.00% 68.43% # Class of executed instruction 27110535Sandreas.hansson@arm.comsystem.cpu.op_class::FloatSqrt 0 0.00% 68.43% # Class of executed instruction 27210535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAdd 0 0.00% 68.43% # Class of executed instruction 27310535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAddAcc 0 0.00% 68.43% # Class of executed instruction 27410535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdAlu 0 0.00% 68.43% # Class of executed instruction 27510535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCmp 0 0.00% 68.43% # Class of executed instruction 27610535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdCvt 0 0.00% 68.43% # Class of executed instruction 27710535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMisc 0 0.00% 68.43% # Class of executed instruction 27810535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMult 0 0.00% 68.43% # Class of executed instruction 27910535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdMultAcc 0 0.00% 68.43% # Class of executed instruction 28010535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShift 0 0.00% 68.43% # Class of executed instruction 28110535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdShiftAcc 0 0.00% 68.43% # Class of executed instruction 28210535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdSqrt 0 0.00% 68.43% # Class of executed instruction 28310535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAdd 0 0.00% 68.43% # Class of executed instruction 28410535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatAlu 0 0.00% 68.43% # Class of executed instruction 28510535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCmp 0 0.00% 68.43% # Class of executed instruction 28610535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatCvt 0 0.00% 68.43% # Class of executed instruction 28710535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatDiv 0 0.00% 68.43% # Class of executed instruction 28810535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Class of executed instruction 28910535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction 29010535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction 29110535Sandreas.hansson@arm.comsystem.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction 29211754Sandreas.hansson@arm.comsystem.cpu.op_class::MemRead 31852868 17.97% 86.41% # Class of executed instruction 29311754Sandreas.hansson@arm.comsystem.cpu.op_class::MemWrite 24074264 13.58% 99.99% # Class of executed instruction 29411687Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMemRead 2708 0.00% 100.00% # Class of executed instruction 29511687Sandreas.hansson@arm.comsystem.cpu.op_class::FloatMemWrite 8772 0.00% 100.00% # Class of executed instruction 29610535Sandreas.hansson@arm.comsystem.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 29710535Sandreas.hansson@arm.comsystem.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 29811754Sandreas.hansson@arm.comsystem.cpu.op_class::total 177218242 # Class of executed instruction 29911754Sandreas.hansson@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 30011754Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 819384 # number of replacements 30110535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use 30211754Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 53783890 # Total number of references to valid blocks. 30311754Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 819896 # Sample count of references to valid blocks. 30411754Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 65.598430 # Average number of references to valid blocks. 30510535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. 30610535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor 30710535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 30810535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy 30910535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 31010535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id 31110535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id 31210535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id 31310535Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 31411754Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 219235120 # Number of tag accesses 31511754Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 219235120 # Number of data accesses 31611754Sandreas.hansson@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 31711754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 30128814 # number of ReadReq hits 31811754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 30128814 # number of ReadReq hits 31911754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 22339797 # number of WriteReq hits 32011754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 22339797 # number of WriteReq hits 32111570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 395067 # number of SoftPFReq hits 32211570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 395067 # number of SoftPFReq hits 32311570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 457333 # number of LoadLockedReq hits 32411570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 457333 # number of LoadLockedReq hits 32511336Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits 32611336Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits 32711754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 52468611 # number of demand (read+write) hits 32811754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 52468611 # number of demand (read+write) hits 32911754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 52863678 # number of overall hits 33011754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 52863678 # number of overall hits 33111754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 396270 # number of ReadReq misses 33211754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 396270 # number of ReadReq misses 33311754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 301666 # number of WriteReq misses 33411754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 301666 # number of WriteReq misses 33511570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 116119 # number of SoftPFReq misses 33611570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 116119 # number of SoftPFReq misses 33711570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 # number of LoadLockedReq misses 33811570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses 33910535Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 34010535Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 34111754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 697936 # number of demand (read+write) misses 34211754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 697936 # number of demand (read+write) misses 34311754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 814055 # number of overall misses 34411754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 814055 # number of overall misses 34511754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 30525084 # number of ReadReq accesses(hits+misses) 34611754Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 30525084 # number of ReadReq accesses(hits+misses) 34711754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 22641463 # number of WriteReq accesses(hits+misses) 34811754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 22641463 # number of WriteReq accesses(hits+misses) 34911336Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses) 35011336Sandreas.hansson@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses) 35111336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses) 35211336Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses) 35311336Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses) 35411336Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses) 35511754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 53166547 # number of demand (read+write) accesses 35611754Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 53166547 # number of demand (read+write) accesses 35711754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 53677733 # number of overall (read+write) accesses 35811754Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 53677733 # number of overall (read+write) accesses 35910535Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses 36010535Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses 36111754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses 36211754Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses 36311570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227156 # miss rate for SoftPFReq accesses 36411570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.227156 # miss rate for SoftPFReq accesses 36511570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018483 # miss rate for LoadLockedReq accesses 36611570SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.018483 # miss rate for LoadLockedReq accesses 36710535Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses 36810535Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses 36911570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.013127 # miss rate for demand accesses 37011570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.013127 # miss rate for demand accesses 37110535Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.015166 # miss rate for overall accesses 37210535Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses 37310535Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 37410535Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 37510535Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 37610535Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 37710535Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 37810535Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 37911754Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 682141 # number of writebacks 38011754Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 682141 # number of writebacks 38111754Sandreas.hansson@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 38211754Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 1698986 # number of replacements 38311336Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use 38411754Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 145341611 # Total number of references to valid blocks. 38511754Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 1699498 # Sample count of references to valid blocks. 38611754Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 85.520319 # Average number of references to valid blocks. 38711570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.warmup_cycle 7831497000 # Cycle when the warmup percentage was hit. 38811336Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor 38910535Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy 39010535Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy 39110535Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 39210535Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id 39310535Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id 39410535Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id 39510535Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id 39610535Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 39711754Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 148740619 # Number of tag accesses 39811754Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 148740619 # Number of data accesses 39911754Sandreas.hansson@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 40011754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 145341611 # number of ReadReq hits 40111754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 145341611 # number of ReadReq hits 40211754Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 145341611 # number of demand (read+write) hits 40311754Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 145341611 # number of demand (read+write) hits 40411754Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 145341611 # number of overall hits 40511754Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 145341611 # number of overall hits 40611754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 1699504 # number of ReadReq misses 40711754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 1699504 # number of ReadReq misses 40811754Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 1699504 # number of demand (read+write) misses 40911754Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 1699504 # number of demand (read+write) misses 41011754Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 1699504 # number of overall misses 41111754Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 1699504 # number of overall misses 41211754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 147041115 # number of ReadReq accesses(hits+misses) 41311754Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 147041115 # number of ReadReq accesses(hits+misses) 41411754Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 147041115 # number of demand (read+write) accesses 41511754Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 147041115 # number of demand (read+write) accesses 41611754Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 147041115 # number of overall (read+write) accesses 41711754Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 147041115 # number of overall (read+write) accesses 41811336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses 41911336Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses 42011336Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses 42111336Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses 42211336Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.011558 # miss rate for overall accesses 42311336Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses 42410535Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 42510535Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 42610535Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 42710535Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 42810535Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 42910535Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 43011754Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::writebacks 1698986 # number of writebacks 43111754Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::total 1698986 # number of writebacks 43211754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 43311754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 109914 # number of replacements 43411754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 65246.862425 # Cycle average of tags in use 43511754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 4827677 # Total number of references to valid blocks. 43611754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 175340 # Sample count of references to valid blocks. 43711754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 27.533233 # Average number of references to valid blocks. 43811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.warmup_cycle 71491095000 # Cycle when the warmup percentage was hit. 43911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.971735 # Average occupied blocks per requestor 44011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.023390 # Average occupied blocks per requestor 44111754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 9170.133245 # Average occupied blocks per requestor 44211754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 56073.734054 # Average occupied blocks per requestor 44310535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy 44410535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy 44511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.139925 # Average percentage of cache occupancy 44611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.855617 # Average percentage of cache occupancy 44711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.995588 # Average percentage of cache occupancy 44810535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id 44911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 65421 # Occupied blocks per task id 45010535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id 45111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id 45211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id 45311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 9745 # Occupied blocks per task id 45411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 55480 # Occupied blocks per task id 45510535Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id 45611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.998245 # Percentage of cache occupancy per task id 45711754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 40257153 # Number of tag accesses 45811754Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 40257153 # Number of data accesses 45911754Sandreas.hansson@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 46011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 5671 # number of ReadReq hits 46111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2714 # number of ReadReq hits 46211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadReq_hits::total 8385 # number of ReadReq hits 46311754Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 682141 # number of WritebackDirty hits 46411754Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 682141 # number of WritebackDirty hits 46511754Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 1666986 # number of WritebackClean hits 46611754Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 1666986 # number of WritebackClean hits 46711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 2746 # number of UpgradeReq hits 46811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 2746 # number of UpgradeReq hits 46911754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 152792 # number of ReadExReq hits 47011754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 152792 # number of ReadExReq hits 47111754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1681189 # number of ReadCleanReq hits 47211754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 1681189 # number of ReadCleanReq hits 47311754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 505433 # number of ReadSharedReq hits 47411754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 505433 # number of ReadSharedReq hits 47511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_hits::cpu.dtb.walker 5671 # number of demand (read+write) hits 47611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_hits::cpu.itb.walker 2714 # number of demand (read+write) hits 47711754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 1681189 # number of demand (read+write) hits 47811754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 658225 # number of demand (read+write) hits 47911754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2347799 # number of demand (read+write) hits 48011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_hits::cpu.dtb.walker 5671 # number of overall hits 48111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_hits::cpu.itb.walker 2714 # number of overall hits 48211754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 1681189 # number of overall hits 48311754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 658225 # number of overall hits 48411754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2347799 # number of overall hits 48510535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses 48610535Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses 48710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 9 # number of ReadReq misses 48811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses 48911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses 49010535Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 49110535Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 49211754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 146119 # number of ReadExReq misses 49311754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 146119 # number of ReadExReq misses 49410892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 18298 # number of ReadCleanReq misses 49510892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 18298 # number of ReadCleanReq misses 49610892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 15568 # number of ReadSharedReq misses 49710892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 15568 # number of ReadSharedReq misses 49810535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses 49910535Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses 50010892Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 18298 # number of demand (read+write) misses 50111754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 161687 # number of demand (read+write) misses 50211754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 179994 # number of demand (read+write) misses 50310535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses 50410535Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses 50510892Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 18298 # number of overall misses 50611754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 161687 # number of overall misses 50711754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 179994 # number of overall misses 50811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 5678 # number of ReadReq accesses(hits+misses) 50911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2716 # number of ReadReq accesses(hits+misses) 51011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 8394 # number of ReadReq accesses(hits+misses) 51111754Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 682141 # number of WritebackDirty accesses(hits+misses) 51211754Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 682141 # number of WritebackDirty accesses(hits+misses) 51311754Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 1666986 # number of WritebackClean accesses(hits+misses) 51411754Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 1666986 # number of WritebackClean accesses(hits+misses) 51511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 2755 # number of UpgradeReq accesses(hits+misses) 51611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 2755 # number of UpgradeReq accesses(hits+misses) 51710535Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 51810535Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 51911754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 298911 # number of ReadExReq accesses(hits+misses) 52011754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 298911 # number of ReadExReq accesses(hits+misses) 52111754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1699487 # number of ReadCleanReq accesses(hits+misses) 52211754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 1699487 # number of ReadCleanReq accesses(hits+misses) 52311754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 521001 # number of ReadSharedReq accesses(hits+misses) 52411754Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 521001 # number of ReadSharedReq accesses(hits+misses) 52511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_accesses::cpu.dtb.walker 5678 # number of demand (read+write) accesses 52611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_accesses::cpu.itb.walker 2716 # number of demand (read+write) accesses 52711754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 1699487 # number of demand (read+write) accesses 52811754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 819912 # number of demand (read+write) accesses 52911754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2527793 # number of demand (read+write) accesses 53011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_accesses::cpu.dtb.walker 5678 # number of overall (read+write) accesses 53111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_accesses::cpu.itb.walker 2716 # number of overall (read+write) accesses 53211754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 1699487 # number of overall (read+write) accesses 53311754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 819912 # number of overall (read+write) accesses 53411754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2527793 # number of overall (read+write) accesses 53511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001233 # miss rate for ReadReq accesses 53611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000736 # miss rate for ReadReq accesses 53711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.001072 # miss rate for ReadReq accesses 53811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.003267 # miss rate for UpgradeReq accesses 53911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.003267 # miss rate for UpgradeReq accesses 54010535Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 54110535Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 54211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.488838 # miss rate for ReadExReq accesses 54311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.488838 # miss rate for ReadExReq accesses 54411336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010767 # miss rate for ReadCleanReq accesses 54511336Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010767 # miss rate for ReadCleanReq accesses 54611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.029881 # miss rate for ReadSharedReq accesses 54711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.029881 # miss rate for ReadSharedReq accesses 54811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001233 # miss rate for demand accesses 54911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000736 # miss rate for demand accesses 55011336Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.010767 # miss rate for demand accesses 55111754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.197200 # miss rate for demand accesses 55211754Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.071206 # miss rate for demand accesses 55311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001233 # miss rate for overall accesses 55411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000736 # miss rate for overall accesses 55511336Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.010767 # miss rate for overall accesses 55611754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.197200 # miss rate for overall accesses 55711754Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.071206 # miss rate for overall accesses 55810535Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 55910535Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 56010535Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 56110535Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 56210535Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 56310535Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 56411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.writebacks::writebacks 101949 # number of writebacks 56511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.writebacks::total 101949 # number of writebacks 56611754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 5059862 # Total number of requests made to the snoop filter. 56711754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 2540459 # Number of requests hitting in the snoop filter with a single holder of the requested data. 56811754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 39267 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 56911754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 427 # Total number of snoops made to the snoop filter. 57011754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 427 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 57111138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 57211754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 57311336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 67800 # Transaction distribution 57411754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 2288305 # Transaction distribution 57510726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution 57610726Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution 57711754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 682141 # Transaction distribution 57811754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 1698986 # Transaction distribution 57911754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 137243 # Transaction distribution 58011606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 2755 # Transaction distribution 58110535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 58211606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 2757 # Transaction distribution 58311754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 298911 # Transaction distribution 58411754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 298911 # Transaction distribution 58511754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 1699504 # Transaction distribution 58611754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 521001 # Transaction distribution 58711754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5116038 # Packet count per connected master and slave (bytes) 58811754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2581944 # Packet count per connected master and slave (bytes) 58910535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) 59011336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 36996 # Packet count per connected master and slave (bytes) 59111754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 7753408 # Packet count per connected master and slave (bytes) 59211754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 217539448 # Cumulative packet size per connected master and slave (bytes) 59311606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96314145 # Cumulative packet size per connected master and slave (bytes) 59410535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) 59511336Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 73992 # Cumulative packet size per connected master and slave (bytes) 59611754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 313964445 # Cumulative packet size per connected master and slave (bytes) 59711754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 115353 # Total snoops (count) 59811754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopTraffic 6542464 # Total snoop traffic (bytes) 59911754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 5251071 # Request fanout histogram 60011754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.018719 # Request fanout histogram 60111754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.135530 # Request fanout histogram 60210535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 60311754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 5152778 98.13% 98.13% # Request fanout histogram 60411754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 98293 1.87% 100.00% # Request fanout histogram 60511138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 60610535Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 60711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 60811138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 60911754Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 5251071 # Request fanout histogram 61011754Sandreas.hansson@arm.comsystem.iobus.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 61110726Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 30164 # Transaction distribution 61210726Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 30164 # Transaction distribution 61310726Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 59002 # Transaction distribution 61410892Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 59002 # Transaction distribution 61510726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes) 61610535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) 61711245Sandreas.sandberg@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 61810535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) 61910535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) 62010535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) 62110535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) 62210535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) 62310535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 62410535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 62510535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 62610535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) 62710535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 62810535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) 62910535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) 63010535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) 63110535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) 63210535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) 63310535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) 63410726Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 105404 # Packet count per connected master and slave (bytes) 63510535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes) 63610535Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes) 63710726Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 178332 # Packet count per connected master and slave (bytes) 63810726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67833 # Cumulative packet size per connected master and slave (bytes) 63910535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) 64011245Sandreas.sandberg@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) 64110535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) 64210535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) 64310535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) 64410535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) 64510535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) 64610535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 64710535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 64810535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 64910535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) 65010535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 65110535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 65210535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) 65310535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) 65410535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 65510535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) 65610535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) 65710726Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes) 65810535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) 65910535Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) 66010726Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) 66111754Sandreas.hansson@arm.comsystem.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 66210535Sandreas.hansson@arm.comsystem.iocache.tags.replacements 36430 # number of replacements 66311754Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 0.909895 # Cycle average of tags in use 66410535Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 66510535Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. 66610535Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 66711606Sandreas.sandberg@arm.comsystem.iocache.tags.warmup_cycle 227410176509 # Cycle when the warmup percentage was hit. 66811754Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 0.909895 # Average occupied blocks per requestor 66911336Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy 67011336Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy 67110535Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 67210535Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 67310535Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 67410535Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 328176 # Number of tag accesses 67510535Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 328176 # Number of data accesses 67611754Sandreas.hansson@arm.comsystem.iocache.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 67710535Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 240 # number of ReadReq misses 67810535Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 240 # number of ReadReq misses 67910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses 68010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses 68111456Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 36464 # number of demand (read+write) misses 68211456Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 36464 # number of demand (read+write) misses 68311456Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 36464 # number of overall misses 68411456Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 36464 # number of overall misses 68510535Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 240 # number of ReadReq accesses(hits+misses) 68610535Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 240 # number of ReadReq accesses(hits+misses) 68710892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) 68810892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) 68911456Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 36464 # number of demand (read+write) accesses 69011456Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 36464 # number of demand (read+write) accesses 69111456Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 36464 # number of overall (read+write) accesses 69211456Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 36464 # number of overall (read+write) accesses 69310535Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 69410535Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 69510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 69610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 69710535Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 69810535Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 69910535Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 70010535Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 70110535Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 70210535Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 70310535Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 70410535Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 70510535Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 70610535Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 70710585Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 36190 # number of writebacks 70810585Sandreas.hansson@arm.comsystem.iocache.writebacks::total 36190 # number of writebacks 70911754Sandreas.hansson@arm.comsystem.membus.snoop_filter.tot_requests 362813 # Total number of requests made to the snoop filter. 71011754Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_single_requests 151005 # Number of requests hitting in the snoop filter with a single holder of the requested data. 71111754Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_multi_requests 526 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 71211606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 71311606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 71411606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 71511754Sandreas.hansson@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 71610892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 40087 # Transaction distribution 71710892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 74202 # Transaction distribution 71810726Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 27546 # Transaction distribution 71910726Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 27546 # Transaction distribution 72011606Sandreas.sandberg@arm.comsystem.membus.trans_dist::WritebackDirty 138139 # Transaction distribution 72111754Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 8205 # Transaction distribution 72211606Sandreas.sandberg@arm.comsystem.membus.trans_dist::UpgradeReq 130 # Transaction distribution 72310513SAli.Saidi@ARM.comsystem.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 72411606Sandreas.sandberg@arm.comsystem.membus.trans_dist::UpgradeResp 132 # Transaction distribution 72511754Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 145998 # Transaction distribution 72611754Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 145998 # Transaction distribution 72710892Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 34115 # Transaction distribution 72810892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 36224 # Transaction distribution 72910892Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 36224 # Transaction distribution 73010726Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes) 73110517SAli.Saidi@ARM.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) 73210513SAli.Saidi@ARM.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) 73311754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 497830 # Packet count per connected master and slave (bytes) 73411754Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 605190 # Packet count per connected master and slave (bytes) 73511336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109358 # Packet count per connected master and slave (bytes) 73611336Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 109358 # Packet count per connected master and slave (bytes) 73711754Sandreas.hansson@arm.comsystem.membus.pkt_count::total 714548 # Packet count per connected master and slave (bytes) 73810726Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) 73910517SAli.Saidi@ARM.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) 74010513SAli.Saidi@ARM.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) 74111754Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18092476 # Cumulative packet size per connected master and slave (bytes) 74211754Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 18255449 # Cumulative packet size per connected master and slave (bytes) 74310892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2331520 # Cumulative packet size per connected master and slave (bytes) 74410892Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 2331520 # Cumulative packet size per connected master and slave (bytes) 74511754Sandreas.hansson@arm.comsystem.membus.pkt_size::total 20586969 # Cumulative packet size per connected master and slave (bytes) 74610409Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 74711570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 74811754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 430446 # Request fanout histogram 74911754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0.012887 # Request fanout histogram 75011754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0.112786 # Request fanout histogram 75110409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 75211754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 424899 98.71% 98.71% # Request fanout histogram 75311754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 5547 1.29% 100.00% # Request fanout histogram 75410409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 75510409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 75611606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 75710409Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 75811754Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 430446 # Request fanout histogram 75911754Sandreas.hansson@arm.comsystem.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 76011754Sandreas.hansson@arm.comsystem.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 76111754Sandreas.hansson@arm.comsystem.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 76211754Sandreas.hansson@arm.comsystem.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 76311754Sandreas.hansson@arm.comsystem.realview.gic.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 76411754Sandreas.hansson@arm.comsystem.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 76511754Sandreas.hansson@arm.comsystem.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 76611239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 76711239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 76811239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 76911239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 77011239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 77111239Sandreas.sandberg@arm.comsystem.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 77211754Sandreas.hansson@arm.comsystem.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 77311754Sandreas.hansson@arm.comsystem.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 77410513SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 77510513SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 77610513SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 77710513SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 77810513SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 77910513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 78010513SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 78110513SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 78210513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 78310513SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 78410513SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 78510513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 78610513SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 78710513SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 78810513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 78910513SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 79010513SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 79110513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 79210513SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 79310513SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 79410513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 79510513SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 79610513SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 79710513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 79810513SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 79910513SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 80010513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 80110513SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 80210513SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 80310513SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 0 # number of posts to CPU 80410513SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 80511754Sandreas.hansson@arm.comsystem.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 80611754Sandreas.hansson@arm.comsystem.realview.ide.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 80711754Sandreas.hansson@arm.comsystem.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 80811754Sandreas.hansson@arm.comsystem.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 80911754Sandreas.hansson@arm.comsystem.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 81011754Sandreas.hansson@arm.comsystem.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 81111754Sandreas.hansson@arm.comsystem.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 81211239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 81311239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 81411239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 81511239Sandreas.sandberg@arm.comsystem.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 81611754Sandreas.hansson@arm.comsystem.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 81711754Sandreas.hansson@arm.comsystem.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 81811754Sandreas.hansson@arm.comsystem.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 81911754Sandreas.hansson@arm.comsystem.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 82011754Sandreas.hansson@arm.comsystem.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 82111754Sandreas.hansson@arm.comsystem.realview.uart.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 82211754Sandreas.hansson@arm.comsystem.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 82311754Sandreas.hansson@arm.comsystem.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 82411754Sandreas.hansson@arm.comsystem.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 82511754Sandreas.hansson@arm.comsystem.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 82611754Sandreas.hansson@arm.comsystem.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 82711754Sandreas.hansson@arm.comsystem.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2783855588000 # Cumulative time (in ticks) in various power states 8287934SN/A 8297934SN/A---------- End Simulation Statistics ---------- 830