stats.txt revision 10260:384d554cea8c
1 2---------- Begin Simulation Statistics ---------- 3final_tick 1252658454500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 4host_inst_rate 126529 # Simulator instruction rate (inst/s) 5host_mem_usage 303852 # Number of bytes of host memory used 6host_op_rate 172315 # Simulator op (including micro ops) rate (op/s) 7host_seconds 10941.24 # Real time elapsed on the host 8host_tick_rate 114489637 # Simulator tick rate (ticks/s) 9sim_freq 1000000000000 # Frequency of simulated ticks 10sim_insts 1384383018 # Number of instructions simulated 11sim_ops 1885337770 # Number of ops (including micro ops) simulated 12sim_seconds 1.252658 # Number of seconds simulated 13sim_ticks 1252658454500 # Number of ticks simulated 14system.clk_domain.clock 1000 # Clock period in ticks 15system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 16system.cpu.branchPred.BTBHitPct 92.275361 # BTB Hit Percentage 17system.cpu.branchPred.BTBHits 183176705 # Number of BTB hits 18system.cpu.branchPred.BTBLookups 198510960 # Number of BTB lookups 19system.cpu.branchPred.RASInCorrect 2809 # Number of incorrect RAS predictions. 20system.cpu.branchPred.condIncorrect 27775706 # Number of conditional branches incorrect 21system.cpu.branchPred.condPredicted 271023918 # Number of conditional branches predicted 22system.cpu.branchPred.lookups 347774230 # Number of BP lookups 23system.cpu.branchPred.usedRAS 40383236 # Number of times the RAS was used to get a target. 24system.cpu.committedInsts 1384383018 # Number of instructions committed 25system.cpu.committedOps 1885337770 # Number of ops (including micro ops) committed 26system.cpu.cpi 1.809699 # CPI: cycles per instruction 27system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 9985 # number of LoadLockedReq accesses(hits+misses) 28system.cpu.dcache.LoadLockedReq_accesses::total 9985 # number of LoadLockedReq accesses(hits+misses) 29system.cpu.dcache.LoadLockedReq_hits::cpu.inst 9985 # number of LoadLockedReq hits 30system.cpu.dcache.LoadLockedReq_hits::total 9985 # number of LoadLockedReq hits 31system.cpu.dcache.ReadReq_accesses::cpu.inst 622157845 # number of ReadReq accesses(hits+misses) 32system.cpu.dcache.ReadReq_accesses::total 622157845 # number of ReadReq accesses(hits+misses) 33system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 30504.122168 # average ReadReq miss latency 34system.cpu.dcache.ReadReq_avg_miss_latency::total 30504.122168 # average ReadReq miss latency 35system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 28441.732178 # average ReadReq mshr miss latency 36system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 28441.732178 # average ReadReq mshr miss latency 37system.cpu.dcache.ReadReq_hits::cpu.inst 620694666 # number of ReadReq hits 38system.cpu.dcache.ReadReq_hits::total 620694666 # number of ReadReq hits 39system.cpu.dcache.ReadReq_miss_latency::cpu.inst 44632990969 # number of ReadReq miss cycles 40system.cpu.dcache.ReadReq_miss_latency::total 44632990969 # number of ReadReq miss cycles 41system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.002352 # miss rate for ReadReq accesses 42system.cpu.dcache.ReadReq_miss_rate::total 0.002352 # miss rate for ReadReq accesses 43system.cpu.dcache.ReadReq_misses::cpu.inst 1463179 # number of ReadReq misses 44system.cpu.dcache.ReadReq_misses::total 1463179 # number of ReadReq misses 45system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 1721 # number of ReadReq MSHR hits 46system.cpu.dcache.ReadReq_mshr_hits::total 1721 # number of ReadReq MSHR hits 47system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 41566397026 # number of ReadReq MSHR miss cycles 48system.cpu.dcache.ReadReq_mshr_miss_latency::total 41566397026 # number of ReadReq MSHR miss cycles 49system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.002349 # mshr miss rate for ReadReq accesses 50system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002349 # mshr miss rate for ReadReq accesses 51system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1461458 # number of ReadReq MSHR misses 52system.cpu.dcache.ReadReq_mshr_misses::total 1461458 # number of ReadReq MSHR misses 53system.cpu.dcache.StoreCondReq_accesses::cpu.inst 9985 # number of StoreCondReq accesses(hits+misses) 54system.cpu.dcache.StoreCondReq_accesses::total 9985 # number of StoreCondReq accesses(hits+misses) 55system.cpu.dcache.StoreCondReq_hits::cpu.inst 9985 # number of StoreCondReq hits 56system.cpu.dcache.StoreCondReq_hits::total 9985 # number of StoreCondReq hits 57system.cpu.dcache.WriteReq_accesses::cpu.inst 276935678 # number of WriteReq accesses(hits+misses) 58system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) 59system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 64418.412606 # average WriteReq miss latency 60system.cpu.dcache.WriteReq_avg_miss_latency::total 64418.412606 # average WriteReq miss latency 61system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 62661.295309 # average WriteReq mshr miss latency 62system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62661.295309 # average WriteReq mshr miss latency 63system.cpu.dcache.WriteReq_hits::cpu.inst 276792059 # number of WriteReq hits 64system.cpu.dcache.WriteReq_hits::total 276792059 # number of WriteReq hits 65system.cpu.dcache.WriteReq_miss_latency::cpu.inst 9251708000 # number of WriteReq miss cycles 66system.cpu.dcache.WriteReq_miss_latency::total 9251708000 # number of WriteReq miss cycles 67system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.000519 # miss rate for WriteReq accesses 68system.cpu.dcache.WriteReq_miss_rate::total 0.000519 # miss rate for WriteReq accesses 69system.cpu.dcache.WriteReq_misses::cpu.inst 143619 # number of WriteReq misses 70system.cpu.dcache.WriteReq_misses::total 143619 # number of WriteReq misses 71system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 70841 # number of WriteReq MSHR hits 72system.cpu.dcache.WriteReq_mshr_hits::total 70841 # number of WriteReq MSHR hits 73system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 4560363750 # number of WriteReq MSHR miss cycles 74system.cpu.dcache.WriteReq_mshr_miss_latency::total 4560363750 # number of WriteReq MSHR miss cycles 75system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.000263 # mshr miss rate for WriteReq accesses 76system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000263 # mshr miss rate for WriteReq accesses 77system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 72778 # number of WriteReq MSHR misses 78system.cpu.dcache.WriteReq_mshr_misses::total 72778 # number of WriteReq MSHR misses 79system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 80system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 81system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 82system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 83system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 84system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 85system.cpu.dcache.cache_copies 0 # number of cache copies performed 86system.cpu.dcache.demand_accesses::cpu.inst 899093523 # number of demand (read+write) accesses 87system.cpu.dcache.demand_accesses::total 899093523 # number of demand (read+write) accesses 88system.cpu.dcache.demand_avg_miss_latency::cpu.inst 33535.453099 # average overall miss latency 89system.cpu.dcache.demand_avg_miss_latency::total 33535.453099 # average overall miss latency 90system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 30064.970954 # average overall mshr miss latency 91system.cpu.dcache.demand_avg_mshr_miss_latency::total 30064.970954 # average overall mshr miss latency 92system.cpu.dcache.demand_hits::cpu.inst 897486725 # number of demand (read+write) hits 93system.cpu.dcache.demand_hits::total 897486725 # number of demand (read+write) hits 94system.cpu.dcache.demand_miss_latency::cpu.inst 53884698969 # number of demand (read+write) miss cycles 95system.cpu.dcache.demand_miss_latency::total 53884698969 # number of demand (read+write) miss cycles 96system.cpu.dcache.demand_miss_rate::cpu.inst 0.001787 # miss rate for demand accesses 97system.cpu.dcache.demand_miss_rate::total 0.001787 # miss rate for demand accesses 98system.cpu.dcache.demand_misses::cpu.inst 1606798 # number of demand (read+write) misses 99system.cpu.dcache.demand_misses::total 1606798 # number of demand (read+write) misses 100system.cpu.dcache.demand_mshr_hits::cpu.inst 72562 # number of demand (read+write) MSHR hits 101system.cpu.dcache.demand_mshr_hits::total 72562 # number of demand (read+write) MSHR hits 102system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 46126760776 # number of demand (read+write) MSHR miss cycles 103system.cpu.dcache.demand_mshr_miss_latency::total 46126760776 # number of demand (read+write) MSHR miss cycles 104system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.001706 # mshr miss rate for demand accesses 105system.cpu.dcache.demand_mshr_miss_rate::total 0.001706 # mshr miss rate for demand accesses 106system.cpu.dcache.demand_mshr_misses::cpu.inst 1534236 # number of demand (read+write) MSHR misses 107system.cpu.dcache.demand_mshr_misses::total 1534236 # number of demand (read+write) MSHR misses 108system.cpu.dcache.fast_writes 0 # number of fast writes performed 109system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 110system.cpu.dcache.overall_accesses::cpu.inst 899093523 # number of overall (read+write) accesses 111system.cpu.dcache.overall_accesses::total 899093523 # number of overall (read+write) accesses 112system.cpu.dcache.overall_avg_miss_latency::cpu.inst 33535.453099 # average overall miss latency 113system.cpu.dcache.overall_avg_miss_latency::total 33535.453099 # average overall miss latency 114system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 30064.970954 # average overall mshr miss latency 115system.cpu.dcache.overall_avg_mshr_miss_latency::total 30064.970954 # average overall mshr miss latency 116system.cpu.dcache.overall_hits::cpu.inst 897486725 # number of overall hits 117system.cpu.dcache.overall_hits::total 897486725 # number of overall hits 118system.cpu.dcache.overall_miss_latency::cpu.inst 53884698969 # number of overall miss cycles 119system.cpu.dcache.overall_miss_latency::total 53884698969 # number of overall miss cycles 120system.cpu.dcache.overall_miss_rate::cpu.inst 0.001787 # miss rate for overall accesses 121system.cpu.dcache.overall_miss_rate::total 0.001787 # miss rate for overall accesses 122system.cpu.dcache.overall_misses::cpu.inst 1606798 # number of overall misses 123system.cpu.dcache.overall_misses::total 1606798 # number of overall misses 124system.cpu.dcache.overall_mshr_hits::cpu.inst 72562 # number of overall MSHR hits 125system.cpu.dcache.overall_mshr_hits::total 72562 # number of overall MSHR hits 126system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 46126760776 # number of overall MSHR miss cycles 127system.cpu.dcache.overall_mshr_miss_latency::total 46126760776 # number of overall MSHR miss cycles 128system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.001706 # mshr miss rate for overall accesses 129system.cpu.dcache.overall_mshr_miss_rate::total 0.001706 # mshr miss rate for overall accesses 130system.cpu.dcache.overall_mshr_misses::cpu.inst 1534236 # number of overall MSHR misses 131system.cpu.dcache.overall_mshr_misses::total 1534236 # number of overall MSHR misses 132system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id 133system.cpu.dcache.tags.age_task_id_blocks_1024::1 160 # Occupied blocks per task id 134system.cpu.dcache.tags.age_task_id_blocks_1024::2 964 # Occupied blocks per task id 135system.cpu.dcache.tags.age_task_id_blocks_1024::3 1240 # Occupied blocks per task id 136system.cpu.dcache.tags.age_task_id_blocks_1024::4 1699 # Occupied blocks per task id 137system.cpu.dcache.tags.avg_refs 584.986075 # Average number of references to valid blocks. 138system.cpu.dcache.tags.data_accesses 1799761222 # Number of data accesses 139system.cpu.dcache.tags.occ_blocks::cpu.inst 4094.531713 # Average occupied blocks per requestor 140system.cpu.dcache.tags.occ_percent::cpu.inst 0.999642 # Average percentage of cache occupancy 141system.cpu.dcache.tags.occ_percent::total 0.999642 # Average percentage of cache occupancy 142system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 143system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 144system.cpu.dcache.tags.replacements 1530140 # number of replacements 145system.cpu.dcache.tags.sampled_refs 1534236 # Sample count of references to valid blocks. 146system.cpu.dcache.tags.tag_accesses 1799761222 # Number of tag accesses 147system.cpu.dcache.tags.tagsinuse 4094.531713 # Cycle average of tags in use 148system.cpu.dcache.tags.total_refs 897506695 # Total number of references to valid blocks. 149system.cpu.dcache.tags.warmup_cycle 756574250 # Cycle when the warmup percentage was hit. 150system.cpu.dcache.writebacks::writebacks 96100 # number of writebacks 151system.cpu.dcache.writebacks::total 96100 # number of writebacks 152system.cpu.discardedOps 58655042 # Number of ops (including micro ops) which were discarded before commit 153system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 154system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 155system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 156system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 157system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 158system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 159system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 160system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 161system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 162system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 163system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 164system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 165system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 166system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 167system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 168system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 169system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 170system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 171system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 172system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 173system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 174system.cpu.dtb.accesses 0 # DTB accesses 175system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 176system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 177system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 178system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 179system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 180system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 181system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 182system.cpu.dtb.hits 0 # DTB hits 183system.cpu.dtb.inst_accesses 0 # ITB inst accesses 184system.cpu.dtb.inst_hits 0 # ITB inst hits 185system.cpu.dtb.inst_misses 0 # ITB inst misses 186system.cpu.dtb.misses 0 # DTB misses 187system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 188system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 189system.cpu.dtb.read_accesses 0 # DTB read accesses 190system.cpu.dtb.read_hits 0 # DTB read hits 191system.cpu.dtb.read_misses 0 # DTB read misses 192system.cpu.dtb.write_accesses 0 # DTB write accesses 193system.cpu.dtb.write_hits 0 # DTB write hits 194system.cpu.dtb.write_misses 0 # DTB write misses 195system.cpu.icache.ReadReq_accesses::cpu.inst 655834828 # number of ReadReq accesses(hits+misses) 196system.cpu.icache.ReadReq_accesses::total 655834828 # number of ReadReq accesses(hits+misses) 197system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15794.863845 # average ReadReq miss latency 198system.cpu.icache.ReadReq_avg_miss_latency::total 15794.863845 # average ReadReq miss latency 199system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13774.677486 # average ReadReq mshr miss latency 200system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13774.677486 # average ReadReq mshr miss latency 201system.cpu.icache.ReadReq_hits::cpu.inst 655779494 # number of ReadReq hits 202system.cpu.icache.ReadReq_hits::total 655779494 # number of ReadReq hits 203system.cpu.icache.ReadReq_miss_latency::cpu.inst 873992996 # number of ReadReq miss cycles 204system.cpu.icache.ReadReq_miss_latency::total 873992996 # number of ReadReq miss cycles 205system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000084 # miss rate for ReadReq accesses 206system.cpu.icache.ReadReq_miss_rate::total 0.000084 # miss rate for ReadReq accesses 207system.cpu.icache.ReadReq_misses::cpu.inst 55334 # number of ReadReq misses 208system.cpu.icache.ReadReq_misses::total 55334 # number of ReadReq misses 209system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 762208004 # number of ReadReq MSHR miss cycles 210system.cpu.icache.ReadReq_mshr_miss_latency::total 762208004 # number of ReadReq MSHR miss cycles 211system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for ReadReq accesses 212system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000084 # mshr miss rate for ReadReq accesses 213system.cpu.icache.ReadReq_mshr_misses::cpu.inst 55334 # number of ReadReq MSHR misses 214system.cpu.icache.ReadReq_mshr_misses::total 55334 # number of ReadReq MSHR misses 215system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 216system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 217system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 218system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 219system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 220system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 221system.cpu.icache.cache_copies 0 # number of cache copies performed 222system.cpu.icache.demand_accesses::cpu.inst 655834828 # number of demand (read+write) accesses 223system.cpu.icache.demand_accesses::total 655834828 # number of demand (read+write) accesses 224system.cpu.icache.demand_avg_miss_latency::cpu.inst 15794.863845 # average overall miss latency 225system.cpu.icache.demand_avg_miss_latency::total 15794.863845 # average overall miss latency 226system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13774.677486 # average overall mshr miss latency 227system.cpu.icache.demand_avg_mshr_miss_latency::total 13774.677486 # average overall mshr miss latency 228system.cpu.icache.demand_hits::cpu.inst 655779494 # number of demand (read+write) hits 229system.cpu.icache.demand_hits::total 655779494 # number of demand (read+write) hits 230system.cpu.icache.demand_miss_latency::cpu.inst 873992996 # number of demand (read+write) miss cycles 231system.cpu.icache.demand_miss_latency::total 873992996 # number of demand (read+write) miss cycles 232system.cpu.icache.demand_miss_rate::cpu.inst 0.000084 # miss rate for demand accesses 233system.cpu.icache.demand_miss_rate::total 0.000084 # miss rate for demand accesses 234system.cpu.icache.demand_misses::cpu.inst 55334 # number of demand (read+write) misses 235system.cpu.icache.demand_misses::total 55334 # number of demand (read+write) misses 236system.cpu.icache.demand_mshr_miss_latency::cpu.inst 762208004 # number of demand (read+write) MSHR miss cycles 237system.cpu.icache.demand_mshr_miss_latency::total 762208004 # number of demand (read+write) MSHR miss cycles 238system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for demand accesses 239system.cpu.icache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses 240system.cpu.icache.demand_mshr_misses::cpu.inst 55334 # number of demand (read+write) MSHR misses 241system.cpu.icache.demand_mshr_misses::total 55334 # number of demand (read+write) MSHR misses 242system.cpu.icache.fast_writes 0 # number of fast writes performed 243system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 244system.cpu.icache.overall_accesses::cpu.inst 655834828 # number of overall (read+write) accesses 245system.cpu.icache.overall_accesses::total 655834828 # number of overall (read+write) accesses 246system.cpu.icache.overall_avg_miss_latency::cpu.inst 15794.863845 # average overall miss latency 247system.cpu.icache.overall_avg_miss_latency::total 15794.863845 # average overall miss latency 248system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13774.677486 # average overall mshr miss latency 249system.cpu.icache.overall_avg_mshr_miss_latency::total 13774.677486 # average overall mshr miss latency 250system.cpu.icache.overall_hits::cpu.inst 655779494 # number of overall hits 251system.cpu.icache.overall_hits::total 655779494 # number of overall hits 252system.cpu.icache.overall_miss_latency::cpu.inst 873992996 # number of overall miss cycles 253system.cpu.icache.overall_miss_latency::total 873992996 # number of overall miss cycles 254system.cpu.icache.overall_miss_rate::cpu.inst 0.000084 # miss rate for overall accesses 255system.cpu.icache.overall_miss_rate::total 0.000084 # miss rate for overall accesses 256system.cpu.icache.overall_misses::cpu.inst 55334 # number of overall misses 257system.cpu.icache.overall_misses::total 55334 # number of overall misses 258system.cpu.icache.overall_mshr_miss_latency::cpu.inst 762208004 # number of overall MSHR miss cycles 259system.cpu.icache.overall_mshr_miss_latency::total 762208004 # number of overall MSHR miss cycles 260system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000084 # mshr miss rate for overall accesses 261system.cpu.icache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses 262system.cpu.icache.overall_mshr_misses::cpu.inst 55334 # number of overall MSHR misses 263system.cpu.icache.overall_mshr_misses::total 55334 # number of overall MSHR misses 264system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 265system.cpu.icache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id 266system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 267system.cpu.icache.tags.age_task_id_blocks_1024::4 1615 # Occupied blocks per task id 268system.cpu.icache.tags.avg_refs 11851.508033 # Average number of references to valid blocks. 269system.cpu.icache.tags.data_accesses 1311724989 # Number of data accesses 270system.cpu.icache.tags.occ_blocks::cpu.inst 1727.262157 # Average occupied blocks per requestor 271system.cpu.icache.tags.occ_percent::cpu.inst 0.843390 # Average percentage of cache occupancy 272system.cpu.icache.tags.occ_percent::total 0.843390 # Average percentage of cache occupancy 273system.cpu.icache.tags.occ_task_id_blocks::1024 1765 # Occupied blocks per task id 274system.cpu.icache.tags.occ_task_id_percent::1024 0.861816 # Percentage of cache occupancy per task id 275system.cpu.icache.tags.replacements 53568 # number of replacements 276system.cpu.icache.tags.sampled_refs 55333 # Sample count of references to valid blocks. 277system.cpu.icache.tags.tag_accesses 1311724989 # Number of tag accesses 278system.cpu.icache.tags.tagsinuse 1727.262157 # Cycle average of tags in use 279system.cpu.icache.tags.total_refs 655779494 # Total number of references to valid blocks. 280system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 281system.cpu.idleCycles 103571975 # Total number of cycles that the CPU has spent unscheduled due to idling 282system.cpu.ipc 0.552578 # IPC: instructions per cycle 283system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 284system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 285system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 286system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 287system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 288system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 289system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 290system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 291system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 292system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 293system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 294system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 295system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 296system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 297system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 298system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 299system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 300system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 301system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 302system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 303system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 304system.cpu.itb.accesses 0 # DTB accesses 305system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 306system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 307system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 308system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 309system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 310system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 311system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 312system.cpu.itb.hits 0 # DTB hits 313system.cpu.itb.inst_accesses 0 # ITB inst accesses 314system.cpu.itb.inst_hits 0 # ITB inst hits 315system.cpu.itb.inst_misses 0 # ITB inst misses 316system.cpu.itb.misses 0 # DTB misses 317system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 318system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 319system.cpu.itb.read_accesses 0 # DTB read accesses 320system.cpu.itb.read_hits 0 # DTB read hits 321system.cpu.itb.read_misses 0 # DTB read misses 322system.cpu.itb.write_accesses 0 # DTB write accesses 323system.cpu.itb.write_hits 0 # DTB write hits 324system.cpu.itb.write_misses 0 # DTB write misses 325system.cpu.l2cache.ReadExReq_accesses::cpu.inst 72778 # number of ReadExReq accesses(hits+misses) 326system.cpu.l2cache.ReadExReq_accesses::total 72778 # number of ReadExReq accesses(hits+misses) 327system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 66889.147375 # average ReadExReq miss latency 328system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66889.147375 # average ReadExReq miss latency 329system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 54354.270691 # average ReadExReq mshr miss latency 330system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54354.270691 # average ReadExReq mshr miss latency 331system.cpu.l2cache.ReadExReq_hits::cpu.inst 6688 # number of ReadExReq hits 332system.cpu.l2cache.ReadExReq_hits::total 6688 # number of ReadExReq hits 333system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 4420703750 # number of ReadExReq miss cycles 334system.cpu.l2cache.ReadExReq_miss_latency::total 4420703750 # number of ReadExReq miss cycles 335system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.908104 # miss rate for ReadExReq accesses 336system.cpu.l2cache.ReadExReq_miss_rate::total 0.908104 # miss rate for ReadExReq accesses 337system.cpu.l2cache.ReadExReq_misses::cpu.inst 66090 # number of ReadExReq misses 338system.cpu.l2cache.ReadExReq_misses::total 66090 # number of ReadExReq misses 339system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 3592273750 # number of ReadExReq MSHR miss cycles 340system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3592273750 # number of ReadExReq MSHR miss cycles 341system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.908104 # mshr miss rate for ReadExReq accesses 342system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.908104 # mshr miss rate for ReadExReq accesses 343system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 66090 # number of ReadExReq MSHR misses 344system.cpu.l2cache.ReadExReq_mshr_misses::total 66090 # number of ReadExReq MSHR misses 345system.cpu.l2cache.ReadReq_accesses::cpu.inst 1516792 # number of ReadReq accesses(hits+misses) 346system.cpu.l2cache.ReadReq_accesses::total 1516792 # number of ReadReq accesses(hits+misses) 347system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72703.861690 # average ReadReq miss latency 348system.cpu.l2cache.ReadReq_avg_miss_latency::total 72703.861690 # average ReadReq miss latency 349system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60134.219047 # average ReadReq mshr miss latency 350system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60134.219047 # average ReadReq mshr miss latency 351system.cpu.l2cache.ReadReq_hits::cpu.inst 1107826 # number of ReadReq hits 352system.cpu.l2cache.ReadReq_hits::total 1107826 # number of ReadReq hits 353system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 29733407500 # number of ReadReq miss cycles 354system.cpu.l2cache.ReadReq_miss_latency::total 29733407500 # number of ReadReq miss cycles 355system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.269626 # miss rate for ReadReq accesses 356system.cpu.l2cache.ReadReq_miss_rate::total 0.269626 # miss rate for ReadReq accesses 357system.cpu.l2cache.ReadReq_misses::cpu.inst 408966 # number of ReadReq misses 358system.cpu.l2cache.ReadReq_misses::total 408966 # number of ReadReq misses 359system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 30 # number of ReadReq MSHR hits 360system.cpu.l2cache.ReadReq_mshr_hits::total 30 # number of ReadReq MSHR hits 361system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24591047000 # number of ReadReq MSHR miss cycles 362system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24591047000 # number of ReadReq MSHR miss cycles 363system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.269606 # mshr miss rate for ReadReq accesses 364system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.269606 # mshr miss rate for ReadReq accesses 365system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 408936 # number of ReadReq MSHR misses 366system.cpu.l2cache.ReadReq_mshr_misses::total 408936 # number of ReadReq MSHR misses 367system.cpu.l2cache.Writeback_accesses::writebacks 96100 # number of Writeback accesses(hits+misses) 368system.cpu.l2cache.Writeback_accesses::total 96100 # number of Writeback accesses(hits+misses) 369system.cpu.l2cache.Writeback_hits::writebacks 96100 # number of Writeback hits 370system.cpu.l2cache.Writeback_hits::total 96100 # number of Writeback hits 371system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 372system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 373system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 374system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 375system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 376system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 377system.cpu.l2cache.cache_copies 0 # number of cache copies performed 378system.cpu.l2cache.demand_accesses::cpu.inst 1589570 # number of demand (read+write) accesses 379system.cpu.l2cache.demand_accesses::total 1589570 # number of demand (read+write) accesses 380system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71894.916073 # average overall miss latency 381system.cpu.l2cache.demand_avg_miss_latency::total 71894.916073 # average overall miss latency 382system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59330.059302 # average overall mshr miss latency 383system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59330.059302 # average overall mshr miss latency 384system.cpu.l2cache.demand_hits::cpu.inst 1114514 # number of demand (read+write) hits 385system.cpu.l2cache.demand_hits::total 1114514 # number of demand (read+write) hits 386system.cpu.l2cache.demand_miss_latency::cpu.inst 34154111250 # number of demand (read+write) miss cycles 387system.cpu.l2cache.demand_miss_latency::total 34154111250 # number of demand (read+write) miss cycles 388system.cpu.l2cache.demand_miss_rate::cpu.inst 0.298858 # miss rate for demand accesses 389system.cpu.l2cache.demand_miss_rate::total 0.298858 # miss rate for demand accesses 390system.cpu.l2cache.demand_misses::cpu.inst 475056 # number of demand (read+write) misses 391system.cpu.l2cache.demand_misses::total 475056 # number of demand (read+write) misses 392system.cpu.l2cache.demand_mshr_hits::cpu.inst 30 # number of demand (read+write) MSHR hits 393system.cpu.l2cache.demand_mshr_hits::total 30 # number of demand (read+write) MSHR hits 394system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28183320750 # number of demand (read+write) MSHR miss cycles 395system.cpu.l2cache.demand_mshr_miss_latency::total 28183320750 # number of demand (read+write) MSHR miss cycles 396system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.298839 # mshr miss rate for demand accesses 397system.cpu.l2cache.demand_mshr_miss_rate::total 0.298839 # mshr miss rate for demand accesses 398system.cpu.l2cache.demand_mshr_misses::cpu.inst 475026 # number of demand (read+write) MSHR misses 399system.cpu.l2cache.demand_mshr_misses::total 475026 # number of demand (read+write) MSHR misses 400system.cpu.l2cache.fast_writes 0 # number of fast writes performed 401system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 402system.cpu.l2cache.overall_accesses::cpu.inst 1589570 # number of overall (read+write) accesses 403system.cpu.l2cache.overall_accesses::total 1589570 # number of overall (read+write) accesses 404system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71894.916073 # average overall miss latency 405system.cpu.l2cache.overall_avg_miss_latency::total 71894.916073 # average overall miss latency 406system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59330.059302 # average overall mshr miss latency 407system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59330.059302 # average overall mshr miss latency 408system.cpu.l2cache.overall_hits::cpu.inst 1114514 # number of overall hits 409system.cpu.l2cache.overall_hits::total 1114514 # number of overall hits 410system.cpu.l2cache.overall_miss_latency::cpu.inst 34154111250 # number of overall miss cycles 411system.cpu.l2cache.overall_miss_latency::total 34154111250 # number of overall miss cycles 412system.cpu.l2cache.overall_miss_rate::cpu.inst 0.298858 # miss rate for overall accesses 413system.cpu.l2cache.overall_miss_rate::total 0.298858 # miss rate for overall accesses 414system.cpu.l2cache.overall_misses::cpu.inst 475056 # number of overall misses 415system.cpu.l2cache.overall_misses::total 475056 # number of overall misses 416system.cpu.l2cache.overall_mshr_hits::cpu.inst 30 # number of overall MSHR hits 417system.cpu.l2cache.overall_mshr_hits::total 30 # number of overall MSHR hits 418system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28183320750 # number of overall MSHR miss cycles 419system.cpu.l2cache.overall_mshr_miss_latency::total 28183320750 # number of overall MSHR miss cycles 420system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.298839 # mshr miss rate for overall accesses 421system.cpu.l2cache.overall_mshr_miss_rate::total 0.298839 # mshr miss rate for overall accesses 422system.cpu.l2cache.overall_mshr_misses::cpu.inst 475026 # number of overall MSHR misses 423system.cpu.l2cache.overall_mshr_misses::total 475026 # number of overall MSHR misses 424system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id 425system.cpu.l2cache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id 426system.cpu.l2cache.tags.age_task_id_blocks_1024::2 268 # Occupied blocks per task id 427system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2580 # Occupied blocks per task id 428system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29670 # Occupied blocks per task id 429system.cpu.l2cache.tags.avg_refs 2.395162 # Average number of references to valid blocks. 430system.cpu.l2cache.tags.data_accesses 14033128 # Number of data accesses 431system.cpu.l2cache.tags.occ_blocks::writebacks 1330.818076 # Average occupied blocks per requestor 432system.cpu.l2cache.tags.occ_blocks::cpu.inst 31344.832788 # Average occupied blocks per requestor 433system.cpu.l2cache.tags.occ_percent::writebacks 0.040613 # Average percentage of cache occupancy 434system.cpu.l2cache.tags.occ_percent::cpu.inst 0.956568 # Average percentage of cache occupancy 435system.cpu.l2cache.tags.occ_percent::total 0.997182 # Average percentage of cache occupancy 436system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id 437system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id 438system.cpu.l2cache.tags.replacements 442246 # number of replacements 439system.cpu.l2cache.tags.sampled_refs 474990 # Sample count of references to valid blocks. 440system.cpu.l2cache.tags.tag_accesses 14033128 # Number of tag accesses 441system.cpu.l2cache.tags.tagsinuse 32675.650864 # Cycle average of tags in use 442system.cpu.l2cache.tags.total_refs 1137678 # Total number of references to valid blocks. 443system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 444system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks 445system.cpu.l2cache.writebacks::total 66099 # number of writebacks 446system.cpu.numCycles 2505316909 # number of cpu cycles simulated 447system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 448system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 449system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 450system.cpu.tickCycles 2401744934 # Number of cycles that the CPU actually ticked 451system.cpu.toL2Bus.data_through_bus 107882816 # Total data (bytes) 452system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 110667 # Packet count per connected master and slave (bytes) 453system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3164572 # Packet count per connected master and slave (bytes) 454system.cpu.toL2Bus.pkt_count::total 3275239 # Packet count per connected master and slave (bytes) 455system.cpu.toL2Bus.reqLayer0.occupancy 938935000 # Layer occupancy (ticks) 456system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 457system.cpu.toL2Bus.respLayer0.occupancy 83558996 # Layer occupancy (ticks) 458system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 459system.cpu.toL2Bus.respLayer1.occupancy 2375968224 # Layer occupancy (ticks) 460system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 461system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 462system.cpu.toL2Bus.throughput 86123089 # Throughput (bytes/s) 463system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3541312 # Cumulative packet size per connected master and slave (bytes) 464system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 104341504 # Cumulative packet size per connected master and slave (bytes) 465system.cpu.toL2Bus.tot_pkt_size::total 107882816 # Cumulative packet size per connected master and slave (bytes) 466system.cpu.toL2Bus.trans_dist::ReadReq 1516792 # Transaction distribution 467system.cpu.toL2Bus.trans_dist::ReadResp 1516791 # Transaction distribution 468system.cpu.toL2Bus.trans_dist::Writeback 96100 # Transaction distribution 469system.cpu.toL2Bus.trans_dist::ReadExReq 72778 # Transaction distribution 470system.cpu.toL2Bus.trans_dist::ReadExResp 72778 # Transaction distribution 471system.cpu.workload.num_syscalls 1411 # Number of system calls 472system.cpu_clk_domain.clock 500 # Clock period in ticks 473system.membus.data_through_bus 34631936 # Total data (bytes) 474system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1016149 # Packet count per connected master and slave (bytes) 475system.membus.pkt_count::total 1016149 # Packet count per connected master and slave (bytes) 476system.membus.reqLayer0.occupancy 1205459500 # Layer occupancy (ticks) 477system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 478system.membus.respLayer1.occupancy 4468586250 # Layer occupancy (ticks) 479system.membus.respLayer1.utilization 0.4 # Layer utilization (%) 480system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 481system.membus.throughput 27646751 # Throughput (bytes/s) 482system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 34631936 # Cumulative packet size per connected master and slave (bytes) 483system.membus.tot_pkt_size::total 34631936 # Cumulative packet size per connected master and slave (bytes) 484system.membus.trans_dist::ReadReq 408935 # Transaction distribution 485system.membus.trans_dist::ReadResp 408935 # Transaction distribution 486system.membus.trans_dist::Writeback 66099 # Transaction distribution 487system.membus.trans_dist::ReadExReq 66090 # Transaction distribution 488system.membus.trans_dist::ReadExResp 66090 # Transaction distribution 489system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 490system.physmem.avgGap 2314919.25 # Average gap between requests 491system.physmem.avgMemAccLat 29362.18 # Average memory access latency per DRAM burst 492system.physmem.avgQLat 10612.18 # Average queueing delay per DRAM burst 493system.physmem.avgRdBW 24.25 # Average DRAM read bandwidth in MiByte/s 494system.physmem.avgRdBWSys 24.27 # Average system read bandwidth in MiByte/s 495system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 496system.physmem.avgWrBW 3.38 # Average achieved write bandwidth in MiByte/s 497system.physmem.avgWrBWSys 3.38 # Average system write bandwidth in MiByte/s 498system.physmem.avgWrQLen 26.46 # Average write queue length when enqueuing 499system.physmem.busUtil 0.22 # Data bus utilization in percentage 500system.physmem.busUtilRead 0.19 # Data bus utilization in percentage for reads 501system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes 502system.physmem.bw_inst_read::cpu.inst 133348 # Instruction read bandwidth from this memory (bytes/s) 503system.physmem.bw_inst_read::total 133348 # Instruction read bandwidth from this memory (bytes/s) 504system.physmem.bw_read::cpu.inst 24269664 # Total read bandwidth from this memory (bytes/s) 505system.physmem.bw_read::total 24269664 # Total read bandwidth from this memory (bytes/s) 506system.physmem.bw_total::writebacks 3377087 # Total bandwidth to/from this memory (bytes/s) 507system.physmem.bw_total::cpu.inst 24269664 # Total bandwidth to/from this memory (bytes/s) 508system.physmem.bw_total::total 27646751 # Total bandwidth to/from this memory (bytes/s) 509system.physmem.bw_write::writebacks 3377087 # Write bandwidth from this memory (bytes/s) 510system.physmem.bw_write::total 3377087 # Write bandwidth from this memory (bytes/s) 511system.physmem.bytesPerActivate::samples 204371 # Bytes accessed per row activation 512system.physmem.bytesPerActivate::mean 169.307779 # Bytes accessed per row activation 513system.physmem.bytesPerActivate::gmean 122.893449 # Bytes accessed per row activation 514system.physmem.bytesPerActivate::stdev 197.869772 # Bytes accessed per row activation 515system.physmem.bytesPerActivate::0-127 84097 41.15% 41.15% # Bytes accessed per row activation 516system.physmem.bytesPerActivate::128-255 91184 44.62% 85.77% # Bytes accessed per row activation 517system.physmem.bytesPerActivate::256-383 16888 8.26% 94.03% # Bytes accessed per row activation 518system.physmem.bytesPerActivate::384-511 803 0.39% 94.42% # Bytes accessed per row activation 519system.physmem.bytesPerActivate::512-639 1089 0.53% 94.96% # Bytes accessed per row activation 520system.physmem.bytesPerActivate::640-767 1331 0.65% 95.61% # Bytes accessed per row activation 521system.physmem.bytesPerActivate::768-895 576 0.28% 95.89% # Bytes accessed per row activation 522system.physmem.bytesPerActivate::896-1023 520 0.25% 96.14% # Bytes accessed per row activation 523system.physmem.bytesPerActivate::1024-1151 7883 3.86% 100.00% # Bytes accessed per row activation 524system.physmem.bytesPerActivate::total 204371 # Bytes accessed per row activation 525system.physmem.bytesReadDRAM 30374976 # Total number of bytes read from DRAM 526system.physmem.bytesReadSys 30401600 # Total read bytes from the system interface side 527system.physmem.bytesReadWrQ 26624 # Total number of bytes read from write queue 528system.physmem.bytesWritten 4228608 # Total number of bytes written to DRAM 529system.physmem.bytesWrittenSys 4230336 # Total written bytes from the system interface side 530system.physmem.bytes_inst_read::cpu.inst 167040 # Number of instructions bytes read from this memory 531system.physmem.bytes_inst_read::total 167040 # Number of instructions bytes read from this memory 532system.physmem.bytes_read::cpu.inst 30401600 # Number of bytes read from this memory 533system.physmem.bytes_read::total 30401600 # Number of bytes read from this memory 534system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory 535system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory 536system.physmem.memoryStateTime::IDLE 639262116250 # Time in different power states 537system.physmem.memoryStateTime::REF 41828800000 # Time in different power states 538system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 539system.physmem.memoryStateTime::ACT 571561257500 # Time in different power states 540system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 541system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 542system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 543system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 544system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 545system.physmem.num_reads::cpu.inst 475025 # Number of read requests responded to by this memory 546system.physmem.num_reads::total 475025 # Number of read requests responded to by this memory 547system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory 548system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory 549system.physmem.pageHitRate 62.20 # Row buffer hit rate, read and write combined 550system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 551system.physmem.perBankRdBursts::0 29837 # Per bank write bursts 552system.physmem.perBankRdBursts::1 29647 # Per bank write bursts 553system.physmem.perBankRdBursts::2 29757 # Per bank write bursts 554system.physmem.perBankRdBursts::3 29702 # Per bank write bursts 555system.physmem.perBankRdBursts::4 29776 # Per bank write bursts 556system.physmem.perBankRdBursts::5 29847 # Per bank write bursts 557system.physmem.perBankRdBursts::6 29613 # Per bank write bursts 558system.physmem.perBankRdBursts::7 29430 # Per bank write bursts 559system.physmem.perBankRdBursts::8 29457 # Per bank write bursts 560system.physmem.perBankRdBursts::9 29488 # Per bank write bursts 561system.physmem.perBankRdBursts::10 29541 # Per bank write bursts 562system.physmem.perBankRdBursts::11 29643 # Per bank write bursts 563system.physmem.perBankRdBursts::12 29678 # Per bank write bursts 564system.physmem.perBankRdBursts::13 29796 # Per bank write bursts 565system.physmem.perBankRdBursts::14 29601 # Per bank write bursts 566system.physmem.perBankRdBursts::15 29796 # Per bank write bursts 567system.physmem.perBankWrBursts::0 4173 # Per bank write bursts 568system.physmem.perBankWrBursts::1 4100 # Per bank write bursts 569system.physmem.perBankWrBursts::2 4137 # Per bank write bursts 570system.physmem.perBankWrBursts::3 4146 # Per bank write bursts 571system.physmem.perBankWrBursts::4 4224 # Per bank write bursts 572system.physmem.perBankWrBursts::5 4225 # Per bank write bursts 573system.physmem.perBankWrBursts::6 4171 # Per bank write bursts 574system.physmem.perBankWrBursts::7 4094 # Per bank write bursts 575system.physmem.perBankWrBursts::8 4094 # Per bank write bursts 576system.physmem.perBankWrBursts::9 4093 # Per bank write bursts 577system.physmem.perBankWrBursts::10 4093 # Per bank write bursts 578system.physmem.perBankWrBursts::11 4097 # Per bank write bursts 579system.physmem.perBankWrBursts::12 4098 # Per bank write bursts 580system.physmem.perBankWrBursts::13 4095 # Per bank write bursts 581system.physmem.perBankWrBursts::14 4094 # Per bank write bursts 582system.physmem.perBankWrBursts::15 4138 # Per bank write bursts 583system.physmem.rdPerTurnAround::samples 4007 # Reads before turning the bus around for writes 584system.physmem.rdPerTurnAround::mean 48.550786 # Reads before turning the bus around for writes 585system.physmem.rdPerTurnAround::gmean 36.067006 # Reads before turning the bus around for writes 586system.physmem.rdPerTurnAround::stdev 508.980201 # Reads before turning the bus around for writes 587system.physmem.rdPerTurnAround::0-1023 4004 99.93% 99.93% # Reads before turning the bus around for writes 588system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes 589system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 590system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes 591system.physmem.rdPerTurnAround::total 4007 # Reads before turning the bus around for writes 592system.physmem.rdQLenPdf::0 474221 # What read queue length does an incoming req see 593system.physmem.rdQLenPdf::1 373 # What read queue length does an incoming req see 594system.physmem.rdQLenPdf::2 15 # What read queue length does an incoming req see 595system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 596system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 597system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 598system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 599system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 600system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 601system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 602system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 603system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 604system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 605system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 606system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 607system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 608system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 609system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 610system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 611system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 612system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 613system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 614system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 615system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 616system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 617system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 618system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 619system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 620system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 621system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 622system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 623system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 624system.physmem.readBursts 475025 # Number of DRAM read bursts, including those serviced by the write queue 625system.physmem.readPktSize::0 0 # Read request sizes (log2) 626system.physmem.readPktSize::1 0 # Read request sizes (log2) 627system.physmem.readPktSize::2 0 # Read request sizes (log2) 628system.physmem.readPktSize::3 0 # Read request sizes (log2) 629system.physmem.readPktSize::4 0 # Read request sizes (log2) 630system.physmem.readPktSize::5 0 # Read request sizes (log2) 631system.physmem.readPktSize::6 475025 # Read request sizes (log2) 632system.physmem.readReqs 475025 # Number of read requests accepted 633system.physmem.readRowHitRate 60.31 # Row buffer hit rate for reads 634system.physmem.readRowHits 286253 # Number of row buffer hits during reads 635system.physmem.servicedByWrQ 416 # Number of DRAM read bursts serviced by the write queue 636system.physmem.totBusLat 2373045000 # Total ticks spent in databus transfers 637system.physmem.totGap 1252658366500 # Total gap between requests 638system.physmem.totMemAccLat 13935557250 # Total ticks spent from burst creation until serviced by the DRAM 639system.physmem.totQLat 5036638500 # Total ticks spent queuing 640system.physmem.wrPerTurnAround::samples 4007 # Writes before turning the bus around for reads 641system.physmem.wrPerTurnAround::mean 16.489144 # Writes before turning the bus around for reads 642system.physmem.wrPerTurnAround::gmean 16.467620 # Writes before turning the bus around for reads 643system.physmem.wrPerTurnAround::stdev 0.859483 # Writes before turning the bus around for reads 644system.physmem.wrPerTurnAround::16 3026 75.52% 75.52% # Writes before turning the bus around for reads 645system.physmem.wrPerTurnAround::17 2 0.05% 75.57% # Writes before turning the bus around for reads 646system.physmem.wrPerTurnAround::18 979 24.43% 100.00% # Writes before turning the bus around for reads 647system.physmem.wrPerTurnAround::total 4007 # Writes before turning the bus around for reads 648system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 649system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 650system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 651system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 652system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 653system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 654system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 655system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 656system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 657system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 658system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 659system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 660system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 661system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 662system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 663system.physmem.wrQLenPdf::15 980 # What write queue length does an incoming req see 664system.physmem.wrQLenPdf::16 982 # What write queue length does an incoming req see 665system.physmem.wrQLenPdf::17 4008 # What write queue length does an incoming req see 666system.physmem.wrQLenPdf::18 4008 # What write queue length does an incoming req see 667system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see 668system.physmem.wrQLenPdf::20 4008 # What write queue length does an incoming req see 669system.physmem.wrQLenPdf::21 4008 # What write queue length does an incoming req see 670system.physmem.wrQLenPdf::22 4008 # What write queue length does an incoming req see 671system.physmem.wrQLenPdf::23 4008 # What write queue length does an incoming req see 672system.physmem.wrQLenPdf::24 4008 # What write queue length does an incoming req see 673system.physmem.wrQLenPdf::25 4008 # What write queue length does an incoming req see 674system.physmem.wrQLenPdf::26 4008 # What write queue length does an incoming req see 675system.physmem.wrQLenPdf::27 4007 # What write queue length does an incoming req see 676system.physmem.wrQLenPdf::28 4007 # What write queue length does an incoming req see 677system.physmem.wrQLenPdf::29 4007 # What write queue length does an incoming req see 678system.physmem.wrQLenPdf::30 4007 # What write queue length does an incoming req see 679system.physmem.wrQLenPdf::31 4007 # What write queue length does an incoming req see 680system.physmem.wrQLenPdf::32 4007 # What write queue length does an incoming req see 681system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 682system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 683system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 684system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 685system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 686system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 687system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 688system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 689system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 690system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 691system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 692system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 693system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 694system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 695system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 696system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 697system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 698system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 699system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 700system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 701system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 702system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 703system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 704system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 705system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 706system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 707system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 708system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 709system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 710system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 711system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 712system.physmem.writeBursts 66099 # Number of DRAM write bursts, including those merged in the write queue 713system.physmem.writePktSize::0 0 # Write request sizes (log2) 714system.physmem.writePktSize::1 0 # Write request sizes (log2) 715system.physmem.writePktSize::2 0 # Write request sizes (log2) 716system.physmem.writePktSize::3 0 # Write request sizes (log2) 717system.physmem.writePktSize::4 0 # Write request sizes (log2) 718system.physmem.writePktSize::5 0 # Write request sizes (log2) 719system.physmem.writePktSize::6 66099 # Write request sizes (log2) 720system.physmem.writeReqs 66099 # Number of write requests accepted 721system.physmem.writeRowHitRate 75.71 # Row buffer hit rate for writes 722system.physmem.writeRowHits 50044 # Number of row buffer hits during writes 723system.voltage_domain.voltage 1 # Voltage in Volts 724 725---------- End Simulation Statistics ---------- 726