xref: /gem5/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.489946                       # Number of seconds simulated
sim_ticks                                489945697500                       # Number of ticks simulated
final_tick                               489945697500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 152136                       # Simulator instruction rate (inst/s)
host_op_rate                                   187299                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                              116346895                       # Simulator tick rate (ticks/s)
host_mem_usage                                 275904                       # Number of bytes of host memory used
host_seconds                                  4211.08                       # Real time elapsed on the host
sim_insts                                   640655085                       # Number of instructions simulated
sim_ops                                     788730744                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            163712                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          18473856                       # Number of bytes read from this memory
system.physmem.bytes_read::total             18637568                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       163712                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          163712                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks      4230272                       # Number of bytes written to this memory
system.physmem.bytes_written::total           4230272                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst               2558                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             288654                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                291212                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks           66098                       # Number of write requests responded to by this memory
system.physmem.num_writes::total                66098                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst               334143                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data             37705926                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                38040069                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          334143                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             334143                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           8634165                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                8634165                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           8634165                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              334143                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data            37705926                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total               46674234                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        291212                       # Number of read requests accepted
system.physmem.writeReqs                        66098                       # Number of write requests accepted
system.physmem.readBursts                      291212                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                      66098                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 18617024                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     20544                       # Total number of bytes read from write queue
system.physmem.bytesWritten                   4228864                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  18637568                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                4230272                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      321                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               18282                       # Per bank write bursts
system.physmem.perBankRdBursts::1               18130                       # Per bank write bursts
system.physmem.perBankRdBursts::2               18217                       # Per bank write bursts
system.physmem.perBankRdBursts::3               18178                       # Per bank write bursts
system.physmem.perBankRdBursts::4               18288                       # Per bank write bursts
system.physmem.perBankRdBursts::5               18411                       # Per bank write bursts
system.physmem.perBankRdBursts::6               18177                       # Per bank write bursts
system.physmem.perBankRdBursts::7               17990                       # Per bank write bursts
system.physmem.perBankRdBursts::8               18028                       # Per bank write bursts
system.physmem.perBankRdBursts::9               18056                       # Per bank write bursts
system.physmem.perBankRdBursts::10              18107                       # Per bank write bursts
system.physmem.perBankRdBursts::11              18202                       # Per bank write bursts
system.physmem.perBankRdBursts::12              18216                       # Per bank write bursts
system.physmem.perBankRdBursts::13              18274                       # Per bank write bursts
system.physmem.perBankRdBursts::14              18077                       # Per bank write bursts
system.physmem.perBankRdBursts::15              18258                       # Per bank write bursts
system.physmem.perBankWrBursts::0                4171                       # Per bank write bursts
system.physmem.perBankWrBursts::1                4099                       # Per bank write bursts
system.physmem.perBankWrBursts::2                4134                       # Per bank write bursts
system.physmem.perBankWrBursts::3                4146                       # Per bank write bursts
system.physmem.perBankWrBursts::4                4225                       # Per bank write bursts
system.physmem.perBankWrBursts::5                4224                       # Per bank write bursts
system.physmem.perBankWrBursts::6                4173                       # Per bank write bursts
system.physmem.perBankWrBursts::7                4094                       # Per bank write bursts
system.physmem.perBankWrBursts::8                4096                       # Per bank write bursts
system.physmem.perBankWrBursts::9                4096                       # Per bank write bursts
system.physmem.perBankWrBursts::10               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::11               4097                       # Per bank write bursts
system.physmem.perBankWrBursts::12               4095                       # Per bank write bursts
system.physmem.perBankWrBursts::13               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::14               4096                       # Per bank write bursts
system.physmem.perBankWrBursts::15               4138                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                    489945603000                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  291212                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                  66098                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    290509                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       369                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                        13                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                      903                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                      903                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                     4014                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                     4018                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                     4018                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                     4018                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                     4018                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                     4017                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                     4017                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                     4017                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                     4017                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                     4017                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                     4017                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                     4017                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                     4019                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                     4019                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                     4017                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                     4017                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       110179                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      207.337369                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     135.107709                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     257.005441                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127          44928     40.78%     40.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255        43473     39.46%     80.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383         9308      8.45%     88.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511         1919      1.74%     90.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639          694      0.63%     91.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767          753      0.68%     91.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895          467      0.42%     92.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023          575      0.52%     92.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151         8062      7.32%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         110179                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples          4017                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        48.520538                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean       34.272045                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      506.481387                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023           4015     99.95%     99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071            1      0.02%     99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::31744-32767            1      0.02%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total            4017                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples          4017                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        16.449091                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.428808                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        0.834669                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16               3115     77.55%     77.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18                902     22.45%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total            4017                       # Writes before turning the bus around for reads
system.physmem.totQLat                     3297540750                       # Total ticks spent queuing
system.physmem.totMemAccLat                8751747000                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   1454455000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       11336.00                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  30086.00                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                          38.00                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           8.63                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                       38.04                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        8.63                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.36                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.30                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.07                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        22.85                       # Average write queue length when enqueuing
system.physmem.readRowHits                     195161                       # Number of row buffer hits during reads
system.physmem.writeRowHits                     51618                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   67.09                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  78.09                       # Row buffer hit rate for writes
system.physmem.avgGap                      1371205.96                       # Average gap between requests
system.physmem.pageHitRate                      69.13                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                  417417840                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  227757750                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                1136210400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                215563680                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy            32000629440                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           104435392590                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           202355359500                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             340788331200                       # Total energy per rank (pJ)
system.physmem_0.averagePower              695.568361                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   335944764000                       # Time in different power states
system.physmem_0.memoryStateTime::REF     16360240000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    137638069000                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                  415474920                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  226697625                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                1132396200                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                212608800                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy            32000629440                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           104010891930                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           202727728500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             340726427415                       # Total energy per rank (pJ)
system.physmem_1.averagePower              695.442012                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   336564996750                       # Time in different power states
system.physmem_1.memoryStateTime::REF     16360240000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    137017032000                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups               144591747                       # Number of BP lookups
system.cpu.branchPred.condPredicted          96197702                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect             97552                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             81370677                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                61978792                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             76.168461                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                19276085                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect               1317                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups        15994685                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits           15989167                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses             5518                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted         8032                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  673                       # Number of system calls
system.cpu.numCycles                        979891395                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.committedInsts                   640655085                       # Number of instructions committed
system.cpu.committedOps                     788730744                       # Number of ops (including micro ops) committed
system.cpu.discardedOps                       6653282                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.cpi                               1.529515                       # CPI: cycles per instruction
system.cpu.ipc                               0.653802                       # IPC: instructions per cycle
system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu               385757467     48.91%     48.91% # Class of committed instruction
system.cpu.op_class_0::IntMult                5173441      0.66%     49.56% # Class of committed instruction
system.cpu.op_class_0::IntDiv                       0      0.00%     49.56% # Class of committed instruction
system.cpu.op_class_0::FloatAdd                     0      0.00%     49.56% # Class of committed instruction
system.cpu.op_class_0::FloatCmp                     0      0.00%     49.56% # Class of committed instruction
system.cpu.op_class_0::FloatCvt                     0      0.00%     49.56% # Class of committed instruction
system.cpu.op_class_0::FloatMult                    0      0.00%     49.56% # Class of committed instruction
system.cpu.op_class_0::FloatDiv                     0      0.00%     49.56% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt                    0      0.00%     49.56% # Class of committed instruction
system.cpu.op_class_0::SimdAdd                      0      0.00%     49.56% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc                   0      0.00%     49.56% # Class of committed instruction
system.cpu.op_class_0::SimdAlu                      0      0.00%     49.56% # Class of committed instruction
system.cpu.op_class_0::SimdCmp                      0      0.00%     49.56% # Class of committed instruction
system.cpu.op_class_0::SimdCvt                      0      0.00%     49.56% # Class of committed instruction
system.cpu.op_class_0::SimdMisc                     0      0.00%     49.56% # Class of committed instruction
system.cpu.op_class_0::SimdMult                     0      0.00%     49.56% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc                  0      0.00%     49.56% # Class of committed instruction
system.cpu.op_class_0::SimdShift                    0      0.00%     49.56% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     49.56% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt                     0      0.00%     49.56% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd            637528      0.08%     49.65% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     49.65% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp           3187668      0.40%     50.05% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt           2550131      0.32%     50.37% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     50.37% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc         10203074      1.29%     51.67% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult                0      0.00%     51.67% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     51.67% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     51.67% # Class of committed instruction
system.cpu.op_class_0::MemRead              252240938     31.98%     83.65% # Class of committed instruction
system.cpu.op_class_0::MemWrite             128980497     16.35%    100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::total                788730744                       # Class of committed instruction
system.cpu.tickCycles                       924243701                       # Number of cycles that the object actually ticked
system.cpu.idleCycles                        55647694                       # Total number of cycles that the object has spent stopped
system.cpu.dcache.tags.replacements            778302                       # number of replacements
system.cpu.dcache.tags.tagsinuse          4092.104499                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           378448234                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs            782398                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            483.702967                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         792959500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data  4092.104499                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999049                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999049                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           31                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          182                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          971                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3         1499                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4         1413                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses         759382252                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses        759382252                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    249619506                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       249619506                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    128813766                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      128813766                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data         3484                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total          3484                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data         5739                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total         5739                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data         5739                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total         5739                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     378433272                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        378433272                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    378436756                       # number of overall hits
system.cpu.dcache.overall_hits::total       378436756                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data       713841                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total        713841                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data       137711                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total       137711                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data          141                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total          141                       # number of SoftPFReq misses
system.cpu.dcache.demand_misses::cpu.data       851552                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         851552                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data       851693                       # number of overall misses
system.cpu.dcache.overall_misses::total        851693                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  25188260500                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  25188260500                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  10109820000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  10109820000                       # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data  35298080500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total  35298080500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data  35298080500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total  35298080500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    250333347                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    250333347                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    128951477                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    128951477                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data         3625                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total         3625                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data         5739                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total         5739                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data         5739                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total         5739                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    379284824                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    379284824                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    379288449                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    379288449                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002852                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.002852                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001068                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.001068                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.038897                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.038897                       # miss rate for SoftPFReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.002245                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.002245                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.002246                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.002246                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35285.533473                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 35285.533473                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73413.307579                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 73413.307579                       # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 41451.468025                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 41451.468025                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 41444.605627                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 41444.605627                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks        88712                       # number of writebacks
system.cpu.dcache.writebacks::total             88712                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data          904                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total          904                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        68389                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        68389                       # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data        69293                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total        69293                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data        69293                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total        69293                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data       712937                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total       712937                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data        69322                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total        69322                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          139                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total          139                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data       782259                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total       782259                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data       782398                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total       782398                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24459771500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  24459771500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5070040000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   5070040000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data      1788000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1788000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data  29529811500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total  29529811500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data  29531599500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total  29531599500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002848                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002848                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000538                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000538                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.038345                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.038345                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002062                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.002062                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002063                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.002063                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34308.461337                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34308.461337                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73137.532097                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73137.532097                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37749.404609                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 37749.404609                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37744.983372                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 37744.983372                       # average overall mshr miss latency
system.cpu.icache.tags.replacements             24859                       # number of replacements
system.cpu.icache.tags.tagsinuse          1712.892625                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           252585994                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             26612                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs           9491.432211                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst  1712.892625                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.836373                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.836373                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024         1753                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           54                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          100                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4         1599                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.855957                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         505251826                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        505251826                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    252585994                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       252585994                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     252585994                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        252585994                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    252585994                       # number of overall hits
system.cpu.icache.overall_hits::total       252585994                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        26613                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         26613                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        26613                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          26613                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        26613                       # number of overall misses
system.cpu.icache.overall_misses::total         26613                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst    516729500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total    516729500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst    516729500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total    516729500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst    516729500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total    516729500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    252612607                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    252612607                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    252612607                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    252612607                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    252612607                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    252612607                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000105                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000105                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000105                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000105                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000105                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000105                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19416.431819                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 19416.431819                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 19416.431819                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 19416.431819                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 19416.431819                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 19416.431819                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks        24859                       # number of writebacks
system.cpu.icache.writebacks::total             24859                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        26613                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        26613                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        26613                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        26613                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        26613                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        26613                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    490117500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total    490117500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst    490117500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total    490117500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst    490117500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total    490117500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000105                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000105                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000105                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000105                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000105                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000105                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18416.469395                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18416.469395                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18416.469395                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 18416.469395                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18416.469395                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 18416.469395                       # average overall mshr miss latency
system.cpu.l2cache.tags.replacements           258808                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        32560.749490                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs            1247790                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs           291552                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs             4.279820                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks  2632.544658                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst    88.421700                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 29839.783132                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.080339                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.002698                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.910638                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.993675                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024        32744                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0          118                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          213                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          326                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         3136                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        28951                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.999268                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses         13231738                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses        13231738                       # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks        88712                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total        88712                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks        23528                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total        23528                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         3231                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         3231                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        24049                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total        24049                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data       490486                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total       490486                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst        24049                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data       493717                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          517766                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        24049                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data       493717                       # number of overall hits
system.cpu.l2cache.overall_hits::total         517766                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data        66091                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total        66091                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         2564                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         2564                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       222590                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       222590                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         2564                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       288681                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        291245                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         2564                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       288681                       # number of overall misses
system.cpu.l2cache.overall_misses::total       291245                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   4932129000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total   4932129000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    196405000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    196405000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  18239788500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  18239788500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    196405000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  23171917500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  23368322500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    196405000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  23171917500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  23368322500                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks        88712                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total        88712                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks        23528                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total        23528                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data        69322                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total        69322                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        26613                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total        26613                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data       713076                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total       713076                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        26613                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data       782398                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       809011                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        26613                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data       782398                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       809011                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.953391                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.953391                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.096344                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.096344                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.312155                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.312155                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.096344                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.368970                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.360001                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.096344                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.368970                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.360001                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74626.333389                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74626.333389                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76601.014041                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76601.014041                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81943.431870                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81943.431870                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76601.014041                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80268.245919                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 80235.961132                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76601.014041                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80268.245919                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 80235.961132                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks        66098                       # number of writebacks
system.cpu.l2cache.writebacks::total            66098                       # number of writebacks
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            5                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            5                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           27                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total           27                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            5                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           27                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           32                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            5                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           27                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           32                       # number of overall MSHR hits
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66091                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total        66091                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         2559                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         2559                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       222563                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       222563                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         2559                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       288654                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       291213                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         2559                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       288654                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       291213                       # number of overall MSHR misses
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4271219000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4271219000                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    170500500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    170500500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  16012410500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  16012410500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    170500500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  20283629500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  20454130000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    170500500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  20283629500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  20454130000                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.953391                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.953391                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.096156                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.096156                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.312117                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.312117                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.096156                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.368935                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.359962                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.096156                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.368935                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.359962                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64626.333389                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64626.333389                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66627.784291                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66627.784291                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71945.518797                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71945.518797                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66627.784291                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70269.698324                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70237.695433                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66627.784291                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70269.698324                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70237.695433                       # average overall mshr miss latency
system.cpu.toL2Bus.snoop_filter.tot_requests      1612172                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests       803221                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3314                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         2027                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2012                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops           15                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp        739688                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty       154810                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean        24859                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict       882300                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq        69322                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp        69322                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq        26613                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq       713076                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side        78084                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      2343098                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total           2421182                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      3294144                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     55751040                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total           59045184                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                      258808                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples      1067819                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.005072                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.071235                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0            1062418     99.49%     99.49% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1               5386      0.50%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                 15      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total        1067819                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy      919657000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      39920495                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy    1173610473                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
system.membus.trans_dist::ReadResp             225121                       # Transaction distribution
system.membus.trans_dist::WritebackDirty        66098                       # Transaction distribution
system.membus.trans_dist::CleanEvict           190682                       # Transaction distribution
system.membus.trans_dist::ReadExReq             66091                       # Transaction distribution
system.membus.trans_dist::ReadExResp            66091                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        225121                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port       839204                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                 839204                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port     22867840                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                22867840                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples            547992                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                  547992    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total              547992                       # Request fanout histogram
system.membus.reqLayer0.occupancy           916865000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.2                       # Layer utilization (%)
system.membus.respLayer1.occupancy         1554037500                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)

---------- End Simulation Statistics   ----------