111507SCurtis.Dunham@arm.com 211507SCurtis.Dunham@arm.com---------- Begin Simulation Statistics ---------- 311860Sandreas.hansson@arm.comsim_seconds 0.525648 # Number of seconds simulated 411860Sandreas.hansson@arm.comsim_ticks 525647850500 # Number of ticks simulated 511860Sandreas.hansson@arm.comfinal_tick 525647850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611507SCurtis.Dunham@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711860Sandreas.hansson@arm.comhost_inst_rate 304424 # Simulator instruction rate (inst/s) 811860Sandreas.hansson@arm.comhost_op_rate 374786 # Simulator op (including micro ops) rate (op/s) 911860Sandreas.hansson@arm.comhost_tick_rate 249775392 # Simulator tick rate (ticks/s) 1011860Sandreas.hansson@arm.comhost_mem_usage 281156 # Number of bytes of host memory used 1111860Sandreas.hansson@arm.comhost_seconds 2104.48 # Real time elapsed on the host 1211507SCurtis.Dunham@arm.comsim_insts 640655085 # Number of instructions simulated 1311507SCurtis.Dunham@arm.comsim_ops 788730744 # Number of ops (including micro ops) simulated 1411507SCurtis.Dunham@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511507SCurtis.Dunham@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611860Sandreas.hansson@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states 1711860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 164544 # Number of bytes read from this memory 1811606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu.data 18474496 # Number of bytes read from this memory 1911860Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 18639040 # Number of bytes read from this memory 2011860Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 164544 # Number of instructions bytes read from this memory 2111860Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 164544 # Number of instructions bytes read from this memory 2211507SCurtis.Dunham@arm.comsystem.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory 2311507SCurtis.Dunham@arm.comsystem.physmem.bytes_written::total 4230272 # Number of bytes written to this memory 2411860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 2571 # Number of read requests responded to by this memory 2511606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu.data 288664 # Number of read requests responded to by this memory 2611860Sandreas.hansson@arm.comsystem.physmem.num_reads::total 291235 # Number of read requests responded to by this memory 2711507SCurtis.Dunham@arm.comsystem.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory 2811507SCurtis.Dunham@arm.comsystem.physmem.num_writes::total 66098 # Number of write requests responded to by this memory 2911860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 313031 # Total read bandwidth from this memory (bytes/s) 3011860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 35146146 # Total read bandwidth from this memory (bytes/s) 3111860Sandreas.hansson@arm.comsystem.physmem.bw_read::total 35459177 # Total read bandwidth from this memory (bytes/s) 3211860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 313031 # Instruction read bandwidth from this memory (bytes/s) 3311860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 313031 # Instruction read bandwidth from this memory (bytes/s) 3411860Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 8047730 # Write bandwidth from this memory (bytes/s) 3511860Sandreas.hansson@arm.comsystem.physmem.bw_write::total 8047730 # Write bandwidth from this memory (bytes/s) 3611860Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 8047730 # Total bandwidth to/from this memory (bytes/s) 3711860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 313031 # Total bandwidth to/from this memory (bytes/s) 3811860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 35146146 # Total bandwidth to/from this memory (bytes/s) 3911860Sandreas.hansson@arm.comsystem.physmem.bw_total::total 43506907 # Total bandwidth to/from this memory (bytes/s) 4011860Sandreas.hansson@arm.comsystem.physmem.readReqs 291235 # Number of read requests accepted 4111507SCurtis.Dunham@arm.comsystem.physmem.writeReqs 66098 # Number of write requests accepted 4211860Sandreas.hansson@arm.comsystem.physmem.readBursts 291235 # Number of DRAM read bursts, including those serviced by the write queue 4311507SCurtis.Dunham@arm.comsystem.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue 4411860Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 18619136 # Total number of bytes read from DRAM 4511860Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 19904 # Total number of bytes read from write queue 4611860Sandreas.hansson@arm.comsystem.physmem.bytesWritten 4228224 # Total number of bytes written to DRAM 4711860Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 18639040 # Total read bytes from the system interface side 4811507SCurtis.Dunham@arm.comsystem.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side 4911860Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 311 # Number of DRAM read bursts serviced by the write queue 5011507SCurtis.Dunham@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 5111507SCurtis.Dunham@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 5211860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 18288 # Per bank write bursts 5311860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 18134 # Per bank write bursts 5411860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 18217 # Per bank write bursts 5511860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 18185 # Per bank write bursts 5611860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 18292 # Per bank write bursts 5711860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 18424 # Per bank write bursts 5811860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 18179 # Per bank write bursts 5911680SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::7 17990 # Per bank write bursts 6011860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 18031 # Per bank write bursts 6111860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 18051 # Per bank write bursts 6211860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 18108 # Per bank write bursts 6311860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 18204 # Per bank write bursts 6411860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 18211 # Per bank write bursts 6511860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 18269 # Per bank write bursts 6611860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 18079 # Per bank write bursts 6711860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 18262 # Per bank write bursts 6811507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::0 4171 # Per bank write bursts 6911680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::1 4099 # Per bank write bursts 7011860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 4134 # Per bank write bursts 7111507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::3 4146 # Per bank write bursts 7211860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 4223 # Per bank write bursts 7311606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::5 4224 # Per bank write bursts 7411860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 4173 # Per bank write bursts 7511680SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::7 4094 # Per bank write bursts 7611860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 4093 # Per bank write bursts 7711860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 4093 # Per bank write bursts 7811507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::10 4096 # Per bank write bursts 7911507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::11 4097 # Per bank write bursts 8011860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 4095 # Per bank write bursts 8111860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 4095 # Per bank write bursts 8211860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 4095 # Per bank write bursts 8311860Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 4138 # Per bank write bursts 8411507SCurtis.Dunham@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 8511507SCurtis.Dunham@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 8611860Sandreas.hansson@arm.comsystem.physmem.totGap 525647749500 # Total gap between requests 8711507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 8811507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 8911507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 9011507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 9111507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 9211507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 9311860Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 291235 # Read request sizes (log2) 9411507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 9511507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 9611507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 9711507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 9811507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 9911507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 10011507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::6 66098 # Write request sizes (log2) 10111860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 290544 # What read queue length does an incoming req see 10211860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 368 # What read queue length does an incoming req see 10311860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see 10411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 10511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 10611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 10711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 10811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 10911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 11011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 11111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 11211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 11311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 11411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 11511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 11611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 11711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 11811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 11911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 12011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 12111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 12211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 12311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 12411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 12511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 12611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 12711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 12811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 12911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 13011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 13111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 13211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 13311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 13411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 13511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 13611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 13711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 13811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 13911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 14011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 14111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 14211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 14311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 14411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 14511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 14611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 14711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 14811680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::15 890 # What write queue length does an incoming req see 14911860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 890 # What write queue length does an incoming req see 15011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 4008 # What write queue length does an incoming req see 15111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 4018 # What write queue length does an incoming req see 15211680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::19 4019 # What write queue length does an incoming req see 15311680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::20 4019 # What write queue length does an incoming req see 15411680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::21 4019 # What write queue length does an incoming req see 15511680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::22 4019 # What write queue length does an incoming req see 15611680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::23 4019 # What write queue length does an incoming req see 15711680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::24 4019 # What write queue length does an incoming req see 15811860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 4020 # What write queue length does an incoming req see 15911680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::26 4020 # What write queue length does an incoming req see 16011860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 4021 # What write queue length does an incoming req see 16111860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 4021 # What write queue length does an incoming req see 16211680SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::29 4020 # What write queue length does an incoming req see 16311860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 4023 # What write queue length does an incoming req see 16411860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 4020 # What write queue length does an incoming req see 16511860Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 4018 # What write queue length does an incoming req see 16611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 16711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 17011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 17111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 17211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 17311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 17411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 17511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 17611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 18011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 18111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 18211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 18311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 18411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 18511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 18611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 19011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 19111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 19211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 19311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 19411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 19511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 19611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19711860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 102644 # Bytes accessed per row activation 19811860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 222.570282 # Bytes accessed per row activation 19911860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 147.559533 # Bytes accessed per row activation 20011860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 262.016403 # Bytes accessed per row activation 20111860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 36015 35.09% 35.09% # Bytes accessed per row activation 20211860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 41909 40.83% 75.92% # Bytes accessed per row activation 20311860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 13148 12.81% 88.73% # Bytes accessed per row activation 20411860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 1006 0.98% 89.71% # Bytes accessed per row activation 20511860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 491 0.48% 90.18% # Bytes accessed per row activation 20611860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 1034 1.01% 91.19% # Bytes accessed per row activation 20711860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 399 0.39% 91.58% # Bytes accessed per row activation 20811860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 481 0.47% 92.05% # Bytes accessed per row activation 20911860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 8161 7.95% 100.00% # Bytes accessed per row activation 21011860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 102644 # Bytes accessed per row activation 21111860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 4018 # Reads before turning the bus around for writes 21211860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 48.515182 # Reads before turning the bus around for writes 21311860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::gmean 34.167653 # Reads before turning the bus around for writes 21411860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 506.604541 # Reads before turning the bus around for writes 21511860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-1023 4016 99.95% 99.95% # Reads before turning the bus around for writes 21611507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 21711507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes 21811860Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 4018 # Reads before turning the bus around for writes 21911860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 4018 # Writes before turning the bus around for reads 22011860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 16.442509 # Writes before turning the bus around for reads 22111860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 16.422441 # Writes before turning the bus around for reads 22211860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 0.830286 # Writes before turning the bus around for reads 22311860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16 3129 77.87% 77.87% # Writes before turning the bus around for reads 22411860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::18 889 22.13% 100.00% # Writes before turning the bus around for reads 22511860Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 4018 # Writes before turning the bus around for reads 22611860Sandreas.hansson@arm.comsystem.physmem.totQLat 15528676000 # Total ticks spent queuing 22711860Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 20983501000 # Total ticks spent from burst creation until serviced by the DRAM 22811860Sandreas.hansson@arm.comsystem.physmem.totBusLat 1454620000 # Total ticks spent in databus transfers 22911860Sandreas.hansson@arm.comsystem.physmem.avgQLat 53377.09 # Average queueing delay per DRAM burst 23011507SCurtis.Dunham@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 23111860Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 72127.09 # Average memory access latency per DRAM burst 23211680SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 35.42 # Average DRAM read bandwidth in MiByte/s 23311860Sandreas.hansson@arm.comsystem.physmem.avgWrBW 8.04 # Average achieved write bandwidth in MiByte/s 23411680SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 35.46 # Average system read bandwidth in MiByte/s 23511680SCurtis.Dunham@arm.comsystem.physmem.avgWrBWSys 8.05 # Average system write bandwidth in MiByte/s 23611507SCurtis.Dunham@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 23711680SCurtis.Dunham@arm.comsystem.physmem.busUtil 0.34 # Data bus utilization in percentage 23811570SCurtis.Dunham@arm.comsystem.physmem.busUtilRead 0.28 # Data bus utilization in percentage for reads 23911570SCurtis.Dunham@arm.comsystem.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes 24011507SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 24111860Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 28.92 # Average write queue length when enqueuing 24211860Sandreas.hansson@arm.comsystem.physmem.readRowHits 202546 # Number of row buffer hits during reads 24311860Sandreas.hansson@arm.comsystem.physmem.writeRowHits 51789 # Number of row buffer hits during writes 24411860Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 69.62 # Row buffer hit rate for reads 24511860Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 78.35 # Row buffer hit rate for writes 24611860Sandreas.hansson@arm.comsystem.physmem.avgGap 1471030.52 # Average gap between requests 24711860Sandreas.hansson@arm.comsystem.physmem.pageHitRate 71.24 # Row buffer hit rate, read and write combined 24811860Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 366410520 # Energy for activate commands per rank (pJ) 24911860Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 194736630 # Energy for precharge commands per rank (pJ) 25011860Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 1040362260 # Energy for read commands per rank (pJ) 25111860Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 173638080 # Energy for write commands per rank (pJ) 25211860Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 28886236080.000008 # Energy for refresh commands per rank (pJ) 25311860Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 8300918550 # Energy for active background per rank (pJ) 25411860Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 1634993280 # Energy for precharge background per rank (pJ) 25511860Sandreas.hansson@arm.comsystem.physmem_0.actPowerDownEnergy 57345491820 # Energy for active power-down per rank (pJ) 25611860Sandreas.hansson@arm.comsystem.physmem_0.prePowerDownEnergy 51305938080 # Energy for precharge power-down per rank (pJ) 25711860Sandreas.hansson@arm.comsystem.physmem_0.selfRefreshEnergy 64928910000 # Energy for self refresh per rank (pJ) 25811860Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 214198815120 # Total energy per rank (pJ) 25911860Sandreas.hansson@arm.comsystem.physmem_0.averagePower 407.494892 # Core power per rank (mW) 26011860Sandreas.hansson@arm.comsystem.physmem_0.totalIdleTime 503139346250 # Total Idle time Per DRAM Rank 26111860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 3209706000 # Time in different power states 26211860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 12289528000 # Time in different power states 26311860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::SREF 243772297750 # Time in different power states 26411860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 133609273250 # Time in different power states 26511860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 7009209500 # Time in different power states 26611860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 125757836000 # Time in different power states 26711860Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 366546180 # Energy for activate commands per rank (pJ) 26811860Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 194797350 # Energy for precharge commands per rank (pJ) 26911680SCurtis.Dunham@arm.comsystem.physmem_1.readEnergy 1036835100 # Energy for read commands per rank (pJ) 27011860Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 171226440 # Energy for write commands per rank (pJ) 27111860Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 28725815040.000008 # Energy for refresh commands per rank (pJ) 27211860Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 8187694890 # Energy for active background per rank (pJ) 27311860Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 1628706720 # Energy for precharge background per rank (pJ) 27411860Sandreas.hansson@arm.comsystem.physmem_1.actPowerDownEnergy 56919000150 # Energy for active power-down per rank (pJ) 27511860Sandreas.hansson@arm.comsystem.physmem_1.prePowerDownEnergy 51113801760 # Energy for precharge power-down per rank (pJ) 27611860Sandreas.hansson@arm.comsystem.physmem_1.selfRefreshEnergy 65311053315 # Energy for self refresh per rank (pJ) 27711860Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 213675530385 # Total energy per rank (pJ) 27811860Sandreas.hansson@arm.comsystem.physmem_1.averagePower 406.499389 # Core power per rank (mW) 27911860Sandreas.hansson@arm.comsystem.physmem_1.totalIdleTime 503405920500 # Total Idle time Per DRAM Rank 28011860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 3197022000 # Time in different power states 28111860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 12221338000 # Time in different power states 28211860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::SREF 245475081750 # Time in different power states 28311860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 133108808000 # Time in different power states 28411860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 6823284750 # Time in different power states 28511860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 124822316000 # Time in different power states 28611860Sandreas.hansson@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states 28711860Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 147257105 # Number of BP lookups 28811860Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 98226689 # Number of conditional branches predicted 28911860Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 1384794 # Number of conditional branches incorrect 29011860Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 89640439 # Number of BTB lookups 29111860Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 63297158 # Number of BTB hits 29211507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 29311860Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 70.612280 # BTB Hit Percentage 29411860Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 19276056 # Number of times the RAS was used to get a target. 29511860Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 1321 # Number of incorrect RAS predictions. 29611860Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectLookups 15995188 # Number of indirect predictor lookups. 29711860Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectHits 15989428 # Number of indirect target hits. 29811860Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectMisses 5760 # Number of indirect misses. 29911570SCurtis.Dunham@arm.comsystem.cpu.branchPredindirectMispredicted 1280093 # Number of mispredicted indirect branches. 30011507SCurtis.Dunham@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 30111860Sandreas.hansson@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states 30211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 30311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 30411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 30511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 30611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 30711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 30811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 30911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 31011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 31111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 31211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 31311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 31411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 31511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 31611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 31711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 31811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 31911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 32011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 32111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 32211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 32311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 32411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 32511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 32611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 32711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 32811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 32911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 33011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 33111860Sandreas.hansson@arm.comsystem.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states 33211507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 33311507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 33411507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 33511507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 33611507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 33711507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 33811507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 33911507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 34011507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 34111507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 34211507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 34311507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 34411507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 34511507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 34611507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 34711507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 34811507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 34911507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 35011507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 35111507SCurtis.Dunham@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 35211507SCurtis.Dunham@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 35311507SCurtis.Dunham@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 35411507SCurtis.Dunham@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 35511507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 35611507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 35711507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 35811507SCurtis.Dunham@arm.comsystem.cpu.dtb.hits 0 # DTB hits 35911507SCurtis.Dunham@arm.comsystem.cpu.dtb.misses 0 # DTB misses 36011507SCurtis.Dunham@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 36111860Sandreas.hansson@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states 36211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 36311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 36411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 36511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 36611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 36711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 36811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 36911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 37011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 37111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 37211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 37311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 37411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 37511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 37611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 37711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 37811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 37911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 38011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 38111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 38211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 38311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 38411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 38511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 38611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 38711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 38811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 38911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 39011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 39111860Sandreas.hansson@arm.comsystem.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states 39211507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 39311507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 39411507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 39511507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 39611507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 39711507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 39811507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 39911507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 40011507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 40111507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 40211507SCurtis.Dunham@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 40311507SCurtis.Dunham@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 40411507SCurtis.Dunham@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 40511507SCurtis.Dunham@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 40611507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 40711507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 40811507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 40911507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 41011507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 41111507SCurtis.Dunham@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 41211507SCurtis.Dunham@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 41311507SCurtis.Dunham@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 41411507SCurtis.Dunham@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 41511507SCurtis.Dunham@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 41611507SCurtis.Dunham@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 41711507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 41811507SCurtis.Dunham@arm.comsystem.cpu.itb.hits 0 # DTB hits 41911507SCurtis.Dunham@arm.comsystem.cpu.itb.misses 0 # DTB misses 42011507SCurtis.Dunham@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 42111955Sgabeblack@google.comsystem.cpu.workload.numSyscalls 673 # Number of system calls 42211860Sandreas.hansson@arm.comsystem.cpu.pwrStateResidencyTicks::ON 525647850500 # Cumulative time (in ticks) in various power states 42311860Sandreas.hansson@arm.comsystem.cpu.numCycles 1051295701 # number of cpu cycles simulated 42411507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 42511507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 42611507SCurtis.Dunham@arm.comsystem.cpu.committedInsts 640655085 # Number of instructions committed 42711507SCurtis.Dunham@arm.comsystem.cpu.committedOps 788730744 # Number of ops (including micro ops) committed 42811860Sandreas.hansson@arm.comsystem.cpu.discardedOps 8620171 # Number of ops (including micro ops) which were discarded before commit 42911507SCurtis.Dunham@arm.comsystem.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 43011860Sandreas.hansson@arm.comsystem.cpu.cpi 1.640970 # CPI: cycles per instruction 43111860Sandreas.hansson@arm.comsystem.cpu.ipc 0.609396 # IPC: instructions per cycle 43211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 43311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntAlu 385757467 48.91% 48.91% # Class of committed instruction 43411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction 43511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction 43611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction 43711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction 43811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction 43911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction 44011687Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatMultAcc 0 0.00% 49.56% # Class of committed instruction 44111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction 44211687Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatMisc 0 0.00% 49.56% # Class of committed instruction 44311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction 44411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction 44511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction 44611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction 44711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction 44811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction 44911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction 45011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction 45111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction 45211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction 45311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction 45411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction 45511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction 45611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction 45711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction 45811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction 45911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction 46011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction 46111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction 46211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction 46311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction 46411687Sandreas.hansson@arm.comsystem.cpu.op_class_0::MemRead 245222568 31.09% 82.76% # Class of committed instruction 46511687Sandreas.hansson@arm.comsystem.cpu.op_class_0::MemWrite 125149823 15.87% 98.62% # Class of committed instruction 46611687Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatMemRead 7018370 0.89% 99.51% # Class of committed instruction 46711687Sandreas.hansson@arm.comsystem.cpu.op_class_0::FloatMemWrite 3830674 0.49% 100.00% # Class of committed instruction 46811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 46911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 47011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::total 788730744 # Class of committed instruction 47111860Sandreas.hansson@arm.comsystem.cpu.tickCycles 955914808 # Number of cycles that the object actually ticked 47211860Sandreas.hansson@arm.comsystem.cpu.idleCycles 95380893 # Total number of cycles that the object has spent stopped 47311860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states 47411570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.replacements 778100 # number of replacements 47511860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 4092.107040 # Cycle average of tags in use 47611860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 378447440 # Total number of references to valid blocks. 47711570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.sampled_refs 782196 # Sample count of references to valid blocks. 47811860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 483.826867 # Average number of references to valid blocks. 47911860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 850680500 # Cycle when the warmup percentage was hit. 48011860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 4092.107040 # Average occupied blocks per requestor 48111680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999050 # Average percentage of cache occupancy 48211680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999050 # Average percentage of cache occupancy 48311507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 48411570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 48511860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id 48611860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 969 # Occupied blocks per task id 48711680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::3 1388 # Occupied blocks per task id 48811680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::4 1537 # Occupied blocks per task id 48911507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 49011860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 759379166 # Number of tag accesses 49111860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 759379166 # Number of data accesses 49211860Sandreas.hansson@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states 49311860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 249618713 # number of ReadReq hits 49411860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 249618713 # number of ReadReq hits 49511570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits 49611570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::total 128813765 # number of WriteReq hits 49711507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 3484 # number of SoftPFReq hits 49811507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 3484 # number of SoftPFReq hits 49911507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits 50011507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits 50111507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits 50211507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits 50311860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 378432478 # number of demand (read+write) hits 50411860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 378432478 # number of demand (read+write) hits 50511860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 378435962 # number of overall hits 50611860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 378435962 # number of overall hits 50711570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 713192 # number of ReadReq misses 50811570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::total 713192 # number of ReadReq misses 50911570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 137712 # number of WriteReq misses 51011570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::total 137712 # number of WriteReq misses 51111507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 141 # number of SoftPFReq misses 51211507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 141 # number of SoftPFReq misses 51311570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::cpu.data 850904 # number of demand (read+write) misses 51411570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::total 850904 # number of demand (read+write) misses 51511570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::cpu.data 851045 # number of overall misses 51611570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::total 851045 # number of overall misses 51711860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 37264745000 # number of ReadReq miss cycles 51811860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 37264745000 # number of ReadReq miss cycles 51911860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 10940214000 # number of WriteReq miss cycles 52011860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 10940214000 # number of WriteReq miss cycles 52111860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 48204959000 # number of demand (read+write) miss cycles 52211860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 48204959000 # number of demand (read+write) miss cycles 52311860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 48204959000 # number of overall miss cycles 52411860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 48204959000 # number of overall miss cycles 52511860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 250331905 # number of ReadReq accesses(hits+misses) 52611860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 250331905 # number of ReadReq accesses(hits+misses) 52711507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 52811507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 52911507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 3625 # number of SoftPFReq accesses(hits+misses) 53011507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 3625 # number of SoftPFReq accesses(hits+misses) 53111507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) 53211507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) 53311507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) 53411507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) 53511860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 379283382 # number of demand (read+write) accesses 53611860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 379283382 # number of demand (read+write) accesses 53711860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 379287007 # number of overall (read+write) accesses 53811860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 379287007 # number of overall (read+write) accesses 53911570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002849 # miss rate for ReadReq accesses 54011570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.002849 # miss rate for ReadReq accesses 54111507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses 54211507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses 54311507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038897 # miss rate for SoftPFReq accesses 54411507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.038897 # miss rate for SoftPFReq accesses 54511570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.002243 # miss rate for demand accesses 54611570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.002243 # miss rate for demand accesses 54711570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.002244 # miss rate for overall accesses 54811570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.002244 # miss rate for overall accesses 54911860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52250.649194 # average ReadReq miss latency 55011860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 52250.649194 # average ReadReq miss latency 55111860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79442.706518 # average WriteReq miss latency 55211860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 79442.706518 # average WriteReq miss latency 55311860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 56651.465970 # average overall miss latency 55411860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 56651.465970 # average overall miss latency 55511860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 56642.080031 # average overall miss latency 55611860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 56642.080031 # average overall miss latency 55711507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 55811507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 55911507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 56011507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 56111507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 56211507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 56311860Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 88684 # number of writebacks 56411860Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 88684 # number of writebacks 56511570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 457 # number of ReadReq MSHR hits 56611570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 457 # number of ReadReq MSHR hits 56711570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits 56811570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 68390 # number of WriteReq MSHR hits 56911570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 68847 # number of demand (read+write) MSHR hits 57011570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::total 68847 # number of demand (read+write) MSHR hits 57111570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 68847 # number of overall MSHR hits 57211570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::total 68847 # number of overall MSHR hits 57311570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 712735 # number of ReadReq MSHR misses 57411570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 712735 # number of ReadReq MSHR misses 57511507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses 57611507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses 57711507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses 57811507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses 57911570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 782057 # number of demand (read+write) MSHR misses 58011570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::total 782057 # number of demand (read+write) MSHR misses 58111570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 782196 # number of overall MSHR misses 58211570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::total 782196 # number of overall MSHR misses 58311860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36543095500 # number of ReadReq MSHR miss cycles 58411860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 36543095500 # number of ReadReq MSHR miss cycles 58511860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5486426000 # number of WriteReq MSHR miss cycles 58611860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 5486426000 # number of WriteReq MSHR miss cycles 58711680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1802000 # number of SoftPFReq MSHR miss cycles 58811680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1802000 # number of SoftPFReq MSHR miss cycles 58911860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 42029521500 # number of demand (read+write) MSHR miss cycles 59011860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 42029521500 # number of demand (read+write) MSHR miss cycles 59111860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 42031323500 # number of overall MSHR miss cycles 59211860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 42031323500 # number of overall MSHR miss cycles 59311570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses 59411570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses 59511507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses 59611507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses 59711507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038345 # mshr miss rate for SoftPFReq accesses 59811507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038345 # mshr miss rate for SoftPFReq accesses 59911507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses 60011507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses 60111570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses 60211570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses 60311860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51271.644440 # average ReadReq mshr miss latency 60411860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51271.644440 # average ReadReq mshr miss latency 60511860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79144.081244 # average WriteReq mshr miss latency 60611860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79144.081244 # average WriteReq mshr miss latency 60711680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12964.028777 # average SoftPFReq mshr miss latency 60811680SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12964.028777 # average SoftPFReq mshr miss latency 60911860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53742.273901 # average overall mshr miss latency 61011860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 53742.273901 # average overall mshr miss latency 61111860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53735.027410 # average overall mshr miss latency 61211860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 53735.027410 # average overall mshr miss latency 61311860Sandreas.hansson@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states 61411860Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 24889 # number of replacements 61511860Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 1710.890314 # Cycle average of tags in use 61611860Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 257795451 # Total number of references to valid blocks. 61711860Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 26639 # Sample count of references to valid blocks. 61811860Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 9677.369684 # Average number of references to valid blocks. 61911507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 62011860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 1710.890314 # Average occupied blocks per requestor 62111860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.835396 # Average percentage of cache occupancy 62211860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.835396 # Average percentage of cache occupancy 62311860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 1750 # Occupied blocks per task id 62411860Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 62511860Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id 62611860Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 1598 # Occupied blocks per task id 62711860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.854492 # Percentage of cache occupancy per task id 62811860Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 515670821 # Number of tag accesses 62911860Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 515670821 # Number of data accesses 63011860Sandreas.hansson@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states 63111860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 257795451 # number of ReadReq hits 63211860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 257795451 # number of ReadReq hits 63311860Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 257795451 # number of demand (read+write) hits 63411860Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 257795451 # number of demand (read+write) hits 63511860Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 257795451 # number of overall hits 63611860Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 257795451 # number of overall hits 63711860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 26640 # number of ReadReq misses 63811860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 26640 # number of ReadReq misses 63911860Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 26640 # number of demand (read+write) misses 64011860Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 26640 # number of demand (read+write) misses 64111860Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 26640 # number of overall misses 64211860Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 26640 # number of overall misses 64311860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 538801500 # number of ReadReq miss cycles 64411860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 538801500 # number of ReadReq miss cycles 64511860Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 538801500 # number of demand (read+write) miss cycles 64611860Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 538801500 # number of demand (read+write) miss cycles 64711860Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 538801500 # number of overall miss cycles 64811860Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 538801500 # number of overall miss cycles 64911860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 257822091 # number of ReadReq accesses(hits+misses) 65011860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 257822091 # number of ReadReq accesses(hits+misses) 65111860Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 257822091 # number of demand (read+write) accesses 65211860Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 257822091 # number of demand (read+write) accesses 65311860Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 257822091 # number of overall (read+write) accesses 65411860Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 257822091 # number of overall (read+write) accesses 65511570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000103 # miss rate for ReadReq accesses 65611570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.000103 # miss rate for ReadReq accesses 65711570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.000103 # miss rate for demand accesses 65811570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::total 0.000103 # miss rate for demand accesses 65911570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.000103 # miss rate for overall accesses 66011570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::total 0.000103 # miss rate for overall accesses 66111860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20225.281532 # average ReadReq miss latency 66211860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 20225.281532 # average ReadReq miss latency 66311860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 20225.281532 # average overall miss latency 66411860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 20225.281532 # average overall miss latency 66511860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 20225.281532 # average overall miss latency 66611860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 20225.281532 # average overall miss latency 66711507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 66811507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 66911507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 67011507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 67111507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 67211507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 67311860Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::writebacks 24889 # number of writebacks 67411860Sandreas.hansson@arm.comsystem.cpu.icache.writebacks::total 24889 # number of writebacks 67511860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 26640 # number of ReadReq MSHR misses 67611860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 26640 # number of ReadReq MSHR misses 67711860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 26640 # number of demand (read+write) MSHR misses 67811860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 26640 # number of demand (read+write) MSHR misses 67911860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 26640 # number of overall MSHR misses 68011860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 26640 # number of overall MSHR misses 68111860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 512162500 # number of ReadReq MSHR miss cycles 68211860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 512162500 # number of ReadReq MSHR miss cycles 68311860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 512162500 # number of demand (read+write) MSHR miss cycles 68411860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 512162500 # number of demand (read+write) MSHR miss cycles 68511860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 512162500 # number of overall MSHR miss cycles 68611860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 512162500 # number of overall MSHR miss cycles 68711570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for ReadReq accesses 68811570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000103 # mshr miss rate for ReadReq accesses 68911570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for demand accesses 69011570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.000103 # mshr miss rate for demand accesses 69111570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for overall accesses 69211570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.000103 # mshr miss rate for overall accesses 69311860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19225.319069 # average ReadReq mshr miss latency 69411860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19225.319069 # average ReadReq mshr miss latency 69511860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19225.319069 # average overall mshr miss latency 69611860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 19225.319069 # average overall mshr miss latency 69711860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19225.319069 # average overall mshr miss latency 69811860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 19225.319069 # average overall mshr miss latency 69911860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states 70011860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 258839 # number of replacements 70111860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 32651.545544 # Cycle average of tags in use 70211860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 1316953 # Total number of references to valid blocks. 70311860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 291607 # Sample count of references to valid blocks. 70411860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 4.516191 # Average number of references to valid blocks. 70511860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 3958663000 # Cycle when the warmup percentage was hit. 70611860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 40.523746 # Average occupied blocks per requestor 70711860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 90.271478 # Average occupied blocks per requestor 70811860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 32520.750321 # Average occupied blocks per requestor 70911860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.001237 # Average percentage of cache occupancy 71011860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.002755 # Average percentage of cache occupancy 71111860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.992455 # Average percentage of cache occupancy 71211860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.996446 # Average percentage of cache occupancy 71311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id 71411860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id 71511860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id 71611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 300 # Occupied blocks per task id 71711680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 2912 # Occupied blocks per task id 71811860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 29227 # Occupied blocks per task id 71911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 72011860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 13160335 # Number of tag accesses 72111860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 13160335 # Number of data accesses 72211860Sandreas.hansson@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states 72311860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 88684 # number of WritebackDirty hits 72411860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 88684 # number of WritebackDirty hits 72511860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 23557 # number of WritebackClean hits 72611860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 23557 # number of WritebackClean hits 72711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits 72811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits 72911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24064 # number of ReadCleanReq hits 73011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 24064 # number of ReadCleanReq hits 73111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 490275 # number of ReadSharedReq hits 73211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 490275 # number of ReadSharedReq hits 73311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 24064 # number of demand (read+write) hits 73411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 493506 # number of demand (read+write) hits 73511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 517570 # number of demand (read+write) hits 73611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 24064 # number of overall hits 73711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 493506 # number of overall hits 73811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 517570 # number of overall hits 73911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 66091 # number of ReadExReq misses 74011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses 74111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2576 # number of ReadCleanReq misses 74211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 2576 # number of ReadCleanReq misses 74311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 222599 # number of ReadSharedReq misses 74411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 222599 # number of ReadSharedReq misses 74511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 2576 # number of demand (read+write) misses 74611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 288690 # number of demand (read+write) misses 74711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 291266 # number of demand (read+write) misses 74811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 2576 # number of overall misses 74911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 288690 # number of overall misses 75011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 291266 # number of overall misses 75111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5348515000 # number of ReadExReq miss cycles 75211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 5348515000 # number of ReadExReq miss cycles 75311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 218253000 # number of ReadCleanReq miss cycles 75411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 218253000 # number of ReadCleanReq miss cycles 75511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30325726000 # number of ReadSharedReq miss cycles 75611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 30325726000 # number of ReadSharedReq miss cycles 75711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 218253000 # number of demand (read+write) miss cycles 75811860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 35674241000 # number of demand (read+write) miss cycles 75911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 35892494000 # number of demand (read+write) miss cycles 76011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 218253000 # number of overall miss cycles 76111860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 35674241000 # number of overall miss cycles 76211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 35892494000 # number of overall miss cycles 76311860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 88684 # number of WritebackDirty accesses(hits+misses) 76411860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 88684 # number of WritebackDirty accesses(hits+misses) 76511860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 23557 # number of WritebackClean accesses(hits+misses) 76611860Sandreas.hansson@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 23557 # number of WritebackClean accesses(hits+misses) 76711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses) 76811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses) 76911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 26640 # number of ReadCleanReq accesses(hits+misses) 77011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 26640 # number of ReadCleanReq accesses(hits+misses) 77111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712874 # number of ReadSharedReq accesses(hits+misses) 77211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 712874 # number of ReadSharedReq accesses(hits+misses) 77311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 26640 # number of demand (read+write) accesses 77411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 782196 # number of demand (read+write) accesses 77511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 808836 # number of demand (read+write) accesses 77611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 26640 # number of overall (read+write) accesses 77711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 782196 # number of overall (read+write) accesses 77811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 808836 # number of overall (read+write) accesses 77911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 # miss rate for ReadExReq accesses 78011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses 78111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.096697 # miss rate for ReadCleanReq accesses 78211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.096697 # miss rate for ReadCleanReq accesses 78311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312256 # miss rate for ReadSharedReq accesses 78411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312256 # miss rate for ReadSharedReq accesses 78511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.096697 # miss rate for demand accesses 78611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.369076 # miss rate for demand accesses 78711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.360105 # miss rate for demand accesses 78811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.096697 # miss rate for overall accesses 78911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.369076 # miss rate for overall accesses 79011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.360105 # miss rate for overall accesses 79111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80926.525548 # average ReadExReq miss latency 79211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 80926.525548 # average ReadExReq miss latency 79311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84725.543478 # average ReadCleanReq miss latency 79411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84725.543478 # average ReadCleanReq miss latency 79511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 136234.780929 # average ReadSharedReq miss latency 79611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 136234.780929 # average ReadSharedReq miss latency 79711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84725.543478 # average overall miss latency 79811860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 123572.832450 # average overall miss latency 79911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 123229.261225 # average overall miss latency 80011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84725.543478 # average overall miss latency 80111860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 123572.832450 # average overall miss latency 80211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 123229.261225 # average overall miss latency 80311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 80411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 80511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 80611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 80711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 80811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 80911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks 81011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.writebacks::total 66098 # number of writebacks 81111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 4 # number of ReadCleanReq MSHR hits 81211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits 81311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 26 # number of ReadSharedReq MSHR hits 81411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 26 # number of ReadSharedReq MSHR hits 81511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits 81611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 26 # number of demand (read+write) MSHR hits 81711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 30 # number of demand (read+write) MSHR hits 81811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits 81911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 26 # number of overall MSHR hits 82011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 30 # number of overall MSHR hits 82111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses 82211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses 82311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2572 # number of ReadCleanReq MSHR misses 82411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 2572 # number of ReadCleanReq MSHR misses 82511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222573 # number of ReadSharedReq MSHR misses 82611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 222573 # number of ReadSharedReq MSHR misses 82711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 2572 # number of demand (read+write) MSHR misses 82811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 288664 # number of demand (read+write) MSHR misses 82911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 291236 # number of demand (read+write) MSHR misses 83011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 2572 # number of overall MSHR misses 83111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 288664 # number of overall MSHR misses 83211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 291236 # number of overall MSHR misses 83311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4687605000 # number of ReadExReq MSHR miss cycles 83411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4687605000 # number of ReadExReq MSHR miss cycles 83511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 192261000 # number of ReadCleanReq MSHR miss cycles 83611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 192261000 # number of ReadCleanReq MSHR miss cycles 83711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28098015500 # number of ReadSharedReq MSHR miss cycles 83811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28098015500 # number of ReadSharedReq MSHR miss cycles 83911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 192261000 # number of demand (read+write) MSHR miss cycles 84011860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32785620500 # number of demand (read+write) MSHR miss cycles 84111860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 32977881500 # number of demand (read+write) MSHR miss cycles 84211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 192261000 # number of overall MSHR miss cycles 84311860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32785620500 # number of overall MSHR miss cycles 84411860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 32977881500 # number of overall MSHR miss cycles 84511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses 84611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses 84711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096547 # mshr miss rate for ReadCleanReq accesses 84811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096547 # mshr miss rate for ReadCleanReq accesses 84911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312219 # mshr miss rate for ReadSharedReq accesses 85011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312219 # mshr miss rate for ReadSharedReq accesses 85111860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096547 # mshr miss rate for demand accesses 85211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for demand accesses 85311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.360068 # mshr miss rate for demand accesses 85411860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096547 # mshr miss rate for overall accesses 85511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for overall accesses 85611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.360068 # mshr miss rate for overall accesses 85711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70926.525548 # average ReadExReq mshr miss latency 85811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70926.525548 # average ReadExReq mshr miss latency 85911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74751.555210 # average ReadCleanReq mshr miss latency 86011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74751.555210 # average ReadCleanReq mshr miss latency 86111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 126241.797073 # average ReadSharedReq mshr miss latency 86211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 126241.797073 # average ReadSharedReq mshr miss latency 86311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74751.555210 # average overall mshr miss latency 86411860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 113577.101752 # average overall mshr miss latency 86511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 113234.220701 # average overall mshr miss latency 86611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74751.555210 # average overall mshr miss latency 86711860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 113577.101752 # average overall mshr miss latency 86811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 113234.220701 # average overall mshr miss latency 86911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 1611825 # Total number of requests made to the snoop filter. 87011860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 803048 # Number of requests hitting in the snoop filter with a single holder of the requested data. 87111570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 3234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 87211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 2033 # Total number of snoops made to the snoop filter. 87311860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 2018 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 87411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 87511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states 87611860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 739513 # Transaction distribution 87711860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 154782 # Transaction distribution 87811860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 24889 # Transaction distribution 87911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 882157 # Transaction distribution 88011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution 88111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution 88211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 26640 # Transaction distribution 88311570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 712874 # Transaction distribution 88411860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 78168 # Packet count per connected master and slave (bytes) 88511570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342492 # Packet count per connected master and slave (bytes) 88611860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 2420660 # Packet count per connected master and slave (bytes) 88711860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3297792 # Cumulative packet size per connected master and slave (bytes) 88811860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55736320 # Cumulative packet size per connected master and slave (bytes) 88911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 59034112 # Cumulative packet size per connected master and slave (bytes) 89011860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 258839 # Total snoops (count) 89111570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoopTraffic 4230272 # Total snoop traffic (bytes) 89211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 1067675 # Request fanout histogram 89311860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.005002 # Request fanout histogram 89411860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.070750 # Request fanout histogram 89511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 89611860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 1062349 99.50% 99.50% # Request fanout histogram 89711860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 5311 0.50% 100.00% # Request fanout histogram 89811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 15 0.00% 100.00% # Request fanout histogram 89911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 90011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 90111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 90211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 1067675 # Request fanout histogram 90311860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 919485500 # Layer occupancy (ticks) 90411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 90511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 39960496 # Layer occupancy (ticks) 90611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 90711570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 1173306974 # Layer occupancy (ticks) 90811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 90911860Sandreas.hansson@arm.comsystem.membus.snoop_filter.tot_requests 548040 # Total number of requests made to the snoop filter. 91011860Sandreas.hansson@arm.comsystem.membus.snoop_filter.hit_single_requests 256844 # Number of requests hitting in the snoop filter with a single holder of the requested data. 91111606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 91211606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 91311606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 91411606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 91511860Sandreas.hansson@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states 91611860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 225144 # Transaction distribution 91711507SCurtis.Dunham@arm.comsystem.membus.trans_dist::WritebackDirty 66098 # Transaction distribution 91811860Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 190707 # Transaction distribution 91911507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 66091 # Transaction distribution 92011507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 66091 # Transaction distribution 92111860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 225144 # Transaction distribution 92211860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839275 # Packet count per connected master and slave (bytes) 92311860Sandreas.hansson@arm.comsystem.membus.pkt_count::total 839275 # Packet count per connected master and slave (bytes) 92411860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22869312 # Cumulative packet size per connected master and slave (bytes) 92511860Sandreas.hansson@arm.comsystem.membus.pkt_size::total 22869312 # Cumulative packet size per connected master and slave (bytes) 92611507SCurtis.Dunham@arm.comsystem.membus.snoops 0 # Total snoops (count) 92711570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 92811860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 291235 # Request fanout histogram 92911507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 93011507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 93111507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 93211860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 291235 100.00% 100.00% # Request fanout histogram 93311507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 93411507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 93511507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 93611507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 93711860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 291235 # Request fanout histogram 93811860Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 917214500 # Layer occupancy (ticks) 93911507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 94011860Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 1553534250 # Layer occupancy (ticks) 94111507SCurtis.Dunham@arm.comsystem.membus.respLayer1.utilization 0.3 # Layer utilization (%) 94211507SCurtis.Dunham@arm.com 94311507SCurtis.Dunham@arm.com---------- End Simulation Statistics ---------- 944