stats.txt revision 9797:9cd5f91e7a79
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.525834 # Number of seconds simulated 4sim_ticks 525834342000 # Number of ticks simulated 5final_tick 525834342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 442791 # Simulator instruction rate (inst/s) 8host_op_rate 566092 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 853689730 # Simulator tick rate (ticks/s) 10host_mem_usage 250392 # Number of bytes of host memory used 11host_seconds 615.96 # Real time elapsed on the host 12sim_insts 272739283 # Number of instructions simulated 13sim_ops 348687122 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 270272 # Number of bytes read from this memory 16system.physmem.bytes_read::total 437248 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 166976 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 317545 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 513987 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 831532 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 317545 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 317545 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 317545 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 513987 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 831532 # Total bandwidth to/from this memory (bytes/s) 30system.membus.throughput 831532 # Throughput (bytes/s) 31system.membus.trans_dist::ReadReq 3976 # Transaction distribution 32system.membus.trans_dist::ReadResp 3976 # Transaction distribution 33system.membus.trans_dist::ReadExReq 2856 # Transaction distribution 34system.membus.trans_dist::ReadExResp 2856 # Transaction distribution 35system.membus.pkt_count_system.cpu.l2cache.mem_side 13664 # Packet count per connected master and slave (bytes) 36system.membus.pkt_count 13664 # Packet count per connected master and slave (bytes) 37system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 437248 # Cumulative packet size per connected master and slave (bytes) 38system.membus.tot_pkt_size 437248 # Cumulative packet size per connected master and slave (bytes) 39system.membus.data_through_bus 437248 # Total data (bytes) 40system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 41system.membus.reqLayer0.occupancy 6832000 # Layer occupancy (ticks) 42system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 43system.membus.respLayer1.occupancy 61488000 # Layer occupancy (ticks) 44system.membus.respLayer1.utilization 0.0 # Layer utilization (%) 45system.cpu.dtb.inst_hits 0 # ITB inst hits 46system.cpu.dtb.inst_misses 0 # ITB inst misses 47system.cpu.dtb.read_hits 0 # DTB read hits 48system.cpu.dtb.read_misses 0 # DTB read misses 49system.cpu.dtb.write_hits 0 # DTB write hits 50system.cpu.dtb.write_misses 0 # DTB write misses 51system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 52system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 53system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 54system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 55system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 56system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 57system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 58system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 59system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 60system.cpu.dtb.read_accesses 0 # DTB read accesses 61system.cpu.dtb.write_accesses 0 # DTB write accesses 62system.cpu.dtb.inst_accesses 0 # ITB inst accesses 63system.cpu.dtb.hits 0 # DTB hits 64system.cpu.dtb.misses 0 # DTB misses 65system.cpu.dtb.accesses 0 # DTB accesses 66system.cpu.itb.inst_hits 0 # ITB inst hits 67system.cpu.itb.inst_misses 0 # ITB inst misses 68system.cpu.itb.read_hits 0 # DTB read hits 69system.cpu.itb.read_misses 0 # DTB read misses 70system.cpu.itb.write_hits 0 # DTB write hits 71system.cpu.itb.write_misses 0 # DTB write misses 72system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 73system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 74system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 75system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 76system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 77system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 78system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 79system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 80system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 81system.cpu.itb.read_accesses 0 # DTB read accesses 82system.cpu.itb.write_accesses 0 # DTB write accesses 83system.cpu.itb.inst_accesses 0 # ITB inst accesses 84system.cpu.itb.hits 0 # DTB hits 85system.cpu.itb.misses 0 # DTB misses 86system.cpu.itb.accesses 0 # DTB accesses 87system.cpu.workload.num_syscalls 191 # Number of system calls 88system.cpu.numCycles 1051668684 # number of cpu cycles simulated 89system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 90system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 91system.cpu.committedInsts 272739283 # Number of instructions committed 92system.cpu.committedOps 348687122 # Number of ops (including micro ops) committed 93system.cpu.num_int_alu_accesses 279584917 # Number of integer alu accesses 94system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses 95system.cpu.num_func_calls 12448615 # number of times a function call or return occured 96system.cpu.num_conditional_control_insts 18105896 # number of instructions that are conditional controls 97system.cpu.num_int_insts 279584917 # number of integer instructions 98system.cpu.num_fp_insts 114216705 # number of float instructions 99system.cpu.num_int_register_reads 2212913168 # number of times the integer registers were read 100system.cpu.num_int_register_writes 251197902 # number of times the integer registers were written 101system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read 102system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written 103system.cpu.num_mem_refs 177024356 # number of memory refs 104system.cpu.num_load_insts 94648757 # Number of load instructions 105system.cpu.num_store_insts 82375599 # Number of store instructions 106system.cpu.num_idle_cycles 0 # Number of idle cycles 107system.cpu.num_busy_cycles 1051668684 # Number of busy cycles 108system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 109system.cpu.idle_fraction 0 # Percentage of idle cycles 110system.cpu.icache.tags.replacements 13796 # number of replacements 111system.cpu.icache.tags.tagsinuse 1765.993223 # Cycle average of tags in use 112system.cpu.icache.tags.total_refs 348644747 # Total number of references to valid blocks. 113system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. 114system.cpu.icache.tags.avg_refs 22344.725181 # Average number of references to valid blocks. 115system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 116system.cpu.icache.tags.occ_blocks::cpu.inst 1765.993223 # Average occupied blocks per requestor 117system.cpu.icache.tags.occ_percent::cpu.inst 0.862301 # Average percentage of cache occupancy 118system.cpu.icache.tags.occ_percent::total 0.862301 # Average percentage of cache occupancy 119system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits 120system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits 121system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits 122system.cpu.icache.demand_hits::total 348644747 # number of demand (read+write) hits 123system.cpu.icache.overall_hits::cpu.inst 348644747 # number of overall hits 124system.cpu.icache.overall_hits::total 348644747 # number of overall hits 125system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses 126system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses 127system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses 128system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses 129system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses 130system.cpu.icache.overall_misses::total 15603 # number of overall misses 131system.cpu.icache.ReadReq_miss_latency::cpu.inst 312417000 # number of ReadReq miss cycles 132system.cpu.icache.ReadReq_miss_latency::total 312417000 # number of ReadReq miss cycles 133system.cpu.icache.demand_miss_latency::cpu.inst 312417000 # number of demand (read+write) miss cycles 134system.cpu.icache.demand_miss_latency::total 312417000 # number of demand (read+write) miss cycles 135system.cpu.icache.overall_miss_latency::cpu.inst 312417000 # number of overall miss cycles 136system.cpu.icache.overall_miss_latency::total 312417000 # number of overall miss cycles 137system.cpu.icache.ReadReq_accesses::cpu.inst 348660350 # number of ReadReq accesses(hits+misses) 138system.cpu.icache.ReadReq_accesses::total 348660350 # number of ReadReq accesses(hits+misses) 139system.cpu.icache.demand_accesses::cpu.inst 348660350 # number of demand (read+write) accesses 140system.cpu.icache.demand_accesses::total 348660350 # number of demand (read+write) accesses 141system.cpu.icache.overall_accesses::cpu.inst 348660350 # number of overall (read+write) accesses 142system.cpu.icache.overall_accesses::total 348660350 # number of overall (read+write) accesses 143system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses 144system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses 145system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses 146system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses 147system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses 148system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses 149system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20022.880215 # average ReadReq miss latency 150system.cpu.icache.ReadReq_avg_miss_latency::total 20022.880215 # average ReadReq miss latency 151system.cpu.icache.demand_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency 152system.cpu.icache.demand_avg_miss_latency::total 20022.880215 # average overall miss latency 153system.cpu.icache.overall_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency 154system.cpu.icache.overall_avg_miss_latency::total 20022.880215 # average overall miss latency 155system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 156system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 157system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 158system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 159system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 160system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 161system.cpu.icache.fast_writes 0 # number of fast writes performed 162system.cpu.icache.cache_copies 0 # number of cache copies performed 163system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses 164system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses 165system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses 166system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses 167system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses 168system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses 169system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281211000 # number of ReadReq MSHR miss cycles 170system.cpu.icache.ReadReq_mshr_miss_latency::total 281211000 # number of ReadReq MSHR miss cycles 171system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281211000 # number of demand (read+write) MSHR miss cycles 172system.cpu.icache.demand_mshr_miss_latency::total 281211000 # number of demand (read+write) MSHR miss cycles 173system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281211000 # number of overall MSHR miss cycles 174system.cpu.icache.overall_mshr_miss_latency::total 281211000 # number of overall MSHR miss cycles 175system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses 176system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses 177system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses 178system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses 179system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses 180system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses 181system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18022.880215 # average ReadReq mshr miss latency 182system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18022.880215 # average ReadReq mshr miss latency 183system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency 184system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency 185system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency 186system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency 187system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 188system.cpu.l2cache.tags.replacements 0 # number of replacements 189system.cpu.l2cache.tags.tagsinuse 3487.723791 # Cycle average of tags in use 190system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks. 191system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. 192system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks. 193system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 194system.cpu.l2cache.tags.occ_blocks::writebacks 341.616093 # Average occupied blocks per requestor 195system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.399470 # Average occupied blocks per requestor 196system.cpu.l2cache.tags.occ_blocks::cpu.data 737.708228 # Average occupied blocks per requestor 197system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy 198system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy 199system.cpu.l2cache.tags.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy 200system.cpu.l2cache.tags.occ_percent::total 0.106437 # Average percentage of cache occupancy 201system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits 202system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits 203system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits 204system.cpu.l2cache.Writeback_hits::writebacks 998 # number of Writeback hits 205system.cpu.l2cache.Writeback_hits::total 998 # number of Writeback hits 206system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits 207system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits 208system.cpu.l2cache.demand_hits::cpu.inst 12994 # number of demand (read+write) hits 209system.cpu.l2cache.demand_hits::cpu.data 255 # number of demand (read+write) hits 210system.cpu.l2cache.demand_hits::total 13249 # number of demand (read+write) hits 211system.cpu.l2cache.overall_hits::cpu.inst 12994 # number of overall hits 212system.cpu.l2cache.overall_hits::cpu.data 255 # number of overall hits 213system.cpu.l2cache.overall_hits::total 13249 # number of overall hits 214system.cpu.l2cache.ReadReq_misses::cpu.inst 2609 # number of ReadReq misses 215system.cpu.l2cache.ReadReq_misses::cpu.data 1367 # number of ReadReq misses 216system.cpu.l2cache.ReadReq_misses::total 3976 # number of ReadReq misses 217system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses 218system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses 219system.cpu.l2cache.demand_misses::cpu.inst 2609 # number of demand (read+write) misses 220system.cpu.l2cache.demand_misses::cpu.data 4223 # number of demand (read+write) misses 221system.cpu.l2cache.demand_misses::total 6832 # number of demand (read+write) misses 222system.cpu.l2cache.overall_misses::cpu.inst 2609 # number of overall misses 223system.cpu.l2cache.overall_misses::cpu.data 4223 # number of overall misses 224system.cpu.l2cache.overall_misses::total 6832 # number of overall misses 225system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135668000 # number of ReadReq miss cycles 226system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71084000 # number of ReadReq miss cycles 227system.cpu.l2cache.ReadReq_miss_latency::total 206752000 # number of ReadReq miss cycles 228system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148512000 # number of ReadExReq miss cycles 229system.cpu.l2cache.ReadExReq_miss_latency::total 148512000 # number of ReadExReq miss cycles 230system.cpu.l2cache.demand_miss_latency::cpu.inst 135668000 # number of demand (read+write) miss cycles 231system.cpu.l2cache.demand_miss_latency::cpu.data 219596000 # number of demand (read+write) miss cycles 232system.cpu.l2cache.demand_miss_latency::total 355264000 # number of demand (read+write) miss cycles 233system.cpu.l2cache.overall_miss_latency::cpu.inst 135668000 # number of overall miss cycles 234system.cpu.l2cache.overall_miss_latency::cpu.data 219596000 # number of overall miss cycles 235system.cpu.l2cache.overall_miss_latency::total 355264000 # number of overall miss cycles 236system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses) 237system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses) 238system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses) 239system.cpu.l2cache.Writeback_accesses::writebacks 998 # number of Writeback accesses(hits+misses) 240system.cpu.l2cache.Writeback_accesses::total 998 # number of Writeback accesses(hits+misses) 241system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses) 242system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses) 243system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses 244system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses 245system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses 246system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses 247system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses 248system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses 249system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.167211 # miss rate for ReadReq accesses 250system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.851183 # miss rate for ReadReq accesses 251system.cpu.l2cache.ReadReq_miss_rate::total 0.231042 # miss rate for ReadReq accesses 252system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses 253system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses 254system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167211 # miss rate for demand accesses 255system.cpu.l2cache.demand_miss_rate::cpu.data 0.943055 # miss rate for demand accesses 256system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses 257system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167211 # miss rate for overall accesses 258system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses 259system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses 260system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 261system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 262system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 263system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 264system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 265system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 266system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 267system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 268system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 269system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 270system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 271system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 272system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 273system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 274system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 275system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 276system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 277system.cpu.l2cache.fast_writes 0 # number of fast writes performed 278system.cpu.l2cache.cache_copies 0 # number of cache copies performed 279system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2609 # number of ReadReq MSHR misses 280system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1367 # number of ReadReq MSHR misses 281system.cpu.l2cache.ReadReq_mshr_misses::total 3976 # number of ReadReq MSHR misses 282system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses 283system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses 284system.cpu.l2cache.demand_mshr_misses::cpu.inst 2609 # number of demand (read+write) MSHR misses 285system.cpu.l2cache.demand_mshr_misses::cpu.data 4223 # number of demand (read+write) MSHR misses 286system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses 287system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses 288system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses 289system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses 290system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104360000 # number of ReadReq MSHR miss cycles 291system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles 292system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159040000 # number of ReadReq MSHR miss cycles 293system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114240000 # number of ReadExReq MSHR miss cycles 294system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114240000 # number of ReadExReq MSHR miss cycles 295system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104360000 # number of demand (read+write) MSHR miss cycles 296system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168920000 # number of demand (read+write) MSHR miss cycles 297system.cpu.l2cache.demand_mshr_miss_latency::total 273280000 # number of demand (read+write) MSHR miss cycles 298system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104360000 # number of overall MSHR miss cycles 299system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168920000 # number of overall MSHR miss cycles 300system.cpu.l2cache.overall_mshr_miss_latency::total 273280000 # number of overall MSHR miss cycles 301system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for ReadReq accesses 302system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses 303system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231042 # mshr miss rate for ReadReq accesses 304system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses 305system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses 306system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for demand accesses 307system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for demand accesses 308system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses 309system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for overall accesses 310system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses 311system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses 312system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 313system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 314system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 315system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 316system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 317system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 318system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 319system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 320system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 321system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 322system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 323system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 324system.cpu.dcache.tags.replacements 1332 # number of replacements 325system.cpu.dcache.tags.tagsinuse 3078.412981 # Cycle average of tags in use 326system.cpu.dcache.tags.total_refs 176641599 # Total number of references to valid blocks. 327system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. 328system.cpu.dcache.tags.avg_refs 39446.538410 # Average number of references to valid blocks. 329system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 330system.cpu.dcache.tags.occ_blocks::cpu.data 3078.412981 # Average occupied blocks per requestor 331system.cpu.dcache.tags.occ_percent::cpu.data 0.751566 # Average percentage of cache occupancy 332system.cpu.dcache.tags.occ_percent::total 0.751566 # Average percentage of cache occupancy 333system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits 334system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits 335system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits 336system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits 337system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits 338system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits 339system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 340system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits 341system.cpu.dcache.demand_hits::cpu.data 176619809 # number of demand (read+write) hits 342system.cpu.dcache.demand_hits::total 176619809 # number of demand (read+write) hits 343system.cpu.dcache.overall_hits::cpu.data 176619809 # number of overall hits 344system.cpu.dcache.overall_hits::total 176619809 # number of overall hits 345system.cpu.dcache.ReadReq_misses::cpu.data 1606 # number of ReadReq misses 346system.cpu.dcache.ReadReq_misses::total 1606 # number of ReadReq misses 347system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses 348system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses 349system.cpu.dcache.demand_misses::cpu.data 4478 # number of demand (read+write) misses 350system.cpu.dcache.demand_misses::total 4478 # number of demand (read+write) misses 351system.cpu.dcache.overall_misses::cpu.data 4478 # number of overall misses 352system.cpu.dcache.overall_misses::total 4478 # number of overall misses 353system.cpu.dcache.ReadReq_miss_latency::cpu.data 78292000 # number of ReadReq miss cycles 354system.cpu.dcache.ReadReq_miss_latency::total 78292000 # number of ReadReq miss cycles 355system.cpu.dcache.WriteReq_miss_latency::cpu.data 157288000 # number of WriteReq miss cycles 356system.cpu.dcache.WriteReq_miss_latency::total 157288000 # number of WriteReq miss cycles 357system.cpu.dcache.demand_miss_latency::cpu.data 235580000 # number of demand (read+write) miss cycles 358system.cpu.dcache.demand_miss_latency::total 235580000 # number of demand (read+write) miss cycles 359system.cpu.dcache.overall_miss_latency::cpu.data 235580000 # number of overall miss cycles 360system.cpu.dcache.overall_miss_latency::total 235580000 # number of overall miss cycles 361system.cpu.dcache.ReadReq_accesses::cpu.data 94571610 # number of ReadReq accesses(hits+misses) 362system.cpu.dcache.ReadReq_accesses::total 94571610 # number of ReadReq accesses(hits+misses) 363system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) 364system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) 365system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) 366system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) 367system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 368system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) 369system.cpu.dcache.demand_accesses::cpu.data 176624287 # number of demand (read+write) accesses 370system.cpu.dcache.demand_accesses::total 176624287 # number of demand (read+write) accesses 371system.cpu.dcache.overall_accesses::cpu.data 176624287 # number of overall (read+write) accesses 372system.cpu.dcache.overall_accesses::total 176624287 # number of overall (read+write) accesses 373system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses 374system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses 375system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses 376system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses 377system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses 378system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses 379system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses 380system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses 381system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48749.688667 # average ReadReq miss latency 382system.cpu.dcache.ReadReq_avg_miss_latency::total 48749.688667 # average ReadReq miss latency 383system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54766.016713 # average WriteReq miss latency 384system.cpu.dcache.WriteReq_avg_miss_latency::total 54766.016713 # average WriteReq miss latency 385system.cpu.dcache.demand_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency 386system.cpu.dcache.demand_avg_miss_latency::total 52608.307280 # average overall miss latency 387system.cpu.dcache.overall_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency 388system.cpu.dcache.overall_avg_miss_latency::total 52608.307280 # average overall miss latency 389system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 390system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 391system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 392system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 393system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 394system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 395system.cpu.dcache.fast_writes 0 # number of fast writes performed 396system.cpu.dcache.cache_copies 0 # number of cache copies performed 397system.cpu.dcache.writebacks::writebacks 998 # number of writebacks 398system.cpu.dcache.writebacks::total 998 # number of writebacks 399system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1606 # number of ReadReq MSHR misses 400system.cpu.dcache.ReadReq_mshr_misses::total 1606 # number of ReadReq MSHR misses 401system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses 402system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses 403system.cpu.dcache.demand_mshr_misses::cpu.data 4478 # number of demand (read+write) MSHR misses 404system.cpu.dcache.demand_mshr_misses::total 4478 # number of demand (read+write) MSHR misses 405system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses 406system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses 407system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75080000 # number of ReadReq MSHR miss cycles 408system.cpu.dcache.ReadReq_mshr_miss_latency::total 75080000 # number of ReadReq MSHR miss cycles 409system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151544000 # number of WriteReq MSHR miss cycles 410system.cpu.dcache.WriteReq_mshr_miss_latency::total 151544000 # number of WriteReq MSHR miss cycles 411system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226624000 # number of demand (read+write) MSHR miss cycles 412system.cpu.dcache.demand_mshr_miss_latency::total 226624000 # number of demand (read+write) MSHR miss cycles 413system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226624000 # number of overall MSHR miss cycles 414system.cpu.dcache.overall_mshr_miss_latency::total 226624000 # number of overall MSHR miss cycles 415system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000017 # mshr miss rate for ReadReq accesses 416system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses 417system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses 418system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 419system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses 420system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses 421system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses 422system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses 423system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667 # average ReadReq mshr miss latency 424system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46749.688667 # average ReadReq mshr miss latency 425system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713 # average WriteReq mshr miss latency 426system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52766.016713 # average WriteReq mshr miss latency 427system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency 428system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency 429system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency 430system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency 431system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 432system.cpu.toL2Bus.throughput 2565553 # Throughput (bytes/s) 433system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution 434system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution 435system.cpu.toL2Bus.trans_dist::Writeback 998 # Transaction distribution 436system.cpu.toL2Bus.trans_dist::ReadExReq 2872 # Transaction distribution 437system.cpu.toL2Bus.trans_dist::ReadExResp 2872 # Transaction distribution 438system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 31206 # Packet count per connected master and slave (bytes) 439system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 9954 # Packet count per connected master and slave (bytes) 440system.cpu.toL2Bus.pkt_count 41160 # Packet count per connected master and slave (bytes) 441system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 998592 # Cumulative packet size per connected master and slave (bytes) 442system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 350464 # Cumulative packet size per connected master and slave (bytes) 443system.cpu.toL2Bus.tot_pkt_size 1349056 # Cumulative packet size per connected master and slave (bytes) 444system.cpu.toL2Bus.data_through_bus 1349056 # Total data (bytes) 445system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 446system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks) 447system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 448system.cpu.toL2Bus.respLayer0.occupancy 23404500 # Layer occupancy (ticks) 449system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 450system.cpu.toL2Bus.respLayer1.occupancy 6717000 # Layer occupancy (ticks) 451system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 452 453---------- End Simulation Statistics ---------- 454