stats.txt revision 9481:b0fa6b872f40
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.525834 # Number of seconds simulated 4sim_ticks 525834342000 # Number of ticks simulated 5final_tick 525834342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 589682 # Simulator instruction rate (inst/s) 8host_op_rate 753887 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1136891744 # Simulator tick rate (ticks/s) 10host_mem_usage 294668 # Number of bytes of host memory used 11host_seconds 462.52 # Real time elapsed on the host 12sim_insts 272739283 # Number of instructions simulated 13sim_ops 348687122 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 270272 # Number of bytes read from this memory 16system.physmem.bytes_read::total 437248 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 166976 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 166976 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 2609 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 4223 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 317545 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 513987 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 831532 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 317545 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 317545 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 317545 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 513987 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 831532 # Total bandwidth to/from this memory (bytes/s) 30system.cpu.dtb.inst_hits 0 # ITB inst hits 31system.cpu.dtb.inst_misses 0 # ITB inst misses 32system.cpu.dtb.read_hits 0 # DTB read hits 33system.cpu.dtb.read_misses 0 # DTB read misses 34system.cpu.dtb.write_hits 0 # DTB write hits 35system.cpu.dtb.write_misses 0 # DTB write misses 36system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 37system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 38system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 39system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 40system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 41system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 42system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 43system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 44system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 45system.cpu.dtb.read_accesses 0 # DTB read accesses 46system.cpu.dtb.write_accesses 0 # DTB write accesses 47system.cpu.dtb.inst_accesses 0 # ITB inst accesses 48system.cpu.dtb.hits 0 # DTB hits 49system.cpu.dtb.misses 0 # DTB misses 50system.cpu.dtb.accesses 0 # DTB accesses 51system.cpu.itb.inst_hits 0 # ITB inst hits 52system.cpu.itb.inst_misses 0 # ITB inst misses 53system.cpu.itb.read_hits 0 # DTB read hits 54system.cpu.itb.read_misses 0 # DTB read misses 55system.cpu.itb.write_hits 0 # DTB write hits 56system.cpu.itb.write_misses 0 # DTB write misses 57system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 58system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 59system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 60system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 61system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 62system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 63system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 64system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 65system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 66system.cpu.itb.read_accesses 0 # DTB read accesses 67system.cpu.itb.write_accesses 0 # DTB write accesses 68system.cpu.itb.inst_accesses 0 # ITB inst accesses 69system.cpu.itb.hits 0 # DTB hits 70system.cpu.itb.misses 0 # DTB misses 71system.cpu.itb.accesses 0 # DTB accesses 72system.cpu.workload.num_syscalls 191 # Number of system calls 73system.cpu.numCycles 1051668684 # number of cpu cycles simulated 74system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 75system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 76system.cpu.committedInsts 272739283 # Number of instructions committed 77system.cpu.committedOps 348687122 # Number of ops (including micro ops) committed 78system.cpu.num_int_alu_accesses 279584917 # Number of integer alu accesses 79system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses 80system.cpu.num_func_calls 12448615 # number of times a function call or return occured 81system.cpu.num_conditional_control_insts 18105896 # number of instructions that are conditional controls 82system.cpu.num_int_insts 279584917 # number of integer instructions 83system.cpu.num_fp_insts 114216705 # number of float instructions 84system.cpu.num_int_register_reads 2212913168 # number of times the integer registers were read 85system.cpu.num_int_register_writes 251197902 # number of times the integer registers were written 86system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read 87system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written 88system.cpu.num_mem_refs 177024356 # number of memory refs 89system.cpu.num_load_insts 94648757 # Number of load instructions 90system.cpu.num_store_insts 82375599 # Number of store instructions 91system.cpu.num_idle_cycles 0 # Number of idle cycles 92system.cpu.num_busy_cycles 1051668684 # Number of busy cycles 93system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 94system.cpu.idle_fraction 0 # Percentage of idle cycles 95system.cpu.icache.replacements 13796 # number of replacements 96system.cpu.icache.tagsinuse 1765.993223 # Cycle average of tags in use 97system.cpu.icache.total_refs 348644747 # Total number of references to valid blocks. 98system.cpu.icache.sampled_refs 15603 # Sample count of references to valid blocks. 99system.cpu.icache.avg_refs 22344.725181 # Average number of references to valid blocks. 100system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 101system.cpu.icache.occ_blocks::cpu.inst 1765.993223 # Average occupied blocks per requestor 102system.cpu.icache.occ_percent::cpu.inst 0.862301 # Average percentage of cache occupancy 103system.cpu.icache.occ_percent::total 0.862301 # Average percentage of cache occupancy 104system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits 105system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits 106system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits 107system.cpu.icache.demand_hits::total 348644747 # number of demand (read+write) hits 108system.cpu.icache.overall_hits::cpu.inst 348644747 # number of overall hits 109system.cpu.icache.overall_hits::total 348644747 # number of overall hits 110system.cpu.icache.ReadReq_misses::cpu.inst 15603 # number of ReadReq misses 111system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses 112system.cpu.icache.demand_misses::cpu.inst 15603 # number of demand (read+write) misses 113system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses 114system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses 115system.cpu.icache.overall_misses::total 15603 # number of overall misses 116system.cpu.icache.ReadReq_miss_latency::cpu.inst 312417000 # number of ReadReq miss cycles 117system.cpu.icache.ReadReq_miss_latency::total 312417000 # number of ReadReq miss cycles 118system.cpu.icache.demand_miss_latency::cpu.inst 312417000 # number of demand (read+write) miss cycles 119system.cpu.icache.demand_miss_latency::total 312417000 # number of demand (read+write) miss cycles 120system.cpu.icache.overall_miss_latency::cpu.inst 312417000 # number of overall miss cycles 121system.cpu.icache.overall_miss_latency::total 312417000 # number of overall miss cycles 122system.cpu.icache.ReadReq_accesses::cpu.inst 348660350 # number of ReadReq accesses(hits+misses) 123system.cpu.icache.ReadReq_accesses::total 348660350 # number of ReadReq accesses(hits+misses) 124system.cpu.icache.demand_accesses::cpu.inst 348660350 # number of demand (read+write) accesses 125system.cpu.icache.demand_accesses::total 348660350 # number of demand (read+write) accesses 126system.cpu.icache.overall_accesses::cpu.inst 348660350 # number of overall (read+write) accesses 127system.cpu.icache.overall_accesses::total 348660350 # number of overall (read+write) accesses 128system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses 129system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses 130system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses 131system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses 132system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses 133system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses 134system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20022.880215 # average ReadReq miss latency 135system.cpu.icache.ReadReq_avg_miss_latency::total 20022.880215 # average ReadReq miss latency 136system.cpu.icache.demand_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency 137system.cpu.icache.demand_avg_miss_latency::total 20022.880215 # average overall miss latency 138system.cpu.icache.overall_avg_miss_latency::cpu.inst 20022.880215 # average overall miss latency 139system.cpu.icache.overall_avg_miss_latency::total 20022.880215 # average overall miss latency 140system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 141system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 142system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 143system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 144system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 145system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 146system.cpu.icache.fast_writes 0 # number of fast writes performed 147system.cpu.icache.cache_copies 0 # number of cache copies performed 148system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15603 # number of ReadReq MSHR misses 149system.cpu.icache.ReadReq_mshr_misses::total 15603 # number of ReadReq MSHR misses 150system.cpu.icache.demand_mshr_misses::cpu.inst 15603 # number of demand (read+write) MSHR misses 151system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses 152system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses 153system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses 154system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281211000 # number of ReadReq MSHR miss cycles 155system.cpu.icache.ReadReq_mshr_miss_latency::total 281211000 # number of ReadReq MSHR miss cycles 156system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281211000 # number of demand (read+write) MSHR miss cycles 157system.cpu.icache.demand_mshr_miss_latency::total 281211000 # number of demand (read+write) MSHR miss cycles 158system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281211000 # number of overall MSHR miss cycles 159system.cpu.icache.overall_mshr_miss_latency::total 281211000 # number of overall MSHR miss cycles 160system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses 161system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses 162system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses 163system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses 164system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses 165system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses 166system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18022.880215 # average ReadReq mshr miss latency 167system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18022.880215 # average ReadReq mshr miss latency 168system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency 169system.cpu.icache.demand_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency 170system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18022.880215 # average overall mshr miss latency 171system.cpu.icache.overall_avg_mshr_miss_latency::total 18022.880215 # average overall mshr miss latency 172system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 173system.cpu.l2cache.replacements 0 # number of replacements 174system.cpu.l2cache.tagsinuse 3487.723791 # Cycle average of tags in use 175system.cpu.l2cache.total_refs 13310 # Total number of references to valid blocks. 176system.cpu.l2cache.sampled_refs 4882 # Sample count of references to valid blocks. 177system.cpu.l2cache.avg_refs 2.726342 # Average number of references to valid blocks. 178system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 179system.cpu.l2cache.occ_blocks::writebacks 341.616093 # Average occupied blocks per requestor 180system.cpu.l2cache.occ_blocks::cpu.inst 2408.399470 # Average occupied blocks per requestor 181system.cpu.l2cache.occ_blocks::cpu.data 737.708228 # Average occupied blocks per requestor 182system.cpu.l2cache.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy 183system.cpu.l2cache.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy 184system.cpu.l2cache.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy 185system.cpu.l2cache.occ_percent::total 0.106437 # Average percentage of cache occupancy 186system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits 187system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits 188system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits 189system.cpu.l2cache.Writeback_hits::writebacks 998 # number of Writeback hits 190system.cpu.l2cache.Writeback_hits::total 998 # number of Writeback hits 191system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits 192system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits 193system.cpu.l2cache.demand_hits::cpu.inst 12994 # number of demand (read+write) hits 194system.cpu.l2cache.demand_hits::cpu.data 255 # number of demand (read+write) hits 195system.cpu.l2cache.demand_hits::total 13249 # number of demand (read+write) hits 196system.cpu.l2cache.overall_hits::cpu.inst 12994 # number of overall hits 197system.cpu.l2cache.overall_hits::cpu.data 255 # number of overall hits 198system.cpu.l2cache.overall_hits::total 13249 # number of overall hits 199system.cpu.l2cache.ReadReq_misses::cpu.inst 2609 # number of ReadReq misses 200system.cpu.l2cache.ReadReq_misses::cpu.data 1367 # number of ReadReq misses 201system.cpu.l2cache.ReadReq_misses::total 3976 # number of ReadReq misses 202system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses 203system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses 204system.cpu.l2cache.demand_misses::cpu.inst 2609 # number of demand (read+write) misses 205system.cpu.l2cache.demand_misses::cpu.data 4223 # number of demand (read+write) misses 206system.cpu.l2cache.demand_misses::total 6832 # number of demand (read+write) misses 207system.cpu.l2cache.overall_misses::cpu.inst 2609 # number of overall misses 208system.cpu.l2cache.overall_misses::cpu.data 4223 # number of overall misses 209system.cpu.l2cache.overall_misses::total 6832 # number of overall misses 210system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135668000 # number of ReadReq miss cycles 211system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71084000 # number of ReadReq miss cycles 212system.cpu.l2cache.ReadReq_miss_latency::total 206752000 # number of ReadReq miss cycles 213system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148512000 # number of ReadExReq miss cycles 214system.cpu.l2cache.ReadExReq_miss_latency::total 148512000 # number of ReadExReq miss cycles 215system.cpu.l2cache.demand_miss_latency::cpu.inst 135668000 # number of demand (read+write) miss cycles 216system.cpu.l2cache.demand_miss_latency::cpu.data 219596000 # number of demand (read+write) miss cycles 217system.cpu.l2cache.demand_miss_latency::total 355264000 # number of demand (read+write) miss cycles 218system.cpu.l2cache.overall_miss_latency::cpu.inst 135668000 # number of overall miss cycles 219system.cpu.l2cache.overall_miss_latency::cpu.data 219596000 # number of overall miss cycles 220system.cpu.l2cache.overall_miss_latency::total 355264000 # number of overall miss cycles 221system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses) 222system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses) 223system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses) 224system.cpu.l2cache.Writeback_accesses::writebacks 998 # number of Writeback accesses(hits+misses) 225system.cpu.l2cache.Writeback_accesses::total 998 # number of Writeback accesses(hits+misses) 226system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses) 227system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses) 228system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses 229system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses 230system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses 231system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses 232system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses 233system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses 234system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.167211 # miss rate for ReadReq accesses 235system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.851183 # miss rate for ReadReq accesses 236system.cpu.l2cache.ReadReq_miss_rate::total 0.231042 # miss rate for ReadReq accesses 237system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses 238system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429 # miss rate for ReadExReq accesses 239system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167211 # miss rate for demand accesses 240system.cpu.l2cache.demand_miss_rate::cpu.data 0.943055 # miss rate for demand accesses 241system.cpu.l2cache.demand_miss_rate::total 0.340222 # miss rate for demand accesses 242system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167211 # miss rate for overall accesses 243system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses 244system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses 245system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 246system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 247system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 248system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 249system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 250system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 251system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 252system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 253system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 254system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 255system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency 256system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 257system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 258system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 259system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 260system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 261system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 262system.cpu.l2cache.fast_writes 0 # number of fast writes performed 263system.cpu.l2cache.cache_copies 0 # number of cache copies performed 264system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2609 # number of ReadReq MSHR misses 265system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1367 # number of ReadReq MSHR misses 266system.cpu.l2cache.ReadReq_mshr_misses::total 3976 # number of ReadReq MSHR misses 267system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses 268system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses 269system.cpu.l2cache.demand_mshr_misses::cpu.inst 2609 # number of demand (read+write) MSHR misses 270system.cpu.l2cache.demand_mshr_misses::cpu.data 4223 # number of demand (read+write) MSHR misses 271system.cpu.l2cache.demand_mshr_misses::total 6832 # number of demand (read+write) MSHR misses 272system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses 273system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses 274system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses 275system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104360000 # number of ReadReq MSHR miss cycles 276system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles 277system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159040000 # number of ReadReq MSHR miss cycles 278system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114240000 # number of ReadExReq MSHR miss cycles 279system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114240000 # number of ReadExReq MSHR miss cycles 280system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104360000 # number of demand (read+write) MSHR miss cycles 281system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168920000 # number of demand (read+write) MSHR miss cycles 282system.cpu.l2cache.demand_mshr_miss_latency::total 273280000 # number of demand (read+write) MSHR miss cycles 283system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104360000 # number of overall MSHR miss cycles 284system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168920000 # number of overall MSHR miss cycles 285system.cpu.l2cache.overall_mshr_miss_latency::total 273280000 # number of overall MSHR miss cycles 286system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for ReadReq accesses 287system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses 288system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231042 # mshr miss rate for ReadReq accesses 289system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses 290system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429 # mshr miss rate for ReadExReq accesses 291system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for demand accesses 292system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for demand accesses 293system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 # mshr miss rate for demand accesses 294system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for overall accesses 295system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses 296system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses 297system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 298system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 299system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 300system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 301system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 302system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 303system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 304system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 305system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 306system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 307system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 308system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 309system.cpu.dcache.replacements 1332 # number of replacements 310system.cpu.dcache.tagsinuse 3078.412981 # Cycle average of tags in use 311system.cpu.dcache.total_refs 176641599 # Total number of references to valid blocks. 312system.cpu.dcache.sampled_refs 4478 # Sample count of references to valid blocks. 313system.cpu.dcache.avg_refs 39446.538410 # Average number of references to valid blocks. 314system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 315system.cpu.dcache.occ_blocks::cpu.data 3078.412981 # Average occupied blocks per requestor 316system.cpu.dcache.occ_percent::cpu.data 0.751566 # Average percentage of cache occupancy 317system.cpu.dcache.occ_percent::total 0.751566 # Average percentage of cache occupancy 318system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits 319system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits 320system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits 321system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits 322system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits 323system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits 324system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits 325system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits 326system.cpu.dcache.demand_hits::cpu.data 176619809 # number of demand (read+write) hits 327system.cpu.dcache.demand_hits::total 176619809 # number of demand (read+write) hits 328system.cpu.dcache.overall_hits::cpu.data 176619809 # number of overall hits 329system.cpu.dcache.overall_hits::total 176619809 # number of overall hits 330system.cpu.dcache.ReadReq_misses::cpu.data 1606 # number of ReadReq misses 331system.cpu.dcache.ReadReq_misses::total 1606 # number of ReadReq misses 332system.cpu.dcache.WriteReq_misses::cpu.data 2872 # number of WriteReq misses 333system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses 334system.cpu.dcache.demand_misses::cpu.data 4478 # number of demand (read+write) misses 335system.cpu.dcache.demand_misses::total 4478 # number of demand (read+write) misses 336system.cpu.dcache.overall_misses::cpu.data 4478 # number of overall misses 337system.cpu.dcache.overall_misses::total 4478 # number of overall misses 338system.cpu.dcache.ReadReq_miss_latency::cpu.data 78292000 # number of ReadReq miss cycles 339system.cpu.dcache.ReadReq_miss_latency::total 78292000 # number of ReadReq miss cycles 340system.cpu.dcache.WriteReq_miss_latency::cpu.data 157288000 # number of WriteReq miss cycles 341system.cpu.dcache.WriteReq_miss_latency::total 157288000 # number of WriteReq miss cycles 342system.cpu.dcache.demand_miss_latency::cpu.data 235580000 # number of demand (read+write) miss cycles 343system.cpu.dcache.demand_miss_latency::total 235580000 # number of demand (read+write) miss cycles 344system.cpu.dcache.overall_miss_latency::cpu.data 235580000 # number of overall miss cycles 345system.cpu.dcache.overall_miss_latency::total 235580000 # number of overall miss cycles 346system.cpu.dcache.ReadReq_accesses::cpu.data 94571610 # number of ReadReq accesses(hits+misses) 347system.cpu.dcache.ReadReq_accesses::total 94571610 # number of ReadReq accesses(hits+misses) 348system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) 349system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) 350system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) 351system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) 352system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) 353system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) 354system.cpu.dcache.demand_accesses::cpu.data 176624287 # number of demand (read+write) accesses 355system.cpu.dcache.demand_accesses::total 176624287 # number of demand (read+write) accesses 356system.cpu.dcache.overall_accesses::cpu.data 176624287 # number of overall (read+write) accesses 357system.cpu.dcache.overall_accesses::total 176624287 # number of overall (read+write) accesses 358system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000017 # miss rate for ReadReq accesses 359system.cpu.dcache.ReadReq_miss_rate::total 0.000017 # miss rate for ReadReq accesses 360system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000035 # miss rate for WriteReq accesses 361system.cpu.dcache.WriteReq_miss_rate::total 0.000035 # miss rate for WriteReq accesses 362system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses 363system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses 364system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses 365system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses 366system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48749.688667 # average ReadReq miss latency 367system.cpu.dcache.ReadReq_avg_miss_latency::total 48749.688667 # average ReadReq miss latency 368system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54766.016713 # average WriteReq miss latency 369system.cpu.dcache.WriteReq_avg_miss_latency::total 54766.016713 # average WriteReq miss latency 370system.cpu.dcache.demand_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency 371system.cpu.dcache.demand_avg_miss_latency::total 52608.307280 # average overall miss latency 372system.cpu.dcache.overall_avg_miss_latency::cpu.data 52608.307280 # average overall miss latency 373system.cpu.dcache.overall_avg_miss_latency::total 52608.307280 # average overall miss latency 374system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 375system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 376system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 377system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 378system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 379system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 380system.cpu.dcache.fast_writes 0 # number of fast writes performed 381system.cpu.dcache.cache_copies 0 # number of cache copies performed 382system.cpu.dcache.writebacks::writebacks 998 # number of writebacks 383system.cpu.dcache.writebacks::total 998 # number of writebacks 384system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1606 # number of ReadReq MSHR misses 385system.cpu.dcache.ReadReq_mshr_misses::total 1606 # number of ReadReq MSHR misses 386system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses 387system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses 388system.cpu.dcache.demand_mshr_misses::cpu.data 4478 # number of demand (read+write) MSHR misses 389system.cpu.dcache.demand_mshr_misses::total 4478 # number of demand (read+write) MSHR misses 390system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses 391system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses 392system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75080000 # number of ReadReq MSHR miss cycles 393system.cpu.dcache.ReadReq_mshr_miss_latency::total 75080000 # number of ReadReq MSHR miss cycles 394system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151544000 # number of WriteReq MSHR miss cycles 395system.cpu.dcache.WriteReq_mshr_miss_latency::total 151544000 # number of WriteReq MSHR miss cycles 396system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226624000 # number of demand (read+write) MSHR miss cycles 397system.cpu.dcache.demand_mshr_miss_latency::total 226624000 # number of demand (read+write) MSHR miss cycles 398system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226624000 # number of overall MSHR miss cycles 399system.cpu.dcache.overall_mshr_miss_latency::total 226624000 # number of overall MSHR miss cycles 400system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000017 # mshr miss rate for ReadReq accesses 401system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000017 # mshr miss rate for ReadReq accesses 402system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses 403system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000035 # mshr miss rate for WriteReq accesses 404system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses 405system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses 406system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses 407system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses 408system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667 # average ReadReq mshr miss latency 409system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46749.688667 # average ReadReq mshr miss latency 410system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713 # average WriteReq mshr miss latency 411system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52766.016713 # average WriteReq mshr miss latency 412system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency 413system.cpu.dcache.demand_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency 414system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280 # average overall mshr miss latency 415system.cpu.dcache.overall_avg_mshr_miss_latency::total 50608.307280 # average overall mshr miss latency 416system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 417 418---------- End Simulation Statistics ---------- 419