stats.txt revision 11606
111507SCurtis.Dunham@arm.com 211507SCurtis.Dunham@arm.com---------- Begin Simulation Statistics ---------- 311606Sandreas.sandberg@arm.comsim_seconds 0.366632 # Number of seconds simulated 411606Sandreas.sandberg@arm.comsim_ticks 366631719500 # Number of ticks simulated 511606Sandreas.sandberg@arm.comfinal_tick 366631719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611507SCurtis.Dunham@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711606Sandreas.sandberg@arm.comhost_inst_rate 211005 # Simulator instruction rate (inst/s) 811606Sandreas.sandberg@arm.comhost_op_rate 228546 # Simulator op (including micro ops) rate (op/s) 911606Sandreas.sandberg@arm.comhost_tick_rate 152712719 # Simulator tick rate (ticks/s) 1011606Sandreas.sandberg@arm.comhost_mem_usage 277288 # Number of bytes of host memory used 1111606Sandreas.sandberg@arm.comhost_seconds 2400.79 # Real time elapsed on the host 1211507SCurtis.Dunham@arm.comsim_insts 506579366 # Number of instructions simulated 1311507SCurtis.Dunham@arm.comsim_ops 548692589 # Number of ops (including micro ops) simulated 1411507SCurtis.Dunham@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511507SCurtis.Dunham@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611606Sandreas.sandberg@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 1711570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.inst 179840 # Number of bytes read from this memory 1811606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::cpu.data 9053376 # Number of bytes read from this memory 1911606Sandreas.sandberg@arm.comsystem.physmem.bytes_read::total 9233216 # Number of bytes read from this memory 2011570SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu.inst 179840 # Number of instructions bytes read from this memory 2111570SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 179840 # Number of instructions bytes read from this memory 2211606Sandreas.sandberg@arm.comsystem.physmem.bytes_written::writebacks 6241792 # Number of bytes written to this memory 2311606Sandreas.sandberg@arm.comsystem.physmem.bytes_written::total 6241792 # Number of bytes written to this memory 2411570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.inst 2810 # Number of read requests responded to by this memory 2511606Sandreas.sandberg@arm.comsystem.physmem.num_reads::cpu.data 141459 # Number of read requests responded to by this memory 2611606Sandreas.sandberg@arm.comsystem.physmem.num_reads::total 144269 # Number of read requests responded to by this memory 2711606Sandreas.sandberg@arm.comsystem.physmem.num_writes::writebacks 97528 # Number of write requests responded to by this memory 2811606Sandreas.sandberg@arm.comsystem.physmem.num_writes::total 97528 # Number of write requests responded to by this memory 2911606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu.inst 490519 # Total read bandwidth from this memory (bytes/s) 3011606Sandreas.sandberg@arm.comsystem.physmem.bw_read::cpu.data 24693379 # Total read bandwidth from this memory (bytes/s) 3111606Sandreas.sandberg@arm.comsystem.physmem.bw_read::total 25183898 # Total read bandwidth from this memory (bytes/s) 3211606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::cpu.inst 490519 # Instruction read bandwidth from this memory (bytes/s) 3311606Sandreas.sandberg@arm.comsystem.physmem.bw_inst_read::total 490519 # Instruction read bandwidth from this memory (bytes/s) 3411606Sandreas.sandberg@arm.comsystem.physmem.bw_write::writebacks 17024692 # Write bandwidth from this memory (bytes/s) 3511606Sandreas.sandberg@arm.comsystem.physmem.bw_write::total 17024692 # Write bandwidth from this memory (bytes/s) 3611606Sandreas.sandberg@arm.comsystem.physmem.bw_total::writebacks 17024692 # Total bandwidth to/from this memory (bytes/s) 3711606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu.inst 490519 # Total bandwidth to/from this memory (bytes/s) 3811606Sandreas.sandberg@arm.comsystem.physmem.bw_total::cpu.data 24693379 # Total bandwidth to/from this memory (bytes/s) 3911606Sandreas.sandberg@arm.comsystem.physmem.bw_total::total 42208590 # Total bandwidth to/from this memory (bytes/s) 4011606Sandreas.sandberg@arm.comsystem.physmem.readReqs 144269 # Number of read requests accepted 4111606Sandreas.sandberg@arm.comsystem.physmem.writeReqs 97528 # Number of write requests accepted 4211606Sandreas.sandberg@arm.comsystem.physmem.readBursts 144269 # Number of DRAM read bursts, including those serviced by the write queue 4311606Sandreas.sandberg@arm.comsystem.physmem.writeBursts 97528 # Number of DRAM write bursts, including those merged in the write queue 4411606Sandreas.sandberg@arm.comsystem.physmem.bytesReadDRAM 9226688 # Total number of bytes read from DRAM 4511606Sandreas.sandberg@arm.comsystem.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue 4611606Sandreas.sandberg@arm.comsystem.physmem.bytesWritten 6240064 # Total number of bytes written to DRAM 4711606Sandreas.sandberg@arm.comsystem.physmem.bytesReadSys 9233216 # Total read bytes from the system interface side 4811606Sandreas.sandberg@arm.comsystem.physmem.bytesWrittenSys 6241792 # Total written bytes from the system interface side 4911606Sandreas.sandberg@arm.comsystem.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue 5011507SCurtis.Dunham@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 5111507SCurtis.Dunham@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 5211606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::0 9376 # Per bank write bursts 5311606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::1 8929 # Per bank write bursts 5411606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::2 8964 # Per bank write bursts 5511606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::3 8666 # Per bank write bursts 5611606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::4 9423 # Per bank write bursts 5711606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::5 9371 # Per bank write bursts 5811606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::6 8974 # Per bank write bursts 5911606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::7 8126 # Per bank write bursts 6011606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::8 8634 # Per bank write bursts 6111606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::9 8697 # Per bank write bursts 6211606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::10 8760 # Per bank write bursts 6311606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::11 9487 # Per bank write bursts 6411606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::12 9347 # Per bank write bursts 6511606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::13 9550 # Per bank write bursts 6611606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::14 8728 # Per bank write bursts 6711606Sandreas.sandberg@arm.comsystem.physmem.perBankRdBursts::15 9135 # Per bank write bursts 6811606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::0 6252 # Per bank write bursts 6911606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::1 6118 # Per bank write bursts 7011606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::2 6042 # Per bank write bursts 7111606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::3 5901 # Per bank write bursts 7211606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::4 6273 # Per bank write bursts 7311606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::5 6263 # Per bank write bursts 7411606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::6 6069 # Per bank write bursts 7511606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::7 5534 # Per bank write bursts 7611606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::8 5815 # Per bank write bursts 7711606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::9 5920 # Per bank write bursts 7811606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::10 5985 # Per bank write bursts 7911606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::11 6510 # Per bank write bursts 8011606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::12 6360 # Per bank write bursts 8111606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::13 6344 # Per bank write bursts 8211606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::14 6013 # Per bank write bursts 8311606Sandreas.sandberg@arm.comsystem.physmem.perBankWrBursts::15 6102 # Per bank write bursts 8411507SCurtis.Dunham@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 8511507SCurtis.Dunham@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 8611606Sandreas.sandberg@arm.comsystem.physmem.totGap 366631694000 # Total gap between requests 8711507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 8811507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 8911507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 9011507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 9111507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 9211507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 9311606Sandreas.sandberg@arm.comsystem.physmem.readPktSize::6 144269 # Read request sizes (log2) 9411507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 9511507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 9611507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 9711507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 9811507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 9911507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 10011606Sandreas.sandberg@arm.comsystem.physmem.writePktSize::6 97528 # Write request sizes (log2) 10111606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::0 143840 # What read queue length does an incoming req see 10211606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::1 311 # What read queue length does an incoming req see 10311606Sandreas.sandberg@arm.comsystem.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see 10411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 10511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 10611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 10711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 10811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 10911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 11011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 11111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 11211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 11311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 11411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 11511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 11611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 11711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 11811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 11911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 12011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 12111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 12211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 12311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 12411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 12511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 12611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 12711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 12811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 12911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 13011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 13111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 13211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 13311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 13411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 13511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 13611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 13711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 13811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 13911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 14011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 14111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 14211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 14311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 14411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 14511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 14611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 14711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 14811606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::15 2842 # What write queue length does an incoming req see 14911606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::16 2979 # What write queue length does an incoming req see 15011606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::17 5670 # What write queue length does an incoming req see 15111606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::18 5725 # What write queue length does an incoming req see 15211606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::19 5731 # What write queue length does an incoming req see 15311606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::20 5730 # What write queue length does an incoming req see 15411606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::21 5730 # What write queue length does an incoming req see 15511606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::22 5734 # What write queue length does an incoming req see 15611606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::23 5731 # What write queue length does an incoming req see 15711606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::24 5736 # What write queue length does an incoming req see 15811606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::25 5741 # What write queue length does an incoming req see 15911606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::26 5739 # What write queue length does an incoming req see 16011606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::27 5746 # What write queue length does an incoming req see 16111606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::28 5754 # What write queue length does an incoming req see 16211606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::29 5737 # What write queue length does an incoming req see 16311606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::30 5732 # What write queue length does an incoming req see 16411606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::31 5729 # What write queue length does an incoming req see 16511606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::32 5727 # What write queue length does an incoming req see 16611606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 16711606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16811606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16911606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 17011606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 17111606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 17211606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 17311606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 17411606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 17511606Sandreas.sandberg@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 17611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 18011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 18111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 18211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 18311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 18411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 18511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 18611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 19011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 19111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 19211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 19311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 19411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 19511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 19611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19711606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::samples 63306 # Bytes accessed per row activation 19811606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::mean 244.314283 # Bytes accessed per row activation 19911606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::gmean 163.017060 # Bytes accessed per row activation 20011606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::stdev 244.594379 # Bytes accessed per row activation 20111606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::0-127 22538 35.60% 35.60% # Bytes accessed per row activation 20211606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::128-255 17961 28.37% 63.97% # Bytes accessed per row activation 20311606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::256-383 7327 11.57% 75.55% # Bytes accessed per row activation 20411606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::384-511 7996 12.63% 88.18% # Bytes accessed per row activation 20511606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::512-639 2051 3.24% 91.42% # Bytes accessed per row activation 20611606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::640-767 1180 1.86% 93.28% # Bytes accessed per row activation 20711606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::768-895 835 1.32% 94.60% # Bytes accessed per row activation 20811606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::896-1023 660 1.04% 95.64% # Bytes accessed per row activation 20911606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::1024-1151 2758 4.36% 100.00% # Bytes accessed per row activation 21011606Sandreas.sandberg@arm.comsystem.physmem.bytesPerActivate::total 63306 # Bytes accessed per row activation 21111606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::samples 5727 # Reads before turning the bus around for writes 21211606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::mean 25.172342 # Reads before turning the bus around for writes 21311606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::gmean 18.597400 # Reads before turning the bus around for writes 21411606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::stdev 376.088417 # Reads before turning the bus around for writes 21511606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::0-1023 5724 99.95% 99.95% # Reads before turning the bus around for writes 21611606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.98% # Reads before turning the bus around for writes 21711507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes 21811606Sandreas.sandberg@arm.comsystem.physmem.rdPerTurnAround::total 5727 # Reads before turning the bus around for writes 21911606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::samples 5727 # Writes before turning the bus around for reads 22011606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::mean 17.024795 # Writes before turning the bus around for reads 22111606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::gmean 16.995243 # Writes before turning the bus around for reads 22211606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::stdev 1.004050 # Writes before turning the bus around for reads 22311606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::16 2743 47.90% 47.90% # Writes before turning the bus around for reads 22411606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::17 142 2.48% 50.38% # Writes before turning the bus around for reads 22511606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::18 2814 49.14% 99.51% # Writes before turning the bus around for reads 22611606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::19 20 0.35% 99.86% # Writes before turning the bus around for reads 22711606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::20 6 0.10% 99.97% # Writes before turning the bus around for reads 22811606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::23 1 0.02% 99.98% # Writes before turning the bus around for reads 22911606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads 23011606Sandreas.sandberg@arm.comsystem.physmem.wrPerTurnAround::total 5727 # Writes before turning the bus around for reads 23111606Sandreas.sandberg@arm.comsystem.physmem.totQLat 1581653750 # Total ticks spent queuing 23211606Sandreas.sandberg@arm.comsystem.physmem.totMemAccLat 4284785000 # Total ticks spent from burst creation until serviced by the DRAM 23311606Sandreas.sandberg@arm.comsystem.physmem.totBusLat 720835000 # Total ticks spent in databus transfers 23411606Sandreas.sandberg@arm.comsystem.physmem.avgQLat 10970.98 # Average queueing delay per DRAM burst 23511507SCurtis.Dunham@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 23611606Sandreas.sandberg@arm.comsystem.physmem.avgMemAccLat 29720.98 # Average memory access latency per DRAM burst 23711606Sandreas.sandberg@arm.comsystem.physmem.avgRdBW 25.17 # Average DRAM read bandwidth in MiByte/s 23811606Sandreas.sandberg@arm.comsystem.physmem.avgWrBW 17.02 # Average achieved write bandwidth in MiByte/s 23911606Sandreas.sandberg@arm.comsystem.physmem.avgRdBWSys 25.18 # Average system read bandwidth in MiByte/s 24011606Sandreas.sandberg@arm.comsystem.physmem.avgWrBWSys 17.02 # Average system write bandwidth in MiByte/s 24111507SCurtis.Dunham@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 24211507SCurtis.Dunham@arm.comsystem.physmem.busUtil 0.33 # Data bus utilization in percentage 24311507SCurtis.Dunham@arm.comsystem.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads 24411507SCurtis.Dunham@arm.comsystem.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes 24511507SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing 24611606Sandreas.sandberg@arm.comsystem.physmem.avgWrQLen 20.20 # Average write queue length when enqueuing 24711606Sandreas.sandberg@arm.comsystem.physmem.readRowHits 110439 # Number of row buffer hits during reads 24811606Sandreas.sandberg@arm.comsystem.physmem.writeRowHits 67921 # Number of row buffer hits during writes 24911606Sandreas.sandberg@arm.comsystem.physmem.readRowHitRate 76.60 # Row buffer hit rate for reads 25011606Sandreas.sandberg@arm.comsystem.physmem.writeRowHitRate 69.64 # Row buffer hit rate for writes 25111606Sandreas.sandberg@arm.comsystem.physmem.avgGap 1516278.92 # Average gap between requests 25211606Sandreas.sandberg@arm.comsystem.physmem.pageHitRate 73.80 # Row buffer hit rate, read and write combined 25311606Sandreas.sandberg@arm.comsystem.physmem_0.actEnergy 239652000 # Energy for activate commands per rank (pJ) 25411606Sandreas.sandberg@arm.comsystem.physmem_0.preEnergy 130762500 # Energy for precharge commands per rank (pJ) 25511606Sandreas.sandberg@arm.comsystem.physmem_0.readEnergy 560266200 # Energy for read commands per rank (pJ) 25611606Sandreas.sandberg@arm.comsystem.physmem_0.writeEnergy 313968960 # Energy for write commands per rank (pJ) 25711606Sandreas.sandberg@arm.comsystem.physmem_0.refreshEnergy 23946564720 # Energy for refresh commands per rank (pJ) 25811606Sandreas.sandberg@arm.comsystem.physmem_0.actBackEnergy 47282173740 # Energy for active background per rank (pJ) 25911606Sandreas.sandberg@arm.comsystem.physmem_0.preBackEnergy 178503263250 # Energy for precharge background per rank (pJ) 26011606Sandreas.sandberg@arm.comsystem.physmem_0.totalEnergy 250976651370 # Total energy per rank (pJ) 26111606Sandreas.sandberg@arm.comsystem.physmem_0.averagePower 684.547573 # Core power per rank (mW) 26211606Sandreas.sandberg@arm.comsystem.physmem_0.memoryStateTime::IDLE 296644648000 # Time in different power states 26311606Sandreas.sandberg@arm.comsystem.physmem_0.memoryStateTime::REF 12242620000 # Time in different power states 26411507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 26511606Sandreas.sandberg@arm.comsystem.physmem_0.memoryStateTime::ACT 57744168750 # Time in different power states 26611507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 26711606Sandreas.sandberg@arm.comsystem.physmem_1.actEnergy 238941360 # Energy for activate commands per rank (pJ) 26811606Sandreas.sandberg@arm.comsystem.physmem_1.preEnergy 130374750 # Energy for precharge commands per rank (pJ) 26911606Sandreas.sandberg@arm.comsystem.physmem_1.readEnergy 564213000 # Energy for read commands per rank (pJ) 27011606Sandreas.sandberg@arm.comsystem.physmem_1.writeEnergy 317837520 # Energy for write commands per rank (pJ) 27111606Sandreas.sandberg@arm.comsystem.physmem_1.refreshEnergy 23946564720 # Energy for refresh commands per rank (pJ) 27211606Sandreas.sandberg@arm.comsystem.physmem_1.actBackEnergy 47121480765 # Energy for active background per rank (pJ) 27311606Sandreas.sandberg@arm.comsystem.physmem_1.preBackEnergy 178644216000 # Energy for precharge background per rank (pJ) 27411606Sandreas.sandberg@arm.comsystem.physmem_1.totalEnergy 250963628115 # Total energy per rank (pJ) 27511606Sandreas.sandberg@arm.comsystem.physmem_1.averagePower 684.512070 # Core power per rank (mW) 27611606Sandreas.sandberg@arm.comsystem.physmem_1.memoryStateTime::IDLE 296880094250 # Time in different power states 27711606Sandreas.sandberg@arm.comsystem.physmem_1.memoryStateTime::REF 12242620000 # Time in different power states 27811507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 27911606Sandreas.sandberg@arm.comsystem.physmem_1.memoryStateTime::ACT 57508713250 # Time in different power states 28011507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 28111606Sandreas.sandberg@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 28211606Sandreas.sandberg@arm.comsystem.cpu.branchPred.lookups 132103795 # Number of BP lookups 28311606Sandreas.sandberg@arm.comsystem.cpu.branchPred.condPredicted 98193288 # Number of conditional branches predicted 28411606Sandreas.sandberg@arm.comsystem.cpu.branchPred.condIncorrect 5910048 # Number of conditional branches incorrect 28511606Sandreas.sandberg@arm.comsystem.cpu.branchPred.BTBLookups 68601542 # Number of BTB lookups 28611606Sandreas.sandberg@arm.comsystem.cpu.branchPred.BTBHits 60590460 # Number of BTB hits 28711507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 28811606Sandreas.sandberg@arm.comsystem.cpu.branchPred.BTBHitPct 88.322300 # BTB Hit Percentage 28911570SCurtis.Dunham@arm.comsystem.cpu.branchPred.usedRAS 10017120 # Number of times the RAS was used to get a target. 29011570SCurtis.Dunham@arm.comsystem.cpu.branchPred.RASInCorrect 18743 # Number of incorrect RAS predictions. 29111606Sandreas.sandberg@arm.comsystem.cpu.branchPred.indirectLookups 3891574 # Number of indirect predictor lookups. 29211570SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectHits 3883027 # Number of indirect target hits. 29311606Sandreas.sandberg@arm.comsystem.cpu.branchPred.indirectMisses 8547 # Number of indirect misses. 29411570SCurtis.Dunham@arm.comsystem.cpu.branchPredindirectMispredicted 54138 # Number of mispredicted indirect branches. 29511507SCurtis.Dunham@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 29611606Sandreas.sandberg@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 29711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 29811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 29911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 30011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 30111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 30211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 30311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 30411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 30511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 30611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 30711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 30811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 30911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 31011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 31111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 31211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 31311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 31411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 31511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 31611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 31711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 31811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 31911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 32011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 32111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 32211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 32311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 32411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 32511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 32611606Sandreas.sandberg@arm.comsystem.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 32711507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 32811507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 32911507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 33011507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 33111507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 33211507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 33311507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 33411507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 33511507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 33611507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 33711507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 33811507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 33911507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 34011507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 34111507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 34211507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 34311507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 34411507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 34511507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 34611507SCurtis.Dunham@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 34711507SCurtis.Dunham@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 34811507SCurtis.Dunham@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 34911507SCurtis.Dunham@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 35011507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 35111507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 35211507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 35311507SCurtis.Dunham@arm.comsystem.cpu.dtb.hits 0 # DTB hits 35411507SCurtis.Dunham@arm.comsystem.cpu.dtb.misses 0 # DTB misses 35511507SCurtis.Dunham@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 35611606Sandreas.sandberg@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 35711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 35811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 36011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 36111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 36211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 36311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 36411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 36511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 36611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 36711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 36811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 36911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 37011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 37111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 37211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 37311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 37411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 37511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 37611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 37711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 37811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 37911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 38011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 38111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 38211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 38311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 38411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 38511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 38611606Sandreas.sandberg@arm.comsystem.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 38711507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 38811507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 38911507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 39011507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 39111507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 39211507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 39311507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 39411507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 39511507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 39611507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 39711507SCurtis.Dunham@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 39811507SCurtis.Dunham@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 39911507SCurtis.Dunham@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 40011507SCurtis.Dunham@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 40111507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 40211507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 40311507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 40411507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 40511507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 40611507SCurtis.Dunham@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 40711507SCurtis.Dunham@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 40811507SCurtis.Dunham@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 40911507SCurtis.Dunham@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 41011507SCurtis.Dunham@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 41111507SCurtis.Dunham@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 41211507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 41311507SCurtis.Dunham@arm.comsystem.cpu.itb.hits 0 # DTB hits 41411507SCurtis.Dunham@arm.comsystem.cpu.itb.misses 0 # DTB misses 41511507SCurtis.Dunham@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 41611507SCurtis.Dunham@arm.comsystem.cpu.workload.num_syscalls 548 # Number of system calls 41711606Sandreas.sandberg@arm.comsystem.cpu.pwrStateResidencyTicks::ON 366631719500 # Cumulative time (in ticks) in various power states 41811606Sandreas.sandberg@arm.comsystem.cpu.numCycles 733263439 # number of cpu cycles simulated 41911507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 42011507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 42111507SCurtis.Dunham@arm.comsystem.cpu.committedInsts 506579366 # Number of instructions committed 42211507SCurtis.Dunham@arm.comsystem.cpu.committedOps 548692589 # Number of ops (including micro ops) committed 42311606Sandreas.sandberg@arm.comsystem.cpu.discardedOps 12939754 # Number of ops (including micro ops) which were discarded before commit 42411507SCurtis.Dunham@arm.comsystem.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 42511606Sandreas.sandberg@arm.comsystem.cpu.cpi 1.447480 # CPI: cycles per instruction 42611606Sandreas.sandberg@arm.comsystem.cpu.ipc 0.690856 # IPC: instructions per cycle 42711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 42811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntAlu 375609862 68.46% 68.46% # Class of committed instruction 42911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction 43011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction 43111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction 43211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction 43311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction 43411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction 43511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction 43611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction 43711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction 43811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction 43911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction 44011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction 44111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction 44211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction 44311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction 44411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction 44511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction 44611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction 44711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction 44811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction 44911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction 45011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction 45111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction 45211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction 45311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction 45411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction 45511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction 45611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction 45711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction 45811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::MemWrite 56860222 10.36% 100.00% # Class of committed instruction 45911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 46011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 46111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::total 548692589 # Class of committed instruction 46211606Sandreas.sandberg@arm.comsystem.cpu.tickCycles 694072576 # Number of cycles that the object actually ticked 46311606Sandreas.sandberg@arm.comsystem.cpu.idleCycles 39190863 # Total number of cycles that the object has spent stopped 46411606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 46511570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.replacements 1141337 # number of replacements 46611606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.tagsinuse 4070.301946 # Cycle average of tags in use 46711606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.total_refs 171083822 # Total number of references to valid blocks. 46811570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.sampled_refs 1145433 # Sample count of references to valid blocks. 46911606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.avg_refs 149.361702 # Average number of references to valid blocks. 47011606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.warmup_cycle 5036525500 # Cycle when the warmup percentage was hit. 47111606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 4070.301946 # Average occupied blocks per requestor 47211606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.993726 # Average percentage of cache occupancy 47311606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.993726 # Average percentage of cache occupancy 47411507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 47511570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id 47611570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id 47711570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 549 # Occupied blocks per task id 47811570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::3 3501 # Occupied blocks per task id 47911507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 48011606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.tag_accesses 346338109 # Number of tag accesses 48111606Sandreas.sandberg@arm.comsystem.cpu.dcache.tags.data_accesses 346338109 # Number of data accesses 48211606Sandreas.sandberg@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 48311606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 114566017 # number of ReadReq hits 48411606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_hits::total 114566017 # number of ReadReq hits 48511570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 53537929 # number of WriteReq hits 48611570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::total 53537929 # number of WriteReq hits 48711570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 2794 # number of SoftPFReq hits 48811570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 2794 # number of SoftPFReq hits 48911507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits 49011507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 49111507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 49211507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 49311606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_hits::cpu.data 168103946 # number of demand (read+write) hits 49411606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_hits::total 168103946 # number of demand (read+write) hits 49511606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_hits::cpu.data 168106740 # number of overall hits 49611606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_hits::total 168106740 # number of overall hits 49711570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 811381 # number of ReadReq misses 49811570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::total 811381 # number of ReadReq misses 49911570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 701120 # number of WriteReq misses 50011570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::total 701120 # number of WriteReq misses 50111570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 15 # number of SoftPFReq misses 50211570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 15 # number of SoftPFReq misses 50311570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::cpu.data 1512501 # number of demand (read+write) misses 50411570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::total 1512501 # number of demand (read+write) misses 50511570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::cpu.data 1512516 # number of overall misses 50611570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::total 1512516 # number of overall misses 50711606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 13515584500 # number of ReadReq miss cycles 50811606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 13515584500 # number of ReadReq miss cycles 50911606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 22200332500 # number of WriteReq miss cycles 51011606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 22200332500 # number of WriteReq miss cycles 51111606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 35715917000 # number of demand (read+write) miss cycles 51211606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_miss_latency::total 35715917000 # number of demand (read+write) miss cycles 51311606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 35715917000 # number of overall miss cycles 51411606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_miss_latency::total 35715917000 # number of overall miss cycles 51511606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 115377398 # number of ReadReq accesses(hits+misses) 51611606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_accesses::total 115377398 # number of ReadReq accesses(hits+misses) 51711507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) 51811507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) 51911570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 2809 # number of SoftPFReq accesses(hits+misses) 52011570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 2809 # number of SoftPFReq accesses(hits+misses) 52111507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) 52211507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 52311507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 52411507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 52511606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 169616447 # number of demand (read+write) accesses 52611606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_accesses::total 169616447 # number of demand (read+write) accesses 52711606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 169619256 # number of overall (read+write) accesses 52811606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_accesses::total 169619256 # number of overall (read+write) accesses 52911570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007032 # miss rate for ReadReq accesses 53011570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.007032 # miss rate for ReadReq accesses 53111570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012926 # miss rate for WriteReq accesses 53211570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.012926 # miss rate for WriteReq accesses 53311570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005340 # miss rate for SoftPFReq accesses 53411570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.005340 # miss rate for SoftPFReq accesses 53511570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.008917 # miss rate for demand accesses 53611570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.008917 # miss rate for demand accesses 53711570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.008917 # miss rate for overall accesses 53811570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.008917 # miss rate for overall accesses 53911606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16657.506769 # average ReadReq miss latency 54011606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 16657.506769 # average ReadReq miss latency 54111606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31664.098157 # average WriteReq miss latency 54211606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 31664.098157 # average WriteReq miss latency 54311606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 23613.813809 # average overall miss latency 54411606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 23613.813809 # average overall miss latency 54511606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 23613.579625 # average overall miss latency 54611606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 23613.579625 # average overall miss latency 54711507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 54811507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 54911507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 55011507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 55111507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 55211507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 55311606Sandreas.sandberg@arm.comsystem.cpu.dcache.writebacks::writebacks 1068942 # number of writebacks 55411606Sandreas.sandberg@arm.comsystem.cpu.dcache.writebacks::total 1068942 # number of writebacks 55511570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 22348 # number of ReadReq MSHR hits 55611570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 22348 # number of ReadReq MSHR hits 55711570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 344732 # number of WriteReq MSHR hits 55811570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 344732 # number of WriteReq MSHR hits 55911570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 367080 # number of demand (read+write) MSHR hits 56011570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::total 367080 # number of demand (read+write) MSHR hits 56111570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 367080 # number of overall MSHR hits 56211570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::total 367080 # number of overall MSHR hits 56311570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 789033 # number of ReadReq MSHR misses 56411570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 789033 # number of ReadReq MSHR misses 56511570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 356388 # number of WriteReq MSHR misses 56611570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 356388 # number of WriteReq MSHR misses 56711570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses 56811570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses 56911570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 1145421 # number of demand (read+write) MSHR misses 57011570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::total 1145421 # number of demand (read+write) MSHR misses 57111570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 1145433 # number of overall MSHR misses 57211570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::total 1145433 # number of overall MSHR misses 57311606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12423186500 # number of ReadReq MSHR miss cycles 57411606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 12423186500 # number of ReadReq MSHR miss cycles 57511606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11274063500 # number of WriteReq MSHR miss cycles 57611606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 11274063500 # number of WriteReq MSHR miss cycles 57711606Sandreas.sandberg@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 942500 # number of SoftPFReq MSHR miss cycles 57811606Sandreas.sandberg@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 942500 # number of SoftPFReq MSHR miss cycles 57911606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 23697250000 # number of demand (read+write) MSHR miss cycles 58011606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 23697250000 # number of demand (read+write) MSHR miss cycles 58111606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 23698192500 # number of overall MSHR miss cycles 58211606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 23698192500 # number of overall MSHR miss cycles 58311570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006839 # mshr miss rate for ReadReq accesses 58411570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006839 # mshr miss rate for ReadReq accesses 58511570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006571 # mshr miss rate for WriteReq accesses 58611570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006571 # mshr miss rate for WriteReq accesses 58711570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004272 # mshr miss rate for SoftPFReq accesses 58811570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004272 # mshr miss rate for SoftPFReq accesses 58911570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for demand accesses 59011570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.006753 # mshr miss rate for demand accesses 59111570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for overall accesses 59211570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.006753 # mshr miss rate for overall accesses 59311606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15744.824995 # average ReadReq mshr miss latency 59411606Sandreas.sandberg@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15744.824995 # average ReadReq mshr miss latency 59511606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31634.239930 # average WriteReq mshr miss latency 59611606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31634.239930 # average WriteReq mshr miss latency 59711606Sandreas.sandberg@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78541.666667 # average SoftPFReq mshr miss latency 59811606Sandreas.sandberg@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78541.666667 # average SoftPFReq mshr miss latency 59911606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20688.681280 # average overall mshr miss latency 60011606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 20688.681280 # average overall mshr miss latency 60111606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20689.287370 # average overall mshr miss latency 60211606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 20689.287370 # average overall mshr miss latency 60311606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 60411570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.replacements 18175 # number of replacements 60511606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.tagsinuse 1187.102530 # Cycle average of tags in use 60611606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.total_refs 199148962 # Total number of references to valid blocks. 60711570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.sampled_refs 20047 # Sample count of references to valid blocks. 60811606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.avg_refs 9934.102958 # Average number of references to valid blocks. 60911507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 61011606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 1187.102530 # Average occupied blocks per requestor 61111606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.579640 # Average percentage of cache occupancy 61211606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.occ_percent::total 0.579640 # Average percentage of cache occupancy 61311570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id 61411507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 61511507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id 61611570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id 61711570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 311 # Occupied blocks per task id 61811570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 1400 # Occupied blocks per task id 61911570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id 62011606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.tag_accesses 398358065 # Number of tag accesses 62111606Sandreas.sandberg@arm.comsystem.cpu.icache.tags.data_accesses 398358065 # Number of data accesses 62211606Sandreas.sandberg@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 62311606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 199148962 # number of ReadReq hits 62411606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_hits::total 199148962 # number of ReadReq hits 62511606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_hits::cpu.inst 199148962 # number of demand (read+write) hits 62611606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_hits::total 199148962 # number of demand (read+write) hits 62711606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_hits::cpu.inst 199148962 # number of overall hits 62811606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_hits::total 199148962 # number of overall hits 62911570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 20047 # number of ReadReq misses 63011570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::total 20047 # number of ReadReq misses 63111570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::cpu.inst 20047 # number of demand (read+write) misses 63211570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::total 20047 # number of demand (read+write) misses 63311570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::cpu.inst 20047 # number of overall misses 63411570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::total 20047 # number of overall misses 63511606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 467837000 # number of ReadReq miss cycles 63611606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 467837000 # number of ReadReq miss cycles 63711606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 467837000 # number of demand (read+write) miss cycles 63811606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_miss_latency::total 467837000 # number of demand (read+write) miss cycles 63911606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 467837000 # number of overall miss cycles 64011606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_miss_latency::total 467837000 # number of overall miss cycles 64111606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 199169009 # number of ReadReq accesses(hits+misses) 64211606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_accesses::total 199169009 # number of ReadReq accesses(hits+misses) 64311606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 199169009 # number of demand (read+write) accesses 64411606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_accesses::total 199169009 # number of demand (read+write) accesses 64511606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 199169009 # number of overall (read+write) accesses 64611606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_accesses::total 199169009 # number of overall (read+write) accesses 64711507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000101 # miss rate for ReadReq accesses 64811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.000101 # miss rate for ReadReq accesses 64911507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.000101 # miss rate for demand accesses 65011507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::total 0.000101 # miss rate for demand accesses 65111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.000101 # miss rate for overall accesses 65211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::total 0.000101 # miss rate for overall accesses 65311606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23337.008031 # average ReadReq miss latency 65411606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 23337.008031 # average ReadReq miss latency 65511606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 23337.008031 # average overall miss latency 65611606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 23337.008031 # average overall miss latency 65711606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 23337.008031 # average overall miss latency 65811606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 23337.008031 # average overall miss latency 65911507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 66011507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 66111507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 66211507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 66311507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 66411507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 66511570SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::writebacks 18175 # number of writebacks 66611570SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::total 18175 # number of writebacks 66711570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 20047 # number of ReadReq MSHR misses 66811570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 20047 # number of ReadReq MSHR misses 66911570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 20047 # number of demand (read+write) MSHR misses 67011570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::total 20047 # number of demand (read+write) MSHR misses 67111570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 20047 # number of overall MSHR misses 67211570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::total 20047 # number of overall MSHR misses 67311606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 447790000 # number of ReadReq MSHR miss cycles 67411606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 447790000 # number of ReadReq MSHR miss cycles 67511606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 447790000 # number of demand (read+write) MSHR miss cycles 67611606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 447790000 # number of demand (read+write) MSHR miss cycles 67711606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 447790000 # number of overall MSHR miss cycles 67811606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 447790000 # number of overall MSHR miss cycles 67911507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for ReadReq accesses 68011507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000101 # mshr miss rate for ReadReq accesses 68111507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for demand accesses 68211507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.000101 # mshr miss rate for demand accesses 68311507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses 68411507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses 68511606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22337.008031 # average ReadReq mshr miss latency 68611606Sandreas.sandberg@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22337.008031 # average ReadReq mshr miss latency 68711606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22337.008031 # average overall mshr miss latency 68811606Sandreas.sandberg@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 22337.008031 # average overall mshr miss latency 68911606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22337.008031 # average overall mshr miss latency 69011606Sandreas.sandberg@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 22337.008031 # average overall mshr miss latency 69111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 69211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.replacements 112761 # number of replacements 69311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.tagsinuse 29068.883602 # Cycle average of tags in use 69411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.total_refs 2174452 # Total number of references to valid blocks. 69511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.sampled_refs 145529 # Sample count of references to valid blocks. 69611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.avg_refs 14.941709 # Average number of references to valid blocks. 69711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.warmup_cycle 101788000000 # Cycle when the warmup percentage was hit. 69811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 134.067060 # Average occupied blocks per requestor 69911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 307.855024 # Average occupied blocks per requestor 70011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 28626.961519 # Average occupied blocks per requestor 70111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.004091 # Average percentage of cache occupancy 70211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.009395 # Average percentage of cache occupancy 70311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.873626 # Average percentage of cache occupancy 70411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.887112 # Average percentage of cache occupancy 70511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id 70611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id 70711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id 70811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 981 # Occupied blocks per task id 70911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 31589 # Occupied blocks per task id 71011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 71111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.tag_accesses 18705497 # Number of tag accesses 71211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.tags.data_accesses 18705497 # Number of data accesses 71311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 71411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 1068942 # number of WritebackDirty hits 71511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 1068942 # number of WritebackDirty hits 71611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 17938 # number of WritebackClean hits 71711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 17938 # number of WritebackClean hits 71811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 255660 # number of ReadExReq hits 71911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 255660 # number of ReadExReq hits 72011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17235 # number of ReadCleanReq hits 72111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 17235 # number of ReadCleanReq hits 72211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 748301 # number of ReadSharedReq hits 72311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 748301 # number of ReadSharedReq hits 72411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 17235 # number of demand (read+write) hits 72511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1003961 # number of demand (read+write) hits 72611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_hits::total 1021196 # number of demand (read+write) hits 72711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 17235 # number of overall hits 72811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1003961 # number of overall hits 72911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_hits::total 1021196 # number of overall hits 73011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 100978 # number of ReadExReq misses 73111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 100978 # number of ReadExReq misses 73211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2812 # number of ReadCleanReq misses 73311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 2812 # number of ReadCleanReq misses 73411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 40494 # number of ReadSharedReq misses 73511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 40494 # number of ReadSharedReq misses 73611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 2812 # number of demand (read+write) misses 73711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 141472 # number of demand (read+write) misses 73811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_misses::total 144284 # number of demand (read+write) misses 73911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 2812 # number of overall misses 74011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 141472 # number of overall misses 74111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_misses::total 144284 # number of overall misses 74211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8057525500 # number of ReadExReq miss cycles 74311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 8057525500 # number of ReadExReq miss cycles 74411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 236084500 # number of ReadCleanReq miss cycles 74511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 236084500 # number of ReadCleanReq miss cycles 74611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3363607000 # number of ReadSharedReq miss cycles 74711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 3363607000 # number of ReadSharedReq miss cycles 74811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 236084500 # number of demand (read+write) miss cycles 74911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 11421132500 # number of demand (read+write) miss cycles 75011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_latency::total 11657217000 # number of demand (read+write) miss cycles 75111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 236084500 # number of overall miss cycles 75211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 11421132500 # number of overall miss cycles 75311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_latency::total 11657217000 # number of overall miss cycles 75411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 1068942 # number of WritebackDirty accesses(hits+misses) 75511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 1068942 # number of WritebackDirty accesses(hits+misses) 75611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 17938 # number of WritebackClean accesses(hits+misses) 75711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 17938 # number of WritebackClean accesses(hits+misses) 75811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 356638 # number of ReadExReq accesses(hits+misses) 75911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 356638 # number of ReadExReq accesses(hits+misses) 76011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 20047 # number of ReadCleanReq accesses(hits+misses) 76111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 20047 # number of ReadCleanReq accesses(hits+misses) 76211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 788795 # number of ReadSharedReq accesses(hits+misses) 76311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 788795 # number of ReadSharedReq accesses(hits+misses) 76411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 20047 # number of demand (read+write) accesses 76511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1145433 # number of demand (read+write) accesses 76611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::total 1165480 # number of demand (read+write) accesses 76711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 20047 # number of overall (read+write) accesses 76811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1145433 # number of overall (read+write) accesses 76911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::total 1165480 # number of overall (read+write) accesses 77011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283139 # miss rate for ReadExReq accesses 77111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.283139 # miss rate for ReadExReq accesses 77211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.140270 # miss rate for ReadCleanReq accesses 77311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.140270 # miss rate for ReadCleanReq accesses 77411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.051337 # miss rate for ReadSharedReq accesses 77511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.051337 # miss rate for ReadSharedReq accesses 77611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.140270 # miss rate for demand accesses 77711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.123510 # miss rate for demand accesses 77811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.123798 # miss rate for demand accesses 77911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.140270 # miss rate for overall accesses 78011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.123510 # miss rate for overall accesses 78111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.123798 # miss rate for overall accesses 78211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79794.861257 # average ReadExReq miss latency 78311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 79794.861257 # average ReadExReq miss latency 78411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83956.081081 # average ReadCleanReq miss latency 78511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83956.081081 # average ReadCleanReq miss latency 78611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83064.330518 # average ReadSharedReq miss latency 78711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83064.330518 # average ReadSharedReq miss latency 78811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83956.081081 # average overall miss latency 78911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 80730.692292 # average overall miss latency 79011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 80793.552993 # average overall miss latency 79111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83956.081081 # average overall miss latency 79211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 80730.692292 # average overall miss latency 79311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 80793.552993 # average overall miss latency 79411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 79511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 79611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 79711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 79811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 79911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 80011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.writebacks::writebacks 97528 # number of writebacks 80111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.writebacks::total 97528 # number of writebacks 80211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits 80311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits 80411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 13 # number of ReadSharedReq MSHR hits 80511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 13 # number of ReadSharedReq MSHR hits 80611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 80711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 13 # number of demand (read+write) MSHR hits 80811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits 80911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 81011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits 81111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits 81211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100978 # number of ReadExReq MSHR misses 81311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 100978 # number of ReadExReq MSHR misses 81411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2810 # number of ReadCleanReq MSHR misses 81511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 2810 # number of ReadCleanReq MSHR misses 81611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40481 # number of ReadSharedReq MSHR misses 81711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 40481 # number of ReadSharedReq MSHR misses 81811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 2810 # number of demand (read+write) MSHR misses 81911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 141459 # number of demand (read+write) MSHR misses 82011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 144269 # number of demand (read+write) MSHR misses 82111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 2810 # number of overall MSHR misses 82211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 141459 # number of overall MSHR misses 82311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 144269 # number of overall MSHR misses 82411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7047745500 # number of ReadExReq MSHR miss cycles 82511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7047745500 # number of ReadExReq MSHR miss cycles 82611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 207624000 # number of ReadCleanReq MSHR miss cycles 82711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 207624000 # number of ReadCleanReq MSHR miss cycles 82811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2957433000 # number of ReadSharedReq MSHR miss cycles 82911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2957433000 # number of ReadSharedReq MSHR miss cycles 83011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 207624000 # number of demand (read+write) MSHR miss cycles 83111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10005178500 # number of demand (read+write) MSHR miss cycles 83211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 10212802500 # number of demand (read+write) MSHR miss cycles 83311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 207624000 # number of overall MSHR miss cycles 83411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10005178500 # number of overall MSHR miss cycles 83511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 10212802500 # number of overall MSHR miss cycles 83611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283139 # mshr miss rate for ReadExReq accesses 83711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283139 # mshr miss rate for ReadExReq accesses 83811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for ReadCleanReq accesses 83911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.140171 # mshr miss rate for ReadCleanReq accesses 84011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.051320 # mshr miss rate for ReadSharedReq accesses 84111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.051320 # mshr miss rate for ReadSharedReq accesses 84211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for demand accesses 84311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123498 # mshr miss rate for demand accesses 84411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.123785 # mshr miss rate for demand accesses 84511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for overall accesses 84611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123498 # mshr miss rate for overall accesses 84711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.123785 # mshr miss rate for overall accesses 84811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69794.861257 # average ReadExReq mshr miss latency 84911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69794.861257 # average ReadExReq mshr miss latency 85011606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73887.544484 # average ReadCleanReq mshr miss latency 85111606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73887.544484 # average ReadCleanReq mshr miss latency 85211606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73057.310837 # average ReadSharedReq mshr miss latency 85311606Sandreas.sandberg@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73057.310837 # average ReadSharedReq mshr miss latency 85411606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73887.544484 # average overall mshr miss latency 85511606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70728.469026 # average overall mshr miss latency 85611606Sandreas.sandberg@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 70789.999931 # average overall mshr miss latency 85711606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73887.544484 # average overall mshr miss latency 85811606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70728.469026 # average overall mshr miss latency 85911606Sandreas.sandberg@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 70789.999931 # average overall mshr miss latency 86011570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 2324992 # Total number of requests made to the snoop filter. 86111570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 1159582 # Number of requests hitting in the snoop filter with a single holder of the requested data. 86211570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 4996 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 86311606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 2618 # Total number of snoops made to the snoop filter. 86411606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 2615 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 86511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 86611606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 86711570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 808842 # Transaction distribution 86811606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 1166470 # Transaction distribution 86911570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 18175 # Transaction distribution 87011606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 87628 # Transaction distribution 87111570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 356638 # Transaction distribution 87211570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 356638 # Transaction distribution 87311570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 20047 # Transaction distribution 87411570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 788795 # Transaction distribution 87511570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58269 # Packet count per connected master and slave (bytes) 87611570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432203 # Packet count per connected master and slave (bytes) 87711570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count::total 3490472 # Packet count per connected master and slave (bytes) 87811570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2446208 # Cumulative packet size per connected master and slave (bytes) 87911606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141720000 # Cumulative packet size per connected master and slave (bytes) 88011606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.pkt_size::total 144166208 # Cumulative packet size per connected master and slave (bytes) 88111606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoops 112761 # Total snoops (count) 88211606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoopTraffic 6241792 # Total snoop traffic (bytes) 88311606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 1278241 # Request fanout histogram 88411606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.006014 # Request fanout histogram 88511606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.077345 # Request fanout histogram 88611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 88711606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 1270557 99.40% 99.40% # Request fanout histogram 88811606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 7681 0.60% 100.00% # Request fanout histogram 88911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram 89011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 89111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 89211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 89311606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 1278241 # Request fanout histogram 89411606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 2249613000 # Layer occupancy (ticks) 89511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 89611606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 30094452 # Layer occupancy (ticks) 89711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 89811606Sandreas.sandberg@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 1718157983 # Layer occupancy (ticks) 89911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 90011606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_requests 254412 # Total number of requests made to the snoop filter. 90111606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_requests 110315 # Number of requests hitting in the snoop filter with a single holder of the requested data. 90211606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 90311606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 90411606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 90511606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 90611606Sandreas.sandberg@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 90711606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadResp 43291 # Transaction distribution 90811606Sandreas.sandberg@arm.comsystem.membus.trans_dist::WritebackDirty 97528 # Transaction distribution 90911606Sandreas.sandberg@arm.comsystem.membus.trans_dist::CleanEvict 12615 # Transaction distribution 91011606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadExReq 100978 # Transaction distribution 91111606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadExResp 100978 # Transaction distribution 91211606Sandreas.sandberg@arm.comsystem.membus.trans_dist::ReadSharedReq 43291 # Transaction distribution 91311606Sandreas.sandberg@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398681 # Packet count per connected master and slave (bytes) 91411606Sandreas.sandberg@arm.comsystem.membus.pkt_count::total 398681 # Packet count per connected master and slave (bytes) 91511606Sandreas.sandberg@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15475008 # Cumulative packet size per connected master and slave (bytes) 91611606Sandreas.sandberg@arm.comsystem.membus.pkt_size::total 15475008 # Cumulative packet size per connected master and slave (bytes) 91711507SCurtis.Dunham@arm.comsystem.membus.snoops 0 # Total snoops (count) 91811570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 91911606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::samples 144269 # Request fanout histogram 92011507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 92111507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 92211507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 92311606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::0 144269 100.00% 100.00% # Request fanout histogram 92411507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 92511507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 92611507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 92711507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 92811606Sandreas.sandberg@arm.comsystem.membus.snoop_fanout::total 144269 # Request fanout histogram 92911606Sandreas.sandberg@arm.comsystem.membus.reqLayer0.occupancy 685129000 # Layer occupancy (ticks) 93011507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 93111606Sandreas.sandberg@arm.comsystem.membus.respLayer1.occupancy 765930250 # Layer occupancy (ticks) 93211507SCurtis.Dunham@arm.comsystem.membus.respLayer1.utilization 0.2 # Layer utilization (%) 93311507SCurtis.Dunham@arm.com 93411507SCurtis.Dunham@arm.com---------- End Simulation Statistics ---------- 935