stats.txt revision 11606
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.366632 # Number of seconds simulated 4sim_ticks 366631719500 # Number of ticks simulated 5final_tick 366631719500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 211005 # Simulator instruction rate (inst/s) 8host_op_rate 228546 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 152712719 # Simulator tick rate (ticks/s) 10host_mem_usage 277288 # Number of bytes of host memory used 11host_seconds 2400.79 # Real time elapsed on the host 12sim_insts 506579366 # Number of instructions simulated 13sim_ops 548692589 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 179840 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9053376 # Number of bytes read from this memory 19system.physmem.bytes_read::total 9233216 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 179840 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 179840 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 6241792 # Number of bytes written to this memory 23system.physmem.bytes_written::total 6241792 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 2810 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 141459 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 144269 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 97528 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 97528 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 490519 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 24693379 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 25183898 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 490519 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 490519 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 17024692 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 17024692 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 17024692 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 490519 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 24693379 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 42208590 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.readReqs 144269 # Number of read requests accepted 41system.physmem.writeReqs 97528 # Number of write requests accepted 42system.physmem.readBursts 144269 # Number of DRAM read bursts, including those serviced by the write queue 43system.physmem.writeBursts 97528 # Number of DRAM write bursts, including those merged in the write queue 44system.physmem.bytesReadDRAM 9226688 # Total number of bytes read from DRAM 45system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue 46system.physmem.bytesWritten 6240064 # Total number of bytes written to DRAM 47system.physmem.bytesReadSys 9233216 # Total read bytes from the system interface side 48system.physmem.bytesWrittenSys 6241792 # Total written bytes from the system interface side 49system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue 50system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 51system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 52system.physmem.perBankRdBursts::0 9376 # Per bank write bursts 53system.physmem.perBankRdBursts::1 8929 # Per bank write bursts 54system.physmem.perBankRdBursts::2 8964 # Per bank write bursts 55system.physmem.perBankRdBursts::3 8666 # Per bank write bursts 56system.physmem.perBankRdBursts::4 9423 # Per bank write bursts 57system.physmem.perBankRdBursts::5 9371 # Per bank write bursts 58system.physmem.perBankRdBursts::6 8974 # Per bank write bursts 59system.physmem.perBankRdBursts::7 8126 # Per bank write bursts 60system.physmem.perBankRdBursts::8 8634 # Per bank write bursts 61system.physmem.perBankRdBursts::9 8697 # Per bank write bursts 62system.physmem.perBankRdBursts::10 8760 # Per bank write bursts 63system.physmem.perBankRdBursts::11 9487 # Per bank write bursts 64system.physmem.perBankRdBursts::12 9347 # Per bank write bursts 65system.physmem.perBankRdBursts::13 9550 # Per bank write bursts 66system.physmem.perBankRdBursts::14 8728 # Per bank write bursts 67system.physmem.perBankRdBursts::15 9135 # Per bank write bursts 68system.physmem.perBankWrBursts::0 6252 # Per bank write bursts 69system.physmem.perBankWrBursts::1 6118 # Per bank write bursts 70system.physmem.perBankWrBursts::2 6042 # Per bank write bursts 71system.physmem.perBankWrBursts::3 5901 # Per bank write bursts 72system.physmem.perBankWrBursts::4 6273 # Per bank write bursts 73system.physmem.perBankWrBursts::5 6263 # Per bank write bursts 74system.physmem.perBankWrBursts::6 6069 # Per bank write bursts 75system.physmem.perBankWrBursts::7 5534 # Per bank write bursts 76system.physmem.perBankWrBursts::8 5815 # Per bank write bursts 77system.physmem.perBankWrBursts::9 5920 # Per bank write bursts 78system.physmem.perBankWrBursts::10 5985 # Per bank write bursts 79system.physmem.perBankWrBursts::11 6510 # Per bank write bursts 80system.physmem.perBankWrBursts::12 6360 # Per bank write bursts 81system.physmem.perBankWrBursts::13 6344 # Per bank write bursts 82system.physmem.perBankWrBursts::14 6013 # Per bank write bursts 83system.physmem.perBankWrBursts::15 6102 # Per bank write bursts 84system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 85system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 86system.physmem.totGap 366631694000 # Total gap between requests 87system.physmem.readPktSize::0 0 # Read request sizes (log2) 88system.physmem.readPktSize::1 0 # Read request sizes (log2) 89system.physmem.readPktSize::2 0 # Read request sizes (log2) 90system.physmem.readPktSize::3 0 # Read request sizes (log2) 91system.physmem.readPktSize::4 0 # Read request sizes (log2) 92system.physmem.readPktSize::5 0 # Read request sizes (log2) 93system.physmem.readPktSize::6 144269 # Read request sizes (log2) 94system.physmem.writePktSize::0 0 # Write request sizes (log2) 95system.physmem.writePktSize::1 0 # Write request sizes (log2) 96system.physmem.writePktSize::2 0 # Write request sizes (log2) 97system.physmem.writePktSize::3 0 # Write request sizes (log2) 98system.physmem.writePktSize::4 0 # Write request sizes (log2) 99system.physmem.writePktSize::5 0 # Write request sizes (log2) 100system.physmem.writePktSize::6 97528 # Write request sizes (log2) 101system.physmem.rdQLenPdf::0 143840 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 311 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 133system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::15 2842 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::16 2979 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::17 5670 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::18 5725 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::19 5731 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::20 5730 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::21 5730 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::22 5734 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::23 5731 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::24 5736 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::25 5741 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::26 5739 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::27 5746 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::28 5754 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::29 5737 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::30 5732 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::31 5729 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::32 5727 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 197system.physmem.bytesPerActivate::samples 63306 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::mean 244.314283 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::gmean 163.017060 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::stdev 244.594379 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::0-127 22538 35.60% 35.60% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::128-255 17961 28.37% 63.97% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::256-383 7327 11.57% 75.55% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::384-511 7996 12.63% 88.18% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::512-639 2051 3.24% 91.42% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::640-767 1180 1.86% 93.28% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::768-895 835 1.32% 94.60% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::896-1023 660 1.04% 95.64% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1024-1151 2758 4.36% 100.00% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::total 63306 # Bytes accessed per row activation 211system.physmem.rdPerTurnAround::samples 5727 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::mean 25.172342 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::gmean 18.597400 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::stdev 376.088417 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::0-1023 5724 99.95% 99.95% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.98% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::total 5727 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 5727 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 17.024795 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 16.995243 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 1.004050 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16 2743 47.90% 47.90% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::17 142 2.48% 50.38% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::18 2814 49.14% 99.51% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::19 20 0.35% 99.86% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::20 6 0.10% 99.97% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::23 1 0.02% 99.98% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::total 5727 # Writes before turning the bus around for reads 231system.physmem.totQLat 1581653750 # Total ticks spent queuing 232system.physmem.totMemAccLat 4284785000 # Total ticks spent from burst creation until serviced by the DRAM 233system.physmem.totBusLat 720835000 # Total ticks spent in databus transfers 234system.physmem.avgQLat 10970.98 # Average queueing delay per DRAM burst 235system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 236system.physmem.avgMemAccLat 29720.98 # Average memory access latency per DRAM burst 237system.physmem.avgRdBW 25.17 # Average DRAM read bandwidth in MiByte/s 238system.physmem.avgWrBW 17.02 # Average achieved write bandwidth in MiByte/s 239system.physmem.avgRdBWSys 25.18 # Average system read bandwidth in MiByte/s 240system.physmem.avgWrBWSys 17.02 # Average system write bandwidth in MiByte/s 241system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 242system.physmem.busUtil 0.33 # Data bus utilization in percentage 243system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads 244system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes 245system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing 246system.physmem.avgWrQLen 20.20 # Average write queue length when enqueuing 247system.physmem.readRowHits 110439 # Number of row buffer hits during reads 248system.physmem.writeRowHits 67921 # Number of row buffer hits during writes 249system.physmem.readRowHitRate 76.60 # Row buffer hit rate for reads 250system.physmem.writeRowHitRate 69.64 # Row buffer hit rate for writes 251system.physmem.avgGap 1516278.92 # Average gap between requests 252system.physmem.pageHitRate 73.80 # Row buffer hit rate, read and write combined 253system.physmem_0.actEnergy 239652000 # Energy for activate commands per rank (pJ) 254system.physmem_0.preEnergy 130762500 # Energy for precharge commands per rank (pJ) 255system.physmem_0.readEnergy 560266200 # Energy for read commands per rank (pJ) 256system.physmem_0.writeEnergy 313968960 # Energy for write commands per rank (pJ) 257system.physmem_0.refreshEnergy 23946564720 # Energy for refresh commands per rank (pJ) 258system.physmem_0.actBackEnergy 47282173740 # Energy for active background per rank (pJ) 259system.physmem_0.preBackEnergy 178503263250 # Energy for precharge background per rank (pJ) 260system.physmem_0.totalEnergy 250976651370 # Total energy per rank (pJ) 261system.physmem_0.averagePower 684.547573 # Core power per rank (mW) 262system.physmem_0.memoryStateTime::IDLE 296644648000 # Time in different power states 263system.physmem_0.memoryStateTime::REF 12242620000 # Time in different power states 264system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 265system.physmem_0.memoryStateTime::ACT 57744168750 # Time in different power states 266system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 267system.physmem_1.actEnergy 238941360 # Energy for activate commands per rank (pJ) 268system.physmem_1.preEnergy 130374750 # Energy for precharge commands per rank (pJ) 269system.physmem_1.readEnergy 564213000 # Energy for read commands per rank (pJ) 270system.physmem_1.writeEnergy 317837520 # Energy for write commands per rank (pJ) 271system.physmem_1.refreshEnergy 23946564720 # Energy for refresh commands per rank (pJ) 272system.physmem_1.actBackEnergy 47121480765 # Energy for active background per rank (pJ) 273system.physmem_1.preBackEnergy 178644216000 # Energy for precharge background per rank (pJ) 274system.physmem_1.totalEnergy 250963628115 # Total energy per rank (pJ) 275system.physmem_1.averagePower 684.512070 # Core power per rank (mW) 276system.physmem_1.memoryStateTime::IDLE 296880094250 # Time in different power states 277system.physmem_1.memoryStateTime::REF 12242620000 # Time in different power states 278system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 279system.physmem_1.memoryStateTime::ACT 57508713250 # Time in different power states 280system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 281system.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 282system.cpu.branchPred.lookups 132103795 # Number of BP lookups 283system.cpu.branchPred.condPredicted 98193288 # Number of conditional branches predicted 284system.cpu.branchPred.condIncorrect 5910048 # Number of conditional branches incorrect 285system.cpu.branchPred.BTBLookups 68601542 # Number of BTB lookups 286system.cpu.branchPred.BTBHits 60590460 # Number of BTB hits 287system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 288system.cpu.branchPred.BTBHitPct 88.322300 # BTB Hit Percentage 289system.cpu.branchPred.usedRAS 10017120 # Number of times the RAS was used to get a target. 290system.cpu.branchPred.RASInCorrect 18743 # Number of incorrect RAS predictions. 291system.cpu.branchPred.indirectLookups 3891574 # Number of indirect predictor lookups. 292system.cpu.branchPred.indirectHits 3883027 # Number of indirect target hits. 293system.cpu.branchPred.indirectMisses 8547 # Number of indirect misses. 294system.cpu.branchPredindirectMispredicted 54138 # Number of mispredicted indirect branches. 295system.cpu_clk_domain.clock 500 # Clock period in ticks 296system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 297system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 298system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 301system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 305system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 306system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 307system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 308system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 309system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 310system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 311system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 312system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 313system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 314system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 315system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 316system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 317system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 318system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 319system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 320system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 321system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 322system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 323system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 324system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 325system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 326system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 327system.cpu.dtb.walker.walks 0 # Table walker walks requested 328system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 329system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 330system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 331system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 332system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 333system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 334system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 335system.cpu.dtb.inst_hits 0 # ITB inst hits 336system.cpu.dtb.inst_misses 0 # ITB inst misses 337system.cpu.dtb.read_hits 0 # DTB read hits 338system.cpu.dtb.read_misses 0 # DTB read misses 339system.cpu.dtb.write_hits 0 # DTB write hits 340system.cpu.dtb.write_misses 0 # DTB write misses 341system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 342system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 343system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 344system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 345system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 346system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 347system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 348system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 349system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 350system.cpu.dtb.read_accesses 0 # DTB read accesses 351system.cpu.dtb.write_accesses 0 # DTB write accesses 352system.cpu.dtb.inst_accesses 0 # ITB inst accesses 353system.cpu.dtb.hits 0 # DTB hits 354system.cpu.dtb.misses 0 # DTB misses 355system.cpu.dtb.accesses 0 # DTB accesses 356system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 357system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 358system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 359system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 360system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 361system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 362system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 363system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 364system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 365system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 366system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 367system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 368system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 369system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 370system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 371system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 372system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 373system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 374system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 375system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 376system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 377system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 378system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 379system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 380system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 381system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 382system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 383system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 384system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 385system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 386system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 387system.cpu.itb.walker.walks 0 # Table walker walks requested 388system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 389system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 390system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 391system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 392system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 393system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 394system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 395system.cpu.itb.inst_hits 0 # ITB inst hits 396system.cpu.itb.inst_misses 0 # ITB inst misses 397system.cpu.itb.read_hits 0 # DTB read hits 398system.cpu.itb.read_misses 0 # DTB read misses 399system.cpu.itb.write_hits 0 # DTB write hits 400system.cpu.itb.write_misses 0 # DTB write misses 401system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 402system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 403system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 404system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 405system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 406system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 407system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 408system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 409system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 410system.cpu.itb.read_accesses 0 # DTB read accesses 411system.cpu.itb.write_accesses 0 # DTB write accesses 412system.cpu.itb.inst_accesses 0 # ITB inst accesses 413system.cpu.itb.hits 0 # DTB hits 414system.cpu.itb.misses 0 # DTB misses 415system.cpu.itb.accesses 0 # DTB accesses 416system.cpu.workload.num_syscalls 548 # Number of system calls 417system.cpu.pwrStateResidencyTicks::ON 366631719500 # Cumulative time (in ticks) in various power states 418system.cpu.numCycles 733263439 # number of cpu cycles simulated 419system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 420system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 421system.cpu.committedInsts 506579366 # Number of instructions committed 422system.cpu.committedOps 548692589 # Number of ops (including micro ops) committed 423system.cpu.discardedOps 12939754 # Number of ops (including micro ops) which were discarded before commit 424system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 425system.cpu.cpi 1.447480 # CPI: cycles per instruction 426system.cpu.ipc 0.690856 # IPC: instructions per cycle 427system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 428system.cpu.op_class_0::IntAlu 375609862 68.46% 68.46% # Class of committed instruction 429system.cpu.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction 430system.cpu.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction 431system.cpu.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction 432system.cpu.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction 433system.cpu.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction 434system.cpu.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction 435system.cpu.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction 436system.cpu.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction 437system.cpu.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction 438system.cpu.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction 439system.cpu.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction 440system.cpu.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction 441system.cpu.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction 442system.cpu.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction 443system.cpu.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction 444system.cpu.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction 445system.cpu.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction 446system.cpu.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction 447system.cpu.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction 448system.cpu.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction 449system.cpu.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction 450system.cpu.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction 451system.cpu.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction 452system.cpu.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction 453system.cpu.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction 454system.cpu.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction 455system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction 456system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction 457system.cpu.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction 458system.cpu.op_class_0::MemWrite 56860222 10.36% 100.00% # Class of committed instruction 459system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 460system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 461system.cpu.op_class_0::total 548692589 # Class of committed instruction 462system.cpu.tickCycles 694072576 # Number of cycles that the object actually ticked 463system.cpu.idleCycles 39190863 # Total number of cycles that the object has spent stopped 464system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 465system.cpu.dcache.tags.replacements 1141337 # number of replacements 466system.cpu.dcache.tags.tagsinuse 4070.301946 # Cycle average of tags in use 467system.cpu.dcache.tags.total_refs 171083822 # Total number of references to valid blocks. 468system.cpu.dcache.tags.sampled_refs 1145433 # Sample count of references to valid blocks. 469system.cpu.dcache.tags.avg_refs 149.361702 # Average number of references to valid blocks. 470system.cpu.dcache.tags.warmup_cycle 5036525500 # Cycle when the warmup percentage was hit. 471system.cpu.dcache.tags.occ_blocks::cpu.data 4070.301946 # Average occupied blocks per requestor 472system.cpu.dcache.tags.occ_percent::cpu.data 0.993726 # Average percentage of cache occupancy 473system.cpu.dcache.tags.occ_percent::total 0.993726 # Average percentage of cache occupancy 474system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 475system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id 476system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id 477system.cpu.dcache.tags.age_task_id_blocks_1024::2 549 # Occupied blocks per task id 478system.cpu.dcache.tags.age_task_id_blocks_1024::3 3501 # Occupied blocks per task id 479system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 480system.cpu.dcache.tags.tag_accesses 346338109 # Number of tag accesses 481system.cpu.dcache.tags.data_accesses 346338109 # Number of data accesses 482system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 483system.cpu.dcache.ReadReq_hits::cpu.data 114566017 # number of ReadReq hits 484system.cpu.dcache.ReadReq_hits::total 114566017 # number of ReadReq hits 485system.cpu.dcache.WriteReq_hits::cpu.data 53537929 # number of WriteReq hits 486system.cpu.dcache.WriteReq_hits::total 53537929 # number of WriteReq hits 487system.cpu.dcache.SoftPFReq_hits::cpu.data 2794 # number of SoftPFReq hits 488system.cpu.dcache.SoftPFReq_hits::total 2794 # number of SoftPFReq hits 489system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits 490system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 491system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 492system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 493system.cpu.dcache.demand_hits::cpu.data 168103946 # number of demand (read+write) hits 494system.cpu.dcache.demand_hits::total 168103946 # number of demand (read+write) hits 495system.cpu.dcache.overall_hits::cpu.data 168106740 # number of overall hits 496system.cpu.dcache.overall_hits::total 168106740 # number of overall hits 497system.cpu.dcache.ReadReq_misses::cpu.data 811381 # number of ReadReq misses 498system.cpu.dcache.ReadReq_misses::total 811381 # number of ReadReq misses 499system.cpu.dcache.WriteReq_misses::cpu.data 701120 # number of WriteReq misses 500system.cpu.dcache.WriteReq_misses::total 701120 # number of WriteReq misses 501system.cpu.dcache.SoftPFReq_misses::cpu.data 15 # number of SoftPFReq misses 502system.cpu.dcache.SoftPFReq_misses::total 15 # number of SoftPFReq misses 503system.cpu.dcache.demand_misses::cpu.data 1512501 # number of demand (read+write) misses 504system.cpu.dcache.demand_misses::total 1512501 # number of demand (read+write) misses 505system.cpu.dcache.overall_misses::cpu.data 1512516 # number of overall misses 506system.cpu.dcache.overall_misses::total 1512516 # number of overall misses 507system.cpu.dcache.ReadReq_miss_latency::cpu.data 13515584500 # number of ReadReq miss cycles 508system.cpu.dcache.ReadReq_miss_latency::total 13515584500 # number of ReadReq miss cycles 509system.cpu.dcache.WriteReq_miss_latency::cpu.data 22200332500 # number of WriteReq miss cycles 510system.cpu.dcache.WriteReq_miss_latency::total 22200332500 # number of WriteReq miss cycles 511system.cpu.dcache.demand_miss_latency::cpu.data 35715917000 # number of demand (read+write) miss cycles 512system.cpu.dcache.demand_miss_latency::total 35715917000 # number of demand (read+write) miss cycles 513system.cpu.dcache.overall_miss_latency::cpu.data 35715917000 # number of overall miss cycles 514system.cpu.dcache.overall_miss_latency::total 35715917000 # number of overall miss cycles 515system.cpu.dcache.ReadReq_accesses::cpu.data 115377398 # number of ReadReq accesses(hits+misses) 516system.cpu.dcache.ReadReq_accesses::total 115377398 # number of ReadReq accesses(hits+misses) 517system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) 518system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) 519system.cpu.dcache.SoftPFReq_accesses::cpu.data 2809 # number of SoftPFReq accesses(hits+misses) 520system.cpu.dcache.SoftPFReq_accesses::total 2809 # number of SoftPFReq accesses(hits+misses) 521system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) 522system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 523system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 524system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 525system.cpu.dcache.demand_accesses::cpu.data 169616447 # number of demand (read+write) accesses 526system.cpu.dcache.demand_accesses::total 169616447 # number of demand (read+write) accesses 527system.cpu.dcache.overall_accesses::cpu.data 169619256 # number of overall (read+write) accesses 528system.cpu.dcache.overall_accesses::total 169619256 # number of overall (read+write) accesses 529system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007032 # miss rate for ReadReq accesses 530system.cpu.dcache.ReadReq_miss_rate::total 0.007032 # miss rate for ReadReq accesses 531system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012926 # miss rate for WriteReq accesses 532system.cpu.dcache.WriteReq_miss_rate::total 0.012926 # miss rate for WriteReq accesses 533system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005340 # miss rate for SoftPFReq accesses 534system.cpu.dcache.SoftPFReq_miss_rate::total 0.005340 # miss rate for SoftPFReq accesses 535system.cpu.dcache.demand_miss_rate::cpu.data 0.008917 # miss rate for demand accesses 536system.cpu.dcache.demand_miss_rate::total 0.008917 # miss rate for demand accesses 537system.cpu.dcache.overall_miss_rate::cpu.data 0.008917 # miss rate for overall accesses 538system.cpu.dcache.overall_miss_rate::total 0.008917 # miss rate for overall accesses 539system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16657.506769 # average ReadReq miss latency 540system.cpu.dcache.ReadReq_avg_miss_latency::total 16657.506769 # average ReadReq miss latency 541system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31664.098157 # average WriteReq miss latency 542system.cpu.dcache.WriteReq_avg_miss_latency::total 31664.098157 # average WriteReq miss latency 543system.cpu.dcache.demand_avg_miss_latency::cpu.data 23613.813809 # average overall miss latency 544system.cpu.dcache.demand_avg_miss_latency::total 23613.813809 # average overall miss latency 545system.cpu.dcache.overall_avg_miss_latency::cpu.data 23613.579625 # average overall miss latency 546system.cpu.dcache.overall_avg_miss_latency::total 23613.579625 # average overall miss latency 547system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 548system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 549system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 550system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 551system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 552system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 553system.cpu.dcache.writebacks::writebacks 1068942 # number of writebacks 554system.cpu.dcache.writebacks::total 1068942 # number of writebacks 555system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22348 # number of ReadReq MSHR hits 556system.cpu.dcache.ReadReq_mshr_hits::total 22348 # number of ReadReq MSHR hits 557system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344732 # number of WriteReq MSHR hits 558system.cpu.dcache.WriteReq_mshr_hits::total 344732 # number of WriteReq MSHR hits 559system.cpu.dcache.demand_mshr_hits::cpu.data 367080 # number of demand (read+write) MSHR hits 560system.cpu.dcache.demand_mshr_hits::total 367080 # number of demand (read+write) MSHR hits 561system.cpu.dcache.overall_mshr_hits::cpu.data 367080 # number of overall MSHR hits 562system.cpu.dcache.overall_mshr_hits::total 367080 # number of overall MSHR hits 563system.cpu.dcache.ReadReq_mshr_misses::cpu.data 789033 # number of ReadReq MSHR misses 564system.cpu.dcache.ReadReq_mshr_misses::total 789033 # number of ReadReq MSHR misses 565system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356388 # number of WriteReq MSHR misses 566system.cpu.dcache.WriteReq_mshr_misses::total 356388 # number of WriteReq MSHR misses 567system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses 568system.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses 569system.cpu.dcache.demand_mshr_misses::cpu.data 1145421 # number of demand (read+write) MSHR misses 570system.cpu.dcache.demand_mshr_misses::total 1145421 # number of demand (read+write) MSHR misses 571system.cpu.dcache.overall_mshr_misses::cpu.data 1145433 # number of overall MSHR misses 572system.cpu.dcache.overall_mshr_misses::total 1145433 # number of overall MSHR misses 573system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12423186500 # number of ReadReq MSHR miss cycles 574system.cpu.dcache.ReadReq_mshr_miss_latency::total 12423186500 # number of ReadReq MSHR miss cycles 575system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11274063500 # number of WriteReq MSHR miss cycles 576system.cpu.dcache.WriteReq_mshr_miss_latency::total 11274063500 # number of WriteReq MSHR miss cycles 577system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 942500 # number of SoftPFReq MSHR miss cycles 578system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 942500 # number of SoftPFReq MSHR miss cycles 579system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23697250000 # number of demand (read+write) MSHR miss cycles 580system.cpu.dcache.demand_mshr_miss_latency::total 23697250000 # number of demand (read+write) MSHR miss cycles 581system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23698192500 # number of overall MSHR miss cycles 582system.cpu.dcache.overall_mshr_miss_latency::total 23698192500 # number of overall MSHR miss cycles 583system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006839 # mshr miss rate for ReadReq accesses 584system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006839 # mshr miss rate for ReadReq accesses 585system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006571 # mshr miss rate for WriteReq accesses 586system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006571 # mshr miss rate for WriteReq accesses 587system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004272 # mshr miss rate for SoftPFReq accesses 588system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004272 # mshr miss rate for SoftPFReq accesses 589system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for demand accesses 590system.cpu.dcache.demand_mshr_miss_rate::total 0.006753 # mshr miss rate for demand accesses 591system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for overall accesses 592system.cpu.dcache.overall_mshr_miss_rate::total 0.006753 # mshr miss rate for overall accesses 593system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15744.824995 # average ReadReq mshr miss latency 594system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15744.824995 # average ReadReq mshr miss latency 595system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31634.239930 # average WriteReq mshr miss latency 596system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31634.239930 # average WriteReq mshr miss latency 597system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 78541.666667 # average SoftPFReq mshr miss latency 598system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 78541.666667 # average SoftPFReq mshr miss latency 599system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20688.681280 # average overall mshr miss latency 600system.cpu.dcache.demand_avg_mshr_miss_latency::total 20688.681280 # average overall mshr miss latency 601system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20689.287370 # average overall mshr miss latency 602system.cpu.dcache.overall_avg_mshr_miss_latency::total 20689.287370 # average overall mshr miss latency 603system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 604system.cpu.icache.tags.replacements 18175 # number of replacements 605system.cpu.icache.tags.tagsinuse 1187.102530 # Cycle average of tags in use 606system.cpu.icache.tags.total_refs 199148962 # Total number of references to valid blocks. 607system.cpu.icache.tags.sampled_refs 20047 # Sample count of references to valid blocks. 608system.cpu.icache.tags.avg_refs 9934.102958 # Average number of references to valid blocks. 609system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 610system.cpu.icache.tags.occ_blocks::cpu.inst 1187.102530 # Average occupied blocks per requestor 611system.cpu.icache.tags.occ_percent::cpu.inst 0.579640 # Average percentage of cache occupancy 612system.cpu.icache.tags.occ_percent::total 0.579640 # Average percentage of cache occupancy 613system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id 614system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 615system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id 616system.cpu.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id 617system.cpu.icache.tags.age_task_id_blocks_1024::3 311 # Occupied blocks per task id 618system.cpu.icache.tags.age_task_id_blocks_1024::4 1400 # Occupied blocks per task id 619system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id 620system.cpu.icache.tags.tag_accesses 398358065 # Number of tag accesses 621system.cpu.icache.tags.data_accesses 398358065 # Number of data accesses 622system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 623system.cpu.icache.ReadReq_hits::cpu.inst 199148962 # number of ReadReq hits 624system.cpu.icache.ReadReq_hits::total 199148962 # number of ReadReq hits 625system.cpu.icache.demand_hits::cpu.inst 199148962 # number of demand (read+write) hits 626system.cpu.icache.demand_hits::total 199148962 # number of demand (read+write) hits 627system.cpu.icache.overall_hits::cpu.inst 199148962 # number of overall hits 628system.cpu.icache.overall_hits::total 199148962 # number of overall hits 629system.cpu.icache.ReadReq_misses::cpu.inst 20047 # number of ReadReq misses 630system.cpu.icache.ReadReq_misses::total 20047 # number of ReadReq misses 631system.cpu.icache.demand_misses::cpu.inst 20047 # number of demand (read+write) misses 632system.cpu.icache.demand_misses::total 20047 # number of demand (read+write) misses 633system.cpu.icache.overall_misses::cpu.inst 20047 # number of overall misses 634system.cpu.icache.overall_misses::total 20047 # number of overall misses 635system.cpu.icache.ReadReq_miss_latency::cpu.inst 467837000 # number of ReadReq miss cycles 636system.cpu.icache.ReadReq_miss_latency::total 467837000 # number of ReadReq miss cycles 637system.cpu.icache.demand_miss_latency::cpu.inst 467837000 # number of demand (read+write) miss cycles 638system.cpu.icache.demand_miss_latency::total 467837000 # number of demand (read+write) miss cycles 639system.cpu.icache.overall_miss_latency::cpu.inst 467837000 # number of overall miss cycles 640system.cpu.icache.overall_miss_latency::total 467837000 # number of overall miss cycles 641system.cpu.icache.ReadReq_accesses::cpu.inst 199169009 # number of ReadReq accesses(hits+misses) 642system.cpu.icache.ReadReq_accesses::total 199169009 # number of ReadReq accesses(hits+misses) 643system.cpu.icache.demand_accesses::cpu.inst 199169009 # number of demand (read+write) accesses 644system.cpu.icache.demand_accesses::total 199169009 # number of demand (read+write) accesses 645system.cpu.icache.overall_accesses::cpu.inst 199169009 # number of overall (read+write) accesses 646system.cpu.icache.overall_accesses::total 199169009 # number of overall (read+write) accesses 647system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000101 # miss rate for ReadReq accesses 648system.cpu.icache.ReadReq_miss_rate::total 0.000101 # miss rate for ReadReq accesses 649system.cpu.icache.demand_miss_rate::cpu.inst 0.000101 # miss rate for demand accesses 650system.cpu.icache.demand_miss_rate::total 0.000101 # miss rate for demand accesses 651system.cpu.icache.overall_miss_rate::cpu.inst 0.000101 # miss rate for overall accesses 652system.cpu.icache.overall_miss_rate::total 0.000101 # miss rate for overall accesses 653system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23337.008031 # average ReadReq miss latency 654system.cpu.icache.ReadReq_avg_miss_latency::total 23337.008031 # average ReadReq miss latency 655system.cpu.icache.demand_avg_miss_latency::cpu.inst 23337.008031 # average overall miss latency 656system.cpu.icache.demand_avg_miss_latency::total 23337.008031 # average overall miss latency 657system.cpu.icache.overall_avg_miss_latency::cpu.inst 23337.008031 # average overall miss latency 658system.cpu.icache.overall_avg_miss_latency::total 23337.008031 # average overall miss latency 659system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 660system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 661system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 662system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 663system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 664system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 665system.cpu.icache.writebacks::writebacks 18175 # number of writebacks 666system.cpu.icache.writebacks::total 18175 # number of writebacks 667system.cpu.icache.ReadReq_mshr_misses::cpu.inst 20047 # number of ReadReq MSHR misses 668system.cpu.icache.ReadReq_mshr_misses::total 20047 # number of ReadReq MSHR misses 669system.cpu.icache.demand_mshr_misses::cpu.inst 20047 # number of demand (read+write) MSHR misses 670system.cpu.icache.demand_mshr_misses::total 20047 # number of demand (read+write) MSHR misses 671system.cpu.icache.overall_mshr_misses::cpu.inst 20047 # number of overall MSHR misses 672system.cpu.icache.overall_mshr_misses::total 20047 # number of overall MSHR misses 673system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 447790000 # number of ReadReq MSHR miss cycles 674system.cpu.icache.ReadReq_mshr_miss_latency::total 447790000 # number of ReadReq MSHR miss cycles 675system.cpu.icache.demand_mshr_miss_latency::cpu.inst 447790000 # number of demand (read+write) MSHR miss cycles 676system.cpu.icache.demand_mshr_miss_latency::total 447790000 # number of demand (read+write) MSHR miss cycles 677system.cpu.icache.overall_mshr_miss_latency::cpu.inst 447790000 # number of overall MSHR miss cycles 678system.cpu.icache.overall_mshr_miss_latency::total 447790000 # number of overall MSHR miss cycles 679system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for ReadReq accesses 680system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000101 # mshr miss rate for ReadReq accesses 681system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for demand accesses 682system.cpu.icache.demand_mshr_miss_rate::total 0.000101 # mshr miss rate for demand accesses 683system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses 684system.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses 685system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22337.008031 # average ReadReq mshr miss latency 686system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22337.008031 # average ReadReq mshr miss latency 687system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22337.008031 # average overall mshr miss latency 688system.cpu.icache.demand_avg_mshr_miss_latency::total 22337.008031 # average overall mshr miss latency 689system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22337.008031 # average overall mshr miss latency 690system.cpu.icache.overall_avg_mshr_miss_latency::total 22337.008031 # average overall mshr miss latency 691system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 692system.cpu.l2cache.tags.replacements 112761 # number of replacements 693system.cpu.l2cache.tags.tagsinuse 29068.883602 # Cycle average of tags in use 694system.cpu.l2cache.tags.total_refs 2174452 # Total number of references to valid blocks. 695system.cpu.l2cache.tags.sampled_refs 145529 # Sample count of references to valid blocks. 696system.cpu.l2cache.tags.avg_refs 14.941709 # Average number of references to valid blocks. 697system.cpu.l2cache.tags.warmup_cycle 101788000000 # Cycle when the warmup percentage was hit. 698system.cpu.l2cache.tags.occ_blocks::writebacks 134.067060 # Average occupied blocks per requestor 699system.cpu.l2cache.tags.occ_blocks::cpu.inst 307.855024 # Average occupied blocks per requestor 700system.cpu.l2cache.tags.occ_blocks::cpu.data 28626.961519 # Average occupied blocks per requestor 701system.cpu.l2cache.tags.occ_percent::writebacks 0.004091 # Average percentage of cache occupancy 702system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009395 # Average percentage of cache occupancy 703system.cpu.l2cache.tags.occ_percent::cpu.data 0.873626 # Average percentage of cache occupancy 704system.cpu.l2cache.tags.occ_percent::total 0.887112 # Average percentage of cache occupancy 705system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id 706system.cpu.l2cache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id 707system.cpu.l2cache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id 708system.cpu.l2cache.tags.age_task_id_blocks_1024::3 981 # Occupied blocks per task id 709system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31589 # Occupied blocks per task id 710system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 711system.cpu.l2cache.tags.tag_accesses 18705497 # Number of tag accesses 712system.cpu.l2cache.tags.data_accesses 18705497 # Number of data accesses 713system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 714system.cpu.l2cache.WritebackDirty_hits::writebacks 1068942 # number of WritebackDirty hits 715system.cpu.l2cache.WritebackDirty_hits::total 1068942 # number of WritebackDirty hits 716system.cpu.l2cache.WritebackClean_hits::writebacks 17938 # number of WritebackClean hits 717system.cpu.l2cache.WritebackClean_hits::total 17938 # number of WritebackClean hits 718system.cpu.l2cache.ReadExReq_hits::cpu.data 255660 # number of ReadExReq hits 719system.cpu.l2cache.ReadExReq_hits::total 255660 # number of ReadExReq hits 720system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17235 # number of ReadCleanReq hits 721system.cpu.l2cache.ReadCleanReq_hits::total 17235 # number of ReadCleanReq hits 722system.cpu.l2cache.ReadSharedReq_hits::cpu.data 748301 # number of ReadSharedReq hits 723system.cpu.l2cache.ReadSharedReq_hits::total 748301 # number of ReadSharedReq hits 724system.cpu.l2cache.demand_hits::cpu.inst 17235 # number of demand (read+write) hits 725system.cpu.l2cache.demand_hits::cpu.data 1003961 # number of demand (read+write) hits 726system.cpu.l2cache.demand_hits::total 1021196 # number of demand (read+write) hits 727system.cpu.l2cache.overall_hits::cpu.inst 17235 # number of overall hits 728system.cpu.l2cache.overall_hits::cpu.data 1003961 # number of overall hits 729system.cpu.l2cache.overall_hits::total 1021196 # number of overall hits 730system.cpu.l2cache.ReadExReq_misses::cpu.data 100978 # number of ReadExReq misses 731system.cpu.l2cache.ReadExReq_misses::total 100978 # number of ReadExReq misses 732system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2812 # number of ReadCleanReq misses 733system.cpu.l2cache.ReadCleanReq_misses::total 2812 # number of ReadCleanReq misses 734system.cpu.l2cache.ReadSharedReq_misses::cpu.data 40494 # number of ReadSharedReq misses 735system.cpu.l2cache.ReadSharedReq_misses::total 40494 # number of ReadSharedReq misses 736system.cpu.l2cache.demand_misses::cpu.inst 2812 # number of demand (read+write) misses 737system.cpu.l2cache.demand_misses::cpu.data 141472 # number of demand (read+write) misses 738system.cpu.l2cache.demand_misses::total 144284 # number of demand (read+write) misses 739system.cpu.l2cache.overall_misses::cpu.inst 2812 # number of overall misses 740system.cpu.l2cache.overall_misses::cpu.data 141472 # number of overall misses 741system.cpu.l2cache.overall_misses::total 144284 # number of overall misses 742system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8057525500 # number of ReadExReq miss cycles 743system.cpu.l2cache.ReadExReq_miss_latency::total 8057525500 # number of ReadExReq miss cycles 744system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 236084500 # number of ReadCleanReq miss cycles 745system.cpu.l2cache.ReadCleanReq_miss_latency::total 236084500 # number of ReadCleanReq miss cycles 746system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3363607000 # number of ReadSharedReq miss cycles 747system.cpu.l2cache.ReadSharedReq_miss_latency::total 3363607000 # number of ReadSharedReq miss cycles 748system.cpu.l2cache.demand_miss_latency::cpu.inst 236084500 # number of demand (read+write) miss cycles 749system.cpu.l2cache.demand_miss_latency::cpu.data 11421132500 # number of demand (read+write) miss cycles 750system.cpu.l2cache.demand_miss_latency::total 11657217000 # number of demand (read+write) miss cycles 751system.cpu.l2cache.overall_miss_latency::cpu.inst 236084500 # number of overall miss cycles 752system.cpu.l2cache.overall_miss_latency::cpu.data 11421132500 # number of overall miss cycles 753system.cpu.l2cache.overall_miss_latency::total 11657217000 # number of overall miss cycles 754system.cpu.l2cache.WritebackDirty_accesses::writebacks 1068942 # number of WritebackDirty accesses(hits+misses) 755system.cpu.l2cache.WritebackDirty_accesses::total 1068942 # number of WritebackDirty accesses(hits+misses) 756system.cpu.l2cache.WritebackClean_accesses::writebacks 17938 # number of WritebackClean accesses(hits+misses) 757system.cpu.l2cache.WritebackClean_accesses::total 17938 # number of WritebackClean accesses(hits+misses) 758system.cpu.l2cache.ReadExReq_accesses::cpu.data 356638 # number of ReadExReq accesses(hits+misses) 759system.cpu.l2cache.ReadExReq_accesses::total 356638 # number of ReadExReq accesses(hits+misses) 760system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 20047 # number of ReadCleanReq accesses(hits+misses) 761system.cpu.l2cache.ReadCleanReq_accesses::total 20047 # number of ReadCleanReq accesses(hits+misses) 762system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 788795 # number of ReadSharedReq accesses(hits+misses) 763system.cpu.l2cache.ReadSharedReq_accesses::total 788795 # number of ReadSharedReq accesses(hits+misses) 764system.cpu.l2cache.demand_accesses::cpu.inst 20047 # number of demand (read+write) accesses 765system.cpu.l2cache.demand_accesses::cpu.data 1145433 # number of demand (read+write) accesses 766system.cpu.l2cache.demand_accesses::total 1165480 # number of demand (read+write) accesses 767system.cpu.l2cache.overall_accesses::cpu.inst 20047 # number of overall (read+write) accesses 768system.cpu.l2cache.overall_accesses::cpu.data 1145433 # number of overall (read+write) accesses 769system.cpu.l2cache.overall_accesses::total 1165480 # number of overall (read+write) accesses 770system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283139 # miss rate for ReadExReq accesses 771system.cpu.l2cache.ReadExReq_miss_rate::total 0.283139 # miss rate for ReadExReq accesses 772system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.140270 # miss rate for ReadCleanReq accesses 773system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.140270 # miss rate for ReadCleanReq accesses 774system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.051337 # miss rate for ReadSharedReq accesses 775system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.051337 # miss rate for ReadSharedReq accesses 776system.cpu.l2cache.demand_miss_rate::cpu.inst 0.140270 # miss rate for demand accesses 777system.cpu.l2cache.demand_miss_rate::cpu.data 0.123510 # miss rate for demand accesses 778system.cpu.l2cache.demand_miss_rate::total 0.123798 # miss rate for demand accesses 779system.cpu.l2cache.overall_miss_rate::cpu.inst 0.140270 # miss rate for overall accesses 780system.cpu.l2cache.overall_miss_rate::cpu.data 0.123510 # miss rate for overall accesses 781system.cpu.l2cache.overall_miss_rate::total 0.123798 # miss rate for overall accesses 782system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79794.861257 # average ReadExReq miss latency 783system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79794.861257 # average ReadExReq miss latency 784system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83956.081081 # average ReadCleanReq miss latency 785system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83956.081081 # average ReadCleanReq miss latency 786system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 83064.330518 # average ReadSharedReq miss latency 787system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 83064.330518 # average ReadSharedReq miss latency 788system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83956.081081 # average overall miss latency 789system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80730.692292 # average overall miss latency 790system.cpu.l2cache.demand_avg_miss_latency::total 80793.552993 # average overall miss latency 791system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83956.081081 # average overall miss latency 792system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80730.692292 # average overall miss latency 793system.cpu.l2cache.overall_avg_miss_latency::total 80793.552993 # average overall miss latency 794system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 795system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 796system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 797system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 798system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 799system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 800system.cpu.l2cache.writebacks::writebacks 97528 # number of writebacks 801system.cpu.l2cache.writebacks::total 97528 # number of writebacks 802system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 2 # number of ReadCleanReq MSHR hits 803system.cpu.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits 804system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 13 # number of ReadSharedReq MSHR hits 805system.cpu.l2cache.ReadSharedReq_mshr_hits::total 13 # number of ReadSharedReq MSHR hits 806system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 807system.cpu.l2cache.demand_mshr_hits::cpu.data 13 # number of demand (read+write) MSHR hits 808system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits 809system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 810system.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits 811system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits 812system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100978 # number of ReadExReq MSHR misses 813system.cpu.l2cache.ReadExReq_mshr_misses::total 100978 # number of ReadExReq MSHR misses 814system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2810 # number of ReadCleanReq MSHR misses 815system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2810 # number of ReadCleanReq MSHR misses 816system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40481 # number of ReadSharedReq MSHR misses 817system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40481 # number of ReadSharedReq MSHR misses 818system.cpu.l2cache.demand_mshr_misses::cpu.inst 2810 # number of demand (read+write) MSHR misses 819system.cpu.l2cache.demand_mshr_misses::cpu.data 141459 # number of demand (read+write) MSHR misses 820system.cpu.l2cache.demand_mshr_misses::total 144269 # number of demand (read+write) MSHR misses 821system.cpu.l2cache.overall_mshr_misses::cpu.inst 2810 # number of overall MSHR misses 822system.cpu.l2cache.overall_mshr_misses::cpu.data 141459 # number of overall MSHR misses 823system.cpu.l2cache.overall_mshr_misses::total 144269 # number of overall MSHR misses 824system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7047745500 # number of ReadExReq MSHR miss cycles 825system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7047745500 # number of ReadExReq MSHR miss cycles 826system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 207624000 # number of ReadCleanReq MSHR miss cycles 827system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 207624000 # number of ReadCleanReq MSHR miss cycles 828system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2957433000 # number of ReadSharedReq MSHR miss cycles 829system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2957433000 # number of ReadSharedReq MSHR miss cycles 830system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 207624000 # number of demand (read+write) MSHR miss cycles 831system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10005178500 # number of demand (read+write) MSHR miss cycles 832system.cpu.l2cache.demand_mshr_miss_latency::total 10212802500 # number of demand (read+write) MSHR miss cycles 833system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 207624000 # number of overall MSHR miss cycles 834system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10005178500 # number of overall MSHR miss cycles 835system.cpu.l2cache.overall_mshr_miss_latency::total 10212802500 # number of overall MSHR miss cycles 836system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283139 # mshr miss rate for ReadExReq accesses 837system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283139 # mshr miss rate for ReadExReq accesses 838system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for ReadCleanReq accesses 839system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.140171 # mshr miss rate for ReadCleanReq accesses 840system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.051320 # mshr miss rate for ReadSharedReq accesses 841system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.051320 # mshr miss rate for ReadSharedReq accesses 842system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for demand accesses 843system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123498 # mshr miss rate for demand accesses 844system.cpu.l2cache.demand_mshr_miss_rate::total 0.123785 # mshr miss rate for demand accesses 845system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for overall accesses 846system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123498 # mshr miss rate for overall accesses 847system.cpu.l2cache.overall_mshr_miss_rate::total 0.123785 # mshr miss rate for overall accesses 848system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69794.861257 # average ReadExReq mshr miss latency 849system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69794.861257 # average ReadExReq mshr miss latency 850system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73887.544484 # average ReadCleanReq mshr miss latency 851system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73887.544484 # average ReadCleanReq mshr miss latency 852system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 73057.310837 # average ReadSharedReq mshr miss latency 853system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 73057.310837 # average ReadSharedReq mshr miss latency 854system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73887.544484 # average overall mshr miss latency 855system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70728.469026 # average overall mshr miss latency 856system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70789.999931 # average overall mshr miss latency 857system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73887.544484 # average overall mshr miss latency 858system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70728.469026 # average overall mshr miss latency 859system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70789.999931 # average overall mshr miss latency 860system.cpu.toL2Bus.snoop_filter.tot_requests 2324992 # Total number of requests made to the snoop filter. 861system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159582 # Number of requests hitting in the snoop filter with a single holder of the requested data. 862system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4996 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 863system.cpu.toL2Bus.snoop_filter.tot_snoops 2618 # Total number of snoops made to the snoop filter. 864system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2615 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 865system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 866system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 867system.cpu.toL2Bus.trans_dist::ReadResp 808842 # Transaction distribution 868system.cpu.toL2Bus.trans_dist::WritebackDirty 1166470 # Transaction distribution 869system.cpu.toL2Bus.trans_dist::WritebackClean 18175 # Transaction distribution 870system.cpu.toL2Bus.trans_dist::CleanEvict 87628 # Transaction distribution 871system.cpu.toL2Bus.trans_dist::ReadExReq 356638 # Transaction distribution 872system.cpu.toL2Bus.trans_dist::ReadExResp 356638 # Transaction distribution 873system.cpu.toL2Bus.trans_dist::ReadCleanReq 20047 # Transaction distribution 874system.cpu.toL2Bus.trans_dist::ReadSharedReq 788795 # Transaction distribution 875system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58269 # Packet count per connected master and slave (bytes) 876system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432203 # Packet count per connected master and slave (bytes) 877system.cpu.toL2Bus.pkt_count::total 3490472 # Packet count per connected master and slave (bytes) 878system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2446208 # Cumulative packet size per connected master and slave (bytes) 879system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141720000 # Cumulative packet size per connected master and slave (bytes) 880system.cpu.toL2Bus.pkt_size::total 144166208 # Cumulative packet size per connected master and slave (bytes) 881system.cpu.toL2Bus.snoops 112761 # Total snoops (count) 882system.cpu.toL2Bus.snoopTraffic 6241792 # Total snoop traffic (bytes) 883system.cpu.toL2Bus.snoop_fanout::samples 1278241 # Request fanout histogram 884system.cpu.toL2Bus.snoop_fanout::mean 0.006014 # Request fanout histogram 885system.cpu.toL2Bus.snoop_fanout::stdev 0.077345 # Request fanout histogram 886system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 887system.cpu.toL2Bus.snoop_fanout::0 1270557 99.40% 99.40% # Request fanout histogram 888system.cpu.toL2Bus.snoop_fanout::1 7681 0.60% 100.00% # Request fanout histogram 889system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram 890system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 891system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 892system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 893system.cpu.toL2Bus.snoop_fanout::total 1278241 # Request fanout histogram 894system.cpu.toL2Bus.reqLayer0.occupancy 2249613000 # Layer occupancy (ticks) 895system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 896system.cpu.toL2Bus.respLayer0.occupancy 30094452 # Layer occupancy (ticks) 897system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 898system.cpu.toL2Bus.respLayer1.occupancy 1718157983 # Layer occupancy (ticks) 899system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 900system.membus.snoop_filter.tot_requests 254412 # Total number of requests made to the snoop filter. 901system.membus.snoop_filter.hit_single_requests 110315 # Number of requests hitting in the snoop filter with a single holder of the requested data. 902system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 903system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 904system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 905system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 906system.membus.pwrStateResidencyTicks::UNDEFINED 366631719500 # Cumulative time (in ticks) in various power states 907system.membus.trans_dist::ReadResp 43291 # Transaction distribution 908system.membus.trans_dist::WritebackDirty 97528 # Transaction distribution 909system.membus.trans_dist::CleanEvict 12615 # Transaction distribution 910system.membus.trans_dist::ReadExReq 100978 # Transaction distribution 911system.membus.trans_dist::ReadExResp 100978 # Transaction distribution 912system.membus.trans_dist::ReadSharedReq 43291 # Transaction distribution 913system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398681 # Packet count per connected master and slave (bytes) 914system.membus.pkt_count::total 398681 # Packet count per connected master and slave (bytes) 915system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15475008 # Cumulative packet size per connected master and slave (bytes) 916system.membus.pkt_size::total 15475008 # Cumulative packet size per connected master and slave (bytes) 917system.membus.snoops 0 # Total snoops (count) 918system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 919system.membus.snoop_fanout::samples 144269 # Request fanout histogram 920system.membus.snoop_fanout::mean 0 # Request fanout histogram 921system.membus.snoop_fanout::stdev 0 # Request fanout histogram 922system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 923system.membus.snoop_fanout::0 144269 100.00% 100.00% # Request fanout histogram 924system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 925system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 926system.membus.snoop_fanout::min_value 0 # Request fanout histogram 927system.membus.snoop_fanout::max_value 0 # Request fanout histogram 928system.membus.snoop_fanout::total 144269 # Request fanout histogram 929system.membus.reqLayer0.occupancy 685129000 # Layer occupancy (ticks) 930system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 931system.membus.respLayer1.occupancy 765930250 # Layer occupancy (ticks) 932system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 933 934---------- End Simulation Statistics ---------- 935