stats.txt revision 11570
111507SCurtis.Dunham@arm.com 211507SCurtis.Dunham@arm.com---------- Begin Simulation Statistics ---------- 311570SCurtis.Dunham@arm.comsim_seconds 0.366439 # Number of seconds simulated 411570SCurtis.Dunham@arm.comsim_ticks 366439129500 # Number of ticks simulated 511570SCurtis.Dunham@arm.comfinal_tick 366439129500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611507SCurtis.Dunham@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711570SCurtis.Dunham@arm.comhost_inst_rate 188596 # Simulator instruction rate (inst/s) 811570SCurtis.Dunham@arm.comhost_op_rate 204275 # Simulator op (including micro ops) rate (op/s) 911570SCurtis.Dunham@arm.comhost_tick_rate 136422977 # Simulator tick rate (ticks/s) 1011570SCurtis.Dunham@arm.comhost_mem_usage 271112 # Number of bytes of host memory used 1111570SCurtis.Dunham@arm.comhost_seconds 2686.05 # Real time elapsed on the host 1211507SCurtis.Dunham@arm.comsim_insts 506579366 # Number of instructions simulated 1311507SCurtis.Dunham@arm.comsim_ops 548692589 # Number of ops (including micro ops) simulated 1411507SCurtis.Dunham@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511507SCurtis.Dunham@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611570SCurtis.Dunham@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states 1711570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.inst 179840 # Number of bytes read from this memory 1811570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.data 9028544 # Number of bytes read from this memory 1911570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 9208384 # Number of bytes read from this memory 2011570SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu.inst 179840 # Number of instructions bytes read from this memory 2111570SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 179840 # Number of instructions bytes read from this memory 2211570SCurtis.Dunham@arm.comsystem.physmem.bytes_written::writebacks 6219648 # Number of bytes written to this memory 2311570SCurtis.Dunham@arm.comsystem.physmem.bytes_written::total 6219648 # Number of bytes written to this memory 2411570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.inst 2810 # Number of read requests responded to by this memory 2511570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.data 141071 # Number of read requests responded to by this memory 2611570SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 143881 # Number of read requests responded to by this memory 2711570SCurtis.Dunham@arm.comsystem.physmem.num_writes::writebacks 97182 # Number of write requests responded to by this memory 2811570SCurtis.Dunham@arm.comsystem.physmem.num_writes::total 97182 # Number of write requests responded to by this memory 2911570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.inst 490777 # Total read bandwidth from this memory (bytes/s) 3011570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.data 24638591 # Total read bandwidth from this memory (bytes/s) 3111570SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 25129369 # Total read bandwidth from this memory (bytes/s) 3211570SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu.inst 490777 # Instruction read bandwidth from this memory (bytes/s) 3311570SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 490777 # Instruction read bandwidth from this memory (bytes/s) 3411570SCurtis.Dunham@arm.comsystem.physmem.bw_write::writebacks 16973209 # Write bandwidth from this memory (bytes/s) 3511570SCurtis.Dunham@arm.comsystem.physmem.bw_write::total 16973209 # Write bandwidth from this memory (bytes/s) 3611570SCurtis.Dunham@arm.comsystem.physmem.bw_total::writebacks 16973209 # Total bandwidth to/from this memory (bytes/s) 3711570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.inst 490777 # Total bandwidth to/from this memory (bytes/s) 3811570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.data 24638591 # Total bandwidth to/from this memory (bytes/s) 3911570SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 42102578 # Total bandwidth to/from this memory (bytes/s) 4011570SCurtis.Dunham@arm.comsystem.physmem.readReqs 143881 # Number of read requests accepted 4111570SCurtis.Dunham@arm.comsystem.physmem.writeReqs 97182 # Number of write requests accepted 4211570SCurtis.Dunham@arm.comsystem.physmem.readBursts 143881 # Number of DRAM read bursts, including those serviced by the write queue 4311570SCurtis.Dunham@arm.comsystem.physmem.writeBursts 97182 # Number of DRAM write bursts, including those merged in the write queue 4411570SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 9201344 # Total number of bytes read from DRAM 4511570SCurtis.Dunham@arm.comsystem.physmem.bytesReadWrQ 7040 # Total number of bytes read from write queue 4611570SCurtis.Dunham@arm.comsystem.physmem.bytesWritten 6217600 # Total number of bytes written to DRAM 4711570SCurtis.Dunham@arm.comsystem.physmem.bytesReadSys 9208384 # Total read bytes from the system interface side 4811570SCurtis.Dunham@arm.comsystem.physmem.bytesWrittenSys 6219648 # Total written bytes from the system interface side 4911570SCurtis.Dunham@arm.comsystem.physmem.servicedByWrQ 110 # Number of DRAM read bursts serviced by the write queue 5011507SCurtis.Dunham@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 5111507SCurtis.Dunham@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 5211570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 9364 # Per bank write bursts 5311570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::1 8912 # Per bank write bursts 5411507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::2 8949 # Per bank write bursts 5511570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::3 8655 # Per bank write bursts 5611570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::4 9392 # Per bank write bursts 5711507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::5 9355 # Per bank write bursts 5811570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::6 8959 # Per bank write bursts 5911570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::7 8100 # Per bank write bursts 6011507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::8 8596 # Per bank write bursts 6111570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::9 8629 # Per bank write bursts 6211570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::10 8739 # Per bank write bursts 6311570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::11 9451 # Per bank write bursts 6411570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::12 9334 # Per bank write bursts 6511570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::13 9512 # Per bank write bursts 6611570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::14 8707 # Per bank write bursts 6711570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::15 9117 # Per bank write bursts 6811570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::0 6231 # Per bank write bursts 6911570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::1 6102 # Per bank write bursts 7011570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::2 6028 # Per bank write bursts 7111570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::3 5879 # Per bank write bursts 7211570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::4 6243 # Per bank write bursts 7311570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::5 6239 # Per bank write bursts 7411570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::6 6050 # Per bank write bursts 7511570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::7 5507 # Per bank write bursts 7611570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::8 5786 # Per bank write bursts 7711570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::9 5859 # Per bank write bursts 7811507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::10 5978 # Per bank write bursts 7911570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::11 6493 # Per bank write bursts 8011570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::12 6351 # Per bank write bursts 8111570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::13 6319 # Per bank write bursts 8211570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::14 5995 # Per bank write bursts 8311570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::15 6090 # Per bank write bursts 8411507SCurtis.Dunham@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 8511507SCurtis.Dunham@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 8611570SCurtis.Dunham@arm.comsystem.physmem.totGap 366439104000 # Total gap between requests 8711507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 8811507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 8911507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 9011507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 9111507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 9211507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 9311570SCurtis.Dunham@arm.comsystem.physmem.readPktSize::6 143881 # Read request sizes (log2) 9411507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 9511507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 9611507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 9711507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 9811507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 9911507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 10011570SCurtis.Dunham@arm.comsystem.physmem.writePktSize::6 97182 # Write request sizes (log2) 10111570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::0 143447 # What read queue length does an incoming req see 10211570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::1 307 # What read queue length does an incoming req see 10311570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see 10411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 10511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 10611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 10711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 10811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 10911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 11011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 11111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 11211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 11311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 11411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 11511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 11611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 11711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 11811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 11911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 12011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 12111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 12211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 12311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 12411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 12511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 12611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 12711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 12811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 12911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 13011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 13111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 13211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 13311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 13411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 13511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 13611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 13711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 13811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 13911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 14011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 14111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 14211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 14311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 14411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 14511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 14611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 14711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 14811570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::15 2945 # What write queue length does an incoming req see 14911570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::16 3139 # What write queue length does an incoming req see 15011570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::17 5546 # What write queue length does an incoming req see 15111570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::18 5695 # What write queue length does an incoming req see 15211570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::19 5698 # What write queue length does an incoming req see 15311570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::20 5688 # What write queue length does an incoming req see 15411570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::21 5708 # What write queue length does an incoming req see 15511570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::22 5717 # What write queue length does an incoming req see 15611570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::23 5734 # What write queue length does an incoming req see 15711570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::24 5737 # What write queue length does an incoming req see 15811570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::25 5721 # What write queue length does an incoming req see 15911570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::26 5718 # What write queue length does an incoming req see 16011570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::27 5715 # What write queue length does an incoming req see 16111570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::28 5728 # What write queue length does an incoming req see 16211570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::29 5685 # What write queue length does an incoming req see 16311570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::30 5691 # What write queue length does an incoming req see 16411570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::31 5629 # What write queue length does an incoming req see 16511570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::32 5618 # What write queue length does an incoming req see 16611570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::33 18 # What write queue length does an incoming req see 16711570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see 16811570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see 16911570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see 17011570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see 17111570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see 17211570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see 17311570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see 17411570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see 17511570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see 17611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 18011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 18111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 18211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 18311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 18411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 18511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 18611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 19011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 19111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 19211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 19311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 19411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 19511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 19611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19711570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::samples 65604 # Bytes accessed per row activation 19811570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::mean 235.015914 # Bytes accessed per row activation 19911570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::gmean 156.088937 # Bytes accessed per row activation 20011570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::stdev 241.071665 # Bytes accessed per row activation 20111570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::0-127 24900 37.96% 37.96% # Bytes accessed per row activation 20211570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::128-255 18453 28.13% 66.08% # Bytes accessed per row activation 20311570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::256-383 7121 10.85% 76.94% # Bytes accessed per row activation 20411570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::384-511 7867 11.99% 88.93% # Bytes accessed per row activation 20511570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::512-639 1977 3.01% 91.94% # Bytes accessed per row activation 20611570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::640-767 1093 1.67% 93.61% # Bytes accessed per row activation 20711570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::768-895 809 1.23% 94.84% # Bytes accessed per row activation 20811570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::896-1023 630 0.96% 95.80% # Bytes accessed per row activation 20911570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::1024-1151 2754 4.20% 100.00% # Bytes accessed per row activation 21011570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::total 65604 # Bytes accessed per row activation 21111507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::samples 5611 # Reads before turning the bus around for writes 21211570SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::mean 25.620745 # Reads before turning the bus around for writes 21311570SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::stdev 380.610137 # Reads before turning the bus around for writes 21411507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::0-1023 5609 99.96% 99.96% # Reads before turning the bus around for writes 21511507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes 21611507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes 21711507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::total 5611 # Reads before turning the bus around for writes 21811507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::samples 5611 # Writes before turning the bus around for reads 21911570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::mean 17.314204 # Writes before turning the bus around for reads 22011570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::gmean 17.219748 # Writes before turning the bus around for reads 22111570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::stdev 2.335766 # Writes before turning the bus around for reads 22211570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::16-17 2654 47.30% 47.30% # Writes before turning the bus around for reads 22311570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::18-19 2805 49.99% 97.29% # Writes before turning the bus around for reads 22411570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::20-21 62 1.10% 98.40% # Writes before turning the bus around for reads 22511570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::22-23 24 0.43% 98.82% # Writes before turning the bus around for reads 22611570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::24-25 17 0.30% 99.13% # Writes before turning the bus around for reads 22711570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::26-27 10 0.18% 99.30% # Writes before turning the bus around for reads 22811570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::28-29 10 0.18% 99.48% # Writes before turning the bus around for reads 22911570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::30-31 10 0.18% 99.66% # Writes before turning the bus around for reads 23011570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::32-33 2 0.04% 99.70% # Writes before turning the bus around for reads 23111570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::34-35 4 0.07% 99.77% # Writes before turning the bus around for reads 23211570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::36-37 2 0.04% 99.80% # Writes before turning the bus around for reads 23311570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::38-39 1 0.02% 99.82% # Writes before turning the bus around for reads 23411570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::40-41 2 0.04% 99.86% # Writes before turning the bus around for reads 23511570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::44-45 1 0.02% 99.88% # Writes before turning the bus around for reads 23611570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::46-47 1 0.02% 99.89% # Writes before turning the bus around for reads 23711570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::48-49 1 0.02% 99.91% # Writes before turning the bus around for reads 23811570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::50-51 1 0.02% 99.93% # Writes before turning the bus around for reads 23911570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::52-53 2 0.04% 99.96% # Writes before turning the bus around for reads 24011570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::62-63 1 0.02% 99.98% # Writes before turning the bus around for reads 24111570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::98-99 1 0.02% 100.00% # Writes before turning the bus around for reads 24211507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::total 5611 # Writes before turning the bus around for reads 24311570SCurtis.Dunham@arm.comsystem.physmem.totQLat 1554447250 # Total ticks spent queuing 24411570SCurtis.Dunham@arm.comsystem.physmem.totMemAccLat 4250153500 # Total ticks spent from burst creation until serviced by the DRAM 24511570SCurtis.Dunham@arm.comsystem.physmem.totBusLat 718855000 # Total ticks spent in databus transfers 24611570SCurtis.Dunham@arm.comsystem.physmem.avgQLat 10811.97 # Average queueing delay per DRAM burst 24711507SCurtis.Dunham@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 24811570SCurtis.Dunham@arm.comsystem.physmem.avgMemAccLat 29561.97 # Average memory access latency per DRAM burst 24911570SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 25.11 # Average DRAM read bandwidth in MiByte/s 25011570SCurtis.Dunham@arm.comsystem.physmem.avgWrBW 16.97 # Average achieved write bandwidth in MiByte/s 25111570SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 25.13 # Average system read bandwidth in MiByte/s 25211570SCurtis.Dunham@arm.comsystem.physmem.avgWrBWSys 16.97 # Average system write bandwidth in MiByte/s 25311507SCurtis.Dunham@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 25411507SCurtis.Dunham@arm.comsystem.physmem.busUtil 0.33 # Data bus utilization in percentage 25511507SCurtis.Dunham@arm.comsystem.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads 25611507SCurtis.Dunham@arm.comsystem.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes 25711507SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing 25811570SCurtis.Dunham@arm.comsystem.physmem.avgWrQLen 19.60 # Average write queue length when enqueuing 25911570SCurtis.Dunham@arm.comsystem.physmem.readRowHits 110522 # Number of row buffer hits during reads 26011570SCurtis.Dunham@arm.comsystem.physmem.writeRowHits 64789 # Number of row buffer hits during writes 26111570SCurtis.Dunham@arm.comsystem.physmem.readRowHitRate 76.87 # Row buffer hit rate for reads 26211570SCurtis.Dunham@arm.comsystem.physmem.writeRowHitRate 66.67 # Row buffer hit rate for writes 26311570SCurtis.Dunham@arm.comsystem.physmem.avgGap 1520096.84 # Average gap between requests 26411570SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 72.76 # Row buffer hit rate, read and write combined 26511570SCurtis.Dunham@arm.comsystem.physmem_0.actEnergy 249842880 # Energy for activate commands per rank (pJ) 26611570SCurtis.Dunham@arm.comsystem.physmem_0.preEnergy 136323000 # Energy for precharge commands per rank (pJ) 26711570SCurtis.Dunham@arm.comsystem.physmem_0.readEnergy 559080600 # Energy for read commands per rank (pJ) 26811570SCurtis.Dunham@arm.comsystem.physmem_0.writeEnergy 312783120 # Energy for write commands per rank (pJ) 26911570SCurtis.Dunham@arm.comsystem.physmem_0.refreshEnergy 23933850720 # Energy for refresh commands per rank (pJ) 27011570SCurtis.Dunham@arm.comsystem.physmem_0.actBackEnergy 47987220420 # Energy for active background per rank (pJ) 27111570SCurtis.Dunham@arm.comsystem.physmem_0.preBackEnergy 177768013500 # Energy for precharge background per rank (pJ) 27211570SCurtis.Dunham@arm.comsystem.physmem_0.totalEnergy 250947114240 # Total energy per rank (pJ) 27311570SCurtis.Dunham@arm.comsystem.physmem_0.averagePower 684.830589 # Core power per rank (mW) 27411570SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::IDLE 295423376000 # Time in different power states 27511570SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::REF 12236120000 # Time in different power states 27611507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 27711570SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT 58777294250 # Time in different power states 27811507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 27911570SCurtis.Dunham@arm.comsystem.physmem_1.actEnergy 246017520 # Energy for activate commands per rank (pJ) 28011570SCurtis.Dunham@arm.comsystem.physmem_1.preEnergy 134235750 # Energy for precharge commands per rank (pJ) 28111570SCurtis.Dunham@arm.comsystem.physmem_1.readEnergy 562114800 # Energy for read commands per rank (pJ) 28211570SCurtis.Dunham@arm.comsystem.physmem_1.writeEnergy 316645200 # Energy for write commands per rank (pJ) 28311570SCurtis.Dunham@arm.comsystem.physmem_1.refreshEnergy 23933850720 # Energy for refresh commands per rank (pJ) 28411570SCurtis.Dunham@arm.comsystem.physmem_1.actBackEnergy 47395195335 # Energy for active background per rank (pJ) 28511570SCurtis.Dunham@arm.comsystem.physmem_1.preBackEnergy 178287321750 # Energy for precharge background per rank (pJ) 28611570SCurtis.Dunham@arm.comsystem.physmem_1.totalEnergy 250875381075 # Total energy per rank (pJ) 28711570SCurtis.Dunham@arm.comsystem.physmem_1.averagePower 684.634868 # Core power per rank (mW) 28811570SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::IDLE 296291389000 # Time in different power states 28911570SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::REF 12236120000 # Time in different power states 29011507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 29111570SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT 57909758500 # Time in different power states 29211507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 29311570SCurtis.Dunham@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states 29411570SCurtis.Dunham@arm.comsystem.cpu.branchPred.lookups 132103761 # Number of BP lookups 29511570SCurtis.Dunham@arm.comsystem.cpu.branchPred.condPredicted 98193255 # Number of conditional branches predicted 29611570SCurtis.Dunham@arm.comsystem.cpu.branchPred.condIncorrect 5910050 # Number of conditional branches incorrect 29711570SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBLookups 68601566 # Number of BTB lookups 29811570SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHits 60590451 # Number of BTB hits 29911507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 30011570SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHitPct 88.322256 # BTB Hit Percentage 30111570SCurtis.Dunham@arm.comsystem.cpu.branchPred.usedRAS 10017120 # Number of times the RAS was used to get a target. 30211570SCurtis.Dunham@arm.comsystem.cpu.branchPred.RASInCorrect 18743 # Number of incorrect RAS predictions. 30311570SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectLookups 3891572 # Number of indirect predictor lookups. 30411570SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectHits 3883027 # Number of indirect target hits. 30511570SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectMisses 8545 # Number of indirect misses. 30611570SCurtis.Dunham@arm.comsystem.cpu.branchPredindirectMispredicted 54138 # Number of mispredicted indirect branches. 30711507SCurtis.Dunham@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 30811570SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states 30911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 31011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 31111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 31211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 31311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 31411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 31511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 31611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 31711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 31811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 31911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 32011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 32111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 32211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 32311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 32411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 32511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 32611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 32711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 32811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 32911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 33011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 33111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 33211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 33311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 33411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 33511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 33611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 33711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 33811570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states 33911507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 34011507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 34111507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 34211507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 34311507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 34411507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 34511507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 34611507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 34711507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 34811507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 34911507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 35011507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 35111507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 35211507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 35311507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 35411507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 35511507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 35611507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 35711507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 35811507SCurtis.Dunham@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 35911507SCurtis.Dunham@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 36011507SCurtis.Dunham@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 36111507SCurtis.Dunham@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 36211507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 36311507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 36411507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 36511507SCurtis.Dunham@arm.comsystem.cpu.dtb.hits 0 # DTB hits 36611507SCurtis.Dunham@arm.comsystem.cpu.dtb.misses 0 # DTB misses 36711507SCurtis.Dunham@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 36811570SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states 36911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 37011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 37111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 37211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 37311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 37411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 37511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 37611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 37711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 37811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 37911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 38011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 38111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 38211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 38311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 38411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 38511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 38611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 38711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 38811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 38911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 39011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 39111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 39211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 39311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 39411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 39511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 39611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 39711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 39811570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states 39911507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 40011507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 40111507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 40211507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 40311507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 40411507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 40511507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 40611507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 40711507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 40811507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 40911507SCurtis.Dunham@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 41011507SCurtis.Dunham@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 41111507SCurtis.Dunham@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 41211507SCurtis.Dunham@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 41311507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 41411507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 41511507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 41611507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 41711507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 41811507SCurtis.Dunham@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 41911507SCurtis.Dunham@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 42011507SCurtis.Dunham@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 42111507SCurtis.Dunham@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 42211507SCurtis.Dunham@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 42311507SCurtis.Dunham@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 42411507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 42511507SCurtis.Dunham@arm.comsystem.cpu.itb.hits 0 # DTB hits 42611507SCurtis.Dunham@arm.comsystem.cpu.itb.misses 0 # DTB misses 42711507SCurtis.Dunham@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 42811507SCurtis.Dunham@arm.comsystem.cpu.workload.num_syscalls 548 # Number of system calls 42911570SCurtis.Dunham@arm.comsystem.cpu.pwrStateResidencyTicks::ON 366439129500 # Cumulative time (in ticks) in various power states 43011570SCurtis.Dunham@arm.comsystem.cpu.numCycles 732878259 # number of cpu cycles simulated 43111507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 43211507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 43311507SCurtis.Dunham@arm.comsystem.cpu.committedInsts 506579366 # Number of instructions committed 43411507SCurtis.Dunham@arm.comsystem.cpu.committedOps 548692589 # Number of ops (including micro ops) committed 43511570SCurtis.Dunham@arm.comsystem.cpu.discardedOps 12939743 # Number of ops (including micro ops) which were discarded before commit 43611507SCurtis.Dunham@arm.comsystem.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 43711570SCurtis.Dunham@arm.comsystem.cpu.cpi 1.446720 # CPI: cycles per instruction 43811570SCurtis.Dunham@arm.comsystem.cpu.ipc 0.691219 # IPC: instructions per cycle 43911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 44011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntAlu 375609862 68.46% 68.46% # Class of committed instruction 44111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction 44211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction 44311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction 44411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction 44511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction 44611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction 44711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction 44811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction 44911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction 45011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction 45111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction 45211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction 45311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction 45411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction 45511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction 45611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction 45711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction 45811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction 45911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction 46011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction 46111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction 46211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction 46311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction 46411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction 46511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction 46611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction 46711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction 46811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction 46911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction 47011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::MemWrite 56860222 10.36% 100.00% # Class of committed instruction 47111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 47211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 47311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::total 548692589 # Class of committed instruction 47411570SCurtis.Dunham@arm.comsystem.cpu.tickCycles 694071941 # Number of cycles that the object actually ticked 47511570SCurtis.Dunham@arm.comsystem.cpu.idleCycles 38806318 # Total number of cycles that the object has spent stopped 47611570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states 47711570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.replacements 1141337 # number of replacements 47811570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tagsinuse 4070.313641 # Cycle average of tags in use 47911570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.total_refs 171083825 # Total number of references to valid blocks. 48011570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.sampled_refs 1145433 # Sample count of references to valid blocks. 48111570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.avg_refs 149.361704 # Average number of references to valid blocks. 48211570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.warmup_cycle 5033914500 # Cycle when the warmup percentage was hit. 48311570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 4070.313641 # Average occupied blocks per requestor 48411570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.993729 # Average percentage of cache occupancy 48511570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.993729 # Average percentage of cache occupancy 48611507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 48711570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id 48811570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id 48911570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 549 # Occupied blocks per task id 49011570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::3 3501 # Occupied blocks per task id 49111507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 49211570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tag_accesses 346338115 # Number of tag accesses 49311570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.data_accesses 346338115 # Number of data accesses 49411570SCurtis.Dunham@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states 49511570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 114566020 # number of ReadReq hits 49611570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::total 114566020 # number of ReadReq hits 49711570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 53537929 # number of WriteReq hits 49811570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::total 53537929 # number of WriteReq hits 49911570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 2794 # number of SoftPFReq hits 50011570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 2794 # number of SoftPFReq hits 50111507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits 50211507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 50311507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 50411507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 50511570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::cpu.data 168103949 # number of demand (read+write) hits 50611570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::total 168103949 # number of demand (read+write) hits 50711570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::cpu.data 168106743 # number of overall hits 50811570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::total 168106743 # number of overall hits 50911570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 811381 # number of ReadReq misses 51011570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::total 811381 # number of ReadReq misses 51111570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 701120 # number of WriteReq misses 51211570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::total 701120 # number of WriteReq misses 51311570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 15 # number of SoftPFReq misses 51411570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 15 # number of SoftPFReq misses 51511570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::cpu.data 1512501 # number of demand (read+write) misses 51611570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::total 1512501 # number of demand (read+write) misses 51711570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::cpu.data 1512516 # number of overall misses 51811570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::total 1512516 # number of overall misses 51911570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 13462011000 # number of ReadReq miss cycles 52011570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 13462011000 # number of ReadReq miss cycles 52111570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 21943272000 # number of WriteReq miss cycles 52211570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 21943272000 # number of WriteReq miss cycles 52311570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 35405283000 # number of demand (read+write) miss cycles 52411570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::total 35405283000 # number of demand (read+write) miss cycles 52511570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 35405283000 # number of overall miss cycles 52611570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::total 35405283000 # number of overall miss cycles 52711570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 115377401 # number of ReadReq accesses(hits+misses) 52811570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::total 115377401 # number of ReadReq accesses(hits+misses) 52911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) 53011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) 53111570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 2809 # number of SoftPFReq accesses(hits+misses) 53211570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 2809 # number of SoftPFReq accesses(hits+misses) 53311507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) 53411507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 53511507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 53611507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 53711570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 169616450 # number of demand (read+write) accesses 53811570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::total 169616450 # number of demand (read+write) accesses 53911570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 169619259 # number of overall (read+write) accesses 54011570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::total 169619259 # number of overall (read+write) accesses 54111570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007032 # miss rate for ReadReq accesses 54211570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.007032 # miss rate for ReadReq accesses 54311570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012926 # miss rate for WriteReq accesses 54411570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.012926 # miss rate for WriteReq accesses 54511570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005340 # miss rate for SoftPFReq accesses 54611570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.005340 # miss rate for SoftPFReq accesses 54711570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.008917 # miss rate for demand accesses 54811570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.008917 # miss rate for demand accesses 54911570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.008917 # miss rate for overall accesses 55011570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.008917 # miss rate for overall accesses 55111570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16591.479219 # average ReadReq miss latency 55211570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 16591.479219 # average ReadReq miss latency 55311570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31297.455500 # average WriteReq miss latency 55411570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 31297.455500 # average WriteReq miss latency 55511570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 23408.436094 # average overall miss latency 55611570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 23408.436094 # average overall miss latency 55711570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 23408.203946 # average overall miss latency 55811570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 23408.203946 # average overall miss latency 55911507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 56011507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 56111507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 56211507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 56311507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 56411507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 56511570SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::writebacks 1069267 # number of writebacks 56611570SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::total 1069267 # number of writebacks 56711570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 22348 # number of ReadReq MSHR hits 56811570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 22348 # number of ReadReq MSHR hits 56911570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 344732 # number of WriteReq MSHR hits 57011570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 344732 # number of WriteReq MSHR hits 57111570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 367080 # number of demand (read+write) MSHR hits 57211570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::total 367080 # number of demand (read+write) MSHR hits 57311570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 367080 # number of overall MSHR hits 57411570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::total 367080 # number of overall MSHR hits 57511570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 789033 # number of ReadReq MSHR misses 57611570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 789033 # number of ReadReq MSHR misses 57711570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 356388 # number of WriteReq MSHR misses 57811570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 356388 # number of WriteReq MSHR misses 57911570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses 58011570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses 58111570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 1145421 # number of demand (read+write) MSHR misses 58211570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::total 1145421 # number of demand (read+write) MSHR misses 58311570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 1145433 # number of overall MSHR misses 58411570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::total 1145433 # number of overall MSHR misses 58511570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12369658000 # number of ReadReq MSHR miss cycles 58611570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 12369658000 # number of ReadReq MSHR miss cycles 58711570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11145800500 # number of WriteReq MSHR miss cycles 58811570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 11145800500 # number of WriteReq MSHR miss cycles 58911570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1093500 # number of SoftPFReq MSHR miss cycles 59011570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1093500 # number of SoftPFReq MSHR miss cycles 59111570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 23515458500 # number of demand (read+write) MSHR miss cycles 59211570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 23515458500 # number of demand (read+write) MSHR miss cycles 59311570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 23516552000 # number of overall MSHR miss cycles 59411570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 23516552000 # number of overall MSHR miss cycles 59511570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006839 # mshr miss rate for ReadReq accesses 59611570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006839 # mshr miss rate for ReadReq accesses 59711570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006571 # mshr miss rate for WriteReq accesses 59811570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006571 # mshr miss rate for WriteReq accesses 59911570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004272 # mshr miss rate for SoftPFReq accesses 60011570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004272 # mshr miss rate for SoftPFReq accesses 60111570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for demand accesses 60211570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.006753 # mshr miss rate for demand accesses 60311570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for overall accesses 60411570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.006753 # mshr miss rate for overall accesses 60511570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15676.984359 # average ReadReq mshr miss latency 60611570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15676.984359 # average ReadReq mshr miss latency 60711570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31274.342851 # average WriteReq mshr miss latency 60811570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31274.342851 # average WriteReq mshr miss latency 60911570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 91125 # average SoftPFReq mshr miss latency 61011570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 91125 # average SoftPFReq mshr miss latency 61111570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20529.969767 # average overall mshr miss latency 61211570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 20529.969767 # average overall mshr miss latency 61311570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20530.709347 # average overall mshr miss latency 61411570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 20530.709347 # average overall mshr miss latency 61511570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states 61611570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.replacements 18175 # number of replacements 61711570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tagsinuse 1187.153068 # Cycle average of tags in use 61811570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.total_refs 199148908 # Total number of references to valid blocks. 61911570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.sampled_refs 20047 # Sample count of references to valid blocks. 62011570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.avg_refs 9934.100264 # Average number of references to valid blocks. 62111507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 62211570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 1187.153068 # Average occupied blocks per requestor 62311570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.579665 # Average percentage of cache occupancy 62411570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::total 0.579665 # Average percentage of cache occupancy 62511570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id 62611507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 62711507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id 62811570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id 62911570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 311 # Occupied blocks per task id 63011570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 1400 # Occupied blocks per task id 63111570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id 63211570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tag_accesses 398357957 # Number of tag accesses 63311570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.data_accesses 398357957 # Number of data accesses 63411570SCurtis.Dunham@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states 63511570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 199148908 # number of ReadReq hits 63611570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::total 199148908 # number of ReadReq hits 63711570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::cpu.inst 199148908 # number of demand (read+write) hits 63811570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::total 199148908 # number of demand (read+write) hits 63911570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::cpu.inst 199148908 # number of overall hits 64011570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::total 199148908 # number of overall hits 64111570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 20047 # number of ReadReq misses 64211570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::total 20047 # number of ReadReq misses 64311570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::cpu.inst 20047 # number of demand (read+write) misses 64411570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::total 20047 # number of demand (read+write) misses 64511570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::cpu.inst 20047 # number of overall misses 64611570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::total 20047 # number of overall misses 64711570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 455856500 # number of ReadReq miss cycles 64811570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 455856500 # number of ReadReq miss cycles 64911570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 455856500 # number of demand (read+write) miss cycles 65011570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::total 455856500 # number of demand (read+write) miss cycles 65111570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 455856500 # number of overall miss cycles 65211570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::total 455856500 # number of overall miss cycles 65311570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 199168955 # number of ReadReq accesses(hits+misses) 65411570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::total 199168955 # number of ReadReq accesses(hits+misses) 65511570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 199168955 # number of demand (read+write) accesses 65611570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::total 199168955 # number of demand (read+write) accesses 65711570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 199168955 # number of overall (read+write) accesses 65811570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::total 199168955 # number of overall (read+write) accesses 65911507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000101 # miss rate for ReadReq accesses 66011507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.000101 # miss rate for ReadReq accesses 66111507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.000101 # miss rate for demand accesses 66211507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::total 0.000101 # miss rate for demand accesses 66311507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.000101 # miss rate for overall accesses 66411507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::total 0.000101 # miss rate for overall accesses 66511570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22739.387440 # average ReadReq miss latency 66611570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 22739.387440 # average ReadReq miss latency 66711570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 22739.387440 # average overall miss latency 66811570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 22739.387440 # average overall miss latency 66911570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 22739.387440 # average overall miss latency 67011570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 22739.387440 # average overall miss latency 67111507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 67211507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 67311507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 67411507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 67511507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 67611507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 67711570SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::writebacks 18175 # number of writebacks 67811570SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::total 18175 # number of writebacks 67911570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 20047 # number of ReadReq MSHR misses 68011570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 20047 # number of ReadReq MSHR misses 68111570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 20047 # number of demand (read+write) MSHR misses 68211570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::total 20047 # number of demand (read+write) MSHR misses 68311570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 20047 # number of overall MSHR misses 68411570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::total 20047 # number of overall MSHR misses 68511570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 435809500 # number of ReadReq MSHR miss cycles 68611570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 435809500 # number of ReadReq MSHR miss cycles 68711570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 435809500 # number of demand (read+write) MSHR miss cycles 68811570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 435809500 # number of demand (read+write) MSHR miss cycles 68911570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 435809500 # number of overall MSHR miss cycles 69011570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 435809500 # number of overall MSHR miss cycles 69111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for ReadReq accesses 69211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000101 # mshr miss rate for ReadReq accesses 69311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for demand accesses 69411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.000101 # mshr miss rate for demand accesses 69511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses 69611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses 69711570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21739.387440 # average ReadReq mshr miss latency 69811570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21739.387440 # average ReadReq mshr miss latency 69911570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21739.387440 # average overall mshr miss latency 70011570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 21739.387440 # average overall mshr miss latency 70111570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21739.387440 # average overall mshr miss latency 70211570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 21739.387440 # average overall mshr miss latency 70311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states 70411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.replacements 112318 # number of replacements 70511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tagsinuse 27616.037174 # Cycle average of tags in use 70611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.total_refs 1771878 # Total number of references to valid blocks. 70711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.sampled_refs 143528 # Sample count of references to valid blocks. 70811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.avg_refs 12.345173 # Average number of references to valid blocks. 70911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.warmup_cycle 165163715500 # Cycle when the warmup percentage was hit. 71011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 23489.264935 # Average occupied blocks per requestor 71111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 308.326790 # Average occupied blocks per requestor 71211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 3818.445449 # Average occupied blocks per requestor 71311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.716835 # Average percentage of cache occupancy 71411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.009409 # Average percentage of cache occupancy 71511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.116530 # Average percentage of cache occupancy 71611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.842775 # Average percentage of cache occupancy 71711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 31210 # Occupied blocks per task id 71811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id 71911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 318 # Occupied blocks per task id 72011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 4934 # Occupied blocks per task id 72111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 25858 # Occupied blocks per task id 72211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.952454 # Percentage of cache occupancy per task id 72311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tag_accesses 19060134 # Number of tag accesses 72411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.data_accesses 19060134 # Number of data accesses 72511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states 72611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 1069267 # number of WritebackDirty hits 72711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 1069267 # number of WritebackDirty hits 72811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 17938 # number of WritebackClean hits 72911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 17938 # number of WritebackClean hits 73011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 255711 # number of ReadExReq hits 73111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 255711 # number of ReadExReq hits 73211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17236 # number of ReadCleanReq hits 73311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 17236 # number of ReadCleanReq hits 73411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 748638 # number of ReadSharedReq hits 73511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 748638 # number of ReadSharedReq hits 73611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 17236 # number of demand (read+write) hits 73711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1004349 # number of demand (read+write) hits 73811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::total 1021585 # number of demand (read+write) hits 73911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 17236 # number of overall hits 74011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1004349 # number of overall hits 74111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::total 1021585 # number of overall hits 74211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 100927 # number of ReadExReq misses 74311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 100927 # number of ReadExReq misses 74411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2811 # number of ReadCleanReq misses 74511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 2811 # number of ReadCleanReq misses 74611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 40157 # number of ReadSharedReq misses 74711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 40157 # number of ReadSharedReq misses 74811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 2811 # number of demand (read+write) misses 74911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 141084 # number of demand (read+write) misses 75011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::total 143895 # number of demand (read+write) misses 75111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 2811 # number of overall misses 75211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 141084 # number of overall misses 75311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::total 143895 # number of overall misses 75411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7928727500 # number of ReadExReq miss cycles 75511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 7928727500 # number of ReadExReq miss cycles 75611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 224093000 # number of ReadCleanReq miss cycles 75711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 224093000 # number of ReadCleanReq miss cycles 75811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3306674000 # number of ReadSharedReq miss cycles 75911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 3306674000 # number of ReadSharedReq miss cycles 76011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 224093000 # number of demand (read+write) miss cycles 76111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 11235401500 # number of demand (read+write) miss cycles 76211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::total 11459494500 # number of demand (read+write) miss cycles 76311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 224093000 # number of overall miss cycles 76411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 11235401500 # number of overall miss cycles 76511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::total 11459494500 # number of overall miss cycles 76611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 1069267 # number of WritebackDirty accesses(hits+misses) 76711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 1069267 # number of WritebackDirty accesses(hits+misses) 76811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 17938 # number of WritebackClean accesses(hits+misses) 76911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 17938 # number of WritebackClean accesses(hits+misses) 77011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 356638 # number of ReadExReq accesses(hits+misses) 77111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 356638 # number of ReadExReq accesses(hits+misses) 77211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 20047 # number of ReadCleanReq accesses(hits+misses) 77311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 20047 # number of ReadCleanReq accesses(hits+misses) 77411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 788795 # number of ReadSharedReq accesses(hits+misses) 77511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 788795 # number of ReadSharedReq accesses(hits+misses) 77611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 20047 # number of demand (read+write) accesses 77711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1145433 # number of demand (read+write) accesses 77811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::total 1165480 # number of demand (read+write) accesses 77911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 20047 # number of overall (read+write) accesses 78011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1145433 # number of overall (read+write) accesses 78111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::total 1165480 # number of overall (read+write) accesses 78211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282996 # miss rate for ReadExReq accesses 78311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.282996 # miss rate for ReadExReq accesses 78411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.140220 # miss rate for ReadCleanReq accesses 78511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.140220 # miss rate for ReadCleanReq accesses 78611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050909 # miss rate for ReadSharedReq accesses 78711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050909 # miss rate for ReadSharedReq accesses 78811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.140220 # miss rate for demand accesses 78911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.123171 # miss rate for demand accesses 79011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.123464 # miss rate for demand accesses 79111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.140220 # miss rate for overall accesses 79211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.123171 # miss rate for overall accesses 79311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.123464 # miss rate for overall accesses 79411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78559.032766 # average ReadExReq miss latency 79511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 78559.032766 # average ReadExReq miss latency 79611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79720.028460 # average ReadCleanReq miss latency 79711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79720.028460 # average ReadCleanReq miss latency 79811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82343.651169 # average ReadSharedReq miss latency 79911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82343.651169 # average ReadSharedReq miss latency 80011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79720.028460 # average overall miss latency 80111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 79636.255706 # average overall miss latency 80211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 79637.892213 # average overall miss latency 80311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79720.028460 # average overall miss latency 80411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 79636.255706 # average overall miss latency 80511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 79637.892213 # average overall miss latency 80611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 80711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 80811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 80911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 81011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 81111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 81211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.writebacks::writebacks 97182 # number of writebacks 81311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.writebacks::total 97182 # number of writebacks 81411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 81511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 81611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 13 # number of ReadSharedReq MSHR hits 81711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 13 # number of ReadSharedReq MSHR hits 81811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 81911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 13 # number of demand (read+write) MSHR hits 82011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits 82111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 82211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits 82311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits 82411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100927 # number of ReadExReq MSHR misses 82511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 100927 # number of ReadExReq MSHR misses 82611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2810 # number of ReadCleanReq MSHR misses 82711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 2810 # number of ReadCleanReq MSHR misses 82811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40144 # number of ReadSharedReq MSHR misses 82911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 40144 # number of ReadSharedReq MSHR misses 83011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 2810 # number of demand (read+write) MSHR misses 83111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 141071 # number of demand (read+write) MSHR misses 83211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 143881 # number of demand (read+write) MSHR misses 83311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 2810 # number of overall MSHR misses 83411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 141071 # number of overall MSHR misses 83511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 143881 # number of overall MSHR misses 83611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6919457500 # number of ReadExReq MSHR miss cycles 83711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6919457500 # number of ReadExReq MSHR miss cycles 83811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 195753000 # number of ReadCleanReq MSHR miss cycles 83911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 195753000 # number of ReadCleanReq MSHR miss cycles 84011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2904162000 # number of ReadSharedReq MSHR miss cycles 84111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2904162000 # number of ReadSharedReq MSHR miss cycles 84211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195753000 # number of demand (read+write) MSHR miss cycles 84311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9823619500 # number of demand (read+write) MSHR miss cycles 84411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 10019372500 # number of demand (read+write) MSHR miss cycles 84511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195753000 # number of overall MSHR miss cycles 84611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9823619500 # number of overall MSHR miss cycles 84711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 10019372500 # number of overall MSHR miss cycles 84811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282996 # mshr miss rate for ReadExReq accesses 84911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282996 # mshr miss rate for ReadExReq accesses 85011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for ReadCleanReq accesses 85111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.140171 # mshr miss rate for ReadCleanReq accesses 85211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050893 # mshr miss rate for ReadSharedReq accesses 85311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050893 # mshr miss rate for ReadSharedReq accesses 85411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for demand accesses 85511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123160 # mshr miss rate for demand accesses 85611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.123452 # mshr miss rate for demand accesses 85711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for overall accesses 85811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123160 # mshr miss rate for overall accesses 85911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.123452 # mshr miss rate for overall accesses 86011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68559.032766 # average ReadExReq mshr miss latency 86111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68559.032766 # average ReadExReq mshr miss latency 86211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69662.989324 # average ReadCleanReq mshr miss latency 86311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69662.989324 # average ReadCleanReq mshr miss latency 86411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72343.612993 # average ReadSharedReq mshr miss latency 86511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72343.612993 # average ReadSharedReq mshr miss latency 86611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69662.989324 # average overall mshr miss latency 86711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69635.995350 # average overall mshr miss latency 86811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 69636.522543 # average overall mshr miss latency 86911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69662.989324 # average overall mshr miss latency 87011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69635.995350 # average overall mshr miss latency 87111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 69636.522543 # average overall mshr miss latency 87211570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 2324992 # Total number of requests made to the snoop filter. 87311570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 1159582 # Number of requests hitting in the snoop filter with a single holder of the requested data. 87411570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 4996 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 87511570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 2610 # Total number of snoops made to the snoop filter. 87611570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 2607 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 87711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 87811570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states 87911570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 808842 # Transaction distribution 88011570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 1166449 # Transaction distribution 88111570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 18175 # Transaction distribution 88211570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 87206 # Transaction distribution 88311570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 356638 # Transaction distribution 88411570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 356638 # Transaction distribution 88511570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 20047 # Transaction distribution 88611570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 788795 # Transaction distribution 88711570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58269 # Packet count per connected master and slave (bytes) 88811570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432203 # Packet count per connected master and slave (bytes) 88911570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count::total 3490472 # Packet count per connected master and slave (bytes) 89011570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2446208 # Cumulative packet size per connected master and slave (bytes) 89111570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141740800 # Cumulative packet size per connected master and slave (bytes) 89211570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size::total 144187008 # Cumulative packet size per connected master and slave (bytes) 89311570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoops 112318 # Total snoops (count) 89411570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoopTraffic 6219648 # Total snoop traffic (bytes) 89511570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 1277798 # Request fanout histogram 89611570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.006010 # Request fanout histogram 89711570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.077318 # Request fanout histogram 89811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 89911570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 1270122 99.40% 99.40% # Request fanout histogram 90011570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 7673 0.60% 100.00% # Request fanout histogram 90111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram 90211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 90311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 90411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 90511570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 1277798 # Request fanout histogram 90611570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 2249938000 # Layer occupancy (ticks) 90711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 90811570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 30093953 # Layer occupancy (ticks) 90911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 91011570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 1718157484 # Layer occupancy (ticks) 91111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 91211570SCurtis.Dunham@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states 91311570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 42954 # Transaction distribution 91411570SCurtis.Dunham@arm.comsystem.membus.trans_dist::WritebackDirty 97182 # Transaction distribution 91511570SCurtis.Dunham@arm.comsystem.membus.trans_dist::CleanEvict 12526 # Transaction distribution 91611570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 100927 # Transaction distribution 91711570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 100927 # Transaction distribution 91811570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 42954 # Transaction distribution 91911570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397470 # Packet count per connected master and slave (bytes) 92011570SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 397470 # Packet count per connected master and slave (bytes) 92111570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15428032 # Cumulative packet size per connected master and slave (bytes) 92211570SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 15428032 # Cumulative packet size per connected master and slave (bytes) 92311507SCurtis.Dunham@arm.comsystem.membus.snoops 0 # Total snoops (count) 92411570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 92511570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 253589 # Request fanout histogram 92611507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 92711507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 92811507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 92911570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 253589 100.00% 100.00% # Request fanout histogram 93011507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 93111507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 93211507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 93311507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 93411570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 253589 # Request fanout histogram 93511570SCurtis.Dunham@arm.comsystem.membus.reqLayer0.occupancy 685523500 # Layer occupancy (ticks) 93611507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 93711570SCurtis.Dunham@arm.comsystem.membus.respLayer1.occupancy 763755750 # Layer occupancy (ticks) 93811507SCurtis.Dunham@arm.comsystem.membus.respLayer1.utilization 0.2 # Layer utilization (%) 93911507SCurtis.Dunham@arm.com 94011507SCurtis.Dunham@arm.com---------- End Simulation Statistics ---------- 941