stats.txt revision 11570
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.366439 # Number of seconds simulated 4sim_ticks 366439129500 # Number of ticks simulated 5final_tick 366439129500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 188596 # Simulator instruction rate (inst/s) 8host_op_rate 204275 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 136422977 # Simulator tick rate (ticks/s) 10host_mem_usage 271112 # Number of bytes of host memory used 11host_seconds 2686.05 # Real time elapsed on the host 12sim_insts 506579366 # Number of instructions simulated 13sim_ops 548692589 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 179840 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 9028544 # Number of bytes read from this memory 19system.physmem.bytes_read::total 9208384 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 179840 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 179840 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 6219648 # Number of bytes written to this memory 23system.physmem.bytes_written::total 6219648 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 2810 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 141071 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 143881 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 97182 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 97182 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 490777 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 24638591 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 25129369 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 490777 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 490777 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 16973209 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 16973209 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 16973209 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 490777 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 24638591 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 42102578 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.readReqs 143881 # Number of read requests accepted 41system.physmem.writeReqs 97182 # Number of write requests accepted 42system.physmem.readBursts 143881 # Number of DRAM read bursts, including those serviced by the write queue 43system.physmem.writeBursts 97182 # Number of DRAM write bursts, including those merged in the write queue 44system.physmem.bytesReadDRAM 9201344 # Total number of bytes read from DRAM 45system.physmem.bytesReadWrQ 7040 # Total number of bytes read from write queue 46system.physmem.bytesWritten 6217600 # Total number of bytes written to DRAM 47system.physmem.bytesReadSys 9208384 # Total read bytes from the system interface side 48system.physmem.bytesWrittenSys 6219648 # Total written bytes from the system interface side 49system.physmem.servicedByWrQ 110 # Number of DRAM read bursts serviced by the write queue 50system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 51system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 52system.physmem.perBankRdBursts::0 9364 # Per bank write bursts 53system.physmem.perBankRdBursts::1 8912 # Per bank write bursts 54system.physmem.perBankRdBursts::2 8949 # Per bank write bursts 55system.physmem.perBankRdBursts::3 8655 # Per bank write bursts 56system.physmem.perBankRdBursts::4 9392 # Per bank write bursts 57system.physmem.perBankRdBursts::5 9355 # Per bank write bursts 58system.physmem.perBankRdBursts::6 8959 # Per bank write bursts 59system.physmem.perBankRdBursts::7 8100 # Per bank write bursts 60system.physmem.perBankRdBursts::8 8596 # Per bank write bursts 61system.physmem.perBankRdBursts::9 8629 # Per bank write bursts 62system.physmem.perBankRdBursts::10 8739 # Per bank write bursts 63system.physmem.perBankRdBursts::11 9451 # Per bank write bursts 64system.physmem.perBankRdBursts::12 9334 # Per bank write bursts 65system.physmem.perBankRdBursts::13 9512 # Per bank write bursts 66system.physmem.perBankRdBursts::14 8707 # Per bank write bursts 67system.physmem.perBankRdBursts::15 9117 # Per bank write bursts 68system.physmem.perBankWrBursts::0 6231 # Per bank write bursts 69system.physmem.perBankWrBursts::1 6102 # Per bank write bursts 70system.physmem.perBankWrBursts::2 6028 # Per bank write bursts 71system.physmem.perBankWrBursts::3 5879 # Per bank write bursts 72system.physmem.perBankWrBursts::4 6243 # Per bank write bursts 73system.physmem.perBankWrBursts::5 6239 # Per bank write bursts 74system.physmem.perBankWrBursts::6 6050 # Per bank write bursts 75system.physmem.perBankWrBursts::7 5507 # Per bank write bursts 76system.physmem.perBankWrBursts::8 5786 # Per bank write bursts 77system.physmem.perBankWrBursts::9 5859 # Per bank write bursts 78system.physmem.perBankWrBursts::10 5978 # Per bank write bursts 79system.physmem.perBankWrBursts::11 6493 # Per bank write bursts 80system.physmem.perBankWrBursts::12 6351 # Per bank write bursts 81system.physmem.perBankWrBursts::13 6319 # Per bank write bursts 82system.physmem.perBankWrBursts::14 5995 # Per bank write bursts 83system.physmem.perBankWrBursts::15 6090 # Per bank write bursts 84system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 85system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 86system.physmem.totGap 366439104000 # Total gap between requests 87system.physmem.readPktSize::0 0 # Read request sizes (log2) 88system.physmem.readPktSize::1 0 # Read request sizes (log2) 89system.physmem.readPktSize::2 0 # Read request sizes (log2) 90system.physmem.readPktSize::3 0 # Read request sizes (log2) 91system.physmem.readPktSize::4 0 # Read request sizes (log2) 92system.physmem.readPktSize::5 0 # Read request sizes (log2) 93system.physmem.readPktSize::6 143881 # Read request sizes (log2) 94system.physmem.writePktSize::0 0 # Write request sizes (log2) 95system.physmem.writePktSize::1 0 # Write request sizes (log2) 96system.physmem.writePktSize::2 0 # Write request sizes (log2) 97system.physmem.writePktSize::3 0 # Write request sizes (log2) 98system.physmem.writePktSize::4 0 # Write request sizes (log2) 99system.physmem.writePktSize::5 0 # Write request sizes (log2) 100system.physmem.writePktSize::6 97182 # Write request sizes (log2) 101system.physmem.rdQLenPdf::0 143447 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 307 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 133system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::15 2945 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::16 3139 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::17 5546 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::18 5695 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::19 5698 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::20 5688 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::21 5708 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::22 5717 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::23 5734 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::24 5737 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::25 5721 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::26 5718 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::27 5715 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::28 5728 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::29 5685 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::30 5691 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::31 5629 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::32 5618 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::33 18 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::37 4 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 197system.physmem.bytesPerActivate::samples 65604 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::mean 235.015914 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::gmean 156.088937 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::stdev 241.071665 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::0-127 24900 37.96% 37.96% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::128-255 18453 28.13% 66.08% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::256-383 7121 10.85% 76.94% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::384-511 7867 11.99% 88.93% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::512-639 1977 3.01% 91.94% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::640-767 1093 1.67% 93.61% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::768-895 809 1.23% 94.84% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::896-1023 630 0.96% 95.80% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1024-1151 2754 4.20% 100.00% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::total 65604 # Bytes accessed per row activation 211system.physmem.rdPerTurnAround::samples 5611 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::mean 25.620745 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::stdev 380.610137 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::0-1023 5609 99.96% 99.96% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::total 5611 # Reads before turning the bus around for writes 218system.physmem.wrPerTurnAround::samples 5611 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::mean 17.314204 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::gmean 17.219748 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::stdev 2.335766 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::16-17 2654 47.30% 47.30% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::18-19 2805 49.99% 97.29% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::20-21 62 1.10% 98.40% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::22-23 24 0.43% 98.82% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::24-25 17 0.30% 99.13% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::26-27 10 0.18% 99.30% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::28-29 10 0.18% 99.48% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::30-31 10 0.18% 99.66% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::32-33 2 0.04% 99.70% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::34-35 4 0.07% 99.77% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::36-37 2 0.04% 99.80% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::38-39 1 0.02% 99.82% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::40-41 2 0.04% 99.86% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::44-45 1 0.02% 99.88% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::46-47 1 0.02% 99.89% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::48-49 1 0.02% 99.91% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::50-51 1 0.02% 99.93% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::52-53 2 0.04% 99.96% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::62-63 1 0.02% 99.98% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::98-99 1 0.02% 100.00% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::total 5611 # Writes before turning the bus around for reads 243system.physmem.totQLat 1554447250 # Total ticks spent queuing 244system.physmem.totMemAccLat 4250153500 # Total ticks spent from burst creation until serviced by the DRAM 245system.physmem.totBusLat 718855000 # Total ticks spent in databus transfers 246system.physmem.avgQLat 10811.97 # Average queueing delay per DRAM burst 247system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 248system.physmem.avgMemAccLat 29561.97 # Average memory access latency per DRAM burst 249system.physmem.avgRdBW 25.11 # Average DRAM read bandwidth in MiByte/s 250system.physmem.avgWrBW 16.97 # Average achieved write bandwidth in MiByte/s 251system.physmem.avgRdBWSys 25.13 # Average system read bandwidth in MiByte/s 252system.physmem.avgWrBWSys 16.97 # Average system write bandwidth in MiByte/s 253system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 254system.physmem.busUtil 0.33 # Data bus utilization in percentage 255system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads 256system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes 257system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing 258system.physmem.avgWrQLen 19.60 # Average write queue length when enqueuing 259system.physmem.readRowHits 110522 # Number of row buffer hits during reads 260system.physmem.writeRowHits 64789 # Number of row buffer hits during writes 261system.physmem.readRowHitRate 76.87 # Row buffer hit rate for reads 262system.physmem.writeRowHitRate 66.67 # Row buffer hit rate for writes 263system.physmem.avgGap 1520096.84 # Average gap between requests 264system.physmem.pageHitRate 72.76 # Row buffer hit rate, read and write combined 265system.physmem_0.actEnergy 249842880 # Energy for activate commands per rank (pJ) 266system.physmem_0.preEnergy 136323000 # Energy for precharge commands per rank (pJ) 267system.physmem_0.readEnergy 559080600 # Energy for read commands per rank (pJ) 268system.physmem_0.writeEnergy 312783120 # Energy for write commands per rank (pJ) 269system.physmem_0.refreshEnergy 23933850720 # Energy for refresh commands per rank (pJ) 270system.physmem_0.actBackEnergy 47987220420 # Energy for active background per rank (pJ) 271system.physmem_0.preBackEnergy 177768013500 # Energy for precharge background per rank (pJ) 272system.physmem_0.totalEnergy 250947114240 # Total energy per rank (pJ) 273system.physmem_0.averagePower 684.830589 # Core power per rank (mW) 274system.physmem_0.memoryStateTime::IDLE 295423376000 # Time in different power states 275system.physmem_0.memoryStateTime::REF 12236120000 # Time in different power states 276system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 277system.physmem_0.memoryStateTime::ACT 58777294250 # Time in different power states 278system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 279system.physmem_1.actEnergy 246017520 # Energy for activate commands per rank (pJ) 280system.physmem_1.preEnergy 134235750 # Energy for precharge commands per rank (pJ) 281system.physmem_1.readEnergy 562114800 # Energy for read commands per rank (pJ) 282system.physmem_1.writeEnergy 316645200 # Energy for write commands per rank (pJ) 283system.physmem_1.refreshEnergy 23933850720 # Energy for refresh commands per rank (pJ) 284system.physmem_1.actBackEnergy 47395195335 # Energy for active background per rank (pJ) 285system.physmem_1.preBackEnergy 178287321750 # Energy for precharge background per rank (pJ) 286system.physmem_1.totalEnergy 250875381075 # Total energy per rank (pJ) 287system.physmem_1.averagePower 684.634868 # Core power per rank (mW) 288system.physmem_1.memoryStateTime::IDLE 296291389000 # Time in different power states 289system.physmem_1.memoryStateTime::REF 12236120000 # Time in different power states 290system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 291system.physmem_1.memoryStateTime::ACT 57909758500 # Time in different power states 292system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 293system.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states 294system.cpu.branchPred.lookups 132103761 # Number of BP lookups 295system.cpu.branchPred.condPredicted 98193255 # Number of conditional branches predicted 296system.cpu.branchPred.condIncorrect 5910050 # Number of conditional branches incorrect 297system.cpu.branchPred.BTBLookups 68601566 # Number of BTB lookups 298system.cpu.branchPred.BTBHits 60590451 # Number of BTB hits 299system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 300system.cpu.branchPred.BTBHitPct 88.322256 # BTB Hit Percentage 301system.cpu.branchPred.usedRAS 10017120 # Number of times the RAS was used to get a target. 302system.cpu.branchPred.RASInCorrect 18743 # Number of incorrect RAS predictions. 303system.cpu.branchPred.indirectLookups 3891572 # Number of indirect predictor lookups. 304system.cpu.branchPred.indirectHits 3883027 # Number of indirect target hits. 305system.cpu.branchPred.indirectMisses 8545 # Number of indirect misses. 306system.cpu.branchPredindirectMispredicted 54138 # Number of mispredicted indirect branches. 307system.cpu_clk_domain.clock 500 # Clock period in ticks 308system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states 309system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 310system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 311system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 312system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 313system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 314system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 315system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 316system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 317system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 318system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 319system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 320system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 321system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 322system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 323system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 324system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 325system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 326system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 327system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 328system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 329system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 330system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 331system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 332system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 333system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 334system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 335system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 336system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 337system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 338system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states 339system.cpu.dtb.walker.walks 0 # Table walker walks requested 340system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 341system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 342system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 343system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 344system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 345system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 346system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 347system.cpu.dtb.inst_hits 0 # ITB inst hits 348system.cpu.dtb.inst_misses 0 # ITB inst misses 349system.cpu.dtb.read_hits 0 # DTB read hits 350system.cpu.dtb.read_misses 0 # DTB read misses 351system.cpu.dtb.write_hits 0 # DTB write hits 352system.cpu.dtb.write_misses 0 # DTB write misses 353system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 354system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 355system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 356system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 357system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 358system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 359system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 360system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 361system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 362system.cpu.dtb.read_accesses 0 # DTB read accesses 363system.cpu.dtb.write_accesses 0 # DTB write accesses 364system.cpu.dtb.inst_accesses 0 # ITB inst accesses 365system.cpu.dtb.hits 0 # DTB hits 366system.cpu.dtb.misses 0 # DTB misses 367system.cpu.dtb.accesses 0 # DTB accesses 368system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states 369system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 370system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 371system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 372system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 373system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 374system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 375system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 376system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 377system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 378system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 379system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 380system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 381system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 382system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 383system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 384system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 385system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 386system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 387system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 388system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 389system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 390system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 391system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 392system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 393system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 394system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 395system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 396system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 397system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 398system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states 399system.cpu.itb.walker.walks 0 # Table walker walks requested 400system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 401system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 402system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 403system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 404system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 405system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 406system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 407system.cpu.itb.inst_hits 0 # ITB inst hits 408system.cpu.itb.inst_misses 0 # ITB inst misses 409system.cpu.itb.read_hits 0 # DTB read hits 410system.cpu.itb.read_misses 0 # DTB read misses 411system.cpu.itb.write_hits 0 # DTB write hits 412system.cpu.itb.write_misses 0 # DTB write misses 413system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 414system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 415system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 416system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 417system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 418system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 419system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 420system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 421system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 422system.cpu.itb.read_accesses 0 # DTB read accesses 423system.cpu.itb.write_accesses 0 # DTB write accesses 424system.cpu.itb.inst_accesses 0 # ITB inst accesses 425system.cpu.itb.hits 0 # DTB hits 426system.cpu.itb.misses 0 # DTB misses 427system.cpu.itb.accesses 0 # DTB accesses 428system.cpu.workload.num_syscalls 548 # Number of system calls 429system.cpu.pwrStateResidencyTicks::ON 366439129500 # Cumulative time (in ticks) in various power states 430system.cpu.numCycles 732878259 # number of cpu cycles simulated 431system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 432system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 433system.cpu.committedInsts 506579366 # Number of instructions committed 434system.cpu.committedOps 548692589 # Number of ops (including micro ops) committed 435system.cpu.discardedOps 12939743 # Number of ops (including micro ops) which were discarded before commit 436system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 437system.cpu.cpi 1.446720 # CPI: cycles per instruction 438system.cpu.ipc 0.691219 # IPC: instructions per cycle 439system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 440system.cpu.op_class_0::IntAlu 375609862 68.46% 68.46% # Class of committed instruction 441system.cpu.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction 442system.cpu.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction 443system.cpu.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction 444system.cpu.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction 445system.cpu.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction 446system.cpu.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction 447system.cpu.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction 448system.cpu.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction 449system.cpu.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction 450system.cpu.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction 451system.cpu.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction 452system.cpu.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction 453system.cpu.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction 454system.cpu.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction 455system.cpu.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction 456system.cpu.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction 457system.cpu.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction 458system.cpu.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction 459system.cpu.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction 460system.cpu.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction 461system.cpu.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction 462system.cpu.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction 463system.cpu.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction 464system.cpu.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction 465system.cpu.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction 466system.cpu.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction 467system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction 468system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction 469system.cpu.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction 470system.cpu.op_class_0::MemWrite 56860222 10.36% 100.00% # Class of committed instruction 471system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 472system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 473system.cpu.op_class_0::total 548692589 # Class of committed instruction 474system.cpu.tickCycles 694071941 # Number of cycles that the object actually ticked 475system.cpu.idleCycles 38806318 # Total number of cycles that the object has spent stopped 476system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states 477system.cpu.dcache.tags.replacements 1141337 # number of replacements 478system.cpu.dcache.tags.tagsinuse 4070.313641 # Cycle average of tags in use 479system.cpu.dcache.tags.total_refs 171083825 # Total number of references to valid blocks. 480system.cpu.dcache.tags.sampled_refs 1145433 # Sample count of references to valid blocks. 481system.cpu.dcache.tags.avg_refs 149.361704 # Average number of references to valid blocks. 482system.cpu.dcache.tags.warmup_cycle 5033914500 # Cycle when the warmup percentage was hit. 483system.cpu.dcache.tags.occ_blocks::cpu.data 4070.313641 # Average occupied blocks per requestor 484system.cpu.dcache.tags.occ_percent::cpu.data 0.993729 # Average percentage of cache occupancy 485system.cpu.dcache.tags.occ_percent::total 0.993729 # Average percentage of cache occupancy 486system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 487system.cpu.dcache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id 488system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id 489system.cpu.dcache.tags.age_task_id_blocks_1024::2 549 # Occupied blocks per task id 490system.cpu.dcache.tags.age_task_id_blocks_1024::3 3501 # Occupied blocks per task id 491system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 492system.cpu.dcache.tags.tag_accesses 346338115 # Number of tag accesses 493system.cpu.dcache.tags.data_accesses 346338115 # Number of data accesses 494system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states 495system.cpu.dcache.ReadReq_hits::cpu.data 114566020 # number of ReadReq hits 496system.cpu.dcache.ReadReq_hits::total 114566020 # number of ReadReq hits 497system.cpu.dcache.WriteReq_hits::cpu.data 53537929 # number of WriteReq hits 498system.cpu.dcache.WriteReq_hits::total 53537929 # number of WriteReq hits 499system.cpu.dcache.SoftPFReq_hits::cpu.data 2794 # number of SoftPFReq hits 500system.cpu.dcache.SoftPFReq_hits::total 2794 # number of SoftPFReq hits 501system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits 502system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 503system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 504system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 505system.cpu.dcache.demand_hits::cpu.data 168103949 # number of demand (read+write) hits 506system.cpu.dcache.demand_hits::total 168103949 # number of demand (read+write) hits 507system.cpu.dcache.overall_hits::cpu.data 168106743 # number of overall hits 508system.cpu.dcache.overall_hits::total 168106743 # number of overall hits 509system.cpu.dcache.ReadReq_misses::cpu.data 811381 # number of ReadReq misses 510system.cpu.dcache.ReadReq_misses::total 811381 # number of ReadReq misses 511system.cpu.dcache.WriteReq_misses::cpu.data 701120 # number of WriteReq misses 512system.cpu.dcache.WriteReq_misses::total 701120 # number of WriteReq misses 513system.cpu.dcache.SoftPFReq_misses::cpu.data 15 # number of SoftPFReq misses 514system.cpu.dcache.SoftPFReq_misses::total 15 # number of SoftPFReq misses 515system.cpu.dcache.demand_misses::cpu.data 1512501 # number of demand (read+write) misses 516system.cpu.dcache.demand_misses::total 1512501 # number of demand (read+write) misses 517system.cpu.dcache.overall_misses::cpu.data 1512516 # number of overall misses 518system.cpu.dcache.overall_misses::total 1512516 # number of overall misses 519system.cpu.dcache.ReadReq_miss_latency::cpu.data 13462011000 # number of ReadReq miss cycles 520system.cpu.dcache.ReadReq_miss_latency::total 13462011000 # number of ReadReq miss cycles 521system.cpu.dcache.WriteReq_miss_latency::cpu.data 21943272000 # number of WriteReq miss cycles 522system.cpu.dcache.WriteReq_miss_latency::total 21943272000 # number of WriteReq miss cycles 523system.cpu.dcache.demand_miss_latency::cpu.data 35405283000 # number of demand (read+write) miss cycles 524system.cpu.dcache.demand_miss_latency::total 35405283000 # number of demand (read+write) miss cycles 525system.cpu.dcache.overall_miss_latency::cpu.data 35405283000 # number of overall miss cycles 526system.cpu.dcache.overall_miss_latency::total 35405283000 # number of overall miss cycles 527system.cpu.dcache.ReadReq_accesses::cpu.data 115377401 # number of ReadReq accesses(hits+misses) 528system.cpu.dcache.ReadReq_accesses::total 115377401 # number of ReadReq accesses(hits+misses) 529system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) 530system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) 531system.cpu.dcache.SoftPFReq_accesses::cpu.data 2809 # number of SoftPFReq accesses(hits+misses) 532system.cpu.dcache.SoftPFReq_accesses::total 2809 # number of SoftPFReq accesses(hits+misses) 533system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) 534system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 535system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 536system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 537system.cpu.dcache.demand_accesses::cpu.data 169616450 # number of demand (read+write) accesses 538system.cpu.dcache.demand_accesses::total 169616450 # number of demand (read+write) accesses 539system.cpu.dcache.overall_accesses::cpu.data 169619259 # number of overall (read+write) accesses 540system.cpu.dcache.overall_accesses::total 169619259 # number of overall (read+write) accesses 541system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007032 # miss rate for ReadReq accesses 542system.cpu.dcache.ReadReq_miss_rate::total 0.007032 # miss rate for ReadReq accesses 543system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012926 # miss rate for WriteReq accesses 544system.cpu.dcache.WriteReq_miss_rate::total 0.012926 # miss rate for WriteReq accesses 545system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005340 # miss rate for SoftPFReq accesses 546system.cpu.dcache.SoftPFReq_miss_rate::total 0.005340 # miss rate for SoftPFReq accesses 547system.cpu.dcache.demand_miss_rate::cpu.data 0.008917 # miss rate for demand accesses 548system.cpu.dcache.demand_miss_rate::total 0.008917 # miss rate for demand accesses 549system.cpu.dcache.overall_miss_rate::cpu.data 0.008917 # miss rate for overall accesses 550system.cpu.dcache.overall_miss_rate::total 0.008917 # miss rate for overall accesses 551system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16591.479219 # average ReadReq miss latency 552system.cpu.dcache.ReadReq_avg_miss_latency::total 16591.479219 # average ReadReq miss latency 553system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31297.455500 # average WriteReq miss latency 554system.cpu.dcache.WriteReq_avg_miss_latency::total 31297.455500 # average WriteReq miss latency 555system.cpu.dcache.demand_avg_miss_latency::cpu.data 23408.436094 # average overall miss latency 556system.cpu.dcache.demand_avg_miss_latency::total 23408.436094 # average overall miss latency 557system.cpu.dcache.overall_avg_miss_latency::cpu.data 23408.203946 # average overall miss latency 558system.cpu.dcache.overall_avg_miss_latency::total 23408.203946 # average overall miss latency 559system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 560system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 561system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 562system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 563system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 564system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 565system.cpu.dcache.writebacks::writebacks 1069267 # number of writebacks 566system.cpu.dcache.writebacks::total 1069267 # number of writebacks 567system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22348 # number of ReadReq MSHR hits 568system.cpu.dcache.ReadReq_mshr_hits::total 22348 # number of ReadReq MSHR hits 569system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344732 # number of WriteReq MSHR hits 570system.cpu.dcache.WriteReq_mshr_hits::total 344732 # number of WriteReq MSHR hits 571system.cpu.dcache.demand_mshr_hits::cpu.data 367080 # number of demand (read+write) MSHR hits 572system.cpu.dcache.demand_mshr_hits::total 367080 # number of demand (read+write) MSHR hits 573system.cpu.dcache.overall_mshr_hits::cpu.data 367080 # number of overall MSHR hits 574system.cpu.dcache.overall_mshr_hits::total 367080 # number of overall MSHR hits 575system.cpu.dcache.ReadReq_mshr_misses::cpu.data 789033 # number of ReadReq MSHR misses 576system.cpu.dcache.ReadReq_mshr_misses::total 789033 # number of ReadReq MSHR misses 577system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356388 # number of WriteReq MSHR misses 578system.cpu.dcache.WriteReq_mshr_misses::total 356388 # number of WriteReq MSHR misses 579system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses 580system.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses 581system.cpu.dcache.demand_mshr_misses::cpu.data 1145421 # number of demand (read+write) MSHR misses 582system.cpu.dcache.demand_mshr_misses::total 1145421 # number of demand (read+write) MSHR misses 583system.cpu.dcache.overall_mshr_misses::cpu.data 1145433 # number of overall MSHR misses 584system.cpu.dcache.overall_mshr_misses::total 1145433 # number of overall MSHR misses 585system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12369658000 # number of ReadReq MSHR miss cycles 586system.cpu.dcache.ReadReq_mshr_miss_latency::total 12369658000 # number of ReadReq MSHR miss cycles 587system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11145800500 # number of WriteReq MSHR miss cycles 588system.cpu.dcache.WriteReq_mshr_miss_latency::total 11145800500 # number of WriteReq MSHR miss cycles 589system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1093500 # number of SoftPFReq MSHR miss cycles 590system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1093500 # number of SoftPFReq MSHR miss cycles 591system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23515458500 # number of demand (read+write) MSHR miss cycles 592system.cpu.dcache.demand_mshr_miss_latency::total 23515458500 # number of demand (read+write) MSHR miss cycles 593system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23516552000 # number of overall MSHR miss cycles 594system.cpu.dcache.overall_mshr_miss_latency::total 23516552000 # number of overall MSHR miss cycles 595system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006839 # mshr miss rate for ReadReq accesses 596system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006839 # mshr miss rate for ReadReq accesses 597system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006571 # mshr miss rate for WriteReq accesses 598system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006571 # mshr miss rate for WriteReq accesses 599system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004272 # mshr miss rate for SoftPFReq accesses 600system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004272 # mshr miss rate for SoftPFReq accesses 601system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for demand accesses 602system.cpu.dcache.demand_mshr_miss_rate::total 0.006753 # mshr miss rate for demand accesses 603system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for overall accesses 604system.cpu.dcache.overall_mshr_miss_rate::total 0.006753 # mshr miss rate for overall accesses 605system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15676.984359 # average ReadReq mshr miss latency 606system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15676.984359 # average ReadReq mshr miss latency 607system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31274.342851 # average WriteReq mshr miss latency 608system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31274.342851 # average WriteReq mshr miss latency 609system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 91125 # average SoftPFReq mshr miss latency 610system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 91125 # average SoftPFReq mshr miss latency 611system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20529.969767 # average overall mshr miss latency 612system.cpu.dcache.demand_avg_mshr_miss_latency::total 20529.969767 # average overall mshr miss latency 613system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20530.709347 # average overall mshr miss latency 614system.cpu.dcache.overall_avg_mshr_miss_latency::total 20530.709347 # average overall mshr miss latency 615system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states 616system.cpu.icache.tags.replacements 18175 # number of replacements 617system.cpu.icache.tags.tagsinuse 1187.153068 # Cycle average of tags in use 618system.cpu.icache.tags.total_refs 199148908 # Total number of references to valid blocks. 619system.cpu.icache.tags.sampled_refs 20047 # Sample count of references to valid blocks. 620system.cpu.icache.tags.avg_refs 9934.100264 # Average number of references to valid blocks. 621system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 622system.cpu.icache.tags.occ_blocks::cpu.inst 1187.153068 # Average occupied blocks per requestor 623system.cpu.icache.tags.occ_percent::cpu.inst 0.579665 # Average percentage of cache occupancy 624system.cpu.icache.tags.occ_percent::total 0.579665 # Average percentage of cache occupancy 625system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id 626system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 627system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id 628system.cpu.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id 629system.cpu.icache.tags.age_task_id_blocks_1024::3 311 # Occupied blocks per task id 630system.cpu.icache.tags.age_task_id_blocks_1024::4 1400 # Occupied blocks per task id 631system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id 632system.cpu.icache.tags.tag_accesses 398357957 # Number of tag accesses 633system.cpu.icache.tags.data_accesses 398357957 # Number of data accesses 634system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states 635system.cpu.icache.ReadReq_hits::cpu.inst 199148908 # number of ReadReq hits 636system.cpu.icache.ReadReq_hits::total 199148908 # number of ReadReq hits 637system.cpu.icache.demand_hits::cpu.inst 199148908 # number of demand (read+write) hits 638system.cpu.icache.demand_hits::total 199148908 # number of demand (read+write) hits 639system.cpu.icache.overall_hits::cpu.inst 199148908 # number of overall hits 640system.cpu.icache.overall_hits::total 199148908 # number of overall hits 641system.cpu.icache.ReadReq_misses::cpu.inst 20047 # number of ReadReq misses 642system.cpu.icache.ReadReq_misses::total 20047 # number of ReadReq misses 643system.cpu.icache.demand_misses::cpu.inst 20047 # number of demand (read+write) misses 644system.cpu.icache.demand_misses::total 20047 # number of demand (read+write) misses 645system.cpu.icache.overall_misses::cpu.inst 20047 # number of overall misses 646system.cpu.icache.overall_misses::total 20047 # number of overall misses 647system.cpu.icache.ReadReq_miss_latency::cpu.inst 455856500 # number of ReadReq miss cycles 648system.cpu.icache.ReadReq_miss_latency::total 455856500 # number of ReadReq miss cycles 649system.cpu.icache.demand_miss_latency::cpu.inst 455856500 # number of demand (read+write) miss cycles 650system.cpu.icache.demand_miss_latency::total 455856500 # number of demand (read+write) miss cycles 651system.cpu.icache.overall_miss_latency::cpu.inst 455856500 # number of overall miss cycles 652system.cpu.icache.overall_miss_latency::total 455856500 # number of overall miss cycles 653system.cpu.icache.ReadReq_accesses::cpu.inst 199168955 # number of ReadReq accesses(hits+misses) 654system.cpu.icache.ReadReq_accesses::total 199168955 # number of ReadReq accesses(hits+misses) 655system.cpu.icache.demand_accesses::cpu.inst 199168955 # number of demand (read+write) accesses 656system.cpu.icache.demand_accesses::total 199168955 # number of demand (read+write) accesses 657system.cpu.icache.overall_accesses::cpu.inst 199168955 # number of overall (read+write) accesses 658system.cpu.icache.overall_accesses::total 199168955 # number of overall (read+write) accesses 659system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000101 # miss rate for ReadReq accesses 660system.cpu.icache.ReadReq_miss_rate::total 0.000101 # miss rate for ReadReq accesses 661system.cpu.icache.demand_miss_rate::cpu.inst 0.000101 # miss rate for demand accesses 662system.cpu.icache.demand_miss_rate::total 0.000101 # miss rate for demand accesses 663system.cpu.icache.overall_miss_rate::cpu.inst 0.000101 # miss rate for overall accesses 664system.cpu.icache.overall_miss_rate::total 0.000101 # miss rate for overall accesses 665system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22739.387440 # average ReadReq miss latency 666system.cpu.icache.ReadReq_avg_miss_latency::total 22739.387440 # average ReadReq miss latency 667system.cpu.icache.demand_avg_miss_latency::cpu.inst 22739.387440 # average overall miss latency 668system.cpu.icache.demand_avg_miss_latency::total 22739.387440 # average overall miss latency 669system.cpu.icache.overall_avg_miss_latency::cpu.inst 22739.387440 # average overall miss latency 670system.cpu.icache.overall_avg_miss_latency::total 22739.387440 # average overall miss latency 671system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 672system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 673system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 674system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 675system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 676system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 677system.cpu.icache.writebacks::writebacks 18175 # number of writebacks 678system.cpu.icache.writebacks::total 18175 # number of writebacks 679system.cpu.icache.ReadReq_mshr_misses::cpu.inst 20047 # number of ReadReq MSHR misses 680system.cpu.icache.ReadReq_mshr_misses::total 20047 # number of ReadReq MSHR misses 681system.cpu.icache.demand_mshr_misses::cpu.inst 20047 # number of demand (read+write) MSHR misses 682system.cpu.icache.demand_mshr_misses::total 20047 # number of demand (read+write) MSHR misses 683system.cpu.icache.overall_mshr_misses::cpu.inst 20047 # number of overall MSHR misses 684system.cpu.icache.overall_mshr_misses::total 20047 # number of overall MSHR misses 685system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 435809500 # number of ReadReq MSHR miss cycles 686system.cpu.icache.ReadReq_mshr_miss_latency::total 435809500 # number of ReadReq MSHR miss cycles 687system.cpu.icache.demand_mshr_miss_latency::cpu.inst 435809500 # number of demand (read+write) MSHR miss cycles 688system.cpu.icache.demand_mshr_miss_latency::total 435809500 # number of demand (read+write) MSHR miss cycles 689system.cpu.icache.overall_mshr_miss_latency::cpu.inst 435809500 # number of overall MSHR miss cycles 690system.cpu.icache.overall_mshr_miss_latency::total 435809500 # number of overall MSHR miss cycles 691system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for ReadReq accesses 692system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000101 # mshr miss rate for ReadReq accesses 693system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for demand accesses 694system.cpu.icache.demand_mshr_miss_rate::total 0.000101 # mshr miss rate for demand accesses 695system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses 696system.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses 697system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21739.387440 # average ReadReq mshr miss latency 698system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21739.387440 # average ReadReq mshr miss latency 699system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21739.387440 # average overall mshr miss latency 700system.cpu.icache.demand_avg_mshr_miss_latency::total 21739.387440 # average overall mshr miss latency 701system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21739.387440 # average overall mshr miss latency 702system.cpu.icache.overall_avg_mshr_miss_latency::total 21739.387440 # average overall mshr miss latency 703system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states 704system.cpu.l2cache.tags.replacements 112318 # number of replacements 705system.cpu.l2cache.tags.tagsinuse 27616.037174 # Cycle average of tags in use 706system.cpu.l2cache.tags.total_refs 1771878 # Total number of references to valid blocks. 707system.cpu.l2cache.tags.sampled_refs 143528 # Sample count of references to valid blocks. 708system.cpu.l2cache.tags.avg_refs 12.345173 # Average number of references to valid blocks. 709system.cpu.l2cache.tags.warmup_cycle 165163715500 # Cycle when the warmup percentage was hit. 710system.cpu.l2cache.tags.occ_blocks::writebacks 23489.264935 # Average occupied blocks per requestor 711system.cpu.l2cache.tags.occ_blocks::cpu.inst 308.326790 # Average occupied blocks per requestor 712system.cpu.l2cache.tags.occ_blocks::cpu.data 3818.445449 # Average occupied blocks per requestor 713system.cpu.l2cache.tags.occ_percent::writebacks 0.716835 # Average percentage of cache occupancy 714system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009409 # Average percentage of cache occupancy 715system.cpu.l2cache.tags.occ_percent::cpu.data 0.116530 # Average percentage of cache occupancy 716system.cpu.l2cache.tags.occ_percent::total 0.842775 # Average percentage of cache occupancy 717system.cpu.l2cache.tags.occ_task_id_blocks::1024 31210 # Occupied blocks per task id 718system.cpu.l2cache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id 719system.cpu.l2cache.tags.age_task_id_blocks_1024::2 318 # Occupied blocks per task id 720system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4934 # Occupied blocks per task id 721system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25858 # Occupied blocks per task id 722system.cpu.l2cache.tags.occ_task_id_percent::1024 0.952454 # Percentage of cache occupancy per task id 723system.cpu.l2cache.tags.tag_accesses 19060134 # Number of tag accesses 724system.cpu.l2cache.tags.data_accesses 19060134 # Number of data accesses 725system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states 726system.cpu.l2cache.WritebackDirty_hits::writebacks 1069267 # number of WritebackDirty hits 727system.cpu.l2cache.WritebackDirty_hits::total 1069267 # number of WritebackDirty hits 728system.cpu.l2cache.WritebackClean_hits::writebacks 17938 # number of WritebackClean hits 729system.cpu.l2cache.WritebackClean_hits::total 17938 # number of WritebackClean hits 730system.cpu.l2cache.ReadExReq_hits::cpu.data 255711 # number of ReadExReq hits 731system.cpu.l2cache.ReadExReq_hits::total 255711 # number of ReadExReq hits 732system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17236 # number of ReadCleanReq hits 733system.cpu.l2cache.ReadCleanReq_hits::total 17236 # number of ReadCleanReq hits 734system.cpu.l2cache.ReadSharedReq_hits::cpu.data 748638 # number of ReadSharedReq hits 735system.cpu.l2cache.ReadSharedReq_hits::total 748638 # number of ReadSharedReq hits 736system.cpu.l2cache.demand_hits::cpu.inst 17236 # number of demand (read+write) hits 737system.cpu.l2cache.demand_hits::cpu.data 1004349 # number of demand (read+write) hits 738system.cpu.l2cache.demand_hits::total 1021585 # number of demand (read+write) hits 739system.cpu.l2cache.overall_hits::cpu.inst 17236 # number of overall hits 740system.cpu.l2cache.overall_hits::cpu.data 1004349 # number of overall hits 741system.cpu.l2cache.overall_hits::total 1021585 # number of overall hits 742system.cpu.l2cache.ReadExReq_misses::cpu.data 100927 # number of ReadExReq misses 743system.cpu.l2cache.ReadExReq_misses::total 100927 # number of ReadExReq misses 744system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2811 # number of ReadCleanReq misses 745system.cpu.l2cache.ReadCleanReq_misses::total 2811 # number of ReadCleanReq misses 746system.cpu.l2cache.ReadSharedReq_misses::cpu.data 40157 # number of ReadSharedReq misses 747system.cpu.l2cache.ReadSharedReq_misses::total 40157 # number of ReadSharedReq misses 748system.cpu.l2cache.demand_misses::cpu.inst 2811 # number of demand (read+write) misses 749system.cpu.l2cache.demand_misses::cpu.data 141084 # number of demand (read+write) misses 750system.cpu.l2cache.demand_misses::total 143895 # number of demand (read+write) misses 751system.cpu.l2cache.overall_misses::cpu.inst 2811 # number of overall misses 752system.cpu.l2cache.overall_misses::cpu.data 141084 # number of overall misses 753system.cpu.l2cache.overall_misses::total 143895 # number of overall misses 754system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7928727500 # number of ReadExReq miss cycles 755system.cpu.l2cache.ReadExReq_miss_latency::total 7928727500 # number of ReadExReq miss cycles 756system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 224093000 # number of ReadCleanReq miss cycles 757system.cpu.l2cache.ReadCleanReq_miss_latency::total 224093000 # number of ReadCleanReq miss cycles 758system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3306674000 # number of ReadSharedReq miss cycles 759system.cpu.l2cache.ReadSharedReq_miss_latency::total 3306674000 # number of ReadSharedReq miss cycles 760system.cpu.l2cache.demand_miss_latency::cpu.inst 224093000 # number of demand (read+write) miss cycles 761system.cpu.l2cache.demand_miss_latency::cpu.data 11235401500 # number of demand (read+write) miss cycles 762system.cpu.l2cache.demand_miss_latency::total 11459494500 # number of demand (read+write) miss cycles 763system.cpu.l2cache.overall_miss_latency::cpu.inst 224093000 # number of overall miss cycles 764system.cpu.l2cache.overall_miss_latency::cpu.data 11235401500 # number of overall miss cycles 765system.cpu.l2cache.overall_miss_latency::total 11459494500 # number of overall miss cycles 766system.cpu.l2cache.WritebackDirty_accesses::writebacks 1069267 # number of WritebackDirty accesses(hits+misses) 767system.cpu.l2cache.WritebackDirty_accesses::total 1069267 # number of WritebackDirty accesses(hits+misses) 768system.cpu.l2cache.WritebackClean_accesses::writebacks 17938 # number of WritebackClean accesses(hits+misses) 769system.cpu.l2cache.WritebackClean_accesses::total 17938 # number of WritebackClean accesses(hits+misses) 770system.cpu.l2cache.ReadExReq_accesses::cpu.data 356638 # number of ReadExReq accesses(hits+misses) 771system.cpu.l2cache.ReadExReq_accesses::total 356638 # number of ReadExReq accesses(hits+misses) 772system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 20047 # number of ReadCleanReq accesses(hits+misses) 773system.cpu.l2cache.ReadCleanReq_accesses::total 20047 # number of ReadCleanReq accesses(hits+misses) 774system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 788795 # number of ReadSharedReq accesses(hits+misses) 775system.cpu.l2cache.ReadSharedReq_accesses::total 788795 # number of ReadSharedReq accesses(hits+misses) 776system.cpu.l2cache.demand_accesses::cpu.inst 20047 # number of demand (read+write) accesses 777system.cpu.l2cache.demand_accesses::cpu.data 1145433 # number of demand (read+write) accesses 778system.cpu.l2cache.demand_accesses::total 1165480 # number of demand (read+write) accesses 779system.cpu.l2cache.overall_accesses::cpu.inst 20047 # number of overall (read+write) accesses 780system.cpu.l2cache.overall_accesses::cpu.data 1145433 # number of overall (read+write) accesses 781system.cpu.l2cache.overall_accesses::total 1165480 # number of overall (read+write) accesses 782system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.282996 # miss rate for ReadExReq accesses 783system.cpu.l2cache.ReadExReq_miss_rate::total 0.282996 # miss rate for ReadExReq accesses 784system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.140220 # miss rate for ReadCleanReq accesses 785system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.140220 # miss rate for ReadCleanReq accesses 786system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050909 # miss rate for ReadSharedReq accesses 787system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050909 # miss rate for ReadSharedReq accesses 788system.cpu.l2cache.demand_miss_rate::cpu.inst 0.140220 # miss rate for demand accesses 789system.cpu.l2cache.demand_miss_rate::cpu.data 0.123171 # miss rate for demand accesses 790system.cpu.l2cache.demand_miss_rate::total 0.123464 # miss rate for demand accesses 791system.cpu.l2cache.overall_miss_rate::cpu.inst 0.140220 # miss rate for overall accesses 792system.cpu.l2cache.overall_miss_rate::cpu.data 0.123171 # miss rate for overall accesses 793system.cpu.l2cache.overall_miss_rate::total 0.123464 # miss rate for overall accesses 794system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78559.032766 # average ReadExReq miss latency 795system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78559.032766 # average ReadExReq miss latency 796system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79720.028460 # average ReadCleanReq miss latency 797system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79720.028460 # average ReadCleanReq miss latency 798system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82343.651169 # average ReadSharedReq miss latency 799system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82343.651169 # average ReadSharedReq miss latency 800system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79720.028460 # average overall miss latency 801system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79636.255706 # average overall miss latency 802system.cpu.l2cache.demand_avg_miss_latency::total 79637.892213 # average overall miss latency 803system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79720.028460 # average overall miss latency 804system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79636.255706 # average overall miss latency 805system.cpu.l2cache.overall_avg_miss_latency::total 79637.892213 # average overall miss latency 806system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 807system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 808system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 809system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 810system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 811system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 812system.cpu.l2cache.writebacks::writebacks 97182 # number of writebacks 813system.cpu.l2cache.writebacks::total 97182 # number of writebacks 814system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 815system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 816system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 13 # number of ReadSharedReq MSHR hits 817system.cpu.l2cache.ReadSharedReq_mshr_hits::total 13 # number of ReadSharedReq MSHR hits 818system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 819system.cpu.l2cache.demand_mshr_hits::cpu.data 13 # number of demand (read+write) MSHR hits 820system.cpu.l2cache.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits 821system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 822system.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits 823system.cpu.l2cache.overall_mshr_hits::total 14 # number of overall MSHR hits 824system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100927 # number of ReadExReq MSHR misses 825system.cpu.l2cache.ReadExReq_mshr_misses::total 100927 # number of ReadExReq MSHR misses 826system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2810 # number of ReadCleanReq MSHR misses 827system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2810 # number of ReadCleanReq MSHR misses 828system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40144 # number of ReadSharedReq MSHR misses 829system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40144 # number of ReadSharedReq MSHR misses 830system.cpu.l2cache.demand_mshr_misses::cpu.inst 2810 # number of demand (read+write) MSHR misses 831system.cpu.l2cache.demand_mshr_misses::cpu.data 141071 # number of demand (read+write) MSHR misses 832system.cpu.l2cache.demand_mshr_misses::total 143881 # number of demand (read+write) MSHR misses 833system.cpu.l2cache.overall_mshr_misses::cpu.inst 2810 # number of overall MSHR misses 834system.cpu.l2cache.overall_mshr_misses::cpu.data 141071 # number of overall MSHR misses 835system.cpu.l2cache.overall_mshr_misses::total 143881 # number of overall MSHR misses 836system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6919457500 # number of ReadExReq MSHR miss cycles 837system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6919457500 # number of ReadExReq MSHR miss cycles 838system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 195753000 # number of ReadCleanReq MSHR miss cycles 839system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 195753000 # number of ReadCleanReq MSHR miss cycles 840system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2904162000 # number of ReadSharedReq MSHR miss cycles 841system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2904162000 # number of ReadSharedReq MSHR miss cycles 842system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195753000 # number of demand (read+write) MSHR miss cycles 843system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9823619500 # number of demand (read+write) MSHR miss cycles 844system.cpu.l2cache.demand_mshr_miss_latency::total 10019372500 # number of demand (read+write) MSHR miss cycles 845system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195753000 # number of overall MSHR miss cycles 846system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9823619500 # number of overall MSHR miss cycles 847system.cpu.l2cache.overall_mshr_miss_latency::total 10019372500 # number of overall MSHR miss cycles 848system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282996 # mshr miss rate for ReadExReq accesses 849system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282996 # mshr miss rate for ReadExReq accesses 850system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for ReadCleanReq accesses 851system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.140171 # mshr miss rate for ReadCleanReq accesses 852system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050893 # mshr miss rate for ReadSharedReq accesses 853system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050893 # mshr miss rate for ReadSharedReq accesses 854system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for demand accesses 855system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123160 # mshr miss rate for demand accesses 856system.cpu.l2cache.demand_mshr_miss_rate::total 0.123452 # mshr miss rate for demand accesses 857system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140171 # mshr miss rate for overall accesses 858system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123160 # mshr miss rate for overall accesses 859system.cpu.l2cache.overall_mshr_miss_rate::total 0.123452 # mshr miss rate for overall accesses 860system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68559.032766 # average ReadExReq mshr miss latency 861system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68559.032766 # average ReadExReq mshr miss latency 862system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69662.989324 # average ReadCleanReq mshr miss latency 863system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69662.989324 # average ReadCleanReq mshr miss latency 864system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72343.612993 # average ReadSharedReq mshr miss latency 865system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72343.612993 # average ReadSharedReq mshr miss latency 866system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69662.989324 # average overall mshr miss latency 867system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69635.995350 # average overall mshr miss latency 868system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69636.522543 # average overall mshr miss latency 869system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69662.989324 # average overall mshr miss latency 870system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69635.995350 # average overall mshr miss latency 871system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69636.522543 # average overall mshr miss latency 872system.cpu.toL2Bus.snoop_filter.tot_requests 2324992 # Total number of requests made to the snoop filter. 873system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159582 # Number of requests hitting in the snoop filter with a single holder of the requested data. 874system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4996 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 875system.cpu.toL2Bus.snoop_filter.tot_snoops 2610 # Total number of snoops made to the snoop filter. 876system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2607 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 877system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 878system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states 879system.cpu.toL2Bus.trans_dist::ReadResp 808842 # Transaction distribution 880system.cpu.toL2Bus.trans_dist::WritebackDirty 1166449 # Transaction distribution 881system.cpu.toL2Bus.trans_dist::WritebackClean 18175 # Transaction distribution 882system.cpu.toL2Bus.trans_dist::CleanEvict 87206 # Transaction distribution 883system.cpu.toL2Bus.trans_dist::ReadExReq 356638 # Transaction distribution 884system.cpu.toL2Bus.trans_dist::ReadExResp 356638 # Transaction distribution 885system.cpu.toL2Bus.trans_dist::ReadCleanReq 20047 # Transaction distribution 886system.cpu.toL2Bus.trans_dist::ReadSharedReq 788795 # Transaction distribution 887system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58269 # Packet count per connected master and slave (bytes) 888system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432203 # Packet count per connected master and slave (bytes) 889system.cpu.toL2Bus.pkt_count::total 3490472 # Packet count per connected master and slave (bytes) 890system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2446208 # Cumulative packet size per connected master and slave (bytes) 891system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141740800 # Cumulative packet size per connected master and slave (bytes) 892system.cpu.toL2Bus.pkt_size::total 144187008 # Cumulative packet size per connected master and slave (bytes) 893system.cpu.toL2Bus.snoops 112318 # Total snoops (count) 894system.cpu.toL2Bus.snoopTraffic 6219648 # Total snoop traffic (bytes) 895system.cpu.toL2Bus.snoop_fanout::samples 1277798 # Request fanout histogram 896system.cpu.toL2Bus.snoop_fanout::mean 0.006010 # Request fanout histogram 897system.cpu.toL2Bus.snoop_fanout::stdev 0.077318 # Request fanout histogram 898system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 899system.cpu.toL2Bus.snoop_fanout::0 1270122 99.40% 99.40% # Request fanout histogram 900system.cpu.toL2Bus.snoop_fanout::1 7673 0.60% 100.00% # Request fanout histogram 901system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram 902system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 903system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 904system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 905system.cpu.toL2Bus.snoop_fanout::total 1277798 # Request fanout histogram 906system.cpu.toL2Bus.reqLayer0.occupancy 2249938000 # Layer occupancy (ticks) 907system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 908system.cpu.toL2Bus.respLayer0.occupancy 30093953 # Layer occupancy (ticks) 909system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 910system.cpu.toL2Bus.respLayer1.occupancy 1718157484 # Layer occupancy (ticks) 911system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 912system.membus.pwrStateResidencyTicks::UNDEFINED 366439129500 # Cumulative time (in ticks) in various power states 913system.membus.trans_dist::ReadResp 42954 # Transaction distribution 914system.membus.trans_dist::WritebackDirty 97182 # Transaction distribution 915system.membus.trans_dist::CleanEvict 12526 # Transaction distribution 916system.membus.trans_dist::ReadExReq 100927 # Transaction distribution 917system.membus.trans_dist::ReadExResp 100927 # Transaction distribution 918system.membus.trans_dist::ReadSharedReq 42954 # Transaction distribution 919system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397470 # Packet count per connected master and slave (bytes) 920system.membus.pkt_count::total 397470 # Packet count per connected master and slave (bytes) 921system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15428032 # Cumulative packet size per connected master and slave (bytes) 922system.membus.pkt_size::total 15428032 # Cumulative packet size per connected master and slave (bytes) 923system.membus.snoops 0 # Total snoops (count) 924system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 925system.membus.snoop_fanout::samples 253589 # Request fanout histogram 926system.membus.snoop_fanout::mean 0 # Request fanout histogram 927system.membus.snoop_fanout::stdev 0 # Request fanout histogram 928system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 929system.membus.snoop_fanout::0 253589 100.00% 100.00% # Request fanout histogram 930system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 931system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 932system.membus.snoop_fanout::min_value 0 # Request fanout histogram 933system.membus.snoop_fanout::max_value 0 # Request fanout histogram 934system.membus.snoop_fanout::total 253589 # Request fanout histogram 935system.membus.reqLayer0.occupancy 685523500 # Layer occupancy (ticks) 936system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 937system.membus.respLayer1.occupancy 763755750 # Layer occupancy (ticks) 938system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 939 940---------- End Simulation Statistics ---------- 941