stats.txt revision 11507
111507SCurtis.Dunham@arm.com 211507SCurtis.Dunham@arm.com---------- Begin Simulation Statistics ---------- 311507SCurtis.Dunham@arm.comsim_seconds 0.362632 # Number of seconds simulated 411507SCurtis.Dunham@arm.comsim_ticks 362631828500 # Number of ticks simulated 511507SCurtis.Dunham@arm.comfinal_tick 362631828500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611507SCurtis.Dunham@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711507SCurtis.Dunham@arm.comhost_inst_rate 177215 # Simulator instruction rate (inst/s) 811507SCurtis.Dunham@arm.comhost_op_rate 191948 # Simulator op (including micro ops) rate (op/s) 911507SCurtis.Dunham@arm.comhost_tick_rate 126858592 # Simulator tick rate (ticks/s) 1011507SCurtis.Dunham@arm.comhost_mem_usage 271160 # Number of bytes of host memory used 1111507SCurtis.Dunham@arm.comhost_seconds 2858.55 # Real time elapsed on the host 1211507SCurtis.Dunham@arm.comsim_insts 506579366 # Number of instructions simulated 1311507SCurtis.Dunham@arm.comsim_ops 548692589 # Number of ops (including micro ops) simulated 1411507SCurtis.Dunham@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511507SCurtis.Dunham@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.inst 179456 # Number of bytes read from this memory 1711507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.data 9032064 # Number of bytes read from this memory 1811507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 9211520 # Number of bytes read from this memory 1911507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu.inst 179456 # Number of instructions bytes read from this memory 2011507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 179456 # Number of instructions bytes read from this memory 2111507SCurtis.Dunham@arm.comsystem.physmem.bytes_written::writebacks 6221440 # Number of bytes written to this memory 2211507SCurtis.Dunham@arm.comsystem.physmem.bytes_written::total 6221440 # Number of bytes written to this memory 2311507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.inst 2804 # Number of read requests responded to by this memory 2411507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.data 141126 # Number of read requests responded to by this memory 2511507SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 143930 # Number of read requests responded to by this memory 2611507SCurtis.Dunham@arm.comsystem.physmem.num_writes::writebacks 97210 # Number of write requests responded to by this memory 2711507SCurtis.Dunham@arm.comsystem.physmem.num_writes::total 97210 # Number of write requests responded to by this memory 2811507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.inst 494871 # Total read bandwidth from this memory (bytes/s) 2911507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.data 24906981 # Total read bandwidth from this memory (bytes/s) 3011507SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 25401852 # Total read bandwidth from this memory (bytes/s) 3111507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu.inst 494871 # Instruction read bandwidth from this memory (bytes/s) 3211507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 494871 # Instruction read bandwidth from this memory (bytes/s) 3311507SCurtis.Dunham@arm.comsystem.physmem.bw_write::writebacks 17156354 # Write bandwidth from this memory (bytes/s) 3411507SCurtis.Dunham@arm.comsystem.physmem.bw_write::total 17156354 # Write bandwidth from this memory (bytes/s) 3511507SCurtis.Dunham@arm.comsystem.physmem.bw_total::writebacks 17156354 # Total bandwidth to/from this memory (bytes/s) 3611507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.inst 494871 # Total bandwidth to/from this memory (bytes/s) 3711507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.data 24906981 # Total bandwidth to/from this memory (bytes/s) 3811507SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 42558206 # Total bandwidth to/from this memory (bytes/s) 3911507SCurtis.Dunham@arm.comsystem.physmem.readReqs 143930 # Number of read requests accepted 4011507SCurtis.Dunham@arm.comsystem.physmem.writeReqs 97210 # Number of write requests accepted 4111507SCurtis.Dunham@arm.comsystem.physmem.readBursts 143930 # Number of DRAM read bursts, including those serviced by the write queue 4211507SCurtis.Dunham@arm.comsystem.physmem.writeBursts 97210 # Number of DRAM write bursts, including those merged in the write queue 4311507SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 9204736 # Total number of bytes read from DRAM 4411507SCurtis.Dunham@arm.comsystem.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue 4511507SCurtis.Dunham@arm.comsystem.physmem.bytesWritten 6219456 # Total number of bytes written to DRAM 4611507SCurtis.Dunham@arm.comsystem.physmem.bytesReadSys 9211520 # Total read bytes from the system interface side 4711507SCurtis.Dunham@arm.comsystem.physmem.bytesWrittenSys 6221440 # Total written bytes from the system interface side 4811507SCurtis.Dunham@arm.comsystem.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue 4911507SCurtis.Dunham@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 5011507SCurtis.Dunham@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 5111507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 9406 # Per bank write bursts 5211507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::1 8921 # Per bank write bursts 5311507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::2 8949 # Per bank write bursts 5411507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::3 8657 # Per bank write bursts 5511507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::4 9384 # Per bank write bursts 5611507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::5 9355 # Per bank write bursts 5711507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::6 8962 # Per bank write bursts 5811507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::7 8101 # Per bank write bursts 5911507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::8 8596 # Per bank write bursts 6011507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::9 8628 # Per bank write bursts 6111507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::10 8740 # Per bank write bursts 6211507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::11 9454 # Per bank write bursts 6311507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::12 9340 # Per bank write bursts 6411507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::13 9510 # Per bank write bursts 6511507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::14 8709 # Per bank write bursts 6611507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::15 9112 # Per bank write bursts 6711507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::0 6249 # Per bank write bursts 6811507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::1 6105 # Per bank write bursts 6911507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::2 6032 # Per bank write bursts 7011507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::3 5882 # Per bank write bursts 7111507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::4 6237 # Per bank write bursts 7211507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::5 6240 # Per bank write bursts 7311507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::6 6051 # Per bank write bursts 7411507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::7 5508 # Per bank write bursts 7511507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::8 5781 # Per bank write bursts 7611507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::9 5861 # Per bank write bursts 7711507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::10 5978 # Per bank write bursts 7811507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::11 6494 # Per bank write bursts 7911507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::12 6355 # Per bank write bursts 8011507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::13 6320 # Per bank write bursts 8111507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::14 6000 # Per bank write bursts 8211507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::15 6086 # Per bank write bursts 8311507SCurtis.Dunham@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 8411507SCurtis.Dunham@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 8511507SCurtis.Dunham@arm.comsystem.physmem.totGap 362631802500 # Total gap between requests 8611507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 8711507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 8811507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 8911507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 9011507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 9111507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 9211507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::6 143930 # Read request sizes (log2) 9311507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 9411507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 9511507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 9611507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 9711507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 9811507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 9911507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::6 97210 # Write request sizes (log2) 10011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::0 143484 # What read queue length does an incoming req see 10111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::1 320 # What read queue length does an incoming req see 10211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see 10311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 10411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 10511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 10611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 10711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 10811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 10911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 11011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 11111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 11211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 11311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 11411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 11511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 11611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 11711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 11811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 11911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 12011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 12111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 12211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 12311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 12411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 12511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 12611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 12711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 12811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 12911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 13011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 13111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 13211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 13311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 13411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 13511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 13611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 13711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 13811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 13911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 14011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 14111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 14211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 14311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 14411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 14511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 14611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 14711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::15 2964 # What write queue length does an incoming req see 14811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::16 3137 # What write queue length does an incoming req see 14911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::17 5566 # What write queue length does an incoming req see 15011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::18 5692 # What write queue length does an incoming req see 15111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::19 5699 # What write queue length does an incoming req see 15211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::20 5705 # What write queue length does an incoming req see 15311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::21 5705 # What write queue length does an incoming req see 15411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::22 5703 # What write queue length does an incoming req see 15511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::23 5710 # What write queue length does an incoming req see 15611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::24 5731 # What write queue length does an incoming req see 15711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::25 5739 # What write queue length does an incoming req see 15811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::26 5733 # What write queue length does an incoming req see 15911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::27 5740 # What write queue length does an incoming req see 16011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::28 5717 # What write queue length does an incoming req see 16111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::29 5686 # What write queue length does an incoming req see 16211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::30 5684 # What write queue length does an incoming req see 16311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::31 5636 # What write queue length does an incoming req see 16411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::32 5622 # What write queue length does an incoming req see 16511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::33 14 # What write queue length does an incoming req see 16611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::34 6 # What write queue length does an incoming req see 16711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::35 3 # What write queue length does an incoming req see 16811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see 16911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see 17011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see 17111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 17211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 17311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 17411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 17511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 18011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 18111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 18211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 18311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 18411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 18511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 19011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 19111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 19211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 19311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 19411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 19511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19611507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::samples 65461 # Bytes accessed per row activation 19711507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::mean 235.617299 # Bytes accessed per row activation 19811507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::gmean 156.242018 # Bytes accessed per row activation 19911507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::stdev 241.589954 # Bytes accessed per row activation 20011507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::0-127 24858 37.97% 37.97% # Bytes accessed per row activation 20111507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::128-255 18413 28.13% 66.10% # Bytes accessed per row activation 20211507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::256-383 6961 10.63% 76.74% # Bytes accessed per row activation 20311507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::384-511 7914 12.09% 88.83% # Bytes accessed per row activation 20411507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::512-639 2009 3.07% 91.89% # Bytes accessed per row activation 20511507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::640-767 1136 1.74% 93.63% # Bytes accessed per row activation 20611507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::768-895 792 1.21% 94.84% # Bytes accessed per row activation 20711507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::896-1023 657 1.00% 95.84% # Bytes accessed per row activation 20811507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::1024-1151 2721 4.16% 100.00% # Bytes accessed per row activation 20911507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::total 65461 # Bytes accessed per row activation 21011507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::samples 5611 # Reads before turning the bus around for writes 21111507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::mean 25.630191 # Reads before turning the bus around for writes 21211507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::stdev 380.618779 # Reads before turning the bus around for writes 21311507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::0-1023 5609 99.96% 99.96% # Reads before turning the bus around for writes 21411507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes 21511507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes 21611507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::total 5611 # Reads before turning the bus around for writes 21711507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::samples 5611 # Writes before turning the bus around for reads 21811507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::mean 17.319373 # Writes before turning the bus around for reads 21911507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::gmean 17.223479 # Writes before turning the bus around for reads 22011507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::stdev 2.351913 # Writes before turning the bus around for reads 22111507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::16-17 2643 47.10% 47.10% # Writes before turning the bus around for reads 22211507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::18-19 2820 50.26% 97.36% # Writes before turning the bus around for reads 22311507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::20-21 52 0.93% 98.29% # Writes before turning the bus around for reads 22411507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::22-23 28 0.50% 98.79% # Writes before turning the bus around for reads 22511507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::24-25 21 0.37% 99.16% # Writes before turning the bus around for reads 22611507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::26-27 8 0.14% 99.30% # Writes before turning the bus around for reads 22711507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::28-29 6 0.11% 99.41% # Writes before turning the bus around for reads 22811507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::30-31 9 0.16% 99.57% # Writes before turning the bus around for reads 22911507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::32-33 4 0.07% 99.64% # Writes before turning the bus around for reads 23011507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::34-35 6 0.11% 99.75% # Writes before turning the bus around for reads 23111507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::36-37 5 0.09% 99.84% # Writes before turning the bus around for reads 23211507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::40-41 1 0.02% 99.86% # Writes before turning the bus around for reads 23311507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::42-43 3 0.05% 99.91% # Writes before turning the bus around for reads 23411507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::44-45 2 0.04% 99.95% # Writes before turning the bus around for reads 23511507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::70-71 1 0.02% 99.96% # Writes before turning the bus around for reads 23611507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::72-73 1 0.02% 99.98% # Writes before turning the bus around for reads 23711507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::90-91 1 0.02% 100.00% # Writes before turning the bus around for reads 23811507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::total 5611 # Writes before turning the bus around for reads 23911507SCurtis.Dunham@arm.comsystem.physmem.totQLat 1538291500 # Total ticks spent queuing 24011507SCurtis.Dunham@arm.comsystem.physmem.totMemAccLat 4234991500 # Total ticks spent from burst creation until serviced by the DRAM 24111507SCurtis.Dunham@arm.comsystem.physmem.totBusLat 719120000 # Total ticks spent in databus transfers 24211507SCurtis.Dunham@arm.comsystem.physmem.avgQLat 10695.65 # Average queueing delay per DRAM burst 24311507SCurtis.Dunham@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 24411507SCurtis.Dunham@arm.comsystem.physmem.avgMemAccLat 29445.65 # Average memory access latency per DRAM burst 24511507SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 25.38 # Average DRAM read bandwidth in MiByte/s 24611507SCurtis.Dunham@arm.comsystem.physmem.avgWrBW 17.15 # Average achieved write bandwidth in MiByte/s 24711507SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 25.40 # Average system read bandwidth in MiByte/s 24811507SCurtis.Dunham@arm.comsystem.physmem.avgWrBWSys 17.16 # Average system write bandwidth in MiByte/s 24911507SCurtis.Dunham@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 25011507SCurtis.Dunham@arm.comsystem.physmem.busUtil 0.33 # Data bus utilization in percentage 25111507SCurtis.Dunham@arm.comsystem.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads 25211507SCurtis.Dunham@arm.comsystem.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes 25311507SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing 25411507SCurtis.Dunham@arm.comsystem.physmem.avgWrQLen 19.56 # Average write queue length when enqueuing 25511507SCurtis.Dunham@arm.comsystem.physmem.readRowHits 110801 # Number of row buffer hits during reads 25611507SCurtis.Dunham@arm.comsystem.physmem.writeRowHits 64737 # Number of row buffer hits during writes 25711507SCurtis.Dunham@arm.comsystem.physmem.readRowHitRate 77.04 # Row buffer hit rate for reads 25811507SCurtis.Dunham@arm.comsystem.physmem.writeRowHitRate 66.60 # Row buffer hit rate for writes 25911507SCurtis.Dunham@arm.comsystem.physmem.avgGap 1503822.69 # Average gap between requests 26011507SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 72.83 # Row buffer hit rate, read and write combined 26111507SCurtis.Dunham@arm.comsystem.physmem_0.actEnergy 249185160 # Energy for activate commands per rank (pJ) 26211507SCurtis.Dunham@arm.comsystem.physmem_0.preEnergy 135964125 # Energy for precharge commands per rank (pJ) 26311507SCurtis.Dunham@arm.comsystem.physmem_0.readEnergy 559455000 # Energy for read commands per rank (pJ) 26411507SCurtis.Dunham@arm.comsystem.physmem_0.writeEnergy 312906240 # Energy for write commands per rank (pJ) 26511507SCurtis.Dunham@arm.comsystem.physmem_0.refreshEnergy 23685164880 # Energy for refresh commands per rank (pJ) 26611507SCurtis.Dunham@arm.comsystem.physmem_0.actBackEnergy 47417547600 # Energy for active background per rank (pJ) 26711507SCurtis.Dunham@arm.comsystem.physmem_0.preBackEnergy 175983265500 # Energy for precharge background per rank (pJ) 26811507SCurtis.Dunham@arm.comsystem.physmem_0.totalEnergy 248343488505 # Total energy per rank (pJ) 26911507SCurtis.Dunham@arm.comsystem.physmem_0.averagePower 684.841129 # Core power per rank (mW) 27011507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::IDLE 292457177000 # Time in different power states 27111507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::REF 12108980000 # Time in different power states 27211507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 27311507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT 58063198250 # Time in different power states 27411507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 27511507SCurtis.Dunham@arm.comsystem.physmem_1.actEnergy 245586600 # Energy for activate commands per rank (pJ) 27611507SCurtis.Dunham@arm.comsystem.physmem_1.preEnergy 134000625 # Energy for precharge commands per rank (pJ) 27711507SCurtis.Dunham@arm.comsystem.physmem_1.readEnergy 562138200 # Energy for read commands per rank (pJ) 27811507SCurtis.Dunham@arm.comsystem.physmem_1.writeEnergy 316684080 # Energy for write commands per rank (pJ) 27911507SCurtis.Dunham@arm.comsystem.physmem_1.refreshEnergy 23685164880 # Energy for refresh commands per rank (pJ) 28011507SCurtis.Dunham@arm.comsystem.physmem_1.actBackEnergy 46768401675 # Energy for active background per rank (pJ) 28111507SCurtis.Dunham@arm.comsystem.physmem_1.preBackEnergy 176552684250 # Energy for precharge background per rank (pJ) 28211507SCurtis.Dunham@arm.comsystem.physmem_1.totalEnergy 248264660310 # Total energy per rank (pJ) 28311507SCurtis.Dunham@arm.comsystem.physmem_1.averagePower 684.623774 # Core power per rank (mW) 28411507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::IDLE 293406599500 # Time in different power states 28511507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::REF 12108980000 # Time in different power states 28611507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 28711507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT 57113763250 # Time in different power states 28811507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 28911507SCurtis.Dunham@arm.comsystem.cpu.branchPred.lookups 131880511 # Number of BP lookups 29011507SCurtis.Dunham@arm.comsystem.cpu.branchPred.condPredicted 98032974 # Number of conditional branches predicted 29111507SCurtis.Dunham@arm.comsystem.cpu.branchPred.condIncorrect 5909980 # Number of conditional branches incorrect 29211507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBLookups 68420287 # Number of BTB lookups 29311507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHits 60518878 # Number of BTB hits 29411507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 29511507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHitPct 88.451658 # BTB Hit Percentage 29611507SCurtis.Dunham@arm.comsystem.cpu.branchPred.usedRAS 9982385 # Number of times the RAS was used to get a target. 29711507SCurtis.Dunham@arm.comsystem.cpu.branchPred.RASInCorrect 18500 # Number of incorrect RAS predictions. 29811507SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectLookups 3889648 # Number of indirect predictor lookups. 29911507SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectHits 3881527 # Number of indirect target hits. 30011507SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectMisses 8121 # Number of indirect misses. 30111507SCurtis.Dunham@arm.comsystem.cpu.branchPredindirectMispredicted 53795 # Number of mispredicted indirect branches. 30211507SCurtis.Dunham@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 30311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 30411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 30511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 30611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 30711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 30811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 30911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 31011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 31111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 31211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 31311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 31411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 31511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 31611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 31711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 31811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 31911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 32011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 32111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 32211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 32311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 32411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 32511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 32611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 32711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 32811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 32911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 33011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 33111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 33211507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 33311507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 33411507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 33511507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 33611507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 33711507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 33811507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 33911507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 34011507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 34111507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 34211507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 34311507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 34411507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 34511507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 34611507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 34711507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 34811507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 34911507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 35011507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 35111507SCurtis.Dunham@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 35211507SCurtis.Dunham@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 35311507SCurtis.Dunham@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 35411507SCurtis.Dunham@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 35511507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 35611507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 35711507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 35811507SCurtis.Dunham@arm.comsystem.cpu.dtb.hits 0 # DTB hits 35911507SCurtis.Dunham@arm.comsystem.cpu.dtb.misses 0 # DTB misses 36011507SCurtis.Dunham@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 36111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 36211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 36311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 36411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 36511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 36611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 36711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 36811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 36911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 37011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 37111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 37211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 37311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 37411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 37511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 37611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 37711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 37811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 37911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 38011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 38111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 38211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 38311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 38411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 38511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 38611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 38711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 38811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 38911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 39011507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 39111507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 39211507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 39311507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 39411507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 39511507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 39611507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 39711507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 39811507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 39911507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 40011507SCurtis.Dunham@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 40111507SCurtis.Dunham@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 40211507SCurtis.Dunham@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 40311507SCurtis.Dunham@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 40411507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 40511507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 40611507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 40711507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 40811507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 40911507SCurtis.Dunham@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 41011507SCurtis.Dunham@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 41111507SCurtis.Dunham@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 41211507SCurtis.Dunham@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 41311507SCurtis.Dunham@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 41411507SCurtis.Dunham@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 41511507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 41611507SCurtis.Dunham@arm.comsystem.cpu.itb.hits 0 # DTB hits 41711507SCurtis.Dunham@arm.comsystem.cpu.itb.misses 0 # DTB misses 41811507SCurtis.Dunham@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 41911507SCurtis.Dunham@arm.comsystem.cpu.workload.num_syscalls 548 # Number of system calls 42011507SCurtis.Dunham@arm.comsystem.cpu.numCycles 725263657 # number of cpu cycles simulated 42111507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 42211507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 42311507SCurtis.Dunham@arm.comsystem.cpu.committedInsts 506579366 # Number of instructions committed 42411507SCurtis.Dunham@arm.comsystem.cpu.committedOps 548692589 # Number of ops (including micro ops) committed 42511507SCurtis.Dunham@arm.comsystem.cpu.discardedOps 12911806 # Number of ops (including micro ops) which were discarded before commit 42611507SCurtis.Dunham@arm.comsystem.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 42711507SCurtis.Dunham@arm.comsystem.cpu.cpi 1.431688 # CPI: cycles per instruction 42811507SCurtis.Dunham@arm.comsystem.cpu.ipc 0.698476 # IPC: instructions per cycle 42911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 43011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntAlu 375609862 68.46% 68.46% # Class of committed instruction 43111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction 43211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction 43311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction 43411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction 43511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction 43611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction 43711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction 43811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction 43911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction 44011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction 44111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction 44211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction 44311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction 44411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction 44511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction 44611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction 44711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction 44811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction 44911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction 45011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction 45111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction 45211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction 45311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction 45411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction 45511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction 45611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction 45711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction 45811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction 45911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction 46011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::MemWrite 56860222 10.36% 100.00% # Class of committed instruction 46111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 46211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 46311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::total 548692589 # Class of committed instruction 46411507SCurtis.Dunham@arm.comsystem.cpu.tickCycles 688919604 # Number of cycles that the object actually ticked 46511507SCurtis.Dunham@arm.comsystem.cpu.idleCycles 36344053 # Total number of cycles that the object has spent stopped 46611507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.replacements 1141477 # number of replacements 46711507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tagsinuse 4070.722142 # Cycle average of tags in use 46811507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.total_refs 170992714 # Total number of references to valid blocks. 46911507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.sampled_refs 1145573 # Sample count of references to valid blocks. 47011507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.avg_refs 149.263918 # Average number of references to valid blocks. 47111507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.warmup_cycle 4896334500 # Cycle when the warmup percentage was hit. 47211507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 4070.722142 # Average occupied blocks per requestor 47311507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.993829 # Average percentage of cache occupancy 47411507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.993829 # Average percentage of cache occupancy 47511507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 47611507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 47711507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id 47811507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 553 # Occupied blocks per task id 47911507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::3 3497 # Occupied blocks per task id 48011507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 48111507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tag_accesses 346245015 # Number of tag accesses 48211507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.data_accesses 346245015 # Number of data accesses 48311507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 114475063 # number of ReadReq hits 48411507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::total 114475063 # number of ReadReq hits 48511507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 53537828 # number of WriteReq hits 48611507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::total 53537828 # number of WriteReq hits 48711507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 2741 # number of SoftPFReq hits 48811507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 2741 # number of SoftPFReq hits 48911507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits 49011507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 49111507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 49211507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 49311507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::cpu.data 168012891 # number of demand (read+write) hits 49411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::total 168012891 # number of demand (read+write) hits 49511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::cpu.data 168015632 # number of overall hits 49611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::total 168015632 # number of overall hits 49711507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 855770 # number of ReadReq misses 49811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::total 855770 # number of ReadReq misses 49911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 701221 # number of WriteReq misses 50011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::total 701221 # number of WriteReq misses 50111507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 16 # number of SoftPFReq misses 50211507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 16 # number of SoftPFReq misses 50311507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::cpu.data 1556991 # number of demand (read+write) misses 50411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::total 1556991 # number of demand (read+write) misses 50511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::cpu.data 1557007 # number of overall misses 50611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::total 1557007 # number of overall misses 50711507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 14058873500 # number of ReadReq miss cycles 50811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 14058873500 # number of ReadReq miss cycles 50911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 21921294000 # number of WriteReq miss cycles 51011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 21921294000 # number of WriteReq miss cycles 51111507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 35980167500 # number of demand (read+write) miss cycles 51211507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::total 35980167500 # number of demand (read+write) miss cycles 51311507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 35980167500 # number of overall miss cycles 51411507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::total 35980167500 # number of overall miss cycles 51511507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 115330833 # number of ReadReq accesses(hits+misses) 51611507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::total 115330833 # number of ReadReq accesses(hits+misses) 51711507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) 51811507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) 51911507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 2757 # number of SoftPFReq accesses(hits+misses) 52011507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 2757 # number of SoftPFReq accesses(hits+misses) 52111507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) 52211507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 52311507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 52411507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 52511507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 169569882 # number of demand (read+write) accesses 52611507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::total 169569882 # number of demand (read+write) accesses 52711507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 169572639 # number of overall (read+write) accesses 52811507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::total 169572639 # number of overall (read+write) accesses 52911507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007420 # miss rate for ReadReq accesses 53011507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.007420 # miss rate for ReadReq accesses 53111507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012928 # miss rate for WriteReq accesses 53211507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.012928 # miss rate for WriteReq accesses 53311507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005803 # miss rate for SoftPFReq accesses 53411507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.005803 # miss rate for SoftPFReq accesses 53511507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.009182 # miss rate for demand accesses 53611507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.009182 # miss rate for demand accesses 53711507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.009182 # miss rate for overall accesses 53811507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.009182 # miss rate for overall accesses 53911507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16428.331795 # average ReadReq miss latency 54011507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 16428.331795 # average ReadReq miss latency 54111507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31261.605115 # average WriteReq miss latency 54211507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 31261.605115 # average WriteReq miss latency 54311507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 23108.783224 # average overall miss latency 54411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 23108.783224 # average overall miss latency 54511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 23108.545755 # average overall miss latency 54611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 23108.545755 # average overall miss latency 54711507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 54811507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 54911507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 55011507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 55111507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 55211507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 55311507SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::writebacks 1069336 # number of writebacks 55411507SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::total 1069336 # number of writebacks 55511507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 66650 # number of ReadReq MSHR hits 55611507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 66650 # number of ReadReq MSHR hits 55711507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 344781 # number of WriteReq MSHR hits 55811507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 344781 # number of WriteReq MSHR hits 55911507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 411431 # number of demand (read+write) MSHR hits 56011507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::total 411431 # number of demand (read+write) MSHR hits 56111507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 411431 # number of overall MSHR hits 56211507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::total 411431 # number of overall MSHR hits 56311507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 789120 # number of ReadReq MSHR misses 56411507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 789120 # number of ReadReq MSHR misses 56511507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 356440 # number of WriteReq MSHR misses 56611507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 356440 # number of WriteReq MSHR misses 56711507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 13 # number of SoftPFReq MSHR misses 56811507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 13 # number of SoftPFReq MSHR misses 56911507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 1145560 # number of demand (read+write) MSHR misses 57011507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::total 1145560 # number of demand (read+write) MSHR misses 57111507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 1145573 # number of overall MSHR misses 57211507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::total 1145573 # number of overall MSHR misses 57311507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12372328000 # number of ReadReq MSHR miss cycles 57411507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 12372328000 # number of ReadReq MSHR miss cycles 57511507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11135047500 # number of WriteReq MSHR miss cycles 57611507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 11135047500 # number of WriteReq MSHR miss cycles 57711507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1042000 # number of SoftPFReq MSHR miss cycles 57811507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1042000 # number of SoftPFReq MSHR miss cycles 57911507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 23507375500 # number of demand (read+write) MSHR miss cycles 58011507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 23507375500 # number of demand (read+write) MSHR miss cycles 58111507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 23508417500 # number of overall MSHR miss cycles 58211507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 23508417500 # number of overall MSHR miss cycles 58311507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006842 # mshr miss rate for ReadReq accesses 58411507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006842 # mshr miss rate for ReadReq accesses 58511507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006572 # mshr miss rate for WriteReq accesses 58611507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006572 # mshr miss rate for WriteReq accesses 58711507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004715 # mshr miss rate for SoftPFReq accesses 58811507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004715 # mshr miss rate for SoftPFReq accesses 58911507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006756 # mshr miss rate for demand accesses 59011507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.006756 # mshr miss rate for demand accesses 59111507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006756 # mshr miss rate for overall accesses 59211507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.006756 # mshr miss rate for overall accesses 59311507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15678.639497 # average ReadReq mshr miss latency 59411507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15678.639497 # average ReadReq mshr miss latency 59511507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31239.612558 # average WriteReq mshr miss latency 59611507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31239.612558 # average WriteReq mshr miss latency 59711507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80153.846154 # average SoftPFReq mshr miss latency 59811507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80153.846154 # average SoftPFReq mshr miss latency 59911507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20520.422763 # average overall mshr miss latency 60011507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 20520.422763 # average overall mshr miss latency 60111507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20521.099485 # average overall mshr miss latency 60211507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 20521.099485 # average overall mshr miss latency 60311507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.replacements 18130 # number of replacements 60411507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tagsinuse 1186.413401 # Cycle average of tags in use 60511507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.total_refs 198770599 # Total number of references to valid blocks. 60611507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.sampled_refs 20001 # Sample count of references to valid blocks. 60711507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.avg_refs 9938.033048 # Average number of references to valid blocks. 60811507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 60911507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 1186.413401 # Average occupied blocks per requestor 61011507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.579303 # Average percentage of cache occupancy 61111507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::total 0.579303 # Average percentage of cache occupancy 61211507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 1871 # Occupied blocks per task id 61311507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 61411507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id 61511507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id 61611507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 312 # Occupied blocks per task id 61711507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 1397 # Occupied blocks per task id 61811507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.913574 # Percentage of cache occupancy per task id 61911507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tag_accesses 397601201 # Number of tag accesses 62011507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.data_accesses 397601201 # Number of data accesses 62111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 198770599 # number of ReadReq hits 62211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::total 198770599 # number of ReadReq hits 62311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::cpu.inst 198770599 # number of demand (read+write) hits 62411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::total 198770599 # number of demand (read+write) hits 62511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::cpu.inst 198770599 # number of overall hits 62611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::total 198770599 # number of overall hits 62711507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 20001 # number of ReadReq misses 62811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::total 20001 # number of ReadReq misses 62911507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::cpu.inst 20001 # number of demand (read+write) misses 63011507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::total 20001 # number of demand (read+write) misses 63111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::cpu.inst 20001 # number of overall misses 63211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::total 20001 # number of overall misses 63311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 455038500 # number of ReadReq miss cycles 63411507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 455038500 # number of ReadReq miss cycles 63511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 455038500 # number of demand (read+write) miss cycles 63611507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::total 455038500 # number of demand (read+write) miss cycles 63711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 455038500 # number of overall miss cycles 63811507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::total 455038500 # number of overall miss cycles 63911507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 198790600 # number of ReadReq accesses(hits+misses) 64011507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::total 198790600 # number of ReadReq accesses(hits+misses) 64111507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 198790600 # number of demand (read+write) accesses 64211507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::total 198790600 # number of demand (read+write) accesses 64311507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 198790600 # number of overall (read+write) accesses 64411507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::total 198790600 # number of overall (read+write) accesses 64511507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000101 # miss rate for ReadReq accesses 64611507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.000101 # miss rate for ReadReq accesses 64711507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.000101 # miss rate for demand accesses 64811507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::total 0.000101 # miss rate for demand accesses 64911507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.000101 # miss rate for overall accesses 65011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::total 0.000101 # miss rate for overall accesses 65111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22750.787461 # average ReadReq miss latency 65211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 22750.787461 # average ReadReq miss latency 65311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 22750.787461 # average overall miss latency 65411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 22750.787461 # average overall miss latency 65511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 22750.787461 # average overall miss latency 65611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 22750.787461 # average overall miss latency 65711507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 65811507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 65911507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 66011507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 66111507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 66211507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 66311507SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::writebacks 18130 # number of writebacks 66411507SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::total 18130 # number of writebacks 66511507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 20001 # number of ReadReq MSHR misses 66611507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 20001 # number of ReadReq MSHR misses 66711507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 20001 # number of demand (read+write) MSHR misses 66811507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::total 20001 # number of demand (read+write) MSHR misses 66911507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 20001 # number of overall MSHR misses 67011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::total 20001 # number of overall MSHR misses 67111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 435037500 # number of ReadReq MSHR miss cycles 67211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 435037500 # number of ReadReq MSHR miss cycles 67311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 435037500 # number of demand (read+write) MSHR miss cycles 67411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 435037500 # number of demand (read+write) MSHR miss cycles 67511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 435037500 # number of overall MSHR miss cycles 67611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 435037500 # number of overall MSHR miss cycles 67711507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for ReadReq accesses 67811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000101 # mshr miss rate for ReadReq accesses 67911507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for demand accesses 68011507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.000101 # mshr miss rate for demand accesses 68111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses 68211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses 68311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21750.787461 # average ReadReq mshr miss latency 68411507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21750.787461 # average ReadReq mshr miss latency 68511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency 68611507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency 68711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency 68811507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency 68911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.replacements 112376 # number of replacements 69011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tagsinuse 27628.930561 # Cycle average of tags in use 69111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.total_refs 1772118 # Total number of references to valid blocks. 69211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.sampled_refs 143588 # Sample count of references to valid blocks. 69311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.avg_refs 12.341686 # Average number of references to valid blocks. 69411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.warmup_cycle 163251686000 # Cycle when the warmup percentage was hit. 69511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 23500.584340 # Average occupied blocks per requestor 69611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 308.787313 # Average occupied blocks per requestor 69711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 3819.558908 # Average occupied blocks per requestor 69811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.717181 # Average percentage of cache occupancy 69911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.009423 # Average percentage of cache occupancy 70011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.116564 # Average percentage of cache occupancy 70111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.843168 # Average percentage of cache occupancy 70211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 31212 # Occupied blocks per task id 70311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 70411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 70511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 324 # Occupied blocks per task id 70611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 4939 # Occupied blocks per task id 70711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 25849 # Occupied blocks per task id 70811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.952515 # Percentage of cache occupancy per task id 70911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tag_accesses 19061751 # Number of tag accesses 71011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.data_accesses 19061751 # Number of data accesses 71111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 1069336 # number of WritebackDirty hits 71211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 1069336 # number of WritebackDirty hits 71311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 17893 # number of WritebackClean hits 71411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 17893 # number of WritebackClean hits 71511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 255742 # number of ReadExReq hits 71611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 255742 # number of ReadExReq hits 71711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17196 # number of ReadCleanReq hits 71811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 17196 # number of ReadCleanReq hits 71911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 748691 # number of ReadSharedReq hits 72011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 748691 # number of ReadSharedReq hits 72111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 17196 # number of demand (read+write) hits 72211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1004433 # number of demand (read+write) hits 72311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::total 1021629 # number of demand (read+write) hits 72411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 17196 # number of overall hits 72511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1004433 # number of overall hits 72611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::total 1021629 # number of overall hits 72711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 100949 # number of ReadExReq misses 72811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 100949 # number of ReadExReq misses 72911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2805 # number of ReadCleanReq misses 73011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 2805 # number of ReadCleanReq misses 73111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 40191 # number of ReadSharedReq misses 73211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 40191 # number of ReadSharedReq misses 73311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 2805 # number of demand (read+write) misses 73411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 141140 # number of demand (read+write) misses 73511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::total 143945 # number of demand (read+write) misses 73611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 2805 # number of overall misses 73711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 141140 # number of overall misses 73811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::total 143945 # number of overall misses 73911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7917540500 # number of ReadExReq miss cycles 74011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 7917540500 # number of ReadExReq miss cycles 74111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 223778500 # number of ReadCleanReq miss cycles 74211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 223778500 # number of ReadCleanReq miss cycles 74311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3305085000 # number of ReadSharedReq miss cycles 74411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 3305085000 # number of ReadSharedReq miss cycles 74511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 223778500 # number of demand (read+write) miss cycles 74611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 11222625500 # number of demand (read+write) miss cycles 74711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::total 11446404000 # number of demand (read+write) miss cycles 74811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 223778500 # number of overall miss cycles 74911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 11222625500 # number of overall miss cycles 75011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::total 11446404000 # number of overall miss cycles 75111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 1069336 # number of WritebackDirty accesses(hits+misses) 75211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 1069336 # number of WritebackDirty accesses(hits+misses) 75311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 17893 # number of WritebackClean accesses(hits+misses) 75411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 17893 # number of WritebackClean accesses(hits+misses) 75511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 356691 # number of ReadExReq accesses(hits+misses) 75611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 356691 # number of ReadExReq accesses(hits+misses) 75711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 20001 # number of ReadCleanReq accesses(hits+misses) 75811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 20001 # number of ReadCleanReq accesses(hits+misses) 75911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 788882 # number of ReadSharedReq accesses(hits+misses) 76011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 788882 # number of ReadSharedReq accesses(hits+misses) 76111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 20001 # number of demand (read+write) accesses 76211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1145573 # number of demand (read+write) accesses 76311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::total 1165574 # number of demand (read+write) accesses 76411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 20001 # number of overall (read+write) accesses 76511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1145573 # number of overall (read+write) accesses 76611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::total 1165574 # number of overall (read+write) accesses 76711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283015 # miss rate for ReadExReq accesses 76811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.283015 # miss rate for ReadExReq accesses 76911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.140243 # miss rate for ReadCleanReq accesses 77011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.140243 # miss rate for ReadCleanReq accesses 77111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050947 # miss rate for ReadSharedReq accesses 77211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050947 # miss rate for ReadSharedReq accesses 77311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.140243 # miss rate for demand accesses 77411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.123205 # miss rate for demand accesses 77511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.123497 # miss rate for demand accesses 77611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.140243 # miss rate for overall accesses 77711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.123205 # miss rate for overall accesses 77811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.123497 # miss rate for overall accesses 77911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78431.093919 # average ReadExReq miss latency 78011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 78431.093919 # average ReadExReq miss latency 78111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79778.431373 # average ReadCleanReq miss latency 78211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79778.431373 # average ReadCleanReq miss latency 78311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82234.455475 # average ReadSharedReq miss latency 78411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82234.455475 # average ReadSharedReq miss latency 78511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79778.431373 # average overall miss latency 78611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 79514.138444 # average overall miss latency 78711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 79519.288617 # average overall miss latency 78811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79778.431373 # average overall miss latency 78911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 79514.138444 # average overall miss latency 79011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 79519.288617 # average overall miss latency 79111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 79211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 79311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 79411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 79511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 79611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 79711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.writebacks::writebacks 97210 # number of writebacks 79811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.writebacks::total 97210 # number of writebacks 79911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 80011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 80111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits 80211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits 80311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 80411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits 80511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits 80611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 80711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits 80811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits 80911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100949 # number of ReadExReq MSHR misses 81011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 100949 # number of ReadExReq MSHR misses 81111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2804 # number of ReadCleanReq MSHR misses 81211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 2804 # number of ReadCleanReq MSHR misses 81311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40177 # number of ReadSharedReq MSHR misses 81411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 40177 # number of ReadSharedReq MSHR misses 81511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 2804 # number of demand (read+write) MSHR misses 81611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 141126 # number of demand (read+write) MSHR misses 81711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 143930 # number of demand (read+write) MSHR misses 81811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 2804 # number of overall MSHR misses 81911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 141126 # number of overall MSHR misses 82011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 143930 # number of overall MSHR misses 82111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6908050500 # number of ReadExReq MSHR miss cycles 82211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6908050500 # number of ReadExReq MSHR miss cycles 82311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 195670500 # number of ReadCleanReq MSHR miss cycles 82411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 195670500 # number of ReadCleanReq MSHR miss cycles 82511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2902356000 # number of ReadSharedReq MSHR miss cycles 82611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2902356000 # number of ReadSharedReq MSHR miss cycles 82711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195670500 # number of demand (read+write) MSHR miss cycles 82811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9810406500 # number of demand (read+write) MSHR miss cycles 82911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 10006077000 # number of demand (read+write) MSHR miss cycles 83011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195670500 # number of overall MSHR miss cycles 83111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9810406500 # number of overall MSHR miss cycles 83211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 10006077000 # number of overall MSHR miss cycles 83311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283015 # mshr miss rate for ReadExReq accesses 83411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283015 # mshr miss rate for ReadExReq accesses 83511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.140193 # mshr miss rate for ReadCleanReq accesses 83611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.140193 # mshr miss rate for ReadCleanReq accesses 83711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050929 # mshr miss rate for ReadSharedReq accesses 83811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050929 # mshr miss rate for ReadSharedReq accesses 83911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.140193 # mshr miss rate for demand accesses 84011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123192 # mshr miss rate for demand accesses 84111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.123484 # mshr miss rate for demand accesses 84211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140193 # mshr miss rate for overall accesses 84311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123192 # mshr miss rate for overall accesses 84411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.123484 # mshr miss rate for overall accesses 84511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68431.093919 # average ReadExReq mshr miss latency 84611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68431.093919 # average ReadExReq mshr miss latency 84711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69782.631954 # average ReadCleanReq mshr miss latency 84811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69782.631954 # average ReadCleanReq mshr miss latency 84911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72239.241357 # average ReadSharedReq mshr miss latency 85011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72239.241357 # average ReadSharedReq mshr miss latency 85111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69782.631954 # average overall mshr miss latency 85211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69515.231070 # average overall mshr miss latency 85311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 69520.440492 # average overall mshr miss latency 85411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69782.631954 # average overall mshr miss latency 85511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69515.231070 # average overall mshr miss latency 85611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 69520.440492 # average overall mshr miss latency 85711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 2325181 # Total number of requests made to the snoop filter. 85811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 1159677 # Number of requests hitting in the snoop filter with a single holder of the requested data. 85911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 4997 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 86011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 2608 # Total number of snoops made to the snoop filter. 86111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 2605 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 86211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 86311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 808883 # Transaction distribution 86411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 1166546 # Transaction distribution 86511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 18130 # Transaction distribution 86611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 87307 # Transaction distribution 86711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 356691 # Transaction distribution 86811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 356691 # Transaction distribution 86911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 20001 # Transaction distribution 87011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 788882 # Transaction distribution 87111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58132 # Packet count per connected master and slave (bytes) 87211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432623 # Packet count per connected master and slave (bytes) 87311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count::total 3490755 # Packet count per connected master and slave (bytes) 87411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2440384 # Cumulative packet size per connected master and slave (bytes) 87511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141754176 # Cumulative packet size per connected master and slave (bytes) 87611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size::total 144194560 # Cumulative packet size per connected master and slave (bytes) 87711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoops 112376 # Total snoops (count) 87811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 1277950 # Request fanout histogram 87911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.006008 # Request fanout histogram 88011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.077309 # Request fanout histogram 88111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 88211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 1270275 99.40% 99.40% # Request fanout histogram 88311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 7672 0.60% 100.00% # Request fanout histogram 88411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram 88511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 88611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 88711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 88811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 1277950 # Request fanout histogram 88911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 2250056500 # Layer occupancy (ticks) 89011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 89111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 30027947 # Layer occupancy (ticks) 89211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 89311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 1718367983 # Layer occupancy (ticks) 89411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 89511507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 42981 # Transaction distribution 89611507SCurtis.Dunham@arm.comsystem.membus.trans_dist::WritebackDirty 97210 # Transaction distribution 89711507SCurtis.Dunham@arm.comsystem.membus.trans_dist::CleanEvict 12558 # Transaction distribution 89811507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 100949 # Transaction distribution 89911507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 100949 # Transaction distribution 90011507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 42981 # Transaction distribution 90111507SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397628 # Packet count per connected master and slave (bytes) 90211507SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 397628 # Packet count per connected master and slave (bytes) 90311507SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15432960 # Cumulative packet size per connected master and slave (bytes) 90411507SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 15432960 # Cumulative packet size per connected master and slave (bytes) 90511507SCurtis.Dunham@arm.comsystem.membus.snoops 0 # Total snoops (count) 90611507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 253698 # Request fanout histogram 90711507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 90811507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 90911507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 91011507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 253698 100.00% 100.00% # Request fanout histogram 91111507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 91211507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 91311507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 91411507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 91511507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 253698 # Request fanout histogram 91611507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.occupancy 685564500 # Layer occupancy (ticks) 91711507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 91811507SCurtis.Dunham@arm.comsystem.membus.respLayer1.occupancy 763995250 # Layer occupancy (ticks) 91911507SCurtis.Dunham@arm.comsystem.membus.respLayer1.utilization 0.2 # Layer utilization (%) 92011507SCurtis.Dunham@arm.com 92111507SCurtis.Dunham@arm.com---------- End Simulation Statistics ---------- 922