stats.txt revision 11507
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.362632 # Number of seconds simulated 4sim_ticks 362631828500 # Number of ticks simulated 5final_tick 362631828500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 177215 # Simulator instruction rate (inst/s) 8host_op_rate 191948 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 126858592 # Simulator tick rate (ticks/s) 10host_mem_usage 271160 # Number of bytes of host memory used 11host_seconds 2858.55 # Real time elapsed on the host 12sim_insts 506579366 # Number of instructions simulated 13sim_ops 548692589 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 179456 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9032064 # Number of bytes read from this memory 18system.physmem.bytes_read::total 9211520 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 179456 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 179456 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 6221440 # Number of bytes written to this memory 22system.physmem.bytes_written::total 6221440 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 2804 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 141126 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 143930 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 97210 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 97210 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 494871 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 24906981 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 25401852 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 494871 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 494871 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 17156354 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 17156354 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 17156354 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 494871 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 24906981 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 42558206 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 143930 # Number of read requests accepted 40system.physmem.writeReqs 97210 # Number of write requests accepted 41system.physmem.readBursts 143930 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 97210 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 9204736 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue 45system.physmem.bytesWritten 6219456 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 9211520 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 6221440 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 9406 # Per bank write bursts 52system.physmem.perBankRdBursts::1 8921 # Per bank write bursts 53system.physmem.perBankRdBursts::2 8949 # Per bank write bursts 54system.physmem.perBankRdBursts::3 8657 # Per bank write bursts 55system.physmem.perBankRdBursts::4 9384 # Per bank write bursts 56system.physmem.perBankRdBursts::5 9355 # Per bank write bursts 57system.physmem.perBankRdBursts::6 8962 # Per bank write bursts 58system.physmem.perBankRdBursts::7 8101 # Per bank write bursts 59system.physmem.perBankRdBursts::8 8596 # Per bank write bursts 60system.physmem.perBankRdBursts::9 8628 # Per bank write bursts 61system.physmem.perBankRdBursts::10 8740 # Per bank write bursts 62system.physmem.perBankRdBursts::11 9454 # Per bank write bursts 63system.physmem.perBankRdBursts::12 9340 # Per bank write bursts 64system.physmem.perBankRdBursts::13 9510 # Per bank write bursts 65system.physmem.perBankRdBursts::14 8709 # Per bank write bursts 66system.physmem.perBankRdBursts::15 9112 # Per bank write bursts 67system.physmem.perBankWrBursts::0 6249 # Per bank write bursts 68system.physmem.perBankWrBursts::1 6105 # Per bank write bursts 69system.physmem.perBankWrBursts::2 6032 # Per bank write bursts 70system.physmem.perBankWrBursts::3 5882 # Per bank write bursts 71system.physmem.perBankWrBursts::4 6237 # Per bank write bursts 72system.physmem.perBankWrBursts::5 6240 # Per bank write bursts 73system.physmem.perBankWrBursts::6 6051 # Per bank write bursts 74system.physmem.perBankWrBursts::7 5508 # Per bank write bursts 75system.physmem.perBankWrBursts::8 5781 # Per bank write bursts 76system.physmem.perBankWrBursts::9 5861 # Per bank write bursts 77system.physmem.perBankWrBursts::10 5978 # Per bank write bursts 78system.physmem.perBankWrBursts::11 6494 # Per bank write bursts 79system.physmem.perBankWrBursts::12 6355 # Per bank write bursts 80system.physmem.perBankWrBursts::13 6320 # Per bank write bursts 81system.physmem.perBankWrBursts::14 6000 # Per bank write bursts 82system.physmem.perBankWrBursts::15 6086 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 362631802500 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 143930 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 97210 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 143484 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 320 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 2964 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 3137 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 5566 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 5692 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 5699 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 5705 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 5705 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 5703 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 5710 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 5731 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 5739 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 5733 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 5740 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 5717 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 5686 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 5684 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 5636 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 5622 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 14 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 6 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 3 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 65461 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 235.617299 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 156.242018 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 241.589954 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 24858 37.97% 37.97% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 18413 28.13% 66.10% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 6961 10.63% 76.74% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 7914 12.09% 88.83% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 2009 3.07% 91.89% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 1136 1.74% 93.63% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 792 1.21% 94.84% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 657 1.00% 95.84% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 2721 4.16% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 65461 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 5611 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 25.630191 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 380.618779 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 5609 99.96% 99.96% # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.98% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::total 5611 # Reads before turning the bus around for writes 217system.physmem.wrPerTurnAround::samples 5611 # Writes before turning the bus around for reads 218system.physmem.wrPerTurnAround::mean 17.319373 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::gmean 17.223479 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::stdev 2.351913 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::16-17 2643 47.10% 47.10% # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::18-19 2820 50.26% 97.36% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::20-21 52 0.93% 98.29% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::22-23 28 0.50% 98.79% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::24-25 21 0.37% 99.16% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::26-27 8 0.14% 99.30% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::28-29 6 0.11% 99.41% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::30-31 9 0.16% 99.57% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::32-33 4 0.07% 99.64% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::34-35 6 0.11% 99.75% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::36-37 5 0.09% 99.84% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::40-41 1 0.02% 99.86% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::42-43 3 0.05% 99.91% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::44-45 2 0.04% 99.95% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::70-71 1 0.02% 99.96% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::72-73 1 0.02% 99.98% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::90-91 1 0.02% 100.00% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::total 5611 # Writes before turning the bus around for reads 239system.physmem.totQLat 1538291500 # Total ticks spent queuing 240system.physmem.totMemAccLat 4234991500 # Total ticks spent from burst creation until serviced by the DRAM 241system.physmem.totBusLat 719120000 # Total ticks spent in databus transfers 242system.physmem.avgQLat 10695.65 # Average queueing delay per DRAM burst 243system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 244system.physmem.avgMemAccLat 29445.65 # Average memory access latency per DRAM burst 245system.physmem.avgRdBW 25.38 # Average DRAM read bandwidth in MiByte/s 246system.physmem.avgWrBW 17.15 # Average achieved write bandwidth in MiByte/s 247system.physmem.avgRdBWSys 25.40 # Average system read bandwidth in MiByte/s 248system.physmem.avgWrBWSys 17.16 # Average system write bandwidth in MiByte/s 249system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 250system.physmem.busUtil 0.33 # Data bus utilization in percentage 251system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads 252system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes 253system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing 254system.physmem.avgWrQLen 19.56 # Average write queue length when enqueuing 255system.physmem.readRowHits 110801 # Number of row buffer hits during reads 256system.physmem.writeRowHits 64737 # Number of row buffer hits during writes 257system.physmem.readRowHitRate 77.04 # Row buffer hit rate for reads 258system.physmem.writeRowHitRate 66.60 # Row buffer hit rate for writes 259system.physmem.avgGap 1503822.69 # Average gap between requests 260system.physmem.pageHitRate 72.83 # Row buffer hit rate, read and write combined 261system.physmem_0.actEnergy 249185160 # Energy for activate commands per rank (pJ) 262system.physmem_0.preEnergy 135964125 # Energy for precharge commands per rank (pJ) 263system.physmem_0.readEnergy 559455000 # Energy for read commands per rank (pJ) 264system.physmem_0.writeEnergy 312906240 # Energy for write commands per rank (pJ) 265system.physmem_0.refreshEnergy 23685164880 # Energy for refresh commands per rank (pJ) 266system.physmem_0.actBackEnergy 47417547600 # Energy for active background per rank (pJ) 267system.physmem_0.preBackEnergy 175983265500 # Energy for precharge background per rank (pJ) 268system.physmem_0.totalEnergy 248343488505 # Total energy per rank (pJ) 269system.physmem_0.averagePower 684.841129 # Core power per rank (mW) 270system.physmem_0.memoryStateTime::IDLE 292457177000 # Time in different power states 271system.physmem_0.memoryStateTime::REF 12108980000 # Time in different power states 272system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 273system.physmem_0.memoryStateTime::ACT 58063198250 # Time in different power states 274system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 275system.physmem_1.actEnergy 245586600 # Energy for activate commands per rank (pJ) 276system.physmem_1.preEnergy 134000625 # Energy for precharge commands per rank (pJ) 277system.physmem_1.readEnergy 562138200 # Energy for read commands per rank (pJ) 278system.physmem_1.writeEnergy 316684080 # Energy for write commands per rank (pJ) 279system.physmem_1.refreshEnergy 23685164880 # Energy for refresh commands per rank (pJ) 280system.physmem_1.actBackEnergy 46768401675 # Energy for active background per rank (pJ) 281system.physmem_1.preBackEnergy 176552684250 # Energy for precharge background per rank (pJ) 282system.physmem_1.totalEnergy 248264660310 # Total energy per rank (pJ) 283system.physmem_1.averagePower 684.623774 # Core power per rank (mW) 284system.physmem_1.memoryStateTime::IDLE 293406599500 # Time in different power states 285system.physmem_1.memoryStateTime::REF 12108980000 # Time in different power states 286system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 287system.physmem_1.memoryStateTime::ACT 57113763250 # Time in different power states 288system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 289system.cpu.branchPred.lookups 131880511 # Number of BP lookups 290system.cpu.branchPred.condPredicted 98032974 # Number of conditional branches predicted 291system.cpu.branchPred.condIncorrect 5909980 # Number of conditional branches incorrect 292system.cpu.branchPred.BTBLookups 68420287 # Number of BTB lookups 293system.cpu.branchPred.BTBHits 60518878 # Number of BTB hits 294system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 295system.cpu.branchPred.BTBHitPct 88.451658 # BTB Hit Percentage 296system.cpu.branchPred.usedRAS 9982385 # Number of times the RAS was used to get a target. 297system.cpu.branchPred.RASInCorrect 18500 # Number of incorrect RAS predictions. 298system.cpu.branchPred.indirectLookups 3889648 # Number of indirect predictor lookups. 299system.cpu.branchPred.indirectHits 3881527 # Number of indirect target hits. 300system.cpu.branchPred.indirectMisses 8121 # Number of indirect misses. 301system.cpu.branchPredindirectMispredicted 53795 # Number of mispredicted indirect branches. 302system.cpu_clk_domain.clock 500 # Clock period in ticks 303system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 310system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 311system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 312system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 313system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 314system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 315system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 316system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 317system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 318system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 319system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 320system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 321system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 322system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 323system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 324system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 325system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 326system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 327system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 328system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 329system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 330system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 331system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 332system.cpu.dtb.walker.walks 0 # Table walker walks requested 333system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 334system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 335system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 336system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 337system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 338system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 339system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 340system.cpu.dtb.inst_hits 0 # ITB inst hits 341system.cpu.dtb.inst_misses 0 # ITB inst misses 342system.cpu.dtb.read_hits 0 # DTB read hits 343system.cpu.dtb.read_misses 0 # DTB read misses 344system.cpu.dtb.write_hits 0 # DTB write hits 345system.cpu.dtb.write_misses 0 # DTB write misses 346system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 347system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 348system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 349system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 350system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 351system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 352system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 353system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 354system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 355system.cpu.dtb.read_accesses 0 # DTB read accesses 356system.cpu.dtb.write_accesses 0 # DTB write accesses 357system.cpu.dtb.inst_accesses 0 # ITB inst accesses 358system.cpu.dtb.hits 0 # DTB hits 359system.cpu.dtb.misses 0 # DTB misses 360system.cpu.dtb.accesses 0 # DTB accesses 361system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 362system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 363system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 364system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 365system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 366system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 367system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 368system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 369system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 370system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 371system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 372system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 373system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 374system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 375system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 376system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 377system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 378system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 379system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 380system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 381system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 382system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 383system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 384system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 385system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 386system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 387system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 388system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 389system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 390system.cpu.itb.walker.walks 0 # Table walker walks requested 391system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 392system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 393system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 394system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 395system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 396system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 397system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 398system.cpu.itb.inst_hits 0 # ITB inst hits 399system.cpu.itb.inst_misses 0 # ITB inst misses 400system.cpu.itb.read_hits 0 # DTB read hits 401system.cpu.itb.read_misses 0 # DTB read misses 402system.cpu.itb.write_hits 0 # DTB write hits 403system.cpu.itb.write_misses 0 # DTB write misses 404system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 405system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 406system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 407system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 408system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 409system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 410system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 411system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 412system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 413system.cpu.itb.read_accesses 0 # DTB read accesses 414system.cpu.itb.write_accesses 0 # DTB write accesses 415system.cpu.itb.inst_accesses 0 # ITB inst accesses 416system.cpu.itb.hits 0 # DTB hits 417system.cpu.itb.misses 0 # DTB misses 418system.cpu.itb.accesses 0 # DTB accesses 419system.cpu.workload.num_syscalls 548 # Number of system calls 420system.cpu.numCycles 725263657 # number of cpu cycles simulated 421system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 422system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 423system.cpu.committedInsts 506579366 # Number of instructions committed 424system.cpu.committedOps 548692589 # Number of ops (including micro ops) committed 425system.cpu.discardedOps 12911806 # Number of ops (including micro ops) which were discarded before commit 426system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 427system.cpu.cpi 1.431688 # CPI: cycles per instruction 428system.cpu.ipc 0.698476 # IPC: instructions per cycle 429system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 430system.cpu.op_class_0::IntAlu 375609862 68.46% 68.46% # Class of committed instruction 431system.cpu.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction 432system.cpu.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction 433system.cpu.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction 434system.cpu.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction 435system.cpu.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction 436system.cpu.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction 437system.cpu.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction 438system.cpu.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction 439system.cpu.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction 440system.cpu.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction 441system.cpu.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction 442system.cpu.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction 443system.cpu.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction 444system.cpu.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction 445system.cpu.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction 446system.cpu.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction 447system.cpu.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction 448system.cpu.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction 449system.cpu.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction 450system.cpu.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction 451system.cpu.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction 452system.cpu.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction 453system.cpu.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction 454system.cpu.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction 455system.cpu.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction 456system.cpu.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction 457system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction 458system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction 459system.cpu.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction 460system.cpu.op_class_0::MemWrite 56860222 10.36% 100.00% # Class of committed instruction 461system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 462system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 463system.cpu.op_class_0::total 548692589 # Class of committed instruction 464system.cpu.tickCycles 688919604 # Number of cycles that the object actually ticked 465system.cpu.idleCycles 36344053 # Total number of cycles that the object has spent stopped 466system.cpu.dcache.tags.replacements 1141477 # number of replacements 467system.cpu.dcache.tags.tagsinuse 4070.722142 # Cycle average of tags in use 468system.cpu.dcache.tags.total_refs 170992714 # Total number of references to valid blocks. 469system.cpu.dcache.tags.sampled_refs 1145573 # Sample count of references to valid blocks. 470system.cpu.dcache.tags.avg_refs 149.263918 # Average number of references to valid blocks. 471system.cpu.dcache.tags.warmup_cycle 4896334500 # Cycle when the warmup percentage was hit. 472system.cpu.dcache.tags.occ_blocks::cpu.data 4070.722142 # Average occupied blocks per requestor 473system.cpu.dcache.tags.occ_percent::cpu.data 0.993829 # Average percentage of cache occupancy 474system.cpu.dcache.tags.occ_percent::total 0.993829 # Average percentage of cache occupancy 475system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 476system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id 477system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id 478system.cpu.dcache.tags.age_task_id_blocks_1024::2 553 # Occupied blocks per task id 479system.cpu.dcache.tags.age_task_id_blocks_1024::3 3497 # Occupied blocks per task id 480system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 481system.cpu.dcache.tags.tag_accesses 346245015 # Number of tag accesses 482system.cpu.dcache.tags.data_accesses 346245015 # Number of data accesses 483system.cpu.dcache.ReadReq_hits::cpu.data 114475063 # number of ReadReq hits 484system.cpu.dcache.ReadReq_hits::total 114475063 # number of ReadReq hits 485system.cpu.dcache.WriteReq_hits::cpu.data 53537828 # number of WriteReq hits 486system.cpu.dcache.WriteReq_hits::total 53537828 # number of WriteReq hits 487system.cpu.dcache.SoftPFReq_hits::cpu.data 2741 # number of SoftPFReq hits 488system.cpu.dcache.SoftPFReq_hits::total 2741 # number of SoftPFReq hits 489system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits 490system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits 491system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits 492system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits 493system.cpu.dcache.demand_hits::cpu.data 168012891 # number of demand (read+write) hits 494system.cpu.dcache.demand_hits::total 168012891 # number of demand (read+write) hits 495system.cpu.dcache.overall_hits::cpu.data 168015632 # number of overall hits 496system.cpu.dcache.overall_hits::total 168015632 # number of overall hits 497system.cpu.dcache.ReadReq_misses::cpu.data 855770 # number of ReadReq misses 498system.cpu.dcache.ReadReq_misses::total 855770 # number of ReadReq misses 499system.cpu.dcache.WriteReq_misses::cpu.data 701221 # number of WriteReq misses 500system.cpu.dcache.WriteReq_misses::total 701221 # number of WriteReq misses 501system.cpu.dcache.SoftPFReq_misses::cpu.data 16 # number of SoftPFReq misses 502system.cpu.dcache.SoftPFReq_misses::total 16 # number of SoftPFReq misses 503system.cpu.dcache.demand_misses::cpu.data 1556991 # number of demand (read+write) misses 504system.cpu.dcache.demand_misses::total 1556991 # number of demand (read+write) misses 505system.cpu.dcache.overall_misses::cpu.data 1557007 # number of overall misses 506system.cpu.dcache.overall_misses::total 1557007 # number of overall misses 507system.cpu.dcache.ReadReq_miss_latency::cpu.data 14058873500 # number of ReadReq miss cycles 508system.cpu.dcache.ReadReq_miss_latency::total 14058873500 # number of ReadReq miss cycles 509system.cpu.dcache.WriteReq_miss_latency::cpu.data 21921294000 # number of WriteReq miss cycles 510system.cpu.dcache.WriteReq_miss_latency::total 21921294000 # number of WriteReq miss cycles 511system.cpu.dcache.demand_miss_latency::cpu.data 35980167500 # number of demand (read+write) miss cycles 512system.cpu.dcache.demand_miss_latency::total 35980167500 # number of demand (read+write) miss cycles 513system.cpu.dcache.overall_miss_latency::cpu.data 35980167500 # number of overall miss cycles 514system.cpu.dcache.overall_miss_latency::total 35980167500 # number of overall miss cycles 515system.cpu.dcache.ReadReq_accesses::cpu.data 115330833 # number of ReadReq accesses(hits+misses) 516system.cpu.dcache.ReadReq_accesses::total 115330833 # number of ReadReq accesses(hits+misses) 517system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) 518system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) 519system.cpu.dcache.SoftPFReq_accesses::cpu.data 2757 # number of SoftPFReq accesses(hits+misses) 520system.cpu.dcache.SoftPFReq_accesses::total 2757 # number of SoftPFReq accesses(hits+misses) 521system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) 522system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) 523system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) 524system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) 525system.cpu.dcache.demand_accesses::cpu.data 169569882 # number of demand (read+write) accesses 526system.cpu.dcache.demand_accesses::total 169569882 # number of demand (read+write) accesses 527system.cpu.dcache.overall_accesses::cpu.data 169572639 # number of overall (read+write) accesses 528system.cpu.dcache.overall_accesses::total 169572639 # number of overall (read+write) accesses 529system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007420 # miss rate for ReadReq accesses 530system.cpu.dcache.ReadReq_miss_rate::total 0.007420 # miss rate for ReadReq accesses 531system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012928 # miss rate for WriteReq accesses 532system.cpu.dcache.WriteReq_miss_rate::total 0.012928 # miss rate for WriteReq accesses 533system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005803 # miss rate for SoftPFReq accesses 534system.cpu.dcache.SoftPFReq_miss_rate::total 0.005803 # miss rate for SoftPFReq accesses 535system.cpu.dcache.demand_miss_rate::cpu.data 0.009182 # miss rate for demand accesses 536system.cpu.dcache.demand_miss_rate::total 0.009182 # miss rate for demand accesses 537system.cpu.dcache.overall_miss_rate::cpu.data 0.009182 # miss rate for overall accesses 538system.cpu.dcache.overall_miss_rate::total 0.009182 # miss rate for overall accesses 539system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16428.331795 # average ReadReq miss latency 540system.cpu.dcache.ReadReq_avg_miss_latency::total 16428.331795 # average ReadReq miss latency 541system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31261.605115 # average WriteReq miss latency 542system.cpu.dcache.WriteReq_avg_miss_latency::total 31261.605115 # average WriteReq miss latency 543system.cpu.dcache.demand_avg_miss_latency::cpu.data 23108.783224 # average overall miss latency 544system.cpu.dcache.demand_avg_miss_latency::total 23108.783224 # average overall miss latency 545system.cpu.dcache.overall_avg_miss_latency::cpu.data 23108.545755 # average overall miss latency 546system.cpu.dcache.overall_avg_miss_latency::total 23108.545755 # average overall miss latency 547system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 548system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 549system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 550system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 551system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 552system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 553system.cpu.dcache.writebacks::writebacks 1069336 # number of writebacks 554system.cpu.dcache.writebacks::total 1069336 # number of writebacks 555system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66650 # number of ReadReq MSHR hits 556system.cpu.dcache.ReadReq_mshr_hits::total 66650 # number of ReadReq MSHR hits 557system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344781 # number of WriteReq MSHR hits 558system.cpu.dcache.WriteReq_mshr_hits::total 344781 # number of WriteReq MSHR hits 559system.cpu.dcache.demand_mshr_hits::cpu.data 411431 # number of demand (read+write) MSHR hits 560system.cpu.dcache.demand_mshr_hits::total 411431 # number of demand (read+write) MSHR hits 561system.cpu.dcache.overall_mshr_hits::cpu.data 411431 # number of overall MSHR hits 562system.cpu.dcache.overall_mshr_hits::total 411431 # number of overall MSHR hits 563system.cpu.dcache.ReadReq_mshr_misses::cpu.data 789120 # number of ReadReq MSHR misses 564system.cpu.dcache.ReadReq_mshr_misses::total 789120 # number of ReadReq MSHR misses 565system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356440 # number of WriteReq MSHR misses 566system.cpu.dcache.WriteReq_mshr_misses::total 356440 # number of WriteReq MSHR misses 567system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 13 # number of SoftPFReq MSHR misses 568system.cpu.dcache.SoftPFReq_mshr_misses::total 13 # number of SoftPFReq MSHR misses 569system.cpu.dcache.demand_mshr_misses::cpu.data 1145560 # number of demand (read+write) MSHR misses 570system.cpu.dcache.demand_mshr_misses::total 1145560 # number of demand (read+write) MSHR misses 571system.cpu.dcache.overall_mshr_misses::cpu.data 1145573 # number of overall MSHR misses 572system.cpu.dcache.overall_mshr_misses::total 1145573 # number of overall MSHR misses 573system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12372328000 # number of ReadReq MSHR miss cycles 574system.cpu.dcache.ReadReq_mshr_miss_latency::total 12372328000 # number of ReadReq MSHR miss cycles 575system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11135047500 # number of WriteReq MSHR miss cycles 576system.cpu.dcache.WriteReq_mshr_miss_latency::total 11135047500 # number of WriteReq MSHR miss cycles 577system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1042000 # number of SoftPFReq MSHR miss cycles 578system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1042000 # number of SoftPFReq MSHR miss cycles 579system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23507375500 # number of demand (read+write) MSHR miss cycles 580system.cpu.dcache.demand_mshr_miss_latency::total 23507375500 # number of demand (read+write) MSHR miss cycles 581system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23508417500 # number of overall MSHR miss cycles 582system.cpu.dcache.overall_mshr_miss_latency::total 23508417500 # number of overall MSHR miss cycles 583system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006842 # mshr miss rate for ReadReq accesses 584system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006842 # mshr miss rate for ReadReq accesses 585system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006572 # mshr miss rate for WriteReq accesses 586system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006572 # mshr miss rate for WriteReq accesses 587system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004715 # mshr miss rate for SoftPFReq accesses 588system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004715 # mshr miss rate for SoftPFReq accesses 589system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006756 # mshr miss rate for demand accesses 590system.cpu.dcache.demand_mshr_miss_rate::total 0.006756 # mshr miss rate for demand accesses 591system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006756 # mshr miss rate for overall accesses 592system.cpu.dcache.overall_mshr_miss_rate::total 0.006756 # mshr miss rate for overall accesses 593system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15678.639497 # average ReadReq mshr miss latency 594system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15678.639497 # average ReadReq mshr miss latency 595system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31239.612558 # average WriteReq mshr miss latency 596system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31239.612558 # average WriteReq mshr miss latency 597system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 80153.846154 # average SoftPFReq mshr miss latency 598system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 80153.846154 # average SoftPFReq mshr miss latency 599system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20520.422763 # average overall mshr miss latency 600system.cpu.dcache.demand_avg_mshr_miss_latency::total 20520.422763 # average overall mshr miss latency 601system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20521.099485 # average overall mshr miss latency 602system.cpu.dcache.overall_avg_mshr_miss_latency::total 20521.099485 # average overall mshr miss latency 603system.cpu.icache.tags.replacements 18130 # number of replacements 604system.cpu.icache.tags.tagsinuse 1186.413401 # Cycle average of tags in use 605system.cpu.icache.tags.total_refs 198770599 # Total number of references to valid blocks. 606system.cpu.icache.tags.sampled_refs 20001 # Sample count of references to valid blocks. 607system.cpu.icache.tags.avg_refs 9938.033048 # Average number of references to valid blocks. 608system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 609system.cpu.icache.tags.occ_blocks::cpu.inst 1186.413401 # Average occupied blocks per requestor 610system.cpu.icache.tags.occ_percent::cpu.inst 0.579303 # Average percentage of cache occupancy 611system.cpu.icache.tags.occ_percent::total 0.579303 # Average percentage of cache occupancy 612system.cpu.icache.tags.occ_task_id_blocks::1024 1871 # Occupied blocks per task id 613system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 614system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id 615system.cpu.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id 616system.cpu.icache.tags.age_task_id_blocks_1024::3 312 # Occupied blocks per task id 617system.cpu.icache.tags.age_task_id_blocks_1024::4 1397 # Occupied blocks per task id 618system.cpu.icache.tags.occ_task_id_percent::1024 0.913574 # Percentage of cache occupancy per task id 619system.cpu.icache.tags.tag_accesses 397601201 # Number of tag accesses 620system.cpu.icache.tags.data_accesses 397601201 # Number of data accesses 621system.cpu.icache.ReadReq_hits::cpu.inst 198770599 # number of ReadReq hits 622system.cpu.icache.ReadReq_hits::total 198770599 # number of ReadReq hits 623system.cpu.icache.demand_hits::cpu.inst 198770599 # number of demand (read+write) hits 624system.cpu.icache.demand_hits::total 198770599 # number of demand (read+write) hits 625system.cpu.icache.overall_hits::cpu.inst 198770599 # number of overall hits 626system.cpu.icache.overall_hits::total 198770599 # number of overall hits 627system.cpu.icache.ReadReq_misses::cpu.inst 20001 # number of ReadReq misses 628system.cpu.icache.ReadReq_misses::total 20001 # number of ReadReq misses 629system.cpu.icache.demand_misses::cpu.inst 20001 # number of demand (read+write) misses 630system.cpu.icache.demand_misses::total 20001 # number of demand (read+write) misses 631system.cpu.icache.overall_misses::cpu.inst 20001 # number of overall misses 632system.cpu.icache.overall_misses::total 20001 # number of overall misses 633system.cpu.icache.ReadReq_miss_latency::cpu.inst 455038500 # number of ReadReq miss cycles 634system.cpu.icache.ReadReq_miss_latency::total 455038500 # number of ReadReq miss cycles 635system.cpu.icache.demand_miss_latency::cpu.inst 455038500 # number of demand (read+write) miss cycles 636system.cpu.icache.demand_miss_latency::total 455038500 # number of demand (read+write) miss cycles 637system.cpu.icache.overall_miss_latency::cpu.inst 455038500 # number of overall miss cycles 638system.cpu.icache.overall_miss_latency::total 455038500 # number of overall miss cycles 639system.cpu.icache.ReadReq_accesses::cpu.inst 198790600 # number of ReadReq accesses(hits+misses) 640system.cpu.icache.ReadReq_accesses::total 198790600 # number of ReadReq accesses(hits+misses) 641system.cpu.icache.demand_accesses::cpu.inst 198790600 # number of demand (read+write) accesses 642system.cpu.icache.demand_accesses::total 198790600 # number of demand (read+write) accesses 643system.cpu.icache.overall_accesses::cpu.inst 198790600 # number of overall (read+write) accesses 644system.cpu.icache.overall_accesses::total 198790600 # number of overall (read+write) accesses 645system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000101 # miss rate for ReadReq accesses 646system.cpu.icache.ReadReq_miss_rate::total 0.000101 # miss rate for ReadReq accesses 647system.cpu.icache.demand_miss_rate::cpu.inst 0.000101 # miss rate for demand accesses 648system.cpu.icache.demand_miss_rate::total 0.000101 # miss rate for demand accesses 649system.cpu.icache.overall_miss_rate::cpu.inst 0.000101 # miss rate for overall accesses 650system.cpu.icache.overall_miss_rate::total 0.000101 # miss rate for overall accesses 651system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22750.787461 # average ReadReq miss latency 652system.cpu.icache.ReadReq_avg_miss_latency::total 22750.787461 # average ReadReq miss latency 653system.cpu.icache.demand_avg_miss_latency::cpu.inst 22750.787461 # average overall miss latency 654system.cpu.icache.demand_avg_miss_latency::total 22750.787461 # average overall miss latency 655system.cpu.icache.overall_avg_miss_latency::cpu.inst 22750.787461 # average overall miss latency 656system.cpu.icache.overall_avg_miss_latency::total 22750.787461 # average overall miss latency 657system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 658system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 659system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 660system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 661system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 662system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 663system.cpu.icache.writebacks::writebacks 18130 # number of writebacks 664system.cpu.icache.writebacks::total 18130 # number of writebacks 665system.cpu.icache.ReadReq_mshr_misses::cpu.inst 20001 # number of ReadReq MSHR misses 666system.cpu.icache.ReadReq_mshr_misses::total 20001 # number of ReadReq MSHR misses 667system.cpu.icache.demand_mshr_misses::cpu.inst 20001 # number of demand (read+write) MSHR misses 668system.cpu.icache.demand_mshr_misses::total 20001 # number of demand (read+write) MSHR misses 669system.cpu.icache.overall_mshr_misses::cpu.inst 20001 # number of overall MSHR misses 670system.cpu.icache.overall_mshr_misses::total 20001 # number of overall MSHR misses 671system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 435037500 # number of ReadReq MSHR miss cycles 672system.cpu.icache.ReadReq_mshr_miss_latency::total 435037500 # number of ReadReq MSHR miss cycles 673system.cpu.icache.demand_mshr_miss_latency::cpu.inst 435037500 # number of demand (read+write) MSHR miss cycles 674system.cpu.icache.demand_mshr_miss_latency::total 435037500 # number of demand (read+write) MSHR miss cycles 675system.cpu.icache.overall_mshr_miss_latency::cpu.inst 435037500 # number of overall MSHR miss cycles 676system.cpu.icache.overall_mshr_miss_latency::total 435037500 # number of overall MSHR miss cycles 677system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for ReadReq accesses 678system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000101 # mshr miss rate for ReadReq accesses 679system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for demand accesses 680system.cpu.icache.demand_mshr_miss_rate::total 0.000101 # mshr miss rate for demand accesses 681system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses 682system.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses 683system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21750.787461 # average ReadReq mshr miss latency 684system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21750.787461 # average ReadReq mshr miss latency 685system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency 686system.cpu.icache.demand_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency 687system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21750.787461 # average overall mshr miss latency 688system.cpu.icache.overall_avg_mshr_miss_latency::total 21750.787461 # average overall mshr miss latency 689system.cpu.l2cache.tags.replacements 112376 # number of replacements 690system.cpu.l2cache.tags.tagsinuse 27628.930561 # Cycle average of tags in use 691system.cpu.l2cache.tags.total_refs 1772118 # Total number of references to valid blocks. 692system.cpu.l2cache.tags.sampled_refs 143588 # Sample count of references to valid blocks. 693system.cpu.l2cache.tags.avg_refs 12.341686 # Average number of references to valid blocks. 694system.cpu.l2cache.tags.warmup_cycle 163251686000 # Cycle when the warmup percentage was hit. 695system.cpu.l2cache.tags.occ_blocks::writebacks 23500.584340 # Average occupied blocks per requestor 696system.cpu.l2cache.tags.occ_blocks::cpu.inst 308.787313 # Average occupied blocks per requestor 697system.cpu.l2cache.tags.occ_blocks::cpu.data 3819.558908 # Average occupied blocks per requestor 698system.cpu.l2cache.tags.occ_percent::writebacks 0.717181 # Average percentage of cache occupancy 699system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009423 # Average percentage of cache occupancy 700system.cpu.l2cache.tags.occ_percent::cpu.data 0.116564 # Average percentage of cache occupancy 701system.cpu.l2cache.tags.occ_percent::total 0.843168 # Average percentage of cache occupancy 702system.cpu.l2cache.tags.occ_task_id_blocks::1024 31212 # Occupied blocks per task id 703system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id 704system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 705system.cpu.l2cache.tags.age_task_id_blocks_1024::2 324 # Occupied blocks per task id 706system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4939 # Occupied blocks per task id 707system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25849 # Occupied blocks per task id 708system.cpu.l2cache.tags.occ_task_id_percent::1024 0.952515 # Percentage of cache occupancy per task id 709system.cpu.l2cache.tags.tag_accesses 19061751 # Number of tag accesses 710system.cpu.l2cache.tags.data_accesses 19061751 # Number of data accesses 711system.cpu.l2cache.WritebackDirty_hits::writebacks 1069336 # number of WritebackDirty hits 712system.cpu.l2cache.WritebackDirty_hits::total 1069336 # number of WritebackDirty hits 713system.cpu.l2cache.WritebackClean_hits::writebacks 17893 # number of WritebackClean hits 714system.cpu.l2cache.WritebackClean_hits::total 17893 # number of WritebackClean hits 715system.cpu.l2cache.ReadExReq_hits::cpu.data 255742 # number of ReadExReq hits 716system.cpu.l2cache.ReadExReq_hits::total 255742 # number of ReadExReq hits 717system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17196 # number of ReadCleanReq hits 718system.cpu.l2cache.ReadCleanReq_hits::total 17196 # number of ReadCleanReq hits 719system.cpu.l2cache.ReadSharedReq_hits::cpu.data 748691 # number of ReadSharedReq hits 720system.cpu.l2cache.ReadSharedReq_hits::total 748691 # number of ReadSharedReq hits 721system.cpu.l2cache.demand_hits::cpu.inst 17196 # number of demand (read+write) hits 722system.cpu.l2cache.demand_hits::cpu.data 1004433 # number of demand (read+write) hits 723system.cpu.l2cache.demand_hits::total 1021629 # number of demand (read+write) hits 724system.cpu.l2cache.overall_hits::cpu.inst 17196 # number of overall hits 725system.cpu.l2cache.overall_hits::cpu.data 1004433 # number of overall hits 726system.cpu.l2cache.overall_hits::total 1021629 # number of overall hits 727system.cpu.l2cache.ReadExReq_misses::cpu.data 100949 # number of ReadExReq misses 728system.cpu.l2cache.ReadExReq_misses::total 100949 # number of ReadExReq misses 729system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2805 # number of ReadCleanReq misses 730system.cpu.l2cache.ReadCleanReq_misses::total 2805 # number of ReadCleanReq misses 731system.cpu.l2cache.ReadSharedReq_misses::cpu.data 40191 # number of ReadSharedReq misses 732system.cpu.l2cache.ReadSharedReq_misses::total 40191 # number of ReadSharedReq misses 733system.cpu.l2cache.demand_misses::cpu.inst 2805 # number of demand (read+write) misses 734system.cpu.l2cache.demand_misses::cpu.data 141140 # number of demand (read+write) misses 735system.cpu.l2cache.demand_misses::total 143945 # number of demand (read+write) misses 736system.cpu.l2cache.overall_misses::cpu.inst 2805 # number of overall misses 737system.cpu.l2cache.overall_misses::cpu.data 141140 # number of overall misses 738system.cpu.l2cache.overall_misses::total 143945 # number of overall misses 739system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7917540500 # number of ReadExReq miss cycles 740system.cpu.l2cache.ReadExReq_miss_latency::total 7917540500 # number of ReadExReq miss cycles 741system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 223778500 # number of ReadCleanReq miss cycles 742system.cpu.l2cache.ReadCleanReq_miss_latency::total 223778500 # number of ReadCleanReq miss cycles 743system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3305085000 # number of ReadSharedReq miss cycles 744system.cpu.l2cache.ReadSharedReq_miss_latency::total 3305085000 # number of ReadSharedReq miss cycles 745system.cpu.l2cache.demand_miss_latency::cpu.inst 223778500 # number of demand (read+write) miss cycles 746system.cpu.l2cache.demand_miss_latency::cpu.data 11222625500 # number of demand (read+write) miss cycles 747system.cpu.l2cache.demand_miss_latency::total 11446404000 # number of demand (read+write) miss cycles 748system.cpu.l2cache.overall_miss_latency::cpu.inst 223778500 # number of overall miss cycles 749system.cpu.l2cache.overall_miss_latency::cpu.data 11222625500 # number of overall miss cycles 750system.cpu.l2cache.overall_miss_latency::total 11446404000 # number of overall miss cycles 751system.cpu.l2cache.WritebackDirty_accesses::writebacks 1069336 # number of WritebackDirty accesses(hits+misses) 752system.cpu.l2cache.WritebackDirty_accesses::total 1069336 # number of WritebackDirty accesses(hits+misses) 753system.cpu.l2cache.WritebackClean_accesses::writebacks 17893 # number of WritebackClean accesses(hits+misses) 754system.cpu.l2cache.WritebackClean_accesses::total 17893 # number of WritebackClean accesses(hits+misses) 755system.cpu.l2cache.ReadExReq_accesses::cpu.data 356691 # number of ReadExReq accesses(hits+misses) 756system.cpu.l2cache.ReadExReq_accesses::total 356691 # number of ReadExReq accesses(hits+misses) 757system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 20001 # number of ReadCleanReq accesses(hits+misses) 758system.cpu.l2cache.ReadCleanReq_accesses::total 20001 # number of ReadCleanReq accesses(hits+misses) 759system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 788882 # number of ReadSharedReq accesses(hits+misses) 760system.cpu.l2cache.ReadSharedReq_accesses::total 788882 # number of ReadSharedReq accesses(hits+misses) 761system.cpu.l2cache.demand_accesses::cpu.inst 20001 # number of demand (read+write) accesses 762system.cpu.l2cache.demand_accesses::cpu.data 1145573 # number of demand (read+write) accesses 763system.cpu.l2cache.demand_accesses::total 1165574 # number of demand (read+write) accesses 764system.cpu.l2cache.overall_accesses::cpu.inst 20001 # number of overall (read+write) accesses 765system.cpu.l2cache.overall_accesses::cpu.data 1145573 # number of overall (read+write) accesses 766system.cpu.l2cache.overall_accesses::total 1165574 # number of overall (read+write) accesses 767system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283015 # miss rate for ReadExReq accesses 768system.cpu.l2cache.ReadExReq_miss_rate::total 0.283015 # miss rate for ReadExReq accesses 769system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.140243 # miss rate for ReadCleanReq accesses 770system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.140243 # miss rate for ReadCleanReq accesses 771system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.050947 # miss rate for ReadSharedReq accesses 772system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.050947 # miss rate for ReadSharedReq accesses 773system.cpu.l2cache.demand_miss_rate::cpu.inst 0.140243 # miss rate for demand accesses 774system.cpu.l2cache.demand_miss_rate::cpu.data 0.123205 # miss rate for demand accesses 775system.cpu.l2cache.demand_miss_rate::total 0.123497 # miss rate for demand accesses 776system.cpu.l2cache.overall_miss_rate::cpu.inst 0.140243 # miss rate for overall accesses 777system.cpu.l2cache.overall_miss_rate::cpu.data 0.123205 # miss rate for overall accesses 778system.cpu.l2cache.overall_miss_rate::total 0.123497 # miss rate for overall accesses 779system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78431.093919 # average ReadExReq miss latency 780system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78431.093919 # average ReadExReq miss latency 781system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79778.431373 # average ReadCleanReq miss latency 782system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79778.431373 # average ReadCleanReq miss latency 783system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82234.455475 # average ReadSharedReq miss latency 784system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82234.455475 # average ReadSharedReq miss latency 785system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79778.431373 # average overall miss latency 786system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79514.138444 # average overall miss latency 787system.cpu.l2cache.demand_avg_miss_latency::total 79519.288617 # average overall miss latency 788system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79778.431373 # average overall miss latency 789system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79514.138444 # average overall miss latency 790system.cpu.l2cache.overall_avg_miss_latency::total 79519.288617 # average overall miss latency 791system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 792system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 793system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 794system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 795system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 796system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 797system.cpu.l2cache.writebacks::writebacks 97210 # number of writebacks 798system.cpu.l2cache.writebacks::total 97210 # number of writebacks 799system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 800system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 801system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 14 # number of ReadSharedReq MSHR hits 802system.cpu.l2cache.ReadSharedReq_mshr_hits::total 14 # number of ReadSharedReq MSHR hits 803system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 804system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits 805system.cpu.l2cache.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits 806system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 807system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits 808system.cpu.l2cache.overall_mshr_hits::total 15 # number of overall MSHR hits 809system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100949 # number of ReadExReq MSHR misses 810system.cpu.l2cache.ReadExReq_mshr_misses::total 100949 # number of ReadExReq MSHR misses 811system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2804 # number of ReadCleanReq MSHR misses 812system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2804 # number of ReadCleanReq MSHR misses 813system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40177 # number of ReadSharedReq MSHR misses 814system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40177 # number of ReadSharedReq MSHR misses 815system.cpu.l2cache.demand_mshr_misses::cpu.inst 2804 # number of demand (read+write) MSHR misses 816system.cpu.l2cache.demand_mshr_misses::cpu.data 141126 # number of demand (read+write) MSHR misses 817system.cpu.l2cache.demand_mshr_misses::total 143930 # number of demand (read+write) MSHR misses 818system.cpu.l2cache.overall_mshr_misses::cpu.inst 2804 # number of overall MSHR misses 819system.cpu.l2cache.overall_mshr_misses::cpu.data 141126 # number of overall MSHR misses 820system.cpu.l2cache.overall_mshr_misses::total 143930 # number of overall MSHR misses 821system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6908050500 # number of ReadExReq MSHR miss cycles 822system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6908050500 # number of ReadExReq MSHR miss cycles 823system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 195670500 # number of ReadCleanReq MSHR miss cycles 824system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 195670500 # number of ReadCleanReq MSHR miss cycles 825system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2902356000 # number of ReadSharedReq MSHR miss cycles 826system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2902356000 # number of ReadSharedReq MSHR miss cycles 827system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195670500 # number of demand (read+write) MSHR miss cycles 828system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9810406500 # number of demand (read+write) MSHR miss cycles 829system.cpu.l2cache.demand_mshr_miss_latency::total 10006077000 # number of demand (read+write) MSHR miss cycles 830system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195670500 # number of overall MSHR miss cycles 831system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9810406500 # number of overall MSHR miss cycles 832system.cpu.l2cache.overall_mshr_miss_latency::total 10006077000 # number of overall MSHR miss cycles 833system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283015 # mshr miss rate for ReadExReq accesses 834system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283015 # mshr miss rate for ReadExReq accesses 835system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.140193 # mshr miss rate for ReadCleanReq accesses 836system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.140193 # mshr miss rate for ReadCleanReq accesses 837system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.050929 # mshr miss rate for ReadSharedReq accesses 838system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.050929 # mshr miss rate for ReadSharedReq accesses 839system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.140193 # mshr miss rate for demand accesses 840system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123192 # mshr miss rate for demand accesses 841system.cpu.l2cache.demand_mshr_miss_rate::total 0.123484 # mshr miss rate for demand accesses 842system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140193 # mshr miss rate for overall accesses 843system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123192 # mshr miss rate for overall accesses 844system.cpu.l2cache.overall_mshr_miss_rate::total 0.123484 # mshr miss rate for overall accesses 845system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68431.093919 # average ReadExReq mshr miss latency 846system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68431.093919 # average ReadExReq mshr miss latency 847system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69782.631954 # average ReadCleanReq mshr miss latency 848system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69782.631954 # average ReadCleanReq mshr miss latency 849system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72239.241357 # average ReadSharedReq mshr miss latency 850system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72239.241357 # average ReadSharedReq mshr miss latency 851system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69782.631954 # average overall mshr miss latency 852system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69515.231070 # average overall mshr miss latency 853system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69520.440492 # average overall mshr miss latency 854system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69782.631954 # average overall mshr miss latency 855system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69515.231070 # average overall mshr miss latency 856system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69520.440492 # average overall mshr miss latency 857system.cpu.toL2Bus.snoop_filter.tot_requests 2325181 # Total number of requests made to the snoop filter. 858system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159677 # Number of requests hitting in the snoop filter with a single holder of the requested data. 859system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4997 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 860system.cpu.toL2Bus.snoop_filter.tot_snoops 2608 # Total number of snoops made to the snoop filter. 861system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2605 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 862system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 863system.cpu.toL2Bus.trans_dist::ReadResp 808883 # Transaction distribution 864system.cpu.toL2Bus.trans_dist::WritebackDirty 1166546 # Transaction distribution 865system.cpu.toL2Bus.trans_dist::WritebackClean 18130 # Transaction distribution 866system.cpu.toL2Bus.trans_dist::CleanEvict 87307 # Transaction distribution 867system.cpu.toL2Bus.trans_dist::ReadExReq 356691 # Transaction distribution 868system.cpu.toL2Bus.trans_dist::ReadExResp 356691 # Transaction distribution 869system.cpu.toL2Bus.trans_dist::ReadCleanReq 20001 # Transaction distribution 870system.cpu.toL2Bus.trans_dist::ReadSharedReq 788882 # Transaction distribution 871system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58132 # Packet count per connected master and slave (bytes) 872system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432623 # Packet count per connected master and slave (bytes) 873system.cpu.toL2Bus.pkt_count::total 3490755 # Packet count per connected master and slave (bytes) 874system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2440384 # Cumulative packet size per connected master and slave (bytes) 875system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141754176 # Cumulative packet size per connected master and slave (bytes) 876system.cpu.toL2Bus.pkt_size::total 144194560 # Cumulative packet size per connected master and slave (bytes) 877system.cpu.toL2Bus.snoops 112376 # Total snoops (count) 878system.cpu.toL2Bus.snoop_fanout::samples 1277950 # Request fanout histogram 879system.cpu.toL2Bus.snoop_fanout::mean 0.006008 # Request fanout histogram 880system.cpu.toL2Bus.snoop_fanout::stdev 0.077309 # Request fanout histogram 881system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 882system.cpu.toL2Bus.snoop_fanout::0 1270275 99.40% 99.40% # Request fanout histogram 883system.cpu.toL2Bus.snoop_fanout::1 7672 0.60% 100.00% # Request fanout histogram 884system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram 885system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 886system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 887system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 888system.cpu.toL2Bus.snoop_fanout::total 1277950 # Request fanout histogram 889system.cpu.toL2Bus.reqLayer0.occupancy 2250056500 # Layer occupancy (ticks) 890system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) 891system.cpu.toL2Bus.respLayer0.occupancy 30027947 # Layer occupancy (ticks) 892system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 893system.cpu.toL2Bus.respLayer1.occupancy 1718367983 # Layer occupancy (ticks) 894system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) 895system.membus.trans_dist::ReadResp 42981 # Transaction distribution 896system.membus.trans_dist::WritebackDirty 97210 # Transaction distribution 897system.membus.trans_dist::CleanEvict 12558 # Transaction distribution 898system.membus.trans_dist::ReadExReq 100949 # Transaction distribution 899system.membus.trans_dist::ReadExResp 100949 # Transaction distribution 900system.membus.trans_dist::ReadSharedReq 42981 # Transaction distribution 901system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 397628 # Packet count per connected master and slave (bytes) 902system.membus.pkt_count::total 397628 # Packet count per connected master and slave (bytes) 903system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15432960 # Cumulative packet size per connected master and slave (bytes) 904system.membus.pkt_size::total 15432960 # Cumulative packet size per connected master and slave (bytes) 905system.membus.snoops 0 # Total snoops (count) 906system.membus.snoop_fanout::samples 253698 # Request fanout histogram 907system.membus.snoop_fanout::mean 0 # Request fanout histogram 908system.membus.snoop_fanout::stdev 0 # Request fanout histogram 909system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 910system.membus.snoop_fanout::0 253698 100.00% 100.00% # Request fanout histogram 911system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 912system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 913system.membus.snoop_fanout::min_value 0 # Request fanout histogram 914system.membus.snoop_fanout::max_value 0 # Request fanout histogram 915system.membus.snoop_fanout::total 253698 # Request fanout histogram 916system.membus.reqLayer0.occupancy 685564500 # Layer occupancy (ticks) 917system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 918system.membus.respLayer1.occupancy 763995250 # Layer occupancy (ticks) 919system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 920 921---------- End Simulation Statistics ---------- 922