stats.txt revision 11507
111507SCurtis.Dunham@arm.com 211507SCurtis.Dunham@arm.com---------- Begin Simulation Statistics ---------- 311507SCurtis.Dunham@arm.comsim_seconds 0.065987 # Number of seconds simulated 411507SCurtis.Dunham@arm.comsim_ticks 65986743500 # Number of ticks simulated 511507SCurtis.Dunham@arm.comfinal_tick 65986743500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611507SCurtis.Dunham@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711507SCurtis.Dunham@arm.comhost_inst_rate 84238 # Simulator instruction rate (inst/s) 811507SCurtis.Dunham@arm.comhost_op_rate 148330 # Simulator op (including micro ops) rate (op/s) 911507SCurtis.Dunham@arm.comhost_tick_rate 35183666 # Simulator tick rate (ticks/s) 1011507SCurtis.Dunham@arm.comhost_mem_usage 410392 # Number of bytes of host memory used 1111507SCurtis.Dunham@arm.comhost_seconds 1875.49 # Real time elapsed on the host 1211507SCurtis.Dunham@arm.comsim_insts 157988547 # Number of instructions simulated 1311507SCurtis.Dunham@arm.comsim_ops 278192464 # Number of ops (including micro ops) simulated 1411507SCurtis.Dunham@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511507SCurtis.Dunham@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.inst 69440 # Number of bytes read from this memory 1711507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.data 1890368 # Number of bytes read from this memory 1811507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 1959808 # Number of bytes read from this memory 1911507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu.inst 69440 # Number of instructions bytes read from this memory 2011507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 69440 # Number of instructions bytes read from this memory 2111507SCurtis.Dunham@arm.comsystem.physmem.bytes_written::writebacks 17920 # Number of bytes written to this memory 2211507SCurtis.Dunham@arm.comsystem.physmem.bytes_written::total 17920 # Number of bytes written to this memory 2311507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.inst 1085 # Number of read requests responded to by this memory 2411507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.data 29537 # Number of read requests responded to by this memory 2511507SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 30622 # Number of read requests responded to by this memory 2611507SCurtis.Dunham@arm.comsystem.physmem.num_writes::writebacks 280 # Number of write requests responded to by this memory 2711507SCurtis.Dunham@arm.comsystem.physmem.num_writes::total 280 # Number of write requests responded to by this memory 2811507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.inst 1052333 # Total read bandwidth from this memory (bytes/s) 2911507SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.data 28647693 # Total read bandwidth from this memory (bytes/s) 3011507SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 29700026 # Total read bandwidth from this memory (bytes/s) 3111507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu.inst 1052333 # Instruction read bandwidth from this memory (bytes/s) 3211507SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 1052333 # Instruction read bandwidth from this memory (bytes/s) 3311507SCurtis.Dunham@arm.comsystem.physmem.bw_write::writebacks 271570 # Write bandwidth from this memory (bytes/s) 3411507SCurtis.Dunham@arm.comsystem.physmem.bw_write::total 271570 # Write bandwidth from this memory (bytes/s) 3511507SCurtis.Dunham@arm.comsystem.physmem.bw_total::writebacks 271570 # Total bandwidth to/from this memory (bytes/s) 3611507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.inst 1052333 # Total bandwidth to/from this memory (bytes/s) 3711507SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.data 28647693 # Total bandwidth to/from this memory (bytes/s) 3811507SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 29971596 # Total bandwidth to/from this memory (bytes/s) 3911507SCurtis.Dunham@arm.comsystem.physmem.readReqs 30622 # Number of read requests accepted 4011507SCurtis.Dunham@arm.comsystem.physmem.writeReqs 280 # Number of write requests accepted 4111507SCurtis.Dunham@arm.comsystem.physmem.readBursts 30622 # Number of DRAM read bursts, including those serviced by the write queue 4211507SCurtis.Dunham@arm.comsystem.physmem.writeBursts 280 # Number of DRAM write bursts, including those merged in the write queue 4311507SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 1952768 # Total number of bytes read from DRAM 4411507SCurtis.Dunham@arm.comsystem.physmem.bytesReadWrQ 7040 # Total number of bytes read from write queue 4511507SCurtis.Dunham@arm.comsystem.physmem.bytesWritten 16064 # Total number of bytes written to DRAM 4611507SCurtis.Dunham@arm.comsystem.physmem.bytesReadSys 1959808 # Total read bytes from the system interface side 4711507SCurtis.Dunham@arm.comsystem.physmem.bytesWrittenSys 17920 # Total written bytes from the system interface side 4811507SCurtis.Dunham@arm.comsystem.physmem.servicedByWrQ 110 # Number of DRAM read bursts serviced by the write queue 4911507SCurtis.Dunham@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 5011507SCurtis.Dunham@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 5111507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 1932 # Per bank write bursts 5211507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::1 2084 # Per bank write bursts 5311507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::2 2041 # Per bank write bursts 5411507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::3 1935 # Per bank write bursts 5511507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::4 2086 # Per bank write bursts 5611507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::5 1909 # Per bank write bursts 5711507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::6 1974 # Per bank write bursts 5811507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::7 1865 # Per bank write bursts 5911507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::8 1948 # Per bank write bursts 6011507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::9 1940 # Per bank write bursts 6111507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::10 1806 # Per bank write bursts 6211507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::11 1794 # Per bank write bursts 6311507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::12 1792 # Per bank write bursts 6411507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::13 1799 # Per bank write bursts 6511507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::14 1828 # Per bank write bursts 6611507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::15 1779 # Per bank write bursts 6711507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::0 10 # Per bank write bursts 6811507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::1 107 # Per bank write bursts 6911507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::2 30 # Per bank write bursts 7011507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::3 12 # Per bank write bursts 7111507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::4 60 # Per bank write bursts 7211507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::5 8 # Per bank write bursts 7311507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::6 16 # Per bank write bursts 7411507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 7511507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 7611507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::9 5 # Per bank write bursts 7711507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::10 3 # Per bank write bursts 7811507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 7911507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 8011507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 8111507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 8211507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 8311507SCurtis.Dunham@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 8411507SCurtis.Dunham@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 8511507SCurtis.Dunham@arm.comsystem.physmem.totGap 65986546500 # Total gap between requests 8611507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 8711507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 8811507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 8911507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 9011507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 9111507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 9211507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::6 30622 # Read request sizes (log2) 9311507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 9411507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 9511507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 9611507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 9711507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 9811507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 9911507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::6 280 # Write request sizes (log2) 10011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::0 29999 # What read queue length does an incoming req see 10111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::1 397 # What read queue length does an incoming req see 10211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 88 # What read queue length does an incoming req see 10311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see 10411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 10511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 10611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 10711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 10811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 10911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 11011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 11111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 11211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 11311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 11411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 11511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 11611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 11711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 11811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 11911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 12011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 12111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 12211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 12311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 12411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 12511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 12611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 12711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 12811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 12911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 13011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 13111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 13211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 13311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 13411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 13511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 13611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 13711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 13811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 13911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 14011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 14111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 14211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 14311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 14411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 14511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 14611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 14711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::15 14 # What write queue length does an incoming req see 14811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::16 14 # What write queue length does an incoming req see 14911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::17 14 # What write queue length does an incoming req see 15011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::18 14 # What write queue length does an incoming req see 15111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::19 15 # What write queue length does an incoming req see 15211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::20 15 # What write queue length does an incoming req see 15311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::21 16 # What write queue length does an incoming req see 15411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::22 15 # What write queue length does an incoming req see 15511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::23 15 # What write queue length does an incoming req see 15611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::24 15 # What write queue length does an incoming req see 15711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::25 15 # What write queue length does an incoming req see 15811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::26 15 # What write queue length does an incoming req see 15911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::27 15 # What write queue length does an incoming req see 16011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see 16111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::29 15 # What write queue length does an incoming req see 16211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see 16311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::31 14 # What write queue length does an incoming req see 16411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::32 14 # What write queue length does an incoming req see 16511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 16611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 17011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 17111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 17211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 17311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 17411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 17511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 18011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 18111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 18211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 18311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 18411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 18511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 19011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 19111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 19211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 19311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 19411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 19511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19611507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::samples 2831 # Bytes accessed per row activation 19711507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::mean 694.731190 # Bytes accessed per row activation 19811507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::gmean 483.360902 # Bytes accessed per row activation 19911507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::stdev 396.952113 # Bytes accessed per row activation 20011507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::0-127 443 15.65% 15.65% # Bytes accessed per row activation 20111507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::128-255 258 9.11% 24.76% # Bytes accessed per row activation 20211507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::256-383 108 3.81% 28.58% # Bytes accessed per row activation 20311507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::384-511 115 4.06% 32.64% # Bytes accessed per row activation 20411507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::512-639 113 3.99% 36.63% # Bytes accessed per row activation 20511507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::640-767 115 4.06% 40.69% # Bytes accessed per row activation 20611507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::768-895 137 4.84% 45.53% # Bytes accessed per row activation 20711507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::896-1023 80 2.83% 48.36% # Bytes accessed per row activation 20811507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::1024-1151 1462 51.64% 100.00% # Bytes accessed per row activation 20911507SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::total 2831 # Bytes accessed per row activation 21011507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::samples 14 # Reads before turning the bus around for writes 21111507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::mean 2175.285714 # Reads before turning the bus around for writes 21211507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::gmean 28.380874 # Reads before turning the bus around for writes 21311507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::stdev 8064.070078 # Reads before turning the bus around for writes 21411507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::0-1023 13 92.86% 92.86% # Reads before turning the bus around for writes 21511507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::29696-30719 1 7.14% 100.00% # Reads before turning the bus around for writes 21611507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::total 14 # Reads before turning the bus around for writes 21711507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::samples 14 # Writes before turning the bus around for reads 21811507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::mean 17.928571 # Writes before turning the bus around for reads 21911507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::gmean 17.918266 # Writes before turning the bus around for reads 22011507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::stdev 0.615728 # Writes before turning the bus around for reads 22111507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::16 1 7.14% 7.14% # Writes before turning the bus around for reads 22211507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::18 12 85.71% 92.86% # Writes before turning the bus around for reads 22311507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::19 1 7.14% 100.00% # Writes before turning the bus around for reads 22411507SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::total 14 # Writes before turning the bus around for reads 22511507SCurtis.Dunham@arm.comsystem.physmem.totQLat 136557750 # Total ticks spent queuing 22611507SCurtis.Dunham@arm.comsystem.physmem.totMemAccLat 708657750 # Total ticks spent from burst creation until serviced by the DRAM 22711507SCurtis.Dunham@arm.comsystem.physmem.totBusLat 152560000 # Total ticks spent in databus transfers 22811507SCurtis.Dunham@arm.comsystem.physmem.avgQLat 4475.54 # Average queueing delay per DRAM burst 22911507SCurtis.Dunham@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 23011507SCurtis.Dunham@arm.comsystem.physmem.avgMemAccLat 23225.54 # Average memory access latency per DRAM burst 23111507SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 29.59 # Average DRAM read bandwidth in MiByte/s 23211507SCurtis.Dunham@arm.comsystem.physmem.avgWrBW 0.24 # Average achieved write bandwidth in MiByte/s 23311507SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 29.70 # Average system read bandwidth in MiByte/s 23411507SCurtis.Dunham@arm.comsystem.physmem.avgWrBWSys 0.27 # Average system write bandwidth in MiByte/s 23511507SCurtis.Dunham@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 23611507SCurtis.Dunham@arm.comsystem.physmem.busUtil 0.23 # Data bus utilization in percentage 23711507SCurtis.Dunham@arm.comsystem.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads 23811507SCurtis.Dunham@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 23911507SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing 24011507SCurtis.Dunham@arm.comsystem.physmem.avgWrQLen 14.53 # Average write queue length when enqueuing 24111507SCurtis.Dunham@arm.comsystem.physmem.readRowHits 27745 # Number of row buffer hits during reads 24211507SCurtis.Dunham@arm.comsystem.physmem.writeRowHits 178 # Number of row buffer hits during writes 24311507SCurtis.Dunham@arm.comsystem.physmem.readRowHitRate 90.93 # Row buffer hit rate for reads 24411507SCurtis.Dunham@arm.comsystem.physmem.writeRowHitRate 63.57 # Row buffer hit rate for writes 24511507SCurtis.Dunham@arm.comsystem.physmem.avgGap 2135348.73 # Average gap between requests 24611507SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 90.68 # Row buffer hit rate, read and write combined 24711507SCurtis.Dunham@arm.comsystem.physmem_0.actEnergy 11551680 # Energy for activate commands per rank (pJ) 24811507SCurtis.Dunham@arm.comsystem.physmem_0.preEnergy 6303000 # Energy for precharge commands per rank (pJ) 24911507SCurtis.Dunham@arm.comsystem.physmem_0.readEnergy 123130800 # Energy for read commands per rank (pJ) 25011507SCurtis.Dunham@arm.comsystem.physmem_0.writeEnergy 1574640 # Energy for write commands per rank (pJ) 25111507SCurtis.Dunham@arm.comsystem.physmem_0.refreshEnergy 4309537440 # Energy for refresh commands per rank (pJ) 25211507SCurtis.Dunham@arm.comsystem.physmem_0.actBackEnergy 3035388510 # Energy for active background per rank (pJ) 25311507SCurtis.Dunham@arm.comsystem.physmem_0.preBackEnergy 36925944000 # Energy for precharge background per rank (pJ) 25411507SCurtis.Dunham@arm.comsystem.physmem_0.totalEnergy 44413430070 # Total energy per rank (pJ) 25511507SCurtis.Dunham@arm.comsystem.physmem_0.averagePower 673.125124 # Core power per rank (mW) 25611507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::IDLE 61414409250 # Time in different power states 25711507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::REF 2203240000 # Time in different power states 25811507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 25911507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT 2364289750 # Time in different power states 26011507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 26111507SCurtis.Dunham@arm.comsystem.physmem_1.actEnergy 9805320 # Energy for activate commands per rank (pJ) 26211507SCurtis.Dunham@arm.comsystem.physmem_1.preEnergy 5350125 # Energy for precharge commands per rank (pJ) 26311507SCurtis.Dunham@arm.comsystem.physmem_1.readEnergy 114441600 # Energy for read commands per rank (pJ) 26411507SCurtis.Dunham@arm.comsystem.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) 26511507SCurtis.Dunham@arm.comsystem.physmem_1.refreshEnergy 4309537440 # Energy for refresh commands per rank (pJ) 26611507SCurtis.Dunham@arm.comsystem.physmem_1.actBackEnergy 3171429270 # Energy for active background per rank (pJ) 26711507SCurtis.Dunham@arm.comsystem.physmem_1.preBackEnergy 36806601750 # Energy for precharge background per rank (pJ) 26811507SCurtis.Dunham@arm.comsystem.physmem_1.totalEnergy 44417217345 # Total energy per rank (pJ) 26911507SCurtis.Dunham@arm.comsystem.physmem_1.averagePower 673.182663 # Core power per rank (mW) 27011507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::IDLE 61216839000 # Time in different power states 27111507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::REF 2203240000 # Time in different power states 27211507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 27311507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT 2563655500 # Time in different power states 27411507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 27511507SCurtis.Dunham@arm.comsystem.cpu.branchPred.lookups 40828848 # Number of BP lookups 27611507SCurtis.Dunham@arm.comsystem.cpu.branchPred.condPredicted 40828848 # Number of conditional branches predicted 27711507SCurtis.Dunham@arm.comsystem.cpu.branchPred.condIncorrect 1470674 # Number of conditional branches incorrect 27811507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBLookups 26813424 # Number of BTB lookups 27911507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHits 0 # Number of BTB hits 28011507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 28111507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage 28211507SCurtis.Dunham@arm.comsystem.cpu.branchPred.usedRAS 6079027 # Number of times the RAS was used to get a target. 28311507SCurtis.Dunham@arm.comsystem.cpu.branchPred.RASInCorrect 92484 # Number of incorrect RAS predictions. 28411507SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectLookups 26813424 # Number of indirect predictor lookups. 28511507SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectHits 21202389 # Number of indirect target hits. 28611507SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectMisses 5611035 # Number of indirect misses. 28711507SCurtis.Dunham@arm.comsystem.cpu.branchPredindirectMispredicted 566146 # Number of mispredicted indirect branches. 28811507SCurtis.Dunham@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 28911507SCurtis.Dunham@arm.comsystem.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 29011507SCurtis.Dunham@arm.comsystem.cpu.workload.num_syscalls 444 # Number of system calls 29111507SCurtis.Dunham@arm.comsystem.cpu.numCycles 131973488 # number of cpu cycles simulated 29211507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 29311507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 29411507SCurtis.Dunham@arm.comsystem.cpu.fetch.icacheStallCycles 30825655 # Number of cycles fetch is stalled on an Icache miss 29511507SCurtis.Dunham@arm.comsystem.cpu.fetch.Insts 222121094 # Number of instructions fetch has processed 29611507SCurtis.Dunham@arm.comsystem.cpu.fetch.Branches 40828848 # Number of branches that fetch encountered 29711507SCurtis.Dunham@arm.comsystem.cpu.fetch.predictedBranches 27281416 # Number of branches that fetch has predicted taken 29811507SCurtis.Dunham@arm.comsystem.cpu.fetch.Cycles 99433771 # Number of cycles fetch has run and was not squashing or blocked 29911507SCurtis.Dunham@arm.comsystem.cpu.fetch.SquashCycles 3060135 # Number of cycles fetch has spent squashing 30011507SCurtis.Dunham@arm.comsystem.cpu.fetch.TlbCycles 329 # Number of cycles fetch has spent waiting for tlb 30111507SCurtis.Dunham@arm.comsystem.cpu.fetch.MiscStallCycles 6280 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 30211507SCurtis.Dunham@arm.comsystem.cpu.fetch.PendingTrapStallCycles 112427 # Number of stall cycles due to pending traps 30311507SCurtis.Dunham@arm.comsystem.cpu.fetch.PendingQuiesceStallCycles 56 # Number of stall cycles due to pending quiesce instructions 30411507SCurtis.Dunham@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 115 # Number of stall cycles due to full MSHR 30511507SCurtis.Dunham@arm.comsystem.cpu.fetch.CacheLines 29997924 # Number of cache lines fetched 30611507SCurtis.Dunham@arm.comsystem.cpu.fetch.IcacheSquashes 374431 # Number of outstanding Icache misses that were squashed 30711507SCurtis.Dunham@arm.comsystem.cpu.fetch.ItlbSquashes 8 # Number of outstanding ITLB misses that were squashed 30811507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::samples 131908700 # Number of instructions fetched each cycle (Total) 30911507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::mean 2.964131 # Number of instructions fetched each cycle (Total) 31011507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::stdev 3.412100 # Number of instructions fetched each cycle (Total) 31111507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 31211507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::0 65727022 49.83% 49.83% # Number of instructions fetched each cycle (Total) 31311507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::1 4068693 3.08% 52.91% # Number of instructions fetched each cycle (Total) 31411507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::2 3626407 2.75% 55.66% # Number of instructions fetched each cycle (Total) 31511507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::3 6133247 4.65% 60.31% # Number of instructions fetched each cycle (Total) 31611507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::4 7782444 5.90% 66.21% # Number of instructions fetched each cycle (Total) 31711507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::5 5574161 4.23% 70.44% # Number of instructions fetched each cycle (Total) 31811507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::6 3387073 2.57% 73.00% # Number of instructions fetched each cycle (Total) 31911507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::7 2926863 2.22% 75.22% # Number of instructions fetched each cycle (Total) 32011507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::8 32682790 24.78% 100.00% # Number of instructions fetched each cycle (Total) 32111507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 32211507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 32311507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 32411507SCurtis.Dunham@arm.comsystem.cpu.fetch.rateDist::total 131908700 # Number of instructions fetched each cycle (Total) 32511507SCurtis.Dunham@arm.comsystem.cpu.fetch.branchRate 0.309372 # Number of branch fetches per cycle 32611507SCurtis.Dunham@arm.comsystem.cpu.fetch.rate 1.683074 # Number of inst fetches per cycle 32711507SCurtis.Dunham@arm.comsystem.cpu.decode.IdleCycles 15512553 # Number of cycles decode is idle 32811507SCurtis.Dunham@arm.comsystem.cpu.decode.BlockedCycles 64273138 # Number of cycles decode is blocked 32911507SCurtis.Dunham@arm.comsystem.cpu.decode.RunCycles 40712149 # Number of cycles decode is running 33011507SCurtis.Dunham@arm.comsystem.cpu.decode.UnblockCycles 9880793 # Number of cycles decode is unblocking 33111507SCurtis.Dunham@arm.comsystem.cpu.decode.SquashCycles 1530067 # Number of cycles decode is squashing 33211507SCurtis.Dunham@arm.comsystem.cpu.decode.DecodedInsts 365468602 # Number of instructions handled by decode 33311507SCurtis.Dunham@arm.comsystem.cpu.rename.SquashCycles 1530067 # Number of cycles rename is squashing 33411507SCurtis.Dunham@arm.comsystem.cpu.rename.IdleCycles 21068463 # Number of cycles rename is idle 33511507SCurtis.Dunham@arm.comsystem.cpu.rename.BlockCycles 11448631 # Number of cycles rename is blocking 33611507SCurtis.Dunham@arm.comsystem.cpu.rename.serializeStallCycles 17559 # count of cycles rename stalled for serializing inst 33711507SCurtis.Dunham@arm.comsystem.cpu.rename.RunCycles 44736331 # Number of cycles rename is running 33811507SCurtis.Dunham@arm.comsystem.cpu.rename.UnblockCycles 53107649 # Number of cycles rename is unblocking 33911507SCurtis.Dunham@arm.comsystem.cpu.rename.RenamedInsts 355543189 # Number of instructions processed by rename 34011507SCurtis.Dunham@arm.comsystem.cpu.rename.ROBFullEvents 24245 # Number of times rename has blocked due to ROB full 34111507SCurtis.Dunham@arm.comsystem.cpu.rename.IQFullEvents 799476 # Number of times rename has blocked due to IQ full 34211507SCurtis.Dunham@arm.comsystem.cpu.rename.LQFullEvents 46595900 # Number of times rename has blocked due to LQ full 34311507SCurtis.Dunham@arm.comsystem.cpu.rename.SQFullEvents 4792588 # Number of times rename has blocked due to SQ full 34411507SCurtis.Dunham@arm.comsystem.cpu.rename.RenamedOperands 358065930 # Number of destination operands rename has renamed 34511507SCurtis.Dunham@arm.comsystem.cpu.rename.RenameLookups 942303414 # Number of register rename lookups that rename has made 34611507SCurtis.Dunham@arm.comsystem.cpu.rename.int_rename_lookups 580264608 # Number of integer rename lookups 34711507SCurtis.Dunham@arm.comsystem.cpu.rename.fp_rename_lookups 22491 # Number of floating rename lookups 34811507SCurtis.Dunham@arm.comsystem.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed 34911507SCurtis.Dunham@arm.comsystem.cpu.rename.UndoneMaps 78853183 # Number of HB maps that are undone due to squashing 35011507SCurtis.Dunham@arm.comsystem.cpu.rename.serializingInsts 501 # count of serializing insts renamed 35111507SCurtis.Dunham@arm.comsystem.cpu.rename.tempSerializingInsts 500 # count of temporary serializing insts renamed 35211507SCurtis.Dunham@arm.comsystem.cpu.rename.skidInsts 64461317 # count of insts added to the skid buffer 35311507SCurtis.Dunham@arm.comsystem.cpu.memDep0.insertedLoads 113156478 # Number of loads inserted to the mem dependence unit. 35411507SCurtis.Dunham@arm.comsystem.cpu.memDep0.insertedStores 38725561 # Number of stores inserted to the mem dependence unit. 35511507SCurtis.Dunham@arm.comsystem.cpu.memDep0.conflictingLoads 51813945 # Number of conflicting loads. 35611507SCurtis.Dunham@arm.comsystem.cpu.memDep0.conflictingStores 9109294 # Number of conflicting stores. 35711507SCurtis.Dunham@arm.comsystem.cpu.iq.iqInstsAdded 346336448 # Number of instructions added to the IQ (excludes non-spec) 35811507SCurtis.Dunham@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 4423 # Number of non-speculative instructions added to the IQ 35911507SCurtis.Dunham@arm.comsystem.cpu.iq.iqInstsIssued 319025181 # Number of instructions issued 36011507SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedInstsIssued 175223 # Number of squashed instructions issued 36111507SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedInstsExamined 68148407 # Number of squashed instructions iterated over during squash; mainly for profiling 36211507SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 106206343 # Number of squashed operands that are examined and possibly removed from graph 36311507SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 3978 # Number of squashed non-spec instructions that were removed 36411507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::samples 131908700 # Number of insts issued each cycle 36511507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::mean 2.418530 # Number of insts issued each cycle 36611507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::stdev 2.165753 # Number of insts issued each cycle 36711507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 36811507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::0 35712645 27.07% 27.07% # Number of insts issued each cycle 36911507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::1 20185531 15.30% 42.38% # Number of insts issued each cycle 37011507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::2 17171104 13.02% 55.39% # Number of insts issued each cycle 37111507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::3 17670057 13.40% 68.79% # Number of insts issued each cycle 37211507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::4 15380757 11.66% 80.45% # Number of insts issued each cycle 37311507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::5 12917935 9.79% 90.24% # Number of insts issued each cycle 37411507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::6 6743014 5.11% 95.35% # Number of insts issued each cycle 37511507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::7 4104772 3.11% 98.47% # Number of insts issued each cycle 37611507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::8 2022885 1.53% 100.00% # Number of insts issued each cycle 37711507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 37811507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 37911507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 38011507SCurtis.Dunham@arm.comsystem.cpu.iq.issued_per_cycle::total 131908700 # Number of insts issued each cycle 38111507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 38211507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntAlu 364922 8.93% 8.93% # attempts to use FU when none available 38311507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available 38411507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available 38511507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available 38611507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available 38711507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available 38811507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available 38911507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available 39011507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available 39111507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available 39211507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available 39311507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available 39411507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available 39511507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available 39611507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available 39711507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available 39811507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available 39911507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available 40011507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available 40111507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available 40211507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available 40311507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available 40411507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available 40511507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available 40611507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available 40711507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available 40811507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available 40911507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available 41011507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available 41111507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::MemRead 3529438 86.37% 95.30% # attempts to use FU when none available 41211507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::MemWrite 191983 4.70% 100.00% # attempts to use FU when none available 41311507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 41411507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 41511507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::No_OpClass 33340 0.01% 0.01% # Type of FU issued 41611507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IntAlu 182585704 57.23% 57.24% # Type of FU issued 41711507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IntMult 11686 0.00% 57.25% # Type of FU issued 41811507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IntDiv 478 0.00% 57.25% # Type of FU issued 41911507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 321 0.00% 57.25% # Type of FU issued 42011507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.25% # Type of FU issued 42111507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.25% # Type of FU issued 42211507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.25% # Type of FU issued 42311507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.25% # Type of FU issued 42411507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.25% # Type of FU issued 42511507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.25% # Type of FU issued 42611507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.25% # Type of FU issued 42711507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.25% # Type of FU issued 42811507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.25% # Type of FU issued 42911507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.25% # Type of FU issued 43011507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.25% # Type of FU issued 43111507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.25% # Type of FU issued 43211507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.25% # Type of FU issued 43311507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.25% # Type of FU issued 43411507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.25% # Type of FU issued 43511507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.25% # Type of FU issued 43611507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.25% # Type of FU issued 43711507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.25% # Type of FU issued 43811507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.25% # Type of FU issued 43911507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.25% # Type of FU issued 44011507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.25% # Type of FU issued 44111507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.25% # Type of FU issued 44211507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.25% # Type of FU issued 44311507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.25% # Type of FU issued 44411507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.25% # Type of FU issued 44511507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::MemRead 101596397 31.85% 89.09% # Type of FU issued 44611507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::MemWrite 34797255 10.91% 100.00% # Type of FU issued 44711507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 44811507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 44911507SCurtis.Dunham@arm.comsystem.cpu.iq.FU_type_0::total 319025181 # Type of FU issued 45011507SCurtis.Dunham@arm.comsystem.cpu.iq.rate 2.417343 # Inst issue rate 45111507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_busy_cnt 4086343 # FU busy when requested 45211507SCurtis.Dunham@arm.comsystem.cpu.iq.fu_busy_rate 0.012809 # FU busy rate (busy events/executed inst) 45311507SCurtis.Dunham@arm.comsystem.cpu.iq.int_inst_queue_reads 774202119 # Number of integer instruction queue reads 45411507SCurtis.Dunham@arm.comsystem.cpu.iq.int_inst_queue_writes 414517759 # Number of integer instruction queue writes 45511507SCurtis.Dunham@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 314637932 # Number of integer instruction queue wakeup accesses 45611507SCurtis.Dunham@arm.comsystem.cpu.iq.fp_inst_queue_reads 18509 # Number of floating instruction queue reads 45711507SCurtis.Dunham@arm.comsystem.cpu.iq.fp_inst_queue_writes 33754 # Number of floating instruction queue writes 45811507SCurtis.Dunham@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 4413 # Number of floating instruction queue wakeup accesses 45911507SCurtis.Dunham@arm.comsystem.cpu.iq.int_alu_accesses 323069884 # Number of integer alu accesses 46011507SCurtis.Dunham@arm.comsystem.cpu.iq.fp_alu_accesses 8300 # Number of floating point alu accesses 46111507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 57418928 # Number of loads that had data forwarded from stores 46211507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 46311507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 22377093 # Number of loads squashed 46411507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 67905 # Number of memory responses ignored because the instruction is squashed 46511507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 65034 # Number of memory ordering violations 46611507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 7285809 # Number of stores squashed 46711507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 46811507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 46911507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 4034 # Number of loads that were rescheduled 47011507SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 140997 # Number of times an access to memory failed due to the cache being blocked 47111507SCurtis.Dunham@arm.comsystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 47211507SCurtis.Dunham@arm.comsystem.cpu.iew.iewSquashCycles 1530067 # Number of cycles IEW is squashing 47311507SCurtis.Dunham@arm.comsystem.cpu.iew.iewBlockCycles 8343953 # Number of cycles IEW is blocking 47411507SCurtis.Dunham@arm.comsystem.cpu.iew.iewUnblockCycles 3020633 # Number of cycles IEW is unblocking 47511507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispatchedInsts 346340871 # Number of instructions dispatched to IQ 47611507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispSquashedInsts 136261 # Number of squashed instructions skipped by dispatch 47711507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispLoadInsts 113156478 # Number of dispatched load instructions 47811507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispStoreInsts 38725561 # Number of dispatched store instructions 47911507SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispNonSpecInsts 1825 # Number of dispatched non-speculative instructions 48011507SCurtis.Dunham@arm.comsystem.cpu.iew.iewIQFullEvents 2944 # Number of times the IQ has become full, causing a stall 48111507SCurtis.Dunham@arm.comsystem.cpu.iew.iewLSQFullEvents 3026950 # Number of times the LSQ has become full, causing a stall 48211507SCurtis.Dunham@arm.comsystem.cpu.iew.memOrderViolationEvents 65034 # Number of memory order violations 48311507SCurtis.Dunham@arm.comsystem.cpu.iew.predictedTakenIncorrect 548248 # Number of branches that were predicted taken incorrectly 48411507SCurtis.Dunham@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 1104057 # Number of branches that were predicted not taken incorrectly 48511507SCurtis.Dunham@arm.comsystem.cpu.iew.branchMispredicts 1652305 # Number of branch mispredicts detected at execute 48611507SCurtis.Dunham@arm.comsystem.cpu.iew.iewExecutedInsts 316487526 # Number of executed instructions 48711507SCurtis.Dunham@arm.comsystem.cpu.iew.iewExecLoadInsts 100816589 # Number of load instructions executed 48811507SCurtis.Dunham@arm.comsystem.cpu.iew.iewExecSquashedInsts 2537655 # Number of squashed instructions skipped in execute 48911507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_swp 0 # number of swp insts executed 49011507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_nop 0 # number of nop insts executed 49111507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_refs 135188403 # number of memory reference insts executed 49211507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_branches 32185799 # Number of branches executed 49311507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_stores 34371814 # Number of stores executed 49411507SCurtis.Dunham@arm.comsystem.cpu.iew.exec_rate 2.398114 # Inst execution rate 49511507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_sent 315304152 # cumulative count of insts sent to commit 49611507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_count 314642345 # cumulative count of insts written-back 49711507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_producers 238446717 # num instructions producing a value 49811507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_consumers 344411432 # num instructions consuming a value 49911507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_rate 2.384133 # insts written-back per cycle 50011507SCurtis.Dunham@arm.comsystem.cpu.iew.wb_fanout 0.692331 # average fanout of values written-back 50111507SCurtis.Dunham@arm.comsystem.cpu.commit.commitSquashedInsts 68273083 # The number of squashed insts skipped by commit 50211507SCurtis.Dunham@arm.comsystem.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards 50311507SCurtis.Dunham@arm.comsystem.cpu.commit.branchMispredicts 1477187 # The number of times a branch was mispredicted 50411507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::samples 122118176 # Number of insts commited each cycle 50511507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::mean 2.278059 # Number of insts commited each cycle 50611507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::stdev 3.046851 # Number of insts commited each cycle 50711507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 50811507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::0 56957157 46.64% 46.64% # Number of insts commited each cycle 50911507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::1 16546673 13.55% 60.19% # Number of insts commited each cycle 51011507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::2 11180219 9.16% 69.35% # Number of insts commited each cycle 51111507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::3 8765216 7.18% 76.52% # Number of insts commited each cycle 51211507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::4 2116572 1.73% 78.26% # Number of insts commited each cycle 51311507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::5 1764817 1.45% 79.70% # Number of insts commited each cycle 51411507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::6 934979 0.77% 80.47% # Number of insts commited each cycle 51511507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::7 730886 0.60% 81.07% # Number of insts commited each cycle 51611507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::8 23121657 18.93% 100.00% # Number of insts commited each cycle 51711507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 51811507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 51911507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 52011507SCurtis.Dunham@arm.comsystem.cpu.commit.committed_per_cycle::total 122118176 # Number of insts commited each cycle 52111507SCurtis.Dunham@arm.comsystem.cpu.commit.committedInsts 157988547 # Number of instructions committed 52211507SCurtis.Dunham@arm.comsystem.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed 52311507SCurtis.Dunham@arm.comsystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 52411507SCurtis.Dunham@arm.comsystem.cpu.commit.refs 122219137 # Number of memory references committed 52511507SCurtis.Dunham@arm.comsystem.cpu.commit.loads 90779385 # Number of loads committed 52611507SCurtis.Dunham@arm.comsystem.cpu.commit.membars 0 # Number of memory barriers committed 52711507SCurtis.Dunham@arm.comsystem.cpu.commit.branches 29309705 # Number of branches committed 52811507SCurtis.Dunham@arm.comsystem.cpu.commit.fp_insts 40 # Number of committed floating point instructions. 52911507SCurtis.Dunham@arm.comsystem.cpu.commit.int_insts 278169481 # Number of committed integer instructions. 53011507SCurtis.Dunham@arm.comsystem.cpu.commit.function_calls 4237596 # Number of function calls committed. 53111507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::No_OpClass 16695 0.01% 0.01% # Class of committed instruction 53211507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::IntAlu 155945353 56.06% 56.06% # Class of committed instruction 53311507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::IntMult 10938 0.00% 56.07% # Class of committed instruction 53411507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::IntDiv 329 0.00% 56.07% # Class of committed instruction 53511507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatAdd 12 0.00% 56.07% # Class of committed instruction 53611507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 56.07% # Class of committed instruction 53711507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 56.07% # Class of committed instruction 53811507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 56.07% # Class of committed instruction 53911507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 56.07% # Class of committed instruction 54011507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 56.07% # Class of committed instruction 54111507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 56.07% # Class of committed instruction 54211507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 56.07% # Class of committed instruction 54311507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 56.07% # Class of committed instruction 54411507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 56.07% # Class of committed instruction 54511507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 56.07% # Class of committed instruction 54611507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 56.07% # Class of committed instruction 54711507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 56.07% # Class of committed instruction 54811507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 56.07% # Class of committed instruction 54911507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 56.07% # Class of committed instruction 55011507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 56.07% # Class of committed instruction 55111507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 56.07% # Class of committed instruction 55211507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 56.07% # Class of committed instruction 55311507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 56.07% # Class of committed instruction 55411507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 56.07% # Class of committed instruction 55511507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 56.07% # Class of committed instruction 55611507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 56.07% # Class of committed instruction 55711507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 56.07% # Class of committed instruction 55811507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 56.07% # Class of committed instruction 55911507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.07% # Class of committed instruction 56011507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.07% # Class of committed instruction 56111507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::MemRead 90779385 32.63% 88.70% # Class of committed instruction 56211507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Class of committed instruction 56311507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 56411507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 56511507SCurtis.Dunham@arm.comsystem.cpu.commit.op_class_0::total 278192464 # Class of committed instruction 56611507SCurtis.Dunham@arm.comsystem.cpu.commit.bw_lim_events 23121657 # number cycles where commit BW limit reached 56711507SCurtis.Dunham@arm.comsystem.cpu.rob.rob_reads 445462066 # The number of ROB reads 56811507SCurtis.Dunham@arm.comsystem.cpu.rob.rob_writes 702797421 # The number of ROB writes 56911507SCurtis.Dunham@arm.comsystem.cpu.timesIdled 887 # Number of times that the entire CPU went into an idle state and unscheduled itself 57011507SCurtis.Dunham@arm.comsystem.cpu.idleCycles 64788 # Total number of cycles that the CPU has spent unscheduled due to idling 57111507SCurtis.Dunham@arm.comsystem.cpu.committedInsts 157988547 # Number of Instructions Simulated 57211507SCurtis.Dunham@arm.comsystem.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated 57311507SCurtis.Dunham@arm.comsystem.cpu.cpi 0.835336 # CPI: Cycles Per Instruction 57411507SCurtis.Dunham@arm.comsystem.cpu.cpi_total 0.835336 # CPI: Total CPI of All Threads 57511507SCurtis.Dunham@arm.comsystem.cpu.ipc 1.197123 # IPC: Instructions Per Cycle 57611507SCurtis.Dunham@arm.comsystem.cpu.ipc_total 1.197123 # IPC: Total IPC of All Threads 57711507SCurtis.Dunham@arm.comsystem.cpu.int_regfile_reads 504041942 # number of integer regfile reads 57811507SCurtis.Dunham@arm.comsystem.cpu.int_regfile_writes 248656420 # number of integer regfile writes 57911507SCurtis.Dunham@arm.comsystem.cpu.fp_regfile_reads 4180 # number of floating regfile reads 58011507SCurtis.Dunham@arm.comsystem.cpu.fp_regfile_writes 782 # number of floating regfile writes 58111507SCurtis.Dunham@arm.comsystem.cpu.cc_regfile_reads 109261684 # number of cc regfile reads 58211507SCurtis.Dunham@arm.comsystem.cpu.cc_regfile_writes 65602098 # number of cc regfile writes 58311507SCurtis.Dunham@arm.comsystem.cpu.misc_regfile_reads 202573497 # number of misc regfile reads 58411507SCurtis.Dunham@arm.comsystem.cpu.misc_regfile_writes 1 # number of misc regfile writes 58511507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.replacements 2073508 # number of replacements 58611507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tagsinuse 4068.413497 # Cycle average of tags in use 58711507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.total_refs 71894591 # Total number of references to valid blocks. 58811507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.sampled_refs 2077604 # Sample count of references to valid blocks. 58911507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.avg_refs 34.604569 # Average number of references to valid blocks. 59011507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.warmup_cycle 21372047500 # Cycle when the warmup percentage was hit. 59111507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 4068.413497 # Average occupied blocks per requestor 59211507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.993265 # Average percentage of cache occupancy 59311507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.993265 # Average percentage of cache occupancy 59411507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 59511507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 542 # Occupied blocks per task id 59611507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 3404 # Occupied blocks per task id 59711507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id 59811507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 59911507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tag_accesses 151442194 # Number of tag accesses 60011507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.data_accesses 151442194 # Number of data accesses 60111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 40548572 # number of ReadReq hits 60211507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::total 40548572 # number of ReadReq hits 60311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 31346019 # number of WriteReq hits 60411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::total 31346019 # number of WriteReq hits 60511507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::cpu.data 71894591 # number of demand (read+write) hits 60611507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::total 71894591 # number of demand (read+write) hits 60711507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::cpu.data 71894591 # number of overall hits 60811507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::total 71894591 # number of overall hits 60911507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 2693971 # number of ReadReq misses 61011507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::total 2693971 # number of ReadReq misses 61111507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 93733 # number of WriteReq misses 61211507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::total 93733 # number of WriteReq misses 61311507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::cpu.data 2787704 # number of demand (read+write) misses 61411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::total 2787704 # number of demand (read+write) misses 61511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::cpu.data 2787704 # number of overall misses 61611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::total 2787704 # number of overall misses 61711507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 32332975500 # number of ReadReq miss cycles 61811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 32332975500 # number of ReadReq miss cycles 61911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 2952822993 # number of WriteReq miss cycles 62011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 2952822993 # number of WriteReq miss cycles 62111507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 35285798493 # number of demand (read+write) miss cycles 62211507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::total 35285798493 # number of demand (read+write) miss cycles 62311507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 35285798493 # number of overall miss cycles 62411507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::total 35285798493 # number of overall miss cycles 62511507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 43242543 # number of ReadReq accesses(hits+misses) 62611507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::total 43242543 # number of ReadReq accesses(hits+misses) 62711507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) 62811507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) 62911507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 74682295 # number of demand (read+write) accesses 63011507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::total 74682295 # number of demand (read+write) accesses 63111507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 74682295 # number of overall (read+write) accesses 63211507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::total 74682295 # number of overall (read+write) accesses 63311507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062299 # miss rate for ReadReq accesses 63411507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.062299 # miss rate for ReadReq accesses 63511507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002981 # miss rate for WriteReq accesses 63611507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.002981 # miss rate for WriteReq accesses 63711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.037328 # miss rate for demand accesses 63811507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.037328 # miss rate for demand accesses 63911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.037328 # miss rate for overall accesses 64011507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.037328 # miss rate for overall accesses 64111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12001.976079 # average ReadReq miss latency 64211507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 12001.976079 # average ReadReq miss latency 64311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31502.491044 # average WriteReq miss latency 64411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 31502.491044 # average WriteReq miss latency 64511507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 12657.656083 # average overall miss latency 64611507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 12657.656083 # average overall miss latency 64711507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 12657.656083 # average overall miss latency 64811507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 12657.656083 # average overall miss latency 64911507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 219202 # number of cycles access was blocked 65011507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 497 # number of cycles access was blocked 65111507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_mshrs 43207 # number of cycles access was blocked 65211507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked 65311507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 5.073298 # average number of cycles each access was blocked 65411507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 124.250000 # average number of cycles each access was blocked 65511507SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::writebacks 2066969 # number of writebacks 65611507SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::total 2066969 # number of writebacks 65711507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 698217 # number of ReadReq MSHR hits 65811507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 698217 # number of ReadReq MSHR hits 65911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 11883 # number of WriteReq MSHR hits 66011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 11883 # number of WriteReq MSHR hits 66111507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 710100 # number of demand (read+write) MSHR hits 66211507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::total 710100 # number of demand (read+write) MSHR hits 66311507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 710100 # number of overall MSHR hits 66411507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::total 710100 # number of overall MSHR hits 66511507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995754 # number of ReadReq MSHR misses 66611507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 1995754 # number of ReadReq MSHR misses 66711507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 81850 # number of WriteReq MSHR misses 66811507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 81850 # number of WriteReq MSHR misses 66911507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 2077604 # number of demand (read+write) MSHR misses 67011507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::total 2077604 # number of demand (read+write) MSHR misses 67111507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 2077604 # number of overall MSHR misses 67211507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::total 2077604 # number of overall MSHR misses 67311507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24221413500 # number of ReadReq MSHR miss cycles 67411507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 24221413500 # number of ReadReq MSHR miss cycles 67511507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2795777993 # number of WriteReq MSHR miss cycles 67611507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 2795777993 # number of WriteReq MSHR miss cycles 67711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 27017191493 # number of demand (read+write) MSHR miss cycles 67811507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 27017191493 # number of demand (read+write) MSHR miss cycles 67911507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 27017191493 # number of overall MSHR miss cycles 68011507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 27017191493 # number of overall MSHR miss cycles 68111507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046153 # mshr miss rate for ReadReq accesses 68211507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046153 # mshr miss rate for ReadReq accesses 68311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002603 # mshr miss rate for WriteReq accesses 68411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002603 # mshr miss rate for WriteReq accesses 68511507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027819 # mshr miss rate for demand accesses 68611507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.027819 # mshr miss rate for demand accesses 68711507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027819 # mshr miss rate for overall accesses 68811507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.027819 # mshr miss rate for overall accesses 68911507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12136.472481 # average ReadReq mshr miss latency 69011507SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12136.472481 # average ReadReq mshr miss latency 69111507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34157.336506 # average WriteReq mshr miss latency 69211507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34157.336506 # average WriteReq mshr miss latency 69311507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency 69411507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency 69511507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13004.013995 # average overall mshr miss latency 69611507SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 13004.013995 # average overall mshr miss latency 69711507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.replacements 93 # number of replacements 69811507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tagsinuse 870.928206 # Cycle average of tags in use 69911507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.total_refs 29996478 # Total number of references to valid blocks. 70011507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.sampled_refs 1113 # Sample count of references to valid blocks. 70111507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.avg_refs 26951.013477 # Average number of references to valid blocks. 70211507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 70311507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 870.928206 # Average occupied blocks per requestor 70411507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.425258 # Average percentage of cache occupancy 70511507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::total 0.425258 # Average percentage of cache occupancy 70611507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 1020 # Occupied blocks per task id 70711507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id 70811507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id 70911507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id 71011507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 34 # Occupied blocks per task id 71111507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 906 # Occupied blocks per task id 71211507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id 71311507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tag_accesses 59996959 # Number of tag accesses 71411507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.data_accesses 59996959 # Number of data accesses 71511507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 29996478 # number of ReadReq hits 71611507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::total 29996478 # number of ReadReq hits 71711507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::cpu.inst 29996478 # number of demand (read+write) hits 71811507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::total 29996478 # number of demand (read+write) hits 71911507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::cpu.inst 29996478 # number of overall hits 72011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::total 29996478 # number of overall hits 72111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 1445 # number of ReadReq misses 72211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::total 1445 # number of ReadReq misses 72311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::cpu.inst 1445 # number of demand (read+write) misses 72411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::total 1445 # number of demand (read+write) misses 72511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::cpu.inst 1445 # number of overall misses 72611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::total 1445 # number of overall misses 72711507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 106088999 # number of ReadReq miss cycles 72811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 106088999 # number of ReadReq miss cycles 72911507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 106088999 # number of demand (read+write) miss cycles 73011507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::total 106088999 # number of demand (read+write) miss cycles 73111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 106088999 # number of overall miss cycles 73211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::total 106088999 # number of overall miss cycles 73311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 29997923 # number of ReadReq accesses(hits+misses) 73411507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::total 29997923 # number of ReadReq accesses(hits+misses) 73511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 29997923 # number of demand (read+write) accesses 73611507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::total 29997923 # number of demand (read+write) accesses 73711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 29997923 # number of overall (read+write) accesses 73811507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::total 29997923 # number of overall (read+write) accesses 73911507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000048 # miss rate for ReadReq accesses 74011507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.000048 # miss rate for ReadReq accesses 74111507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.000048 # miss rate for demand accesses 74211507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses 74311507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses 74411507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses 74511507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73417.992388 # average ReadReq miss latency 74611507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 73417.992388 # average ReadReq miss latency 74711507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 73417.992388 # average overall miss latency 74811507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 73417.992388 # average overall miss latency 74911507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 73417.992388 # average overall miss latency 75011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 73417.992388 # average overall miss latency 75111507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 515 # number of cycles access was blocked 75211507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 75311507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked 75411507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 75511507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 46.818182 # average number of cycles each access was blocked 75611507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 75711507SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::writebacks 93 # number of writebacks 75811507SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::total 93 # number of writebacks 75911507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 332 # number of ReadReq MSHR hits 76011507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 332 # number of ReadReq MSHR hits 76111507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 332 # number of demand (read+write) MSHR hits 76211507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_hits::total 332 # number of demand (read+write) MSHR hits 76311507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 332 # number of overall MSHR hits 76411507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_hits::total 332 # number of overall MSHR hits 76511507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 1113 # number of ReadReq MSHR misses 76611507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 1113 # number of ReadReq MSHR misses 76711507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 1113 # number of demand (read+write) MSHR misses 76811507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::total 1113 # number of demand (read+write) MSHR misses 76911507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 1113 # number of overall MSHR misses 77011507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::total 1113 # number of overall MSHR misses 77111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 84684499 # number of ReadReq MSHR miss cycles 77211507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 84684499 # number of ReadReq MSHR miss cycles 77311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 84684499 # number of demand (read+write) MSHR miss cycles 77411507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 84684499 # number of demand (read+write) MSHR miss cycles 77511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 84684499 # number of overall MSHR miss cycles 77611507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 84684499 # number of overall MSHR miss cycles 77711507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses 77811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses 77911507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses 78011507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses 78111507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses 78211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses 78311507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76086.701707 # average ReadReq mshr miss latency 78411507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76086.701707 # average ReadReq mshr miss latency 78511507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76086.701707 # average overall mshr miss latency 78611507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency 78711507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76086.701707 # average overall mshr miss latency 78811507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 76086.701707 # average overall mshr miss latency 78911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.replacements 650 # number of replacements 79011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tagsinuse 20606.403574 # Cycle average of tags in use 79111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.total_refs 4037654 # Total number of references to valid blocks. 79211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.sampled_refs 30622 # Sample count of references to valid blocks. 79311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.avg_refs 131.854680 # Average number of references to valid blocks. 79411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 79511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 19620.454834 # Average occupied blocks per requestor 79611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 710.830105 # Average occupied blocks per requestor 79711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 275.118635 # Average occupied blocks per requestor 79811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.598769 # Average percentage of cache occupancy 79911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.021693 # Average percentage of cache occupancy 80011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.008396 # Average percentage of cache occupancy 80111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.628858 # Average percentage of cache occupancy 80211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 29972 # Occupied blocks per task id 80311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 80411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id 80511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 833 # Occupied blocks per task id 80611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 1405 # Occupied blocks per task id 80711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 27613 # Occupied blocks per task id 80811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.914673 # Percentage of cache occupancy per task id 80911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tag_accesses 33330894 # Number of tag accesses 81011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.data_accesses 33330894 # Number of data accesses 81111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 2066969 # number of WritebackDirty hits 81211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 2066969 # number of WritebackDirty hits 81311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 93 # number of WritebackClean hits 81411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 93 # number of WritebackClean hits 81511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 52906 # number of ReadExReq hits 81611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 52906 # number of ReadExReq hits 81711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 28 # number of ReadCleanReq hits 81811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 28 # number of ReadCleanReq hits 81911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 1995161 # number of ReadSharedReq hits 82011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 1995161 # number of ReadSharedReq hits 82111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits 82211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 2048067 # number of demand (read+write) hits 82311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::total 2048095 # number of demand (read+write) hits 82411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits 82511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 2048067 # number of overall hits 82611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::total 2048095 # number of overall hits 82711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 28982 # number of ReadExReq misses 82811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 28982 # number of ReadExReq misses 82911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1085 # number of ReadCleanReq misses 83011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 1085 # number of ReadCleanReq misses 83111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 555 # number of ReadSharedReq misses 83211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 555 # number of ReadSharedReq misses 83311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 1085 # number of demand (read+write) misses 83411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 29537 # number of demand (read+write) misses 83511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::total 30622 # number of demand (read+write) misses 83611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 1085 # number of overall misses 83711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 29537 # number of overall misses 83811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::total 30622 # number of overall misses 83911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2117059500 # number of ReadExReq miss cycles 84011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 2117059500 # number of ReadExReq miss cycles 84111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 82707500 # number of ReadCleanReq miss cycles 84211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 82707500 # number of ReadCleanReq miss cycles 84311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 43407000 # number of ReadSharedReq miss cycles 84411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 43407000 # number of ReadSharedReq miss cycles 84511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 82707500 # number of demand (read+write) miss cycles 84611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 2160466500 # number of demand (read+write) miss cycles 84711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::total 2243174000 # number of demand (read+write) miss cycles 84811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 82707500 # number of overall miss cycles 84911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 2160466500 # number of overall miss cycles 85011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::total 2243174000 # number of overall miss cycles 85111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 2066969 # number of WritebackDirty accesses(hits+misses) 85211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 2066969 # number of WritebackDirty accesses(hits+misses) 85311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 93 # number of WritebackClean accesses(hits+misses) 85411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 93 # number of WritebackClean accesses(hits+misses) 85511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 81888 # number of ReadExReq accesses(hits+misses) 85611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 81888 # number of ReadExReq accesses(hits+misses) 85711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1113 # number of ReadCleanReq accesses(hits+misses) 85811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 1113 # number of ReadCleanReq accesses(hits+misses) 85911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1995716 # number of ReadSharedReq accesses(hits+misses) 86011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 1995716 # number of ReadSharedReq accesses(hits+misses) 86111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 1113 # number of demand (read+write) accesses 86211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 2077604 # number of demand (read+write) accesses 86311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::total 2078717 # number of demand (read+write) accesses 86411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 1113 # number of overall (read+write) accesses 86511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 2077604 # number of overall (read+write) accesses 86611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::total 2078717 # number of overall (read+write) accesses 86711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353922 # miss rate for ReadExReq accesses 86811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.353922 # miss rate for ReadExReq accesses 86911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.974843 # miss rate for ReadCleanReq accesses 87011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.974843 # miss rate for ReadCleanReq accesses 87111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000278 # miss rate for ReadSharedReq accesses 87211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000278 # miss rate for ReadSharedReq accesses 87311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.974843 # miss rate for demand accesses 87411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.014217 # miss rate for demand accesses 87511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.014731 # miss rate for demand accesses 87611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.974843 # miss rate for overall accesses 87711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.014217 # miss rate for overall accesses 87811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.014731 # miss rate for overall accesses 87911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73047.391484 # average ReadExReq miss latency 88011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 73047.391484 # average ReadExReq miss latency 88111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76228.110599 # average ReadCleanReq miss latency 88211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76228.110599 # average ReadCleanReq miss latency 88311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78210.810811 # average ReadSharedReq miss latency 88411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78210.810811 # average ReadSharedReq miss latency 88511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76228.110599 # average overall miss latency 88611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 73144.412093 # average overall miss latency 88711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 73253.673829 # average overall miss latency 88811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76228.110599 # average overall miss latency 88911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 73144.412093 # average overall miss latency 89011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 73253.673829 # average overall miss latency 89111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 89211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 89311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 89411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 89511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 89611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 89711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.writebacks::writebacks 280 # number of writebacks 89811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.writebacks::total 280 # number of writebacks 89911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28982 # number of ReadExReq MSHR misses 90011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 28982 # number of ReadExReq MSHR misses 90111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1085 # number of ReadCleanReq MSHR misses 90211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 1085 # number of ReadCleanReq MSHR misses 90311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 555 # number of ReadSharedReq MSHR misses 90411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 555 # number of ReadSharedReq MSHR misses 90511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 1085 # number of demand (read+write) MSHR misses 90611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 29537 # number of demand (read+write) MSHR misses 90711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 30622 # number of demand (read+write) MSHR misses 90811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 1085 # number of overall MSHR misses 90911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 29537 # number of overall MSHR misses 91011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 30622 # number of overall MSHR misses 91111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1827239500 # number of ReadExReq MSHR miss cycles 91211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1827239500 # number of ReadExReq MSHR miss cycles 91311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 71857500 # number of ReadCleanReq MSHR miss cycles 91411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 71857500 # number of ReadCleanReq MSHR miss cycles 91511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 37857000 # number of ReadSharedReq MSHR miss cycles 91611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 37857000 # number of ReadSharedReq MSHR miss cycles 91711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 71857500 # number of demand (read+write) MSHR miss cycles 91811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1865096500 # number of demand (read+write) MSHR miss cycles 91911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 1936954000 # number of demand (read+write) MSHR miss cycles 92011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 71857500 # number of overall MSHR miss cycles 92111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1865096500 # number of overall MSHR miss cycles 92211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 1936954000 # number of overall MSHR miss cycles 92311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353922 # mshr miss rate for ReadExReq accesses 92411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353922 # mshr miss rate for ReadExReq accesses 92511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.974843 # mshr miss rate for ReadCleanReq accesses 92611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.974843 # mshr miss rate for ReadCleanReq accesses 92711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for ReadSharedReq accesses 92811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000278 # mshr miss rate for ReadSharedReq accesses 92911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.974843 # mshr miss rate for demand accesses 93011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014217 # mshr miss rate for demand accesses 93111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.014731 # mshr miss rate for demand accesses 93211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.974843 # mshr miss rate for overall accesses 93311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014217 # mshr miss rate for overall accesses 93411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.014731 # mshr miss rate for overall accesses 93511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63047.391484 # average ReadExReq mshr miss latency 93611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63047.391484 # average ReadExReq mshr miss latency 93711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66228.110599 # average ReadCleanReq mshr miss latency 93811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66228.110599 # average ReadCleanReq mshr miss latency 93911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 68210.810811 # average ReadSharedReq mshr miss latency 94011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 68210.810811 # average ReadSharedReq mshr miss latency 94111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66228.110599 # average overall mshr miss latency 94211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63144.412093 # average overall mshr miss latency 94311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 63253.673829 # average overall mshr miss latency 94411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66228.110599 # average overall mshr miss latency 94511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63144.412093 # average overall mshr miss latency 94611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 63253.673829 # average overall mshr miss latency 94711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 4152318 # Total number of requests made to the snoop filter. 94811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 2073604 # Number of requests hitting in the snoop filter with a single holder of the requested data. 94911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 20 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 95011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 325 # Total number of snoops made to the snoop filter. 95111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 325 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 95211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 95311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 1996829 # Transaction distribution 95411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 2067249 # Transaction distribution 95511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 93 # Transaction distribution 95611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 6909 # Transaction distribution 95711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 81888 # Transaction distribution 95811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 81888 # Transaction distribution 95911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 1113 # Transaction distribution 96011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 1995716 # Transaction distribution 96111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2319 # Packet count per connected master and slave (bytes) 96211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228716 # Packet count per connected master and slave (bytes) 96311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count::total 6231035 # Packet count per connected master and slave (bytes) 96411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77184 # Cumulative packet size per connected master and slave (bytes) 96511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265252672 # Cumulative packet size per connected master and slave (bytes) 96611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size::total 265329856 # Cumulative packet size per connected master and slave (bytes) 96711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoops 650 # Total snoops (count) 96811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 2079367 # Request fanout histogram 96911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.000167 # Request fanout histogram 97011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.012936 # Request fanout histogram 97111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 97211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 2079019 99.98% 99.98% # Request fanout histogram 97311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 348 0.02% 100.00% # Request fanout histogram 97411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 97511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 97611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 97711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 97811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 2079367 # Request fanout histogram 97911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 4143221000 # Layer occupancy (ticks) 98011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) 98111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 1670997 # Layer occupancy (ticks) 98211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 98311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 3116406000 # Layer occupancy (ticks) 98411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 4.7 # Layer utilization (%) 98511507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 1640 # Transaction distribution 98611507SCurtis.Dunham@arm.comsystem.membus.trans_dist::WritebackDirty 280 # Transaction distribution 98711507SCurtis.Dunham@arm.comsystem.membus.trans_dist::CleanEvict 45 # Transaction distribution 98811507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 28982 # Transaction distribution 98911507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 28982 # Transaction distribution 99011507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 1640 # Transaction distribution 99111507SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61569 # Packet count per connected master and slave (bytes) 99211507SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 61569 # Packet count per connected master and slave (bytes) 99311507SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 61569 # Packet count per connected master and slave (bytes) 99411507SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1977728 # Cumulative packet size per connected master and slave (bytes) 99511507SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::total 1977728 # Cumulative packet size per connected master and slave (bytes) 99611507SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 1977728 # Cumulative packet size per connected master and slave (bytes) 99711507SCurtis.Dunham@arm.comsystem.membus.snoops 0 # Total snoops (count) 99811507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 30947 # Request fanout histogram 99911507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 100011507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 100111507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 100211507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 30947 100.00% 100.00% # Request fanout histogram 100311507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 100411507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 100511507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 100611507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 100711507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 30947 # Request fanout histogram 100811507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.occupancy 43483000 # Layer occupancy (ticks) 100911507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.utilization 0.1 # Layer utilization (%) 101011507SCurtis.Dunham@arm.comsystem.membus.respLayer1.occupancy 161384500 # Layer occupancy (ticks) 101111507SCurtis.Dunham@arm.comsystem.membus.respLayer1.utilization 0.2 # Layer utilization (%) 101211507SCurtis.Dunham@arm.com 101311507SCurtis.Dunham@arm.com---------- End Simulation Statistics ---------- 1014