stats.txt revision 11570
111507SCurtis.Dunham@arm.com 211507SCurtis.Dunham@arm.com---------- Begin Simulation Statistics ---------- 311570SCurtis.Dunham@arm.comsim_seconds 0.062409 # Number of seconds simulated 411570SCurtis.Dunham@arm.comsim_ticks 62408957500 # Number of ticks simulated 511570SCurtis.Dunham@arm.comfinal_tick 62408957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611507SCurtis.Dunham@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711570SCurtis.Dunham@arm.comhost_inst_rate 176281 # Simulator instruction rate (inst/s) 811570SCurtis.Dunham@arm.comhost_op_rate 177159 # Simulator op (including micro ops) rate (op/s) 911570SCurtis.Dunham@arm.comhost_tick_rate 121425676 # Simulator tick rate (ticks/s) 1011570SCurtis.Dunham@arm.comhost_mem_usage 399932 # Number of bytes of host memory used 1111570SCurtis.Dunham@arm.comhost_seconds 513.97 # Real time elapsed on the host 1211507SCurtis.Dunham@arm.comsim_insts 90602850 # Number of instructions simulated 1311507SCurtis.Dunham@arm.comsim_ops 91054081 # Number of ops (including micro ops) simulated 1411507SCurtis.Dunham@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511507SCurtis.Dunham@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611570SCurtis.Dunham@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 1711507SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory 1811570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.data 947264 # Number of bytes read from this memory 1911570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 996736 # Number of bytes read from this memory 2011507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu.inst 49472 # Number of instructions bytes read from this memory 2111507SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 49472 # Number of instructions bytes read from this memory 2211507SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory 2311570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.data 14801 # Number of read requests responded to by this memory 2411570SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 15574 # Number of read requests responded to by this memory 2511570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.inst 792707 # Total read bandwidth from this memory (bytes/s) 2611570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.data 15178334 # Total read bandwidth from this memory (bytes/s) 2711570SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 15971041 # Total read bandwidth from this memory (bytes/s) 2811570SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu.inst 792707 # Instruction read bandwidth from this memory (bytes/s) 2911570SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 792707 # Instruction read bandwidth from this memory (bytes/s) 3011570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.inst 792707 # Total bandwidth to/from this memory (bytes/s) 3111570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.data 15178334 # Total bandwidth to/from this memory (bytes/s) 3211570SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 15971041 # Total bandwidth to/from this memory (bytes/s) 3311570SCurtis.Dunham@arm.comsystem.physmem.readReqs 15574 # Number of read requests accepted 3411507SCurtis.Dunham@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3511570SCurtis.Dunham@arm.comsystem.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue 3611507SCurtis.Dunham@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 3711570SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 996736 # Total number of bytes read from DRAM 3811507SCurtis.Dunham@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 3911507SCurtis.Dunham@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 4011570SCurtis.Dunham@arm.comsystem.physmem.bytesReadSys 996736 # Total read bytes from the system interface side 4111507SCurtis.Dunham@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 4211507SCurtis.Dunham@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 4311507SCurtis.Dunham@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 4411507SCurtis.Dunham@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4511507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 993 # Per bank write bursts 4611570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::1 891 # Per bank write bursts 4711507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::2 949 # Per bank write bursts 4811507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::3 1027 # Per bank write bursts 4911507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::4 1050 # Per bank write bursts 5011507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::5 1113 # Per bank write bursts 5111507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::6 1087 # Per bank write bursts 5211507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::7 1088 # Per bank write bursts 5311507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::8 1024 # Per bank write bursts 5411507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::9 962 # Per bank write bursts 5511507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::10 938 # Per bank write bursts 5611507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::11 899 # Per bank write bursts 5711507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::12 904 # Per bank write bursts 5811507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::13 867 # Per bank write bursts 5911507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::14 876 # Per bank write bursts 6011507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::15 906 # Per bank write bursts 6111507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 6211507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 6311507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 6411507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 6511507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 6611507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 6711507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 6811507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 6911507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 7011507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 7111507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 7211507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 7311507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 7411507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 7511507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 7611507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 7711507SCurtis.Dunham@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 7811507SCurtis.Dunham@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7911570SCurtis.Dunham@arm.comsystem.physmem.totGap 62408863500 # Total gap between requests 8011507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 8111507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 8211507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 8311507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 8411507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 8511507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8611570SCurtis.Dunham@arm.comsystem.physmem.readPktSize::6 15574 # Read request sizes (log2) 8711507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 8811507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 8911507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 9011507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 9111507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 9211507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 9311507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9411570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::0 15459 # What read queue length does an incoming req see 9511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::1 109 # What read queue length does an incoming req see 9611570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 6 # What read queue length does an incoming req see 9711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 9811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 9911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 10011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 10111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 10211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 10311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 10411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 10511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 10611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 10711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 10811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 10911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 11011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 11111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 11211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 11311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 11411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 11511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 11611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 11711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 11811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 11911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 12011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 12111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 12211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 12311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 12411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 12511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 12611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 12711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 12811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 12911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 13011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 13111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 13211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 13311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 13411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 13511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 13611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 13711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 13811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 13911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 14011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 14111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 14211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 14311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 14411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 14511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 14611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 14711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 14811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 14911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 15011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 15111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 15211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 15311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 15411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 15511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 15611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 15711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 16011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19011570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::samples 1549 # Bytes accessed per row activation 19111570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::mean 642.437702 # Bytes accessed per row activation 19211570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::gmean 437.017774 # Bytes accessed per row activation 19311570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::stdev 401.182344 # Bytes accessed per row activation 19411570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::0-127 251 16.20% 16.20% # Bytes accessed per row activation 19511570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::128-255 185 11.94% 28.15% # Bytes accessed per row activation 19611570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::256-383 90 5.81% 33.96% # Bytes accessed per row activation 19711570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::384-511 67 4.33% 38.28% # Bytes accessed per row activation 19811570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::512-639 77 4.97% 43.25% # Bytes accessed per row activation 19911570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::640-767 93 6.00% 49.26% # Bytes accessed per row activation 20011570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::768-895 42 2.71% 51.97% # Bytes accessed per row activation 20111570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::896-1023 43 2.78% 54.74% # Bytes accessed per row activation 20211570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::1024-1151 701 45.26% 100.00% # Bytes accessed per row activation 20311570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::total 1549 # Bytes accessed per row activation 20411570SCurtis.Dunham@arm.comsystem.physmem.totQLat 75120250 # Total ticks spent queuing 20511570SCurtis.Dunham@arm.comsystem.physmem.totMemAccLat 367132750 # Total ticks spent from burst creation until serviced by the DRAM 20611570SCurtis.Dunham@arm.comsystem.physmem.totBusLat 77870000 # Total ticks spent in databus transfers 20711570SCurtis.Dunham@arm.comsystem.physmem.avgQLat 4823.44 # Average queueing delay per DRAM burst 20811507SCurtis.Dunham@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20911570SCurtis.Dunham@arm.comsystem.physmem.avgMemAccLat 23573.44 # Average memory access latency per DRAM burst 21011570SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 15.97 # Average DRAM read bandwidth in MiByte/s 21111507SCurtis.Dunham@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21211570SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 15.97 # Average system read bandwidth in MiByte/s 21311507SCurtis.Dunham@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 21411507SCurtis.Dunham@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21511570SCurtis.Dunham@arm.comsystem.physmem.busUtil 0.12 # Data bus utilization in percentage 21611570SCurtis.Dunham@arm.comsystem.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads 21711507SCurtis.Dunham@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21811507SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 21911507SCurtis.Dunham@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 22011570SCurtis.Dunham@arm.comsystem.physmem.readRowHits 14020 # Number of row buffer hits during reads 22111507SCurtis.Dunham@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22211570SCurtis.Dunham@arm.comsystem.physmem.readRowHitRate 90.02 # Row buffer hit rate for reads 22311507SCurtis.Dunham@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22411570SCurtis.Dunham@arm.comsystem.physmem.avgGap 4007246.92 # Average gap between requests 22511570SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 90.02 # Row buffer hit rate, read and write combined 22611570SCurtis.Dunham@arm.comsystem.physmem_0.actEnergy 6395760 # Energy for activate commands per rank (pJ) 22711570SCurtis.Dunham@arm.comsystem.physmem_0.preEnergy 3489750 # Energy for precharge commands per rank (pJ) 22811570SCurtis.Dunham@arm.comsystem.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ) 22911507SCurtis.Dunham@arm.comsystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 23011570SCurtis.Dunham@arm.comsystem.physmem_0.refreshEnergy 4076108400 # Energy for refresh commands per rank (pJ) 23111570SCurtis.Dunham@arm.comsystem.physmem_0.actBackEnergy 2565881505 # Energy for active background per rank (pJ) 23211570SCurtis.Dunham@arm.comsystem.physmem_0.preBackEnergy 35193459000 # Energy for precharge background per rank (pJ) 23311570SCurtis.Dunham@arm.comsystem.physmem_0.totalEnergy 41909107215 # Total energy per rank (pJ) 23411570SCurtis.Dunham@arm.comsystem.physmem_0.averagePower 671.544396 # Core power per rank (mW) 23511570SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::IDLE 58537353750 # Time in different power states 23611570SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::REF 2083900000 # Time in different power states 23711507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 23811570SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT 1785901250 # Time in different power states 23911507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 24011507SCurtis.Dunham@arm.comsystem.physmem_1.actEnergy 5314680 # Energy for activate commands per rank (pJ) 24111507SCurtis.Dunham@arm.comsystem.physmem_1.preEnergy 2899875 # Energy for precharge commands per rank (pJ) 24211570SCurtis.Dunham@arm.comsystem.physmem_1.readEnergy 57509400 # Energy for read commands per rank (pJ) 24311507SCurtis.Dunham@arm.comsystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24411570SCurtis.Dunham@arm.comsystem.physmem_1.refreshEnergy 4076108400 # Energy for refresh commands per rank (pJ) 24511570SCurtis.Dunham@arm.comsystem.physmem_1.actBackEnergy 2571480045 # Energy for active background per rank (pJ) 24611570SCurtis.Dunham@arm.comsystem.physmem_1.preBackEnergy 35188548000 # Energy for precharge background per rank (pJ) 24711570SCurtis.Dunham@arm.comsystem.physmem_1.totalEnergy 41901860400 # Total energy per rank (pJ) 24811570SCurtis.Dunham@arm.comsystem.physmem_1.averagePower 671.428274 # Core power per rank (mW) 24911570SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::IDLE 58529558500 # Time in different power states 25011570SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::REF 2083900000 # Time in different power states 25111507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 25211570SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT 1793609000 # Time in different power states 25311507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 25411570SCurtis.Dunham@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 25511570SCurtis.Dunham@arm.comsystem.cpu.branchPred.lookups 20808236 # Number of BP lookups 25611570SCurtis.Dunham@arm.comsystem.cpu.branchPred.condPredicted 17115622 # Number of conditional branches predicted 25711507SCurtis.Dunham@arm.comsystem.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect 25811570SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBLookups 8965652 # Number of BTB lookups 25911570SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHits 8840815 # Number of BTB hits 26011507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 26111570SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHitPct 98.607608 # BTB Hit Percentage 26211570SCurtis.Dunham@arm.comsystem.cpu.branchPred.usedRAS 61995 # Number of times the RAS was used to get a target. 26311507SCurtis.Dunham@arm.comsystem.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. 26411570SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectLookups 26211 # Number of indirect predictor lookups. 26511507SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectHits 24795 # Number of indirect target hits. 26611570SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectMisses 1416 # Number of indirect misses. 26711507SCurtis.Dunham@arm.comsystem.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches. 26811507SCurtis.Dunham@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 26911570SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 27011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 27111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 27211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 27311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 27411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 27511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 27611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 27711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 27811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 27911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 28011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 28111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 28211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 28311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 28411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 28511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 28611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 28711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 28811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 28911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 29011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 29111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 29211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 29311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 29411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 29511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 29611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 29711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 29811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 29911570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 30011507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 30111507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 30211507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 30311507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 30411507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 30511507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 30611507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 30711507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 30811507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 30911507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 31011507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 31111507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 31211507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 31311507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 31411507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 31511507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 31611507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 31711507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 31811507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 31911507SCurtis.Dunham@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 32011507SCurtis.Dunham@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 32111507SCurtis.Dunham@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 32211507SCurtis.Dunham@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 32311507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 32411507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 32511507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 32611507SCurtis.Dunham@arm.comsystem.cpu.dtb.hits 0 # DTB hits 32711507SCurtis.Dunham@arm.comsystem.cpu.dtb.misses 0 # DTB misses 32811507SCurtis.Dunham@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 32911570SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 33011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 33111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 33211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 33311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 33411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 33511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 33611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 33711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 33811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 33911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 34011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 34111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 34211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 34311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 34411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 34511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 34611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 34711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 34811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 34911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 35011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 35111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 35211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 35311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 35411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 35511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 35611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 35711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 35811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 35911570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 36011507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 36111507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 36211507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 36311507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 36411507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 36511507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 36611507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 36711507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 36811507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 36911507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 37011507SCurtis.Dunham@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 37111507SCurtis.Dunham@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 37211507SCurtis.Dunham@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 37311507SCurtis.Dunham@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 37411507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 37511507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 37611507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 37711507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 37811507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 37911507SCurtis.Dunham@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 38011507SCurtis.Dunham@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 38111507SCurtis.Dunham@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 38211507SCurtis.Dunham@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 38311507SCurtis.Dunham@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 38411507SCurtis.Dunham@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 38511507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 38611507SCurtis.Dunham@arm.comsystem.cpu.itb.hits 0 # DTB hits 38711507SCurtis.Dunham@arm.comsystem.cpu.itb.misses 0 # DTB misses 38811507SCurtis.Dunham@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 38911507SCurtis.Dunham@arm.comsystem.cpu.workload.num_syscalls 442 # Number of system calls 39011570SCurtis.Dunham@arm.comsystem.cpu.pwrStateResidencyTicks::ON 62408957500 # Cumulative time (in ticks) in various power states 39111570SCurtis.Dunham@arm.comsystem.cpu.numCycles 124817915 # number of cpu cycles simulated 39211507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 39311507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 39411507SCurtis.Dunham@arm.comsystem.cpu.committedInsts 90602850 # Number of instructions committed 39511507SCurtis.Dunham@arm.comsystem.cpu.committedOps 91054081 # Number of ops (including micro ops) committed 39611570SCurtis.Dunham@arm.comsystem.cpu.discardedOps 2182474 # Number of ops (including micro ops) which were discarded before commit 39711507SCurtis.Dunham@arm.comsystem.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 39811570SCurtis.Dunham@arm.comsystem.cpu.cpi 1.377638 # CPI: cycles per instruction 39911570SCurtis.Dunham@arm.comsystem.cpu.ipc 0.725880 # IPC: instructions per cycle 40011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 40111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction 40211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction 40311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction 40411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction 40511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction 40611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction 40711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction 40811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction 40911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction 41011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction 41111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction 41211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction 41311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction 41411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction 41511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction 41611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction 41711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction 41811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction 41911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction 42011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction 42111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction 42211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction 42311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction 42411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction 42511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction 42611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction 42711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction 42811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction 42911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction 43011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction 43111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction 43211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 43311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 43411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::total 91054081 # Class of committed instruction 43511570SCurtis.Dunham@arm.comsystem.cpu.tickCycles 110516717 # Number of cycles that the object actually ticked 43611570SCurtis.Dunham@arm.comsystem.cpu.idleCycles 14301198 # Total number of cycles that the object has spent stopped 43711570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 43811570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.replacements 946101 # number of replacements 43911570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tagsinuse 3621.431844 # Cycle average of tags in use 44011570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.total_refs 26274920 # Total number of references to valid blocks. 44111570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.sampled_refs 950197 # Sample count of references to valid blocks. 44211570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.avg_refs 27.652076 # Average number of references to valid blocks. 44311570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.warmup_cycle 20702462500 # Cycle when the warmup percentage was hit. 44411570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 3621.431844 # Average occupied blocks per requestor 44511570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.884139 # Average percentage of cache occupancy 44611570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.884139 # Average percentage of cache occupancy 44711507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 44811570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 242 # Occupied blocks per task id 44911570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 2203 # Occupied blocks per task id 45011570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 1651 # Occupied blocks per task id 45111507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 45211570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tag_accesses 55461267 # Number of tag accesses 45311570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.data_accesses 55461267 # Number of data accesses 45411570SCurtis.Dunham@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 45511570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 21605941 # number of ReadReq hits 45611570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::total 21605941 # number of ReadReq hits 45711570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 4660697 # number of WriteReq hits 45811570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::total 4660697 # number of WriteReq hits 45911507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits 46011507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits 46111507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits 46211507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits 46311507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 46411507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits 46511570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::cpu.data 26266638 # number of demand (read+write) hits 46611570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::total 26266638 # number of demand (read+write) hits 46711570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::cpu.data 26267146 # number of overall hits 46811570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::total 26267146 # number of overall hits 46911570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 906327 # number of ReadReq misses 47011570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::total 906327 # number of ReadReq misses 47111570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 74284 # number of WriteReq misses 47211570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::total 74284 # number of WriteReq misses 47311507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses 47411507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses 47511570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::cpu.data 980611 # number of demand (read+write) misses 47611570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::total 980611 # number of demand (read+write) misses 47711570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::cpu.data 980615 # number of overall misses 47811570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::total 980615 # number of overall misses 47911570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 11805097500 # number of ReadReq miss cycles 48011570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 11805097500 # number of ReadReq miss cycles 48111570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 2540928500 # number of WriteReq miss cycles 48211570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 2540928500 # number of WriteReq miss cycles 48311570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 14346026000 # number of demand (read+write) miss cycles 48411570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::total 14346026000 # number of demand (read+write) miss cycles 48511570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 14346026000 # number of overall miss cycles 48611570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::total 14346026000 # number of overall miss cycles 48711570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 22512268 # number of ReadReq accesses(hits+misses) 48811570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::total 22512268 # number of ReadReq accesses(hits+misses) 48911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 49011507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 49111507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) 49211507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 512 # number of SoftPFReq accesses(hits+misses) 49311507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) 49411507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 49511507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 49611507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) 49711570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 27247249 # number of demand (read+write) accesses 49811570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::total 27247249 # number of demand (read+write) accesses 49911570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 27247761 # number of overall (read+write) accesses 50011570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::total 27247761 # number of overall (read+write) accesses 50111570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040259 # miss rate for ReadReq accesses 50211570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.040259 # miss rate for ReadReq accesses 50311570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015688 # miss rate for WriteReq accesses 50411570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.015688 # miss rate for WriteReq accesses 50511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses 50611507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses 50711570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.035989 # miss rate for demand accesses 50811570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.035989 # miss rate for demand accesses 50911570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.035989 # miss rate for overall accesses 51011570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.035989 # miss rate for overall accesses 51111570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13025.207789 # average ReadReq miss latency 51211570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 13025.207789 # average ReadReq miss latency 51311570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34205.596091 # average WriteReq miss latency 51411570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 34205.596091 # average WriteReq miss latency 51511570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 14629.680883 # average overall miss latency 51611570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 14629.680883 # average overall miss latency 51711570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 14629.621207 # average overall miss latency 51811570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 14629.621207 # average overall miss latency 51911507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 52011507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 52111507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 52211507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 52311507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 52411507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 52511570SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::writebacks 943282 # number of writebacks 52611570SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::total 943282 # number of writebacks 52711570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 2897 # number of ReadReq MSHR hits 52811570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 2897 # number of ReadReq MSHR hits 52911570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 27520 # number of WriteReq MSHR hits 53011570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 27520 # number of WriteReq MSHR hits 53111570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 30417 # number of demand (read+write) MSHR hits 53211570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::total 30417 # number of demand (read+write) MSHR hits 53311570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 30417 # number of overall MSHR hits 53411570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::total 30417 # number of overall MSHR hits 53511570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 903430 # number of ReadReq MSHR misses 53611570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 903430 # number of ReadReq MSHR misses 53711507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses 53811507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 46764 # number of WriteReq MSHR misses 53911507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses 54011507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses 54111570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 950194 # number of demand (read+write) MSHR misses 54211570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::total 950194 # number of demand (read+write) MSHR misses 54311570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 950197 # number of overall MSHR misses 54411570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::total 950197 # number of overall MSHR misses 54511570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10863020500 # number of ReadReq MSHR miss cycles 54611570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 10863020500 # number of ReadReq MSHR miss cycles 54711570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1482579500 # number of WriteReq MSHR miss cycles 54811570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 1482579500 # number of WriteReq MSHR miss cycles 54911570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156000 # number of SoftPFReq MSHR miss cycles 55011570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156000 # number of SoftPFReq MSHR miss cycles 55111570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 12345600000 # number of demand (read+write) MSHR miss cycles 55211570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 12345600000 # number of demand (read+write) MSHR miss cycles 55311570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 12345756000 # number of overall MSHR miss cycles 55411570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 12345756000 # number of overall MSHR miss cycles 55511570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040131 # mshr miss rate for ReadReq accesses 55611570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040131 # mshr miss rate for ReadReq accesses 55711507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses 55811507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses 55911507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses 56011507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses 56111570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034873 # mshr miss rate for demand accesses 56211570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.034873 # mshr miss rate for demand accesses 56311570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for overall accesses 56411570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses 56511570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12024.197226 # average ReadReq mshr miss latency 56611570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12024.197226 # average ReadReq mshr miss latency 56711570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31703.436404 # average WriteReq mshr miss latency 56811570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31703.436404 # average WriteReq mshr miss latency 56911570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52000 # average SoftPFReq mshr miss latency 57011570SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52000 # average SoftPFReq mshr miss latency 57111570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12992.715172 # average overall mshr miss latency 57211570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 12992.715172 # average overall mshr miss latency 57311570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12992.838327 # average overall mshr miss latency 57411570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 12992.838327 # average overall mshr miss latency 57511570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 57611507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.replacements 5 # number of replacements 57711570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tagsinuse 689.591924 # Cycle average of tags in use 57811570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.total_refs 27835291 # Total number of references to valid blocks. 57911507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks. 58011570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.avg_refs 34750.675406 # Average number of references to valid blocks. 58111507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 58211570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 689.591924 # Average occupied blocks per requestor 58311570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.336715 # Average percentage of cache occupancy 58411570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::total 0.336715 # Average percentage of cache occupancy 58511507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id 58611507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 58711507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id 58811507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 58911507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id 59011507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id 59111570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tag_accesses 55672985 # Number of tag accesses 59211570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.data_accesses 55672985 # Number of data accesses 59311570SCurtis.Dunham@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 59411570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 27835291 # number of ReadReq hits 59511570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::total 27835291 # number of ReadReq hits 59611570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::cpu.inst 27835291 # number of demand (read+write) hits 59711570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::total 27835291 # number of demand (read+write) hits 59811570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::cpu.inst 27835291 # number of overall hits 59911570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::total 27835291 # number of overall hits 60011507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 801 # number of ReadReq misses 60111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::total 801 # number of ReadReq misses 60211507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::cpu.inst 801 # number of demand (read+write) misses 60311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::total 801 # number of demand (read+write) misses 60411507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::cpu.inst 801 # number of overall misses 60511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::total 801 # number of overall misses 60611570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 60446000 # number of ReadReq miss cycles 60711570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 60446000 # number of ReadReq miss cycles 60811570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 60446000 # number of demand (read+write) miss cycles 60911570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::total 60446000 # number of demand (read+write) miss cycles 61011570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 60446000 # number of overall miss cycles 61111570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::total 60446000 # number of overall miss cycles 61211570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 27836092 # number of ReadReq accesses(hits+misses) 61311570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::total 27836092 # number of ReadReq accesses(hits+misses) 61411570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 27836092 # number of demand (read+write) accesses 61511570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::total 27836092 # number of demand (read+write) accesses 61611570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 27836092 # number of overall (read+write) accesses 61711570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::total 27836092 # number of overall (read+write) accesses 61811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses 61911507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses 62011507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses 62111507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses 62211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses 62311507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses 62411570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75463.171036 # average ReadReq miss latency 62511570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 75463.171036 # average ReadReq miss latency 62611570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 75463.171036 # average overall miss latency 62711570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 75463.171036 # average overall miss latency 62811570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 75463.171036 # average overall miss latency 62911570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 75463.171036 # average overall miss latency 63011507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 63111507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 63211507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 63311507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 63411507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 63511507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 63611507SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::writebacks 5 # number of writebacks 63711507SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::total 5 # number of writebacks 63811507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 801 # number of ReadReq MSHR misses 63911507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 801 # number of ReadReq MSHR misses 64011507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 801 # number of demand (read+write) MSHR misses 64111507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses 64211507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses 64311507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses 64411570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59645000 # number of ReadReq MSHR miss cycles 64511570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 59645000 # number of ReadReq MSHR miss cycles 64611570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 59645000 # number of demand (read+write) MSHR miss cycles 64711570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 59645000 # number of demand (read+write) MSHR miss cycles 64811570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 59645000 # number of overall MSHR miss cycles 64911570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 59645000 # number of overall MSHR miss cycles 65011507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses 65111507SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses 65211507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses 65311507SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses 65411507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses 65511507SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses 65611570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74463.171036 # average ReadReq mshr miss latency 65711570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74463.171036 # average ReadReq mshr miss latency 65811570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74463.171036 # average overall mshr miss latency 65911570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 74463.171036 # average overall mshr miss latency 66011570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74463.171036 # average overall mshr miss latency 66111570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 74463.171036 # average overall mshr miss latency 66211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 66311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 66411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tagsinuse 10294.680667 # Cycle average of tags in use 66511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.total_refs 1834001 # Total number of references to valid blocks. 66611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks. 66711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.avg_refs 117.889117 # Average number of references to valid blocks. 66811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 66911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 9404.439964 # Average occupied blocks per requestor 67011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 674.596313 # Average occupied blocks per requestor 67111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 215.644390 # Average occupied blocks per requestor 67211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.287001 # Average percentage of cache occupancy 67311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.020587 # Average percentage of cache occupancy 67411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.006581 # Average percentage of cache occupancy 67511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.314169 # Average percentage of cache occupancy 67611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id 67711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id 67811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id 67911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 524 # Occupied blocks per task id 68011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id 68111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 # Occupied blocks per task id 68211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id 68311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tag_accesses 15237953 # Number of tag accesses 68411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.data_accesses 15237953 # Number of data accesses 68511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 68611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 943282 # number of WritebackDirty hits 68711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 943282 # number of WritebackDirty hits 68811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits 68911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 4 # number of WritebackClean hits 69011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 32220 # number of ReadExReq hits 69111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 32220 # number of ReadExReq hits 69211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 27 # number of ReadCleanReq hits 69311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 27 # number of ReadCleanReq hits 69411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 903170 # number of ReadSharedReq hits 69511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 903170 # number of ReadSharedReq hits 69611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits 69711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 935390 # number of demand (read+write) hits 69811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::total 935417 # number of demand (read+write) hits 69911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits 70011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 935390 # number of overall hits 70111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::total 935417 # number of overall hits 70211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 14544 # number of ReadExReq misses 70311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses 70411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 774 # number of ReadCleanReq misses 70511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 774 # number of ReadCleanReq misses 70611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 263 # number of ReadSharedReq misses 70711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 263 # number of ReadSharedReq misses 70811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 774 # number of demand (read+write) misses 70911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 14807 # number of demand (read+write) misses 71011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::total 15581 # number of demand (read+write) misses 71111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 774 # number of overall misses 71211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 14807 # number of overall misses 71311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::total 15581 # number of overall misses 71411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1068633000 # number of ReadExReq miss cycles 71511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 1068633000 # number of ReadExReq miss cycles 71611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58136500 # number of ReadCleanReq miss cycles 71711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 58136500 # number of ReadCleanReq miss cycles 71811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22289000 # number of ReadSharedReq miss cycles 71911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 22289000 # number of ReadSharedReq miss cycles 72011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 58136500 # number of demand (read+write) miss cycles 72111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 1090922000 # number of demand (read+write) miss cycles 72211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::total 1149058500 # number of demand (read+write) miss cycles 72311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 58136500 # number of overall miss cycles 72411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 1090922000 # number of overall miss cycles 72511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::total 1149058500 # number of overall miss cycles 72611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 943282 # number of WritebackDirty accesses(hits+misses) 72711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 943282 # number of WritebackDirty accesses(hits+misses) 72811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses) 72911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 4 # number of WritebackClean accesses(hits+misses) 73011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 46764 # number of ReadExReq accesses(hits+misses) 73111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 46764 # number of ReadExReq accesses(hits+misses) 73211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 801 # number of ReadCleanReq accesses(hits+misses) 73311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 801 # number of ReadCleanReq accesses(hits+misses) 73411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 903433 # number of ReadSharedReq accesses(hits+misses) 73511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 903433 # number of ReadSharedReq accesses(hits+misses) 73611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 801 # number of demand (read+write) accesses 73711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 950197 # number of demand (read+write) accesses 73811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::total 950998 # number of demand (read+write) accesses 73911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 801 # number of overall (read+write) accesses 74011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 950197 # number of overall (read+write) accesses 74111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::total 950998 # number of overall (read+write) accesses 74211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311008 # miss rate for ReadExReq accesses 74311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.311008 # miss rate for ReadExReq accesses 74411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.966292 # miss rate for ReadCleanReq accesses 74511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.966292 # miss rate for ReadCleanReq accesses 74611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000291 # miss rate for ReadSharedReq accesses 74711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000291 # miss rate for ReadSharedReq accesses 74811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.966292 # miss rate for demand accesses 74911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.015583 # miss rate for demand accesses 75011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.016384 # miss rate for demand accesses 75111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.966292 # miss rate for overall accesses 75211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.015583 # miss rate for overall accesses 75311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.016384 # miss rate for overall accesses 75411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73475.866337 # average ReadExReq miss latency 75511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 73475.866337 # average ReadExReq miss latency 75611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75111.757106 # average ReadCleanReq miss latency 75711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75111.757106 # average ReadCleanReq miss latency 75811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84749.049430 # average ReadSharedReq miss latency 75911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84749.049430 # average ReadSharedReq miss latency 76011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75111.757106 # average overall miss latency 76111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 73676.099142 # average overall miss latency 76211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 73747.416725 # average overall miss latency 76311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75111.757106 # average overall miss latency 76411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 73676.099142 # average overall miss latency 76511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 73747.416725 # average overall miss latency 76611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 76711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 76811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 76911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 77011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 77111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 77211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 77311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 77411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits 77511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits 77611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 77711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits 77811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits 77911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 78011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits 78111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits 78211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14544 # number of ReadExReq MSHR misses 78311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses 78411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 773 # number of ReadCleanReq MSHR misses 78511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 773 # number of ReadCleanReq MSHR misses 78611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 257 # number of ReadSharedReq MSHR misses 78711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 257 # number of ReadSharedReq MSHR misses 78811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 773 # number of demand (read+write) MSHR misses 78911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 14801 # number of demand (read+write) MSHR misses 79011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 15574 # number of demand (read+write) MSHR misses 79111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses 79211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 14801 # number of overall MSHR misses 79311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses 79411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 923193000 # number of ReadExReq MSHR miss cycles 79511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 923193000 # number of ReadExReq MSHR miss cycles 79611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 50340000 # number of ReadCleanReq MSHR miss cycles 79711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 50340000 # number of ReadCleanReq MSHR miss cycles 79811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19328000 # number of ReadSharedReq MSHR miss cycles 79911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19328000 # number of ReadSharedReq MSHR miss cycles 80011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50340000 # number of demand (read+write) MSHR miss cycles 80111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 942521000 # number of demand (read+write) MSHR miss cycles 80211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 992861000 # number of demand (read+write) MSHR miss cycles 80311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50340000 # number of overall MSHR miss cycles 80411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 942521000 # number of overall MSHR miss cycles 80511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 992861000 # number of overall MSHR miss cycles 80611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses 80711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses 80811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for ReadCleanReq accesses 80911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965044 # mshr miss rate for ReadCleanReq accesses 81011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000284 # mshr miss rate for ReadSharedReq accesses 81111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000284 # mshr miss rate for ReadSharedReq accesses 81211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for demand accesses 81311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for demand accesses 81411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.016376 # mshr miss rate for demand accesses 81511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for overall accesses 81611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for overall accesses 81711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.016376 # mshr miss rate for overall accesses 81811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63475.866337 # average ReadExReq mshr miss latency 81911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63475.866337 # average ReadExReq mshr miss latency 82011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65122.897801 # average ReadCleanReq mshr miss latency 82111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65122.897801 # average ReadCleanReq mshr miss latency 82211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75206.225681 # average ReadSharedReq mshr miss latency 82311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75206.225681 # average ReadSharedReq mshr miss latency 82411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65122.897801 # average overall mshr miss latency 82511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63679.548679 # average overall mshr miss latency 82611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 63751.187877 # average overall mshr miss latency 82711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65122.897801 # average overall mshr miss latency 82811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63679.548679 # average overall mshr miss latency 82911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 63751.187877 # average overall mshr miss latency 83011570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 1897104 # Total number of requests made to the snoop filter. 83111570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 946122 # Number of requests hitting in the snoop filter with a single holder of the requested data. 83211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 83311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 83411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 83511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 83611570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 83711570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 904234 # Transaction distribution 83811570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 943282 # Transaction distribution 83911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution 84011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 2819 # Transaction distribution 84111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution 84211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution 84311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 801 # Transaction distribution 84411570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 903433 # Transaction distribution 84511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1607 # Packet count per connected master and slave (bytes) 84611570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846495 # Packet count per connected master and slave (bytes) 84711570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count::total 2848102 # Packet count per connected master and slave (bytes) 84811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51584 # Cumulative packet size per connected master and slave (bytes) 84911570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182656 # Cumulative packet size per connected master and slave (bytes) 85011570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size::total 121234240 # Cumulative packet size per connected master and slave (bytes) 85111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 85211570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 85311570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 950998 # Request fanout histogram 85411507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.000175 # Request fanout histogram 85511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.013211 # Request fanout histogram 85611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 85711570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 950832 99.98% 99.98% # Request fanout histogram 85811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 166 0.02% 100.00% # Request fanout histogram 85911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 86011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 86111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 86211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 86311570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 950998 # Request fanout histogram 86411570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 1891839000 # Layer occupancy (ticks) 86511570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 3.0 # Layer utilization (%) 86611570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 1201999 # Layer occupancy (ticks) 86711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 86811570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 1425298494 # Layer occupancy (ticks) 86911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) 87011570SCurtis.Dunham@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 87111570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 1030 # Transaction distribution 87211507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 14544 # Transaction distribution 87311507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 14544 # Transaction distribution 87411570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 1030 # Transaction distribution 87511570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31148 # Packet count per connected master and slave (bytes) 87611570SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 31148 # Packet count per connected master and slave (bytes) 87711570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes) 87811570SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes) 87911507SCurtis.Dunham@arm.comsystem.membus.snoops 0 # Total snoops (count) 88011570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 88111570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 15574 # Request fanout histogram 88211507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 88311507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 88411507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 88511570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 15574 100.00% 100.00% # Request fanout histogram 88611507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 88711507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 88811507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 88911507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 89011570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 15574 # Request fanout histogram 89111570SCurtis.Dunham@arm.comsystem.membus.reqLayer0.occupancy 21833000 # Layer occupancy (ticks) 89211507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 89311570SCurtis.Dunham@arm.comsystem.membus.respLayer1.occupancy 82137750 # Layer occupancy (ticks) 89411507SCurtis.Dunham@arm.comsystem.membus.respLayer1.utilization 0.1 # Layer utilization (%) 89511507SCurtis.Dunham@arm.com 89611507SCurtis.Dunham@arm.com---------- End Simulation Statistics ---------- 897