stats.txt revision 11570
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.062409 # Number of seconds simulated 4sim_ticks 62408957500 # Number of ticks simulated 5final_tick 62408957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 176281 # Simulator instruction rate (inst/s) 8host_op_rate 177159 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 121425676 # Simulator tick rate (ticks/s) 10host_mem_usage 399932 # Number of bytes of host memory used 11host_seconds 513.97 # Real time elapsed on the host 12sim_insts 90602850 # Number of instructions simulated 13sim_ops 91054081 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 947264 # Number of bytes read from this memory 19system.physmem.bytes_read::total 996736 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 49472 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 49472 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 14801 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 792707 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 15178334 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 15971041 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 792707 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 792707 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 792707 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 15178334 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 15971041 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 15574 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 996736 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 996736 # Total read bytes from the system interface side 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 45system.physmem.perBankRdBursts::0 993 # Per bank write bursts 46system.physmem.perBankRdBursts::1 891 # Per bank write bursts 47system.physmem.perBankRdBursts::2 949 # Per bank write bursts 48system.physmem.perBankRdBursts::3 1027 # Per bank write bursts 49system.physmem.perBankRdBursts::4 1050 # Per bank write bursts 50system.physmem.perBankRdBursts::5 1113 # Per bank write bursts 51system.physmem.perBankRdBursts::6 1087 # Per bank write bursts 52system.physmem.perBankRdBursts::7 1088 # Per bank write bursts 53system.physmem.perBankRdBursts::8 1024 # Per bank write bursts 54system.physmem.perBankRdBursts::9 962 # Per bank write bursts 55system.physmem.perBankRdBursts::10 938 # Per bank write bursts 56system.physmem.perBankRdBursts::11 899 # Per bank write bursts 57system.physmem.perBankRdBursts::12 904 # Per bank write bursts 58system.physmem.perBankRdBursts::13 867 # Per bank write bursts 59system.physmem.perBankRdBursts::14 876 # Per bank write bursts 60system.physmem.perBankRdBursts::15 906 # Per bank write bursts 61system.physmem.perBankWrBursts::0 0 # Per bank write bursts 62system.physmem.perBankWrBursts::1 0 # Per bank write bursts 63system.physmem.perBankWrBursts::2 0 # Per bank write bursts 64system.physmem.perBankWrBursts::3 0 # Per bank write bursts 65system.physmem.perBankWrBursts::4 0 # Per bank write bursts 66system.physmem.perBankWrBursts::5 0 # Per bank write bursts 67system.physmem.perBankWrBursts::6 0 # Per bank write bursts 68system.physmem.perBankWrBursts::7 0 # Per bank write bursts 69system.physmem.perBankWrBursts::8 0 # Per bank write bursts 70system.physmem.perBankWrBursts::9 0 # Per bank write bursts 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 79system.physmem.totGap 62408863500 # Total gap between requests 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 15574 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) 94system.physmem.rdQLenPdf::0 15459 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::1 109 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 6 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 126system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 190system.physmem.bytesPerActivate::samples 1549 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 642.437702 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 437.017774 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 401.182344 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 251 16.20% 16.20% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 185 11.94% 28.15% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 90 5.81% 33.96% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 67 4.33% 38.28% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 77 4.97% 43.25% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 93 6.00% 49.26% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 42 2.71% 51.97% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 43 2.78% 54.74% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 701 45.26% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 1549 # Bytes accessed per row activation 204system.physmem.totQLat 75120250 # Total ticks spent queuing 205system.physmem.totMemAccLat 367132750 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 4823.44 # Average queueing delay per DRAM burst 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 209system.physmem.avgMemAccLat 23573.44 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 15.97 # Average DRAM read bandwidth in MiByte/s 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 212system.physmem.avgRdBWSys 15.97 # Average system read bandwidth in MiByte/s 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 0.12 # Data bus utilization in percentage 216system.physmem.busUtilRead 0.12 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 220system.physmem.readRowHits 14020 # Number of row buffer hits during reads 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes 222system.physmem.readRowHitRate 90.02 # Row buffer hit rate for reads 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 224system.physmem.avgGap 4007246.92 # Average gap between requests 225system.physmem.pageHitRate 90.02 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 6395760 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 3489750 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 63772800 # Energy for read commands per rank (pJ) 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 4076108400 # Energy for refresh commands per rank (pJ) 231system.physmem_0.actBackEnergy 2565881505 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 35193459000 # Energy for precharge background per rank (pJ) 233system.physmem_0.totalEnergy 41909107215 # Total energy per rank (pJ) 234system.physmem_0.averagePower 671.544396 # Core power per rank (mW) 235system.physmem_0.memoryStateTime::IDLE 58537353750 # Time in different power states 236system.physmem_0.memoryStateTime::REF 2083900000 # Time in different power states 237system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 238system.physmem_0.memoryStateTime::ACT 1785901250 # Time in different power states 239system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 240system.physmem_1.actEnergy 5314680 # Energy for activate commands per rank (pJ) 241system.physmem_1.preEnergy 2899875 # Energy for precharge commands per rank (pJ) 242system.physmem_1.readEnergy 57509400 # Energy for read commands per rank (pJ) 243system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 244system.physmem_1.refreshEnergy 4076108400 # Energy for refresh commands per rank (pJ) 245system.physmem_1.actBackEnergy 2571480045 # Energy for active background per rank (pJ) 246system.physmem_1.preBackEnergy 35188548000 # Energy for precharge background per rank (pJ) 247system.physmem_1.totalEnergy 41901860400 # Total energy per rank (pJ) 248system.physmem_1.averagePower 671.428274 # Core power per rank (mW) 249system.physmem_1.memoryStateTime::IDLE 58529558500 # Time in different power states 250system.physmem_1.memoryStateTime::REF 2083900000 # Time in different power states 251system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 252system.physmem_1.memoryStateTime::ACT 1793609000 # Time in different power states 253system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 254system.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 255system.cpu.branchPred.lookups 20808236 # Number of BP lookups 256system.cpu.branchPred.condPredicted 17115622 # Number of conditional branches predicted 257system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect 258system.cpu.branchPred.BTBLookups 8965652 # Number of BTB lookups 259system.cpu.branchPred.BTBHits 8840815 # Number of BTB hits 260system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 261system.cpu.branchPred.BTBHitPct 98.607608 # BTB Hit Percentage 262system.cpu.branchPred.usedRAS 61995 # Number of times the RAS was used to get a target. 263system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. 264system.cpu.branchPred.indirectLookups 26211 # Number of indirect predictor lookups. 265system.cpu.branchPred.indirectHits 24795 # Number of indirect target hits. 266system.cpu.branchPred.indirectMisses 1416 # Number of indirect misses. 267system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches. 268system.cpu_clk_domain.clock 500 # Clock period in ticks 269system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 270system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 278system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 279system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 280system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 281system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 282system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 283system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 284system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 285system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 286system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 287system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 288system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 289system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 290system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 291system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 292system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 293system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 294system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 295system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 296system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 297system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 298system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 299system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 300system.cpu.dtb.walker.walks 0 # Table walker walks requested 301system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 302system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 303system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 305system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 306system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 307system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 308system.cpu.dtb.inst_hits 0 # ITB inst hits 309system.cpu.dtb.inst_misses 0 # ITB inst misses 310system.cpu.dtb.read_hits 0 # DTB read hits 311system.cpu.dtb.read_misses 0 # DTB read misses 312system.cpu.dtb.write_hits 0 # DTB write hits 313system.cpu.dtb.write_misses 0 # DTB write misses 314system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 315system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 316system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 317system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 318system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 319system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 320system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 321system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 322system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 323system.cpu.dtb.read_accesses 0 # DTB read accesses 324system.cpu.dtb.write_accesses 0 # DTB write accesses 325system.cpu.dtb.inst_accesses 0 # ITB inst accesses 326system.cpu.dtb.hits 0 # DTB hits 327system.cpu.dtb.misses 0 # DTB misses 328system.cpu.dtb.accesses 0 # DTB accesses 329system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 330system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 333system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 334system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 337system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 338system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 339system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 340system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 341system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 342system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 343system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 344system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 345system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 346system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 347system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 348system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 349system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 350system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 351system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 352system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 353system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 354system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 355system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 356system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 357system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 358system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 359system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 360system.cpu.itb.walker.walks 0 # Table walker walks requested 361system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 362system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 363system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 364system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 365system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 366system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 367system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 368system.cpu.itb.inst_hits 0 # ITB inst hits 369system.cpu.itb.inst_misses 0 # ITB inst misses 370system.cpu.itb.read_hits 0 # DTB read hits 371system.cpu.itb.read_misses 0 # DTB read misses 372system.cpu.itb.write_hits 0 # DTB write hits 373system.cpu.itb.write_misses 0 # DTB write misses 374system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 375system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 376system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 377system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 378system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 379system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 380system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 381system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 382system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 383system.cpu.itb.read_accesses 0 # DTB read accesses 384system.cpu.itb.write_accesses 0 # DTB write accesses 385system.cpu.itb.inst_accesses 0 # ITB inst accesses 386system.cpu.itb.hits 0 # DTB hits 387system.cpu.itb.misses 0 # DTB misses 388system.cpu.itb.accesses 0 # DTB accesses 389system.cpu.workload.num_syscalls 442 # Number of system calls 390system.cpu.pwrStateResidencyTicks::ON 62408957500 # Cumulative time (in ticks) in various power states 391system.cpu.numCycles 124817915 # number of cpu cycles simulated 392system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 393system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 394system.cpu.committedInsts 90602850 # Number of instructions committed 395system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed 396system.cpu.discardedOps 2182474 # Number of ops (including micro ops) which were discarded before commit 397system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 398system.cpu.cpi 1.377638 # CPI: cycles per instruction 399system.cpu.ipc 0.725880 # IPC: instructions per cycle 400system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 401system.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction 402system.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction 403system.cpu.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction 404system.cpu.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction 405system.cpu.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction 406system.cpu.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction 407system.cpu.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction 408system.cpu.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction 409system.cpu.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction 410system.cpu.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction 411system.cpu.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction 412system.cpu.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction 413system.cpu.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction 414system.cpu.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction 415system.cpu.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction 416system.cpu.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction 417system.cpu.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction 418system.cpu.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction 419system.cpu.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction 420system.cpu.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction 421system.cpu.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction 422system.cpu.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction 423system.cpu.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction 424system.cpu.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction 425system.cpu.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction 426system.cpu.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction 427system.cpu.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction 428system.cpu.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction 429system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction 430system.cpu.op_class_0::MemRead 22475911 24.68% 94.79% # Class of committed instruction 431system.cpu.op_class_0::MemWrite 4744844 5.21% 100.00% # Class of committed instruction 432system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 433system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 434system.cpu.op_class_0::total 91054081 # Class of committed instruction 435system.cpu.tickCycles 110516717 # Number of cycles that the object actually ticked 436system.cpu.idleCycles 14301198 # Total number of cycles that the object has spent stopped 437system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 438system.cpu.dcache.tags.replacements 946101 # number of replacements 439system.cpu.dcache.tags.tagsinuse 3621.431844 # Cycle average of tags in use 440system.cpu.dcache.tags.total_refs 26274920 # Total number of references to valid blocks. 441system.cpu.dcache.tags.sampled_refs 950197 # Sample count of references to valid blocks. 442system.cpu.dcache.tags.avg_refs 27.652076 # Average number of references to valid blocks. 443system.cpu.dcache.tags.warmup_cycle 20702462500 # Cycle when the warmup percentage was hit. 444system.cpu.dcache.tags.occ_blocks::cpu.data 3621.431844 # Average occupied blocks per requestor 445system.cpu.dcache.tags.occ_percent::cpu.data 0.884139 # Average percentage of cache occupancy 446system.cpu.dcache.tags.occ_percent::total 0.884139 # Average percentage of cache occupancy 447system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 448system.cpu.dcache.tags.age_task_id_blocks_1024::0 242 # Occupied blocks per task id 449system.cpu.dcache.tags.age_task_id_blocks_1024::1 2203 # Occupied blocks per task id 450system.cpu.dcache.tags.age_task_id_blocks_1024::2 1651 # Occupied blocks per task id 451system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 452system.cpu.dcache.tags.tag_accesses 55461267 # Number of tag accesses 453system.cpu.dcache.tags.data_accesses 55461267 # Number of data accesses 454system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 455system.cpu.dcache.ReadReq_hits::cpu.data 21605941 # number of ReadReq hits 456system.cpu.dcache.ReadReq_hits::total 21605941 # number of ReadReq hits 457system.cpu.dcache.WriteReq_hits::cpu.data 4660697 # number of WriteReq hits 458system.cpu.dcache.WriteReq_hits::total 4660697 # number of WriteReq hits 459system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits 460system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits 461system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits 462system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits 463system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits 464system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits 465system.cpu.dcache.demand_hits::cpu.data 26266638 # number of demand (read+write) hits 466system.cpu.dcache.demand_hits::total 26266638 # number of demand (read+write) hits 467system.cpu.dcache.overall_hits::cpu.data 26267146 # number of overall hits 468system.cpu.dcache.overall_hits::total 26267146 # number of overall hits 469system.cpu.dcache.ReadReq_misses::cpu.data 906327 # number of ReadReq misses 470system.cpu.dcache.ReadReq_misses::total 906327 # number of ReadReq misses 471system.cpu.dcache.WriteReq_misses::cpu.data 74284 # number of WriteReq misses 472system.cpu.dcache.WriteReq_misses::total 74284 # number of WriteReq misses 473system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses 474system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses 475system.cpu.dcache.demand_misses::cpu.data 980611 # number of demand (read+write) misses 476system.cpu.dcache.demand_misses::total 980611 # number of demand (read+write) misses 477system.cpu.dcache.overall_misses::cpu.data 980615 # number of overall misses 478system.cpu.dcache.overall_misses::total 980615 # number of overall misses 479system.cpu.dcache.ReadReq_miss_latency::cpu.data 11805097500 # number of ReadReq miss cycles 480system.cpu.dcache.ReadReq_miss_latency::total 11805097500 # number of ReadReq miss cycles 481system.cpu.dcache.WriteReq_miss_latency::cpu.data 2540928500 # number of WriteReq miss cycles 482system.cpu.dcache.WriteReq_miss_latency::total 2540928500 # number of WriteReq miss cycles 483system.cpu.dcache.demand_miss_latency::cpu.data 14346026000 # number of demand (read+write) miss cycles 484system.cpu.dcache.demand_miss_latency::total 14346026000 # number of demand (read+write) miss cycles 485system.cpu.dcache.overall_miss_latency::cpu.data 14346026000 # number of overall miss cycles 486system.cpu.dcache.overall_miss_latency::total 14346026000 # number of overall miss cycles 487system.cpu.dcache.ReadReq_accesses::cpu.data 22512268 # number of ReadReq accesses(hits+misses) 488system.cpu.dcache.ReadReq_accesses::total 22512268 # number of ReadReq accesses(hits+misses) 489system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) 490system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) 491system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) 492system.cpu.dcache.SoftPFReq_accesses::total 512 # number of SoftPFReq accesses(hits+misses) 493system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) 494system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) 495system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) 496system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) 497system.cpu.dcache.demand_accesses::cpu.data 27247249 # number of demand (read+write) accesses 498system.cpu.dcache.demand_accesses::total 27247249 # number of demand (read+write) accesses 499system.cpu.dcache.overall_accesses::cpu.data 27247761 # number of overall (read+write) accesses 500system.cpu.dcache.overall_accesses::total 27247761 # number of overall (read+write) accesses 501system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040259 # miss rate for ReadReq accesses 502system.cpu.dcache.ReadReq_miss_rate::total 0.040259 # miss rate for ReadReq accesses 503system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015688 # miss rate for WriteReq accesses 504system.cpu.dcache.WriteReq_miss_rate::total 0.015688 # miss rate for WriteReq accesses 505system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.007812 # miss rate for SoftPFReq accesses 506system.cpu.dcache.SoftPFReq_miss_rate::total 0.007812 # miss rate for SoftPFReq accesses 507system.cpu.dcache.demand_miss_rate::cpu.data 0.035989 # miss rate for demand accesses 508system.cpu.dcache.demand_miss_rate::total 0.035989 # miss rate for demand accesses 509system.cpu.dcache.overall_miss_rate::cpu.data 0.035989 # miss rate for overall accesses 510system.cpu.dcache.overall_miss_rate::total 0.035989 # miss rate for overall accesses 511system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13025.207789 # average ReadReq miss latency 512system.cpu.dcache.ReadReq_avg_miss_latency::total 13025.207789 # average ReadReq miss latency 513system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34205.596091 # average WriteReq miss latency 514system.cpu.dcache.WriteReq_avg_miss_latency::total 34205.596091 # average WriteReq miss latency 515system.cpu.dcache.demand_avg_miss_latency::cpu.data 14629.680883 # average overall miss latency 516system.cpu.dcache.demand_avg_miss_latency::total 14629.680883 # average overall miss latency 517system.cpu.dcache.overall_avg_miss_latency::cpu.data 14629.621207 # average overall miss latency 518system.cpu.dcache.overall_avg_miss_latency::total 14629.621207 # average overall miss latency 519system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 520system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 521system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 522system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 523system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 524system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 525system.cpu.dcache.writebacks::writebacks 943282 # number of writebacks 526system.cpu.dcache.writebacks::total 943282 # number of writebacks 527system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2897 # number of ReadReq MSHR hits 528system.cpu.dcache.ReadReq_mshr_hits::total 2897 # number of ReadReq MSHR hits 529system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27520 # number of WriteReq MSHR hits 530system.cpu.dcache.WriteReq_mshr_hits::total 27520 # number of WriteReq MSHR hits 531system.cpu.dcache.demand_mshr_hits::cpu.data 30417 # number of demand (read+write) MSHR hits 532system.cpu.dcache.demand_mshr_hits::total 30417 # number of demand (read+write) MSHR hits 533system.cpu.dcache.overall_mshr_hits::cpu.data 30417 # number of overall MSHR hits 534system.cpu.dcache.overall_mshr_hits::total 30417 # number of overall MSHR hits 535system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903430 # number of ReadReq MSHR misses 536system.cpu.dcache.ReadReq_mshr_misses::total 903430 # number of ReadReq MSHR misses 537system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses 538system.cpu.dcache.WriteReq_mshr_misses::total 46764 # number of WriteReq MSHR misses 539system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses 540system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses 541system.cpu.dcache.demand_mshr_misses::cpu.data 950194 # number of demand (read+write) MSHR misses 542system.cpu.dcache.demand_mshr_misses::total 950194 # number of demand (read+write) MSHR misses 543system.cpu.dcache.overall_mshr_misses::cpu.data 950197 # number of overall MSHR misses 544system.cpu.dcache.overall_mshr_misses::total 950197 # number of overall MSHR misses 545system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10863020500 # number of ReadReq MSHR miss cycles 546system.cpu.dcache.ReadReq_mshr_miss_latency::total 10863020500 # number of ReadReq MSHR miss cycles 547system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1482579500 # number of WriteReq MSHR miss cycles 548system.cpu.dcache.WriteReq_mshr_miss_latency::total 1482579500 # number of WriteReq MSHR miss cycles 549system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 156000 # number of SoftPFReq MSHR miss cycles 550system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 156000 # number of SoftPFReq MSHR miss cycles 551system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12345600000 # number of demand (read+write) MSHR miss cycles 552system.cpu.dcache.demand_mshr_miss_latency::total 12345600000 # number of demand (read+write) MSHR miss cycles 553system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12345756000 # number of overall MSHR miss cycles 554system.cpu.dcache.overall_mshr_miss_latency::total 12345756000 # number of overall MSHR miss cycles 555system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040131 # mshr miss rate for ReadReq accesses 556system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040131 # mshr miss rate for ReadReq accesses 557system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses 558system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009876 # mshr miss rate for WriteReq accesses 559system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 # mshr miss rate for SoftPFReq accesses 560system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses 561system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034873 # mshr miss rate for demand accesses 562system.cpu.dcache.demand_mshr_miss_rate::total 0.034873 # mshr miss rate for demand accesses 563system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for overall accesses 564system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses 565system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12024.197226 # average ReadReq mshr miss latency 566system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12024.197226 # average ReadReq mshr miss latency 567system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31703.436404 # average WriteReq mshr miss latency 568system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31703.436404 # average WriteReq mshr miss latency 569system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 52000 # average SoftPFReq mshr miss latency 570system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 52000 # average SoftPFReq mshr miss latency 571system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12992.715172 # average overall mshr miss latency 572system.cpu.dcache.demand_avg_mshr_miss_latency::total 12992.715172 # average overall mshr miss latency 573system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12992.838327 # average overall mshr miss latency 574system.cpu.dcache.overall_avg_mshr_miss_latency::total 12992.838327 # average overall mshr miss latency 575system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 576system.cpu.icache.tags.replacements 5 # number of replacements 577system.cpu.icache.tags.tagsinuse 689.591924 # Cycle average of tags in use 578system.cpu.icache.tags.total_refs 27835291 # Total number of references to valid blocks. 579system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks. 580system.cpu.icache.tags.avg_refs 34750.675406 # Average number of references to valid blocks. 581system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 582system.cpu.icache.tags.occ_blocks::cpu.inst 689.591924 # Average occupied blocks per requestor 583system.cpu.icache.tags.occ_percent::cpu.inst 0.336715 # Average percentage of cache occupancy 584system.cpu.icache.tags.occ_percent::total 0.336715 # Average percentage of cache occupancy 585system.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id 586system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 587system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id 588system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 589system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id 590system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id 591system.cpu.icache.tags.tag_accesses 55672985 # Number of tag accesses 592system.cpu.icache.tags.data_accesses 55672985 # Number of data accesses 593system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 594system.cpu.icache.ReadReq_hits::cpu.inst 27835291 # number of ReadReq hits 595system.cpu.icache.ReadReq_hits::total 27835291 # number of ReadReq hits 596system.cpu.icache.demand_hits::cpu.inst 27835291 # number of demand (read+write) hits 597system.cpu.icache.demand_hits::total 27835291 # number of demand (read+write) hits 598system.cpu.icache.overall_hits::cpu.inst 27835291 # number of overall hits 599system.cpu.icache.overall_hits::total 27835291 # number of overall hits 600system.cpu.icache.ReadReq_misses::cpu.inst 801 # number of ReadReq misses 601system.cpu.icache.ReadReq_misses::total 801 # number of ReadReq misses 602system.cpu.icache.demand_misses::cpu.inst 801 # number of demand (read+write) misses 603system.cpu.icache.demand_misses::total 801 # number of demand (read+write) misses 604system.cpu.icache.overall_misses::cpu.inst 801 # number of overall misses 605system.cpu.icache.overall_misses::total 801 # number of overall misses 606system.cpu.icache.ReadReq_miss_latency::cpu.inst 60446000 # number of ReadReq miss cycles 607system.cpu.icache.ReadReq_miss_latency::total 60446000 # number of ReadReq miss cycles 608system.cpu.icache.demand_miss_latency::cpu.inst 60446000 # number of demand (read+write) miss cycles 609system.cpu.icache.demand_miss_latency::total 60446000 # number of demand (read+write) miss cycles 610system.cpu.icache.overall_miss_latency::cpu.inst 60446000 # number of overall miss cycles 611system.cpu.icache.overall_miss_latency::total 60446000 # number of overall miss cycles 612system.cpu.icache.ReadReq_accesses::cpu.inst 27836092 # number of ReadReq accesses(hits+misses) 613system.cpu.icache.ReadReq_accesses::total 27836092 # number of ReadReq accesses(hits+misses) 614system.cpu.icache.demand_accesses::cpu.inst 27836092 # number of demand (read+write) accesses 615system.cpu.icache.demand_accesses::total 27836092 # number of demand (read+write) accesses 616system.cpu.icache.overall_accesses::cpu.inst 27836092 # number of overall (read+write) accesses 617system.cpu.icache.overall_accesses::total 27836092 # number of overall (read+write) accesses 618system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses 619system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses 620system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses 621system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses 622system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses 623system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses 624system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75463.171036 # average ReadReq miss latency 625system.cpu.icache.ReadReq_avg_miss_latency::total 75463.171036 # average ReadReq miss latency 626system.cpu.icache.demand_avg_miss_latency::cpu.inst 75463.171036 # average overall miss latency 627system.cpu.icache.demand_avg_miss_latency::total 75463.171036 # average overall miss latency 628system.cpu.icache.overall_avg_miss_latency::cpu.inst 75463.171036 # average overall miss latency 629system.cpu.icache.overall_avg_miss_latency::total 75463.171036 # average overall miss latency 630system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 631system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 632system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 633system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 634system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 635system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 636system.cpu.icache.writebacks::writebacks 5 # number of writebacks 637system.cpu.icache.writebacks::total 5 # number of writebacks 638system.cpu.icache.ReadReq_mshr_misses::cpu.inst 801 # number of ReadReq MSHR misses 639system.cpu.icache.ReadReq_mshr_misses::total 801 # number of ReadReq MSHR misses 640system.cpu.icache.demand_mshr_misses::cpu.inst 801 # number of demand (read+write) MSHR misses 641system.cpu.icache.demand_mshr_misses::total 801 # number of demand (read+write) MSHR misses 642system.cpu.icache.overall_mshr_misses::cpu.inst 801 # number of overall MSHR misses 643system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses 644system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59645000 # number of ReadReq MSHR miss cycles 645system.cpu.icache.ReadReq_mshr_miss_latency::total 59645000 # number of ReadReq MSHR miss cycles 646system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59645000 # number of demand (read+write) MSHR miss cycles 647system.cpu.icache.demand_mshr_miss_latency::total 59645000 # number of demand (read+write) MSHR miss cycles 648system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59645000 # number of overall MSHR miss cycles 649system.cpu.icache.overall_mshr_miss_latency::total 59645000 # number of overall MSHR miss cycles 650system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses 651system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses 652system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses 653system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses 654system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses 655system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses 656system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74463.171036 # average ReadReq mshr miss latency 657system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74463.171036 # average ReadReq mshr miss latency 658system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74463.171036 # average overall mshr miss latency 659system.cpu.icache.demand_avg_mshr_miss_latency::total 74463.171036 # average overall mshr miss latency 660system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74463.171036 # average overall mshr miss latency 661system.cpu.icache.overall_avg_mshr_miss_latency::total 74463.171036 # average overall mshr miss latency 662system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 663system.cpu.l2cache.tags.replacements 0 # number of replacements 664system.cpu.l2cache.tags.tagsinuse 10294.680667 # Cycle average of tags in use 665system.cpu.l2cache.tags.total_refs 1834001 # Total number of references to valid blocks. 666system.cpu.l2cache.tags.sampled_refs 15557 # Sample count of references to valid blocks. 667system.cpu.l2cache.tags.avg_refs 117.889117 # Average number of references to valid blocks. 668system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 669system.cpu.l2cache.tags.occ_blocks::writebacks 9404.439964 # Average occupied blocks per requestor 670system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.596313 # Average occupied blocks per requestor 671system.cpu.l2cache.tags.occ_blocks::cpu.data 215.644390 # Average occupied blocks per requestor 672system.cpu.l2cache.tags.occ_percent::writebacks 0.287001 # Average percentage of cache occupancy 673system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020587 # Average percentage of cache occupancy 674system.cpu.l2cache.tags.occ_percent::cpu.data 0.006581 # Average percentage of cache occupancy 675system.cpu.l2cache.tags.occ_percent::total 0.314169 # Average percentage of cache occupancy 676system.cpu.l2cache.tags.occ_task_id_blocks::1024 15557 # Occupied blocks per task id 677system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id 678system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id 679system.cpu.l2cache.tags.age_task_id_blocks_1024::2 524 # Occupied blocks per task id 680system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1094 # Occupied blocks per task id 681system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 # Occupied blocks per task id 682system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474762 # Percentage of cache occupancy per task id 683system.cpu.l2cache.tags.tag_accesses 15237953 # Number of tag accesses 684system.cpu.l2cache.tags.data_accesses 15237953 # Number of data accesses 685system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 686system.cpu.l2cache.WritebackDirty_hits::writebacks 943282 # number of WritebackDirty hits 687system.cpu.l2cache.WritebackDirty_hits::total 943282 # number of WritebackDirty hits 688system.cpu.l2cache.WritebackClean_hits::writebacks 4 # number of WritebackClean hits 689system.cpu.l2cache.WritebackClean_hits::total 4 # number of WritebackClean hits 690system.cpu.l2cache.ReadExReq_hits::cpu.data 32220 # number of ReadExReq hits 691system.cpu.l2cache.ReadExReq_hits::total 32220 # number of ReadExReq hits 692system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 27 # number of ReadCleanReq hits 693system.cpu.l2cache.ReadCleanReq_hits::total 27 # number of ReadCleanReq hits 694system.cpu.l2cache.ReadSharedReq_hits::cpu.data 903170 # number of ReadSharedReq hits 695system.cpu.l2cache.ReadSharedReq_hits::total 903170 # number of ReadSharedReq hits 696system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits 697system.cpu.l2cache.demand_hits::cpu.data 935390 # number of demand (read+write) hits 698system.cpu.l2cache.demand_hits::total 935417 # number of demand (read+write) hits 699system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits 700system.cpu.l2cache.overall_hits::cpu.data 935390 # number of overall hits 701system.cpu.l2cache.overall_hits::total 935417 # number of overall hits 702system.cpu.l2cache.ReadExReq_misses::cpu.data 14544 # number of ReadExReq misses 703system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses 704system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 774 # number of ReadCleanReq misses 705system.cpu.l2cache.ReadCleanReq_misses::total 774 # number of ReadCleanReq misses 706system.cpu.l2cache.ReadSharedReq_misses::cpu.data 263 # number of ReadSharedReq misses 707system.cpu.l2cache.ReadSharedReq_misses::total 263 # number of ReadSharedReq misses 708system.cpu.l2cache.demand_misses::cpu.inst 774 # number of demand (read+write) misses 709system.cpu.l2cache.demand_misses::cpu.data 14807 # number of demand (read+write) misses 710system.cpu.l2cache.demand_misses::total 15581 # number of demand (read+write) misses 711system.cpu.l2cache.overall_misses::cpu.inst 774 # number of overall misses 712system.cpu.l2cache.overall_misses::cpu.data 14807 # number of overall misses 713system.cpu.l2cache.overall_misses::total 15581 # number of overall misses 714system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1068633000 # number of ReadExReq miss cycles 715system.cpu.l2cache.ReadExReq_miss_latency::total 1068633000 # number of ReadExReq miss cycles 716system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 58136500 # number of ReadCleanReq miss cycles 717system.cpu.l2cache.ReadCleanReq_miss_latency::total 58136500 # number of ReadCleanReq miss cycles 718system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 22289000 # number of ReadSharedReq miss cycles 719system.cpu.l2cache.ReadSharedReq_miss_latency::total 22289000 # number of ReadSharedReq miss cycles 720system.cpu.l2cache.demand_miss_latency::cpu.inst 58136500 # number of demand (read+write) miss cycles 721system.cpu.l2cache.demand_miss_latency::cpu.data 1090922000 # number of demand (read+write) miss cycles 722system.cpu.l2cache.demand_miss_latency::total 1149058500 # number of demand (read+write) miss cycles 723system.cpu.l2cache.overall_miss_latency::cpu.inst 58136500 # number of overall miss cycles 724system.cpu.l2cache.overall_miss_latency::cpu.data 1090922000 # number of overall miss cycles 725system.cpu.l2cache.overall_miss_latency::total 1149058500 # number of overall miss cycles 726system.cpu.l2cache.WritebackDirty_accesses::writebacks 943282 # number of WritebackDirty accesses(hits+misses) 727system.cpu.l2cache.WritebackDirty_accesses::total 943282 # number of WritebackDirty accesses(hits+misses) 728system.cpu.l2cache.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses) 729system.cpu.l2cache.WritebackClean_accesses::total 4 # number of WritebackClean accesses(hits+misses) 730system.cpu.l2cache.ReadExReq_accesses::cpu.data 46764 # number of ReadExReq accesses(hits+misses) 731system.cpu.l2cache.ReadExReq_accesses::total 46764 # number of ReadExReq accesses(hits+misses) 732system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 801 # number of ReadCleanReq accesses(hits+misses) 733system.cpu.l2cache.ReadCleanReq_accesses::total 801 # number of ReadCleanReq accesses(hits+misses) 734system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 903433 # number of ReadSharedReq accesses(hits+misses) 735system.cpu.l2cache.ReadSharedReq_accesses::total 903433 # number of ReadSharedReq accesses(hits+misses) 736system.cpu.l2cache.demand_accesses::cpu.inst 801 # number of demand (read+write) accesses 737system.cpu.l2cache.demand_accesses::cpu.data 950197 # number of demand (read+write) accesses 738system.cpu.l2cache.demand_accesses::total 950998 # number of demand (read+write) accesses 739system.cpu.l2cache.overall_accesses::cpu.inst 801 # number of overall (read+write) accesses 740system.cpu.l2cache.overall_accesses::cpu.data 950197 # number of overall (read+write) accesses 741system.cpu.l2cache.overall_accesses::total 950998 # number of overall (read+write) accesses 742system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311008 # miss rate for ReadExReq accesses 743system.cpu.l2cache.ReadExReq_miss_rate::total 0.311008 # miss rate for ReadExReq accesses 744system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.966292 # miss rate for ReadCleanReq accesses 745system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.966292 # miss rate for ReadCleanReq accesses 746system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000291 # miss rate for ReadSharedReq accesses 747system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000291 # miss rate for ReadSharedReq accesses 748system.cpu.l2cache.demand_miss_rate::cpu.inst 0.966292 # miss rate for demand accesses 749system.cpu.l2cache.demand_miss_rate::cpu.data 0.015583 # miss rate for demand accesses 750system.cpu.l2cache.demand_miss_rate::total 0.016384 # miss rate for demand accesses 751system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966292 # miss rate for overall accesses 752system.cpu.l2cache.overall_miss_rate::cpu.data 0.015583 # miss rate for overall accesses 753system.cpu.l2cache.overall_miss_rate::total 0.016384 # miss rate for overall accesses 754system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73475.866337 # average ReadExReq miss latency 755system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73475.866337 # average ReadExReq miss latency 756system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75111.757106 # average ReadCleanReq miss latency 757system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75111.757106 # average ReadCleanReq miss latency 758system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 84749.049430 # average ReadSharedReq miss latency 759system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 84749.049430 # average ReadSharedReq miss latency 760system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75111.757106 # average overall miss latency 761system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73676.099142 # average overall miss latency 762system.cpu.l2cache.demand_avg_miss_latency::total 73747.416725 # average overall miss latency 763system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75111.757106 # average overall miss latency 764system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73676.099142 # average overall miss latency 765system.cpu.l2cache.overall_avg_miss_latency::total 73747.416725 # average overall miss latency 766system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 767system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 768system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 769system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 770system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 771system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 772system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 773system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 774system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits 775system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits 776system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 777system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits 778system.cpu.l2cache.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits 779system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 780system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits 781system.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits 782system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14544 # number of ReadExReq MSHR misses 783system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses 784system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 773 # number of ReadCleanReq MSHR misses 785system.cpu.l2cache.ReadCleanReq_mshr_misses::total 773 # number of ReadCleanReq MSHR misses 786system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 257 # number of ReadSharedReq MSHR misses 787system.cpu.l2cache.ReadSharedReq_mshr_misses::total 257 # number of ReadSharedReq MSHR misses 788system.cpu.l2cache.demand_mshr_misses::cpu.inst 773 # number of demand (read+write) MSHR misses 789system.cpu.l2cache.demand_mshr_misses::cpu.data 14801 # number of demand (read+write) MSHR misses 790system.cpu.l2cache.demand_mshr_misses::total 15574 # number of demand (read+write) MSHR misses 791system.cpu.l2cache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses 792system.cpu.l2cache.overall_mshr_misses::cpu.data 14801 # number of overall MSHR misses 793system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses 794system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 923193000 # number of ReadExReq MSHR miss cycles 795system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 923193000 # number of ReadExReq MSHR miss cycles 796system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 50340000 # number of ReadCleanReq MSHR miss cycles 797system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 50340000 # number of ReadCleanReq MSHR miss cycles 798system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 19328000 # number of ReadSharedReq MSHR miss cycles 799system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 19328000 # number of ReadSharedReq MSHR miss cycles 800system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50340000 # number of demand (read+write) MSHR miss cycles 801system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 942521000 # number of demand (read+write) MSHR miss cycles 802system.cpu.l2cache.demand_mshr_miss_latency::total 992861000 # number of demand (read+write) MSHR miss cycles 803system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50340000 # number of overall MSHR miss cycles 804system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 942521000 # number of overall MSHR miss cycles 805system.cpu.l2cache.overall_mshr_miss_latency::total 992861000 # number of overall MSHR miss cycles 806system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses 807system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses 808system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for ReadCleanReq accesses 809system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965044 # mshr miss rate for ReadCleanReq accesses 810system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000284 # mshr miss rate for ReadSharedReq accesses 811system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000284 # mshr miss rate for ReadSharedReq accesses 812system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for demand accesses 813system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for demand accesses 814system.cpu.l2cache.demand_mshr_miss_rate::total 0.016376 # mshr miss rate for demand accesses 815system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for overall accesses 816system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for overall accesses 817system.cpu.l2cache.overall_mshr_miss_rate::total 0.016376 # mshr miss rate for overall accesses 818system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63475.866337 # average ReadExReq mshr miss latency 819system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63475.866337 # average ReadExReq mshr miss latency 820system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65122.897801 # average ReadCleanReq mshr miss latency 821system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65122.897801 # average ReadCleanReq mshr miss latency 822system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75206.225681 # average ReadSharedReq mshr miss latency 823system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75206.225681 # average ReadSharedReq mshr miss latency 824system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65122.897801 # average overall mshr miss latency 825system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63679.548679 # average overall mshr miss latency 826system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63751.187877 # average overall mshr miss latency 827system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65122.897801 # average overall mshr miss latency 828system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63679.548679 # average overall mshr miss latency 829system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63751.187877 # average overall mshr miss latency 830system.cpu.toL2Bus.snoop_filter.tot_requests 1897104 # Total number of requests made to the snoop filter. 831system.cpu.toL2Bus.snoop_filter.hit_single_requests 946122 # Number of requests hitting in the snoop filter with a single holder of the requested data. 832system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 833system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 834system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 835system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 836system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 837system.cpu.toL2Bus.trans_dist::ReadResp 904234 # Transaction distribution 838system.cpu.toL2Bus.trans_dist::WritebackDirty 943282 # Transaction distribution 839system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution 840system.cpu.toL2Bus.trans_dist::CleanEvict 2819 # Transaction distribution 841system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution 842system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution 843system.cpu.toL2Bus.trans_dist::ReadCleanReq 801 # Transaction distribution 844system.cpu.toL2Bus.trans_dist::ReadSharedReq 903433 # Transaction distribution 845system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1607 # Packet count per connected master and slave (bytes) 846system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846495 # Packet count per connected master and slave (bytes) 847system.cpu.toL2Bus.pkt_count::total 2848102 # Packet count per connected master and slave (bytes) 848system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51584 # Cumulative packet size per connected master and slave (bytes) 849system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182656 # Cumulative packet size per connected master and slave (bytes) 850system.cpu.toL2Bus.pkt_size::total 121234240 # Cumulative packet size per connected master and slave (bytes) 851system.cpu.toL2Bus.snoops 0 # Total snoops (count) 852system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 853system.cpu.toL2Bus.snoop_fanout::samples 950998 # Request fanout histogram 854system.cpu.toL2Bus.snoop_fanout::mean 0.000175 # Request fanout histogram 855system.cpu.toL2Bus.snoop_fanout::stdev 0.013211 # Request fanout histogram 856system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 857system.cpu.toL2Bus.snoop_fanout::0 950832 99.98% 99.98% # Request fanout histogram 858system.cpu.toL2Bus.snoop_fanout::1 166 0.02% 100.00% # Request fanout histogram 859system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 860system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 861system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 862system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 863system.cpu.toL2Bus.snoop_fanout::total 950998 # Request fanout histogram 864system.cpu.toL2Bus.reqLayer0.occupancy 1891839000 # Layer occupancy (ticks) 865system.cpu.toL2Bus.reqLayer0.utilization 3.0 # Layer utilization (%) 866system.cpu.toL2Bus.respLayer0.occupancy 1201999 # Layer occupancy (ticks) 867system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 868system.cpu.toL2Bus.respLayer1.occupancy 1425298494 # Layer occupancy (ticks) 869system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) 870system.membus.pwrStateResidencyTicks::UNDEFINED 62408957500 # Cumulative time (in ticks) in various power states 871system.membus.trans_dist::ReadResp 1030 # Transaction distribution 872system.membus.trans_dist::ReadExReq 14544 # Transaction distribution 873system.membus.trans_dist::ReadExResp 14544 # Transaction distribution 874system.membus.trans_dist::ReadSharedReq 1030 # Transaction distribution 875system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31148 # Packet count per connected master and slave (bytes) 876system.membus.pkt_count::total 31148 # Packet count per connected master and slave (bytes) 877system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes) 878system.membus.pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes) 879system.membus.snoops 0 # Total snoops (count) 880system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 881system.membus.snoop_fanout::samples 15574 # Request fanout histogram 882system.membus.snoop_fanout::mean 0 # Request fanout histogram 883system.membus.snoop_fanout::stdev 0 # Request fanout histogram 884system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 885system.membus.snoop_fanout::0 15574 100.00% 100.00% # Request fanout histogram 886system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 887system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 888system.membus.snoop_fanout::min_value 0 # Request fanout histogram 889system.membus.snoop_fanout::max_value 0 # Request fanout histogram 890system.membus.snoop_fanout::total 15574 # Request fanout histogram 891system.membus.reqLayer0.occupancy 21833000 # Layer occupancy (ticks) 892system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 893system.membus.respLayer1.occupancy 82137750 # Layer occupancy (ticks) 894system.membus.respLayer1.utilization 0.1 # Layer utilization (%) 895 896---------- End Simulation Statistics ---------- 897