stats.txt revision 9283:490958b032d6
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.163939 # Number of seconds simulated 4sim_ticks 5163939423500 # Number of ticks simulated 5final_tick 5163939423500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 202828 # Simulator instruction rate (inst/s) 8host_op_rate 400952 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2568035232 # Simulator tick rate (ticks/s) 10host_mem_usage 368532 # Number of bytes of host memory used 11host_seconds 2010.85 # Real time elapsed on the host 12sim_insts 407858031 # Number of instructions simulated 13sim_ops 806254969 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::pc.south_bridge.ide 2460224 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.dtb.walker 2944 # Number of bytes read from this memory 16system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.inst 1069888 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 10576384 # Number of bytes read from this memory 19system.physmem.bytes_read::total 14109824 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 1069888 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 1069888 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 9320448 # Number of bytes written to this memory 23system.physmem.bytes_written::total 9320448 # Number of bytes written to this memory 24system.physmem.num_reads::pc.south_bridge.ide 38441 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.dtb.walker 46 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.inst 16717 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.data 165256 # Number of read requests responded to by this memory 29system.physmem.num_reads::total 220466 # Number of read requests responded to by this memory 30system.physmem.num_writes::writebacks 145632 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 145632 # Number of write requests responded to by this memory 32system.physmem.bw_read::pc.south_bridge.ide 476424 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.dtb.walker 570 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.inst 207184 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.data 2048123 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::total 2732376 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_inst_read::cpu.inst 207184 # Instruction read bandwidth from this memory (bytes/s) 39system.physmem.bw_inst_read::total 207184 # Instruction read bandwidth from this memory (bytes/s) 40system.physmem.bw_write::writebacks 1804910 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_write::total 1804910 # Write bandwidth from this memory (bytes/s) 42system.physmem.bw_total::writebacks 1804910 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::pc.south_bridge.ide 476424 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::cpu.dtb.walker 570 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.inst 207184 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.data 2048123 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::total 4537286 # Total bandwidth to/from this memory (bytes/s) 49system.cpu.l2cache.replacements 109190 # number of replacements 50system.cpu.l2cache.tagsinuse 64839.015299 # Cycle average of tags in use 51system.cpu.l2cache.total_refs 3984882 # Total number of references to valid blocks. 52system.cpu.l2cache.sampled_refs 173424 # Sample count of references to valid blocks. 53system.cpu.l2cache.avg_refs 22.977685 # Average number of references to valid blocks. 54system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 55system.cpu.l2cache.occ_blocks::writebacks 49968.765370 # Average occupied blocks per requestor 56system.cpu.l2cache.occ_blocks::cpu.dtb.walker 13.151051 # Average occupied blocks per requestor 57system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.155230 # Average occupied blocks per requestor 58system.cpu.l2cache.occ_blocks::cpu.inst 3435.794855 # Average occupied blocks per requestor 59system.cpu.l2cache.occ_blocks::cpu.data 11421.148791 # Average occupied blocks per requestor 60system.cpu.l2cache.occ_percent::writebacks 0.762463 # Average percentage of cache occupancy 61system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000201 # Average percentage of cache occupancy 62system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 63system.cpu.l2cache.occ_percent::cpu.inst 0.052426 # Average percentage of cache occupancy 64system.cpu.l2cache.occ_percent::cpu.data 0.174273 # Average percentage of cache occupancy 65system.cpu.l2cache.occ_percent::total 0.989365 # Average percentage of cache occupancy 66system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 103321 # number of ReadReq hits 67system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 8437 # number of ReadReq hits 68system.cpu.l2cache.ReadReq_hits::cpu.inst 1055749 # number of ReadReq hits 69system.cpu.l2cache.ReadReq_hits::cpu.data 1347777 # number of ReadReq hits 70system.cpu.l2cache.ReadReq_hits::total 2515284 # number of ReadReq hits 71system.cpu.l2cache.Writeback_hits::writebacks 1610495 # number of Writeback hits 72system.cpu.l2cache.Writeback_hits::total 1610495 # number of Writeback hits 73system.cpu.l2cache.UpgradeReq_hits::cpu.data 337 # number of UpgradeReq hits 74system.cpu.l2cache.UpgradeReq_hits::total 337 # number of UpgradeReq hits 75system.cpu.l2cache.ReadExReq_hits::cpu.data 158131 # number of ReadExReq hits 76system.cpu.l2cache.ReadExReq_hits::total 158131 # number of ReadExReq hits 77system.cpu.l2cache.demand_hits::cpu.dtb.walker 103321 # number of demand (read+write) hits 78system.cpu.l2cache.demand_hits::cpu.itb.walker 8437 # number of demand (read+write) hits 79system.cpu.l2cache.demand_hits::cpu.inst 1055749 # number of demand (read+write) hits 80system.cpu.l2cache.demand_hits::cpu.data 1505908 # number of demand (read+write) hits 81system.cpu.l2cache.demand_hits::total 2673415 # number of demand (read+write) hits 82system.cpu.l2cache.overall_hits::cpu.dtb.walker 103321 # number of overall hits 83system.cpu.l2cache.overall_hits::cpu.itb.walker 8437 # number of overall hits 84system.cpu.l2cache.overall_hits::cpu.inst 1055749 # number of overall hits 85system.cpu.l2cache.overall_hits::cpu.data 1505908 # number of overall hits 86system.cpu.l2cache.overall_hits::total 2673415 # number of overall hits 87system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 46 # number of ReadReq misses 88system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses 89system.cpu.l2cache.ReadReq_misses::cpu.inst 16718 # number of ReadReq misses 90system.cpu.l2cache.ReadReq_misses::cpu.data 35983 # number of ReadReq misses 91system.cpu.l2cache.ReadReq_misses::total 52753 # number of ReadReq misses 92system.cpu.l2cache.UpgradeReq_misses::cpu.data 3384 # number of UpgradeReq misses 93system.cpu.l2cache.UpgradeReq_misses::total 3384 # number of UpgradeReq misses 94system.cpu.l2cache.ReadExReq_misses::cpu.data 130218 # number of ReadExReq misses 95system.cpu.l2cache.ReadExReq_misses::total 130218 # number of ReadExReq misses 96system.cpu.l2cache.demand_misses::cpu.dtb.walker 46 # number of demand (read+write) misses 97system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses 98system.cpu.l2cache.demand_misses::cpu.inst 16718 # number of demand (read+write) misses 99system.cpu.l2cache.demand_misses::cpu.data 166201 # number of demand (read+write) misses 100system.cpu.l2cache.demand_misses::total 182971 # number of demand (read+write) misses 101system.cpu.l2cache.overall_misses::cpu.dtb.walker 46 # number of overall misses 102system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses 103system.cpu.l2cache.overall_misses::cpu.inst 16718 # number of overall misses 104system.cpu.l2cache.overall_misses::cpu.data 166201 # number of overall misses 105system.cpu.l2cache.overall_misses::total 182971 # number of overall misses 106system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2414500 # number of ReadReq miss cycles 107system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 312500 # number of ReadReq miss cycles 108system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 887508500 # number of ReadReq miss cycles 109system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1921141998 # number of ReadReq miss cycles 110system.cpu.l2cache.ReadReq_miss_latency::total 2811377498 # number of ReadReq miss cycles 111system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 38315000 # number of UpgradeReq miss cycles 112system.cpu.l2cache.UpgradeReq_miss_latency::total 38315000 # number of UpgradeReq miss cycles 113system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6787419499 # number of ReadExReq miss cycles 114system.cpu.l2cache.ReadExReq_miss_latency::total 6787419499 # number of ReadExReq miss cycles 115system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2414500 # number of demand (read+write) miss cycles 116system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 312500 # number of demand (read+write) miss cycles 117system.cpu.l2cache.demand_miss_latency::cpu.inst 887508500 # number of demand (read+write) miss cycles 118system.cpu.l2cache.demand_miss_latency::cpu.data 8708561497 # number of demand (read+write) miss cycles 119system.cpu.l2cache.demand_miss_latency::total 9598796997 # number of demand (read+write) miss cycles 120system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2414500 # number of overall miss cycles 121system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 312500 # number of overall miss cycles 122system.cpu.l2cache.overall_miss_latency::cpu.inst 887508500 # number of overall miss cycles 123system.cpu.l2cache.overall_miss_latency::cpu.data 8708561497 # number of overall miss cycles 124system.cpu.l2cache.overall_miss_latency::total 9598796997 # number of overall miss cycles 125system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 103367 # number of ReadReq accesses(hits+misses) 126system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 8443 # number of ReadReq accesses(hits+misses) 127system.cpu.l2cache.ReadReq_accesses::cpu.inst 1072467 # number of ReadReq accesses(hits+misses) 128system.cpu.l2cache.ReadReq_accesses::cpu.data 1383760 # number of ReadReq accesses(hits+misses) 129system.cpu.l2cache.ReadReq_accesses::total 2568037 # number of ReadReq accesses(hits+misses) 130system.cpu.l2cache.Writeback_accesses::writebacks 1610495 # number of Writeback accesses(hits+misses) 131system.cpu.l2cache.Writeback_accesses::total 1610495 # number of Writeback accesses(hits+misses) 132system.cpu.l2cache.UpgradeReq_accesses::cpu.data 3721 # number of UpgradeReq accesses(hits+misses) 133system.cpu.l2cache.UpgradeReq_accesses::total 3721 # number of UpgradeReq accesses(hits+misses) 134system.cpu.l2cache.ReadExReq_accesses::cpu.data 288349 # number of ReadExReq accesses(hits+misses) 135system.cpu.l2cache.ReadExReq_accesses::total 288349 # number of ReadExReq accesses(hits+misses) 136system.cpu.l2cache.demand_accesses::cpu.dtb.walker 103367 # number of demand (read+write) accesses 137system.cpu.l2cache.demand_accesses::cpu.itb.walker 8443 # number of demand (read+write) accesses 138system.cpu.l2cache.demand_accesses::cpu.inst 1072467 # number of demand (read+write) accesses 139system.cpu.l2cache.demand_accesses::cpu.data 1672109 # number of demand (read+write) accesses 140system.cpu.l2cache.demand_accesses::total 2856386 # number of demand (read+write) accesses 141system.cpu.l2cache.overall_accesses::cpu.dtb.walker 103367 # number of overall (read+write) accesses 142system.cpu.l2cache.overall_accesses::cpu.itb.walker 8443 # number of overall (read+write) accesses 143system.cpu.l2cache.overall_accesses::cpu.inst 1072467 # number of overall (read+write) accesses 144system.cpu.l2cache.overall_accesses::cpu.data 1672109 # number of overall (read+write) accesses 145system.cpu.l2cache.overall_accesses::total 2856386 # number of overall (read+write) accesses 146system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000445 # miss rate for ReadReq accesses 147system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000711 # miss rate for ReadReq accesses 148system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.015588 # miss rate for ReadReq accesses 149system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026004 # miss rate for ReadReq accesses 150system.cpu.l2cache.ReadReq_miss_rate::total 0.020542 # miss rate for ReadReq accesses 151system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.909433 # miss rate for UpgradeReq accesses 152system.cpu.l2cache.UpgradeReq_miss_rate::total 0.909433 # miss rate for UpgradeReq accesses 153system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.451599 # miss rate for ReadExReq accesses 154system.cpu.l2cache.ReadExReq_miss_rate::total 0.451599 # miss rate for ReadExReq accesses 155system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000445 # miss rate for demand accesses 156system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000711 # miss rate for demand accesses 157system.cpu.l2cache.demand_miss_rate::cpu.inst 0.015588 # miss rate for demand accesses 158system.cpu.l2cache.demand_miss_rate::cpu.data 0.099396 # miss rate for demand accesses 159system.cpu.l2cache.demand_miss_rate::total 0.064057 # miss rate for demand accesses 160system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000445 # miss rate for overall accesses 161system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000711 # miss rate for overall accesses 162system.cpu.l2cache.overall_miss_rate::cpu.inst 0.015588 # miss rate for overall accesses 163system.cpu.l2cache.overall_miss_rate::cpu.data 0.099396 # miss rate for overall accesses 164system.cpu.l2cache.overall_miss_rate::total 0.064057 # miss rate for overall accesses 165system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 52489.130435 # average ReadReq miss latency 166system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 52083.333333 # average ReadReq miss latency 167system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 53087.002034 # average ReadReq miss latency 168system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53390.267571 # average ReadReq miss latency 169system.cpu.l2cache.ReadReq_avg_miss_latency::total 53293.224992 # average ReadReq miss latency 170system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11322.399527 # average UpgradeReq miss latency 171system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11322.399527 # average UpgradeReq miss latency 172system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52123.512103 # average ReadExReq miss latency 173system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52123.512103 # average ReadExReq miss latency 174system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 52489.130435 # average overall miss latency 175system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 52083.333333 # average overall miss latency 176system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 53087.002034 # average overall miss latency 177system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52397.768347 # average overall miss latency 178system.cpu.l2cache.demand_avg_miss_latency::total 52460.756060 # average overall miss latency 179system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 52489.130435 # average overall miss latency 180system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 52083.333333 # average overall miss latency 181system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 53087.002034 # average overall miss latency 182system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52397.768347 # average overall miss latency 183system.cpu.l2cache.overall_avg_miss_latency::total 52460.756060 # average overall miss latency 184system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 185system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 186system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 187system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 188system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 189system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 190system.cpu.l2cache.fast_writes 0 # number of fast writes performed 191system.cpu.l2cache.cache_copies 0 # number of cache copies performed 192system.cpu.l2cache.writebacks::writebacks 98965 # number of writebacks 193system.cpu.l2cache.writebacks::total 98965 # number of writebacks 194system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 195system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits 196system.cpu.l2cache.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits 197system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 198system.cpu.l2cache.demand_mshr_hits::cpu.data 2 # number of demand (read+write) MSHR hits 199system.cpu.l2cache.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits 200system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 201system.cpu.l2cache.overall_mshr_hits::cpu.data 2 # number of overall MSHR hits 202system.cpu.l2cache.overall_mshr_hits::total 3 # number of overall MSHR hits 203system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 46 # number of ReadReq MSHR misses 204system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses 205system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16717 # number of ReadReq MSHR misses 206system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35981 # number of ReadReq MSHR misses 207system.cpu.l2cache.ReadReq_mshr_misses::total 52750 # number of ReadReq MSHR misses 208system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3384 # number of UpgradeReq MSHR misses 209system.cpu.l2cache.UpgradeReq_mshr_misses::total 3384 # number of UpgradeReq MSHR misses 210system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130218 # number of ReadExReq MSHR misses 211system.cpu.l2cache.ReadExReq_mshr_misses::total 130218 # number of ReadExReq MSHR misses 212system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 46 # number of demand (read+write) MSHR misses 213system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses 214system.cpu.l2cache.demand_mshr_misses::cpu.inst 16717 # number of demand (read+write) MSHR misses 215system.cpu.l2cache.demand_mshr_misses::cpu.data 166199 # number of demand (read+write) MSHR misses 216system.cpu.l2cache.demand_mshr_misses::total 182968 # number of demand (read+write) MSHR misses 217system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 46 # number of overall MSHR misses 218system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses 219system.cpu.l2cache.overall_mshr_misses::cpu.inst 16717 # number of overall MSHR misses 220system.cpu.l2cache.overall_mshr_misses::cpu.data 166199 # number of overall MSHR misses 221system.cpu.l2cache.overall_mshr_misses::total 182968 # number of overall MSHR misses 222system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1856000 # number of ReadReq MSHR miss cycles 223system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 240000 # number of ReadReq MSHR miss cycles 224system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 683651500 # number of ReadReq MSHR miss cycles 225system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1481312999 # number of ReadReq MSHR miss cycles 226system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2167060499 # number of ReadReq MSHR miss cycles 227system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 135806000 # number of UpgradeReq MSHR miss cycles 228system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 135806000 # number of UpgradeReq MSHR miss cycles 229system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5218894001 # number of ReadExReq MSHR miss cycles 230system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5218894001 # number of ReadExReq MSHR miss cycles 231system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1856000 # number of demand (read+write) MSHR miss cycles 232system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 240000 # number of demand (read+write) MSHR miss cycles 233system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 683651500 # number of demand (read+write) MSHR miss cycles 234system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6700207000 # number of demand (read+write) MSHR miss cycles 235system.cpu.l2cache.demand_mshr_miss_latency::total 7385954500 # number of demand (read+write) MSHR miss cycles 236system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1856000 # number of overall MSHR miss cycles 237system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 240000 # number of overall MSHR miss cycles 238system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 683651500 # number of overall MSHR miss cycles 239system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6700207000 # number of overall MSHR miss cycles 240system.cpu.l2cache.overall_mshr_miss_latency::total 7385954500 # number of overall MSHR miss cycles 241system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 88673398500 # number of ReadReq MSHR uncacheable cycles 242system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 88673398500 # number of ReadReq MSHR uncacheable cycles 243system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2308733000 # number of WriteReq MSHR uncacheable cycles 244system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2308733000 # number of WriteReq MSHR uncacheable cycles 245system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 90982131500 # number of overall MSHR uncacheable cycles 246system.cpu.l2cache.overall_mshr_uncacheable_latency::total 90982131500 # number of overall MSHR uncacheable cycles 247system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for ReadReq accesses 248system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000711 # mshr miss rate for ReadReq accesses 249system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.015587 # mshr miss rate for ReadReq accesses 250system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026002 # mshr miss rate for ReadReq accesses 251system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.020541 # mshr miss rate for ReadReq accesses 252system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.909433 # mshr miss rate for UpgradeReq accesses 253system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.909433 # mshr miss rate for UpgradeReq accesses 254system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.451599 # mshr miss rate for ReadExReq accesses 255system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.451599 # mshr miss rate for ReadExReq accesses 256system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for demand accesses 257system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000711 # mshr miss rate for demand accesses 258system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.015587 # mshr miss rate for demand accesses 259system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.099395 # mshr miss rate for demand accesses 260system.cpu.l2cache.demand_mshr_miss_rate::total 0.064056 # mshr miss rate for demand accesses 261system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000445 # mshr miss rate for overall accesses 262system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000711 # mshr miss rate for overall accesses 263system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.015587 # mshr miss rate for overall accesses 264system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.099395 # mshr miss rate for overall accesses 265system.cpu.l2cache.overall_mshr_miss_rate::total 0.064056 # mshr miss rate for overall accesses 266system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40347.826087 # average ReadReq mshr miss latency 267system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency 268system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40895.585332 # average ReadReq mshr miss latency 269system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41169.311553 # average ReadReq mshr miss latency 270system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41081.715621 # average ReadReq mshr miss latency 271system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 40131.796690 # average UpgradeReq mshr miss latency 272system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 40131.796690 # average UpgradeReq mshr miss latency 273system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40078.130527 # average ReadExReq mshr miss latency 274system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40078.130527 # average ReadExReq mshr miss latency 275system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 40347.826087 # average overall mshr miss latency 276system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 277system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40895.585332 # average overall mshr miss latency 278system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40314.364106 # average overall mshr miss latency 279system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40367.465896 # average overall mshr miss latency 280system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 40347.826087 # average overall mshr miss latency 281system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 282system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40895.585332 # average overall mshr miss latency 283system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40314.364106 # average overall mshr miss latency 284system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40367.465896 # average overall mshr miss latency 285system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 286system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 287system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 288system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 289system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 290system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 291system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 292system.iocache.replacements 47573 # number of replacements 293system.iocache.tagsinuse 0.184801 # Cycle average of tags in use 294system.iocache.total_refs 0 # Total number of references to valid blocks. 295system.iocache.sampled_refs 47589 # Sample count of references to valid blocks. 296system.iocache.avg_refs 0 # Average number of references to valid blocks. 297system.iocache.warmup_cycle 4996693675000 # Cycle when the warmup percentage was hit. 298system.iocache.occ_blocks::pc.south_bridge.ide 0.184801 # Average occupied blocks per requestor 299system.iocache.occ_percent::pc.south_bridge.ide 0.011550 # Average percentage of cache occupancy 300system.iocache.occ_percent::total 0.011550 # Average percentage of cache occupancy 301system.iocache.ReadReq_misses::pc.south_bridge.ide 908 # number of ReadReq misses 302system.iocache.ReadReq_misses::total 908 # number of ReadReq misses 303system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 304system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 305system.iocache.demand_misses::pc.south_bridge.ide 47628 # number of demand (read+write) misses 306system.iocache.demand_misses::total 47628 # number of demand (read+write) misses 307system.iocache.overall_misses::pc.south_bridge.ide 47628 # number of overall misses 308system.iocache.overall_misses::total 47628 # number of overall misses 309system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 137681932 # number of ReadReq miss cycles 310system.iocache.ReadReq_miss_latency::total 137681932 # number of ReadReq miss cycles 311system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9939428160 # number of WriteReq miss cycles 312system.iocache.WriteReq_miss_latency::total 9939428160 # number of WriteReq miss cycles 313system.iocache.demand_miss_latency::pc.south_bridge.ide 10077110092 # number of demand (read+write) miss cycles 314system.iocache.demand_miss_latency::total 10077110092 # number of demand (read+write) miss cycles 315system.iocache.overall_miss_latency::pc.south_bridge.ide 10077110092 # number of overall miss cycles 316system.iocache.overall_miss_latency::total 10077110092 # number of overall miss cycles 317system.iocache.ReadReq_accesses::pc.south_bridge.ide 908 # number of ReadReq accesses(hits+misses) 318system.iocache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) 319system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 320system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 321system.iocache.demand_accesses::pc.south_bridge.ide 47628 # number of demand (read+write) accesses 322system.iocache.demand_accesses::total 47628 # number of demand (read+write) accesses 323system.iocache.overall_accesses::pc.south_bridge.ide 47628 # number of overall (read+write) accesses 324system.iocache.overall_accesses::total 47628 # number of overall (read+write) accesses 325system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 326system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 327system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 328system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 329system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 330system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 331system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 332system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 333system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 151632.083700 # average ReadReq miss latency 334system.iocache.ReadReq_avg_miss_latency::total 151632.083700 # average ReadReq miss latency 335system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 212744.609589 # average WriteReq miss latency 336system.iocache.WriteReq_avg_miss_latency::total 212744.609589 # average WriteReq miss latency 337system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 211579.534979 # average overall miss latency 338system.iocache.demand_avg_miss_latency::total 211579.534979 # average overall miss latency 339system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 211579.534979 # average overall miss latency 340system.iocache.overall_avg_miss_latency::total 211579.534979 # average overall miss latency 341system.iocache.blocked_cycles::no_mshrs 72537008 # number of cycles access was blocked 342system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 343system.iocache.blocked::no_mshrs 8981 # number of cycles access was blocked 344system.iocache.blocked::no_targets 0 # number of cycles access was blocked 345system.iocache.avg_blocked_cycles::no_mshrs 8076.718406 # average number of cycles each access was blocked 346system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 347system.iocache.fast_writes 0 # number of fast writes performed 348system.iocache.cache_copies 0 # number of cache copies performed 349system.iocache.writebacks::writebacks 46667 # number of writebacks 350system.iocache.writebacks::total 46667 # number of writebacks 351system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 908 # number of ReadReq MSHR misses 352system.iocache.ReadReq_mshr_misses::total 908 # number of ReadReq MSHR misses 353system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 354system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses 355system.iocache.demand_mshr_misses::pc.south_bridge.ide 47628 # number of demand (read+write) MSHR misses 356system.iocache.demand_mshr_misses::total 47628 # number of demand (read+write) MSHR misses 357system.iocache.overall_mshr_misses::pc.south_bridge.ide 47628 # number of overall MSHR misses 358system.iocache.overall_mshr_misses::total 47628 # number of overall MSHR misses 359system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 90434000 # number of ReadReq MSHR miss cycles 360system.iocache.ReadReq_mshr_miss_latency::total 90434000 # number of ReadReq MSHR miss cycles 361system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 7509668946 # number of WriteReq MSHR miss cycles 362system.iocache.WriteReq_mshr_miss_latency::total 7509668946 # number of WriteReq MSHR miss cycles 363system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 7600102946 # number of demand (read+write) MSHR miss cycles 364system.iocache.demand_mshr_miss_latency::total 7600102946 # number of demand (read+write) MSHR miss cycles 365system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 7600102946 # number of overall MSHR miss cycles 366system.iocache.overall_mshr_miss_latency::total 7600102946 # number of overall MSHR miss cycles 367system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 368system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 369system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 370system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 371system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 372system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 373system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 374system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 375system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 99596.916300 # average ReadReq mshr miss latency 376system.iocache.ReadReq_avg_mshr_miss_latency::total 99596.916300 # average ReadReq mshr miss latency 377system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 160737.777098 # average WriteReq mshr miss latency 378system.iocache.WriteReq_avg_mshr_miss_latency::total 160737.777098 # average WriteReq mshr miss latency 379system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 159572.162299 # average overall mshr miss latency 380system.iocache.demand_avg_mshr_miss_latency::total 159572.162299 # average overall mshr miss latency 381system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 159572.162299 # average overall mshr miss latency 382system.iocache.overall_avg_mshr_miss_latency::total 159572.162299 # average overall mshr miss latency 383system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 384system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 385system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 386system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 387system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 388system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 389system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 390system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 391system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 392system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 393system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 394system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 395system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 396system.cpu.numCycles 465816448 # number of cpu cycles simulated 397system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 398system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 399system.cpu.BPredUnit.lookups 86514848 # Number of BP lookups 400system.cpu.BPredUnit.condPredicted 86514848 # Number of conditional branches predicted 401system.cpu.BPredUnit.condIncorrect 1196192 # Number of conditional branches incorrect 402system.cpu.BPredUnit.BTBLookups 82053392 # Number of BTB lookups 403system.cpu.BPredUnit.BTBHits 79452542 # Number of BTB hits 404system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 405system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 406system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. 407system.cpu.fetch.icacheStallCycles 31181464 # Number of cycles fetch is stalled on an Icache miss 408system.cpu.fetch.Insts 427226624 # Number of instructions fetch has processed 409system.cpu.fetch.Branches 86514848 # Number of branches that fetch encountered 410system.cpu.fetch.predictedBranches 79452542 # Number of branches that fetch has predicted taken 411system.cpu.fetch.Cycles 164016210 # Number of cycles fetch has run and was not squashing or blocked 412system.cpu.fetch.SquashCycles 5124580 # Number of cycles fetch has spent squashing 413system.cpu.fetch.TlbCycles 155814 # Number of cycles fetch has spent waiting for tlb 414system.cpu.fetch.BlockedCycles 72471814 # Number of cycles fetch has spent blocked 415system.cpu.fetch.MiscStallCycles 36433 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 416system.cpu.fetch.PendingTrapStallCycles 65503 # Number of stall cycles due to pending traps 417system.cpu.fetch.IcacheWaitRetryStallCycles 372 # Number of stall cycles due to full MSHR 418system.cpu.fetch.CacheLines 9296745 # Number of cache lines fetched 419system.cpu.fetch.IcacheSquashes 539923 # Number of outstanding Icache misses that were squashed 420system.cpu.fetch.ItlbSquashes 4055 # Number of outstanding ITLB misses that were squashed 421system.cpu.fetch.rateDist::samples 271815204 # Number of instructions fetched each cycle (Total) 422system.cpu.fetch.rateDist::mean 3.102878 # Number of instructions fetched each cycle (Total) 423system.cpu.fetch.rateDist::stdev 3.406830 # Number of instructions fetched each cycle (Total) 424system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 425system.cpu.fetch.rateDist::0 108229721 39.82% 39.82% # Number of instructions fetched each cycle (Total) 426system.cpu.fetch.rateDist::1 1589699 0.58% 40.40% # Number of instructions fetched each cycle (Total) 427system.cpu.fetch.rateDist::2 71960202 26.47% 66.88% # Number of instructions fetched each cycle (Total) 428system.cpu.fetch.rateDist::3 971866 0.36% 67.23% # Number of instructions fetched each cycle (Total) 429system.cpu.fetch.rateDist::4 1623537 0.60% 67.83% # Number of instructions fetched each cycle (Total) 430system.cpu.fetch.rateDist::5 2454126 0.90% 68.73% # Number of instructions fetched each cycle (Total) 431system.cpu.fetch.rateDist::6 1122252 0.41% 69.15% # Number of instructions fetched each cycle (Total) 432system.cpu.fetch.rateDist::7 1424890 0.52% 69.67% # Number of instructions fetched each cycle (Total) 433system.cpu.fetch.rateDist::8 82438911 30.33% 100.00% # Number of instructions fetched each cycle (Total) 434system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 435system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 436system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 437system.cpu.fetch.rateDist::total 271815204 # Number of instructions fetched each cycle (Total) 438system.cpu.fetch.branchRate 0.185727 # Number of branch fetches per cycle 439system.cpu.fetch.rate 0.917157 # Number of inst fetches per cycle 440system.cpu.decode.IdleCycles 34976255 # Number of cycles decode is idle 441system.cpu.decode.BlockedCycles 69906357 # Number of cycles decode is blocked 442system.cpu.decode.RunCycles 159691682 # Number of cycles decode is running 443system.cpu.decode.UnblockCycles 3353316 # Number of cycles decode is unblocking 444system.cpu.decode.SquashCycles 3887594 # Number of cycles decode is squashing 445system.cpu.decode.DecodedInsts 840157503 # Number of instructions handled by decode 446system.cpu.decode.SquashedInsts 1253 # Number of squashed instructions handled by decode 447system.cpu.rename.SquashCycles 3887594 # Number of cycles rename is squashing 448system.cpu.rename.IdleCycles 37933620 # Number of cycles rename is idle 449system.cpu.rename.BlockCycles 43316590 # Number of cycles rename is blocking 450system.cpu.rename.serializeStallCycles 11886084 # count of cycles rename stalled for serializing inst 451system.cpu.rename.RunCycles 159761513 # Number of cycles rename is running 452system.cpu.rename.UnblockCycles 15029803 # Number of cycles rename is unblocking 453system.cpu.rename.RenamedInsts 836332638 # Number of instructions processed by rename 454system.cpu.rename.ROBFullEvents 33622 # Number of times rename has blocked due to ROB full 455system.cpu.rename.IQFullEvents 7171271 # Number of times rename has blocked due to IQ full 456system.cpu.rename.LSQFullEvents 5982447 # Number of times rename has blocked due to LSQ full 457system.cpu.rename.FullRegisterEvents 16586 # Number of times there has been no free registers 458system.cpu.rename.RenamedOperands 998051723 # Number of destination operands rename has renamed 459system.cpu.rename.RenameLookups 1816227596 # Number of register rename lookups that rename has made 460system.cpu.rename.int_rename_lookups 1816227024 # Number of integer rename lookups 461system.cpu.rename.fp_rename_lookups 572 # Number of floating rename lookups 462system.cpu.rename.CommittedMaps 964187470 # Number of HB maps that are committed 463system.cpu.rename.UndoneMaps 33864246 # Number of HB maps that are undone due to squashing 464system.cpu.rename.serializingInsts 467105 # count of serializing insts renamed 465system.cpu.rename.tempSerializingInsts 474137 # count of temporary serializing insts renamed 466system.cpu.rename.skidInsts 32047540 # count of insts added to the skid buffer 467system.cpu.memDep0.insertedLoads 17336278 # Number of loads inserted to the mem dependence unit. 468system.cpu.memDep0.insertedStores 10273791 # Number of stores inserted to the mem dependence unit. 469system.cpu.memDep0.conflictingLoads 1251259 # Number of conflicting loads. 470system.cpu.memDep0.conflictingStores 987046 # Number of conflicting stores. 471system.cpu.iq.iqInstsAdded 829985579 # Number of instructions added to the IQ (excludes non-spec) 472system.cpu.iq.iqNonSpecInstsAdded 1254715 # Number of non-speculative instructions added to the IQ 473system.cpu.iq.iqInstsIssued 824362930 # Number of instructions issued 474system.cpu.iq.iqSquashedInstsIssued 185325 # Number of squashed instructions issued 475system.cpu.iq.iqSquashedInstsExamined 23972130 # Number of squashed instructions iterated over during squash; mainly for profiling 476system.cpu.iq.iqSquashedOperandsExamined 36446956 # Number of squashed operands that are examined and possibly removed from graph 477system.cpu.iq.iqSquashedNonSpecRemoved 204607 # Number of squashed non-spec instructions that were removed 478system.cpu.iq.issued_per_cycle::samples 271815204 # Number of insts issued each cycle 479system.cpu.iq.issued_per_cycle::mean 3.032807 # Number of insts issued each cycle 480system.cpu.iq.issued_per_cycle::stdev 2.413784 # Number of insts issued each cycle 481system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 482system.cpu.iq.issued_per_cycle::0 82518813 30.36% 30.36% # Number of insts issued each cycle 483system.cpu.iq.issued_per_cycle::1 18405041 6.77% 37.13% # Number of insts issued each cycle 484system.cpu.iq.issued_per_cycle::2 10590940 3.90% 41.03% # Number of insts issued each cycle 485system.cpu.iq.issued_per_cycle::3 7611334 2.80% 43.83% # Number of insts issued each cycle 486system.cpu.iq.issued_per_cycle::4 75787785 27.88% 71.71% # Number of insts issued each cycle 487system.cpu.iq.issued_per_cycle::5 3621369 1.33% 73.04% # Number of insts issued each cycle 488system.cpu.iq.issued_per_cycle::6 72414876 26.64% 99.68% # Number of insts issued each cycle 489system.cpu.iq.issued_per_cycle::7 725602 0.27% 99.95% # Number of insts issued each cycle 490system.cpu.iq.issued_per_cycle::8 139444 0.05% 100.00% # Number of insts issued each cycle 491system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 492system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 493system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 494system.cpu.iq.issued_per_cycle::total 271815204 # Number of insts issued each cycle 495system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 496system.cpu.iq.fu_full::IntAlu 330736 32.15% 32.15% # attempts to use FU when none available 497system.cpu.iq.fu_full::IntMult 0 0.00% 32.15% # attempts to use FU when none available 498system.cpu.iq.fu_full::IntDiv 0 0.00% 32.15% # attempts to use FU when none available 499system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.15% # attempts to use FU when none available 500system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.15% # attempts to use FU when none available 501system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.15% # attempts to use FU when none available 502system.cpu.iq.fu_full::FloatMult 0 0.00% 32.15% # attempts to use FU when none available 503system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.15% # attempts to use FU when none available 504system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.15% # attempts to use FU when none available 505system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.15% # attempts to use FU when none available 506system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.15% # attempts to use FU when none available 507system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.15% # attempts to use FU when none available 508system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.15% # attempts to use FU when none available 509system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.15% # attempts to use FU when none available 510system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.15% # attempts to use FU when none available 511system.cpu.iq.fu_full::SimdMult 0 0.00% 32.15% # attempts to use FU when none available 512system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.15% # attempts to use FU when none available 513system.cpu.iq.fu_full::SimdShift 0 0.00% 32.15% # attempts to use FU when none available 514system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.15% # attempts to use FU when none available 515system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.15% # attempts to use FU when none available 516system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.15% # attempts to use FU when none available 517system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.15% # attempts to use FU when none available 518system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.15% # attempts to use FU when none available 519system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.15% # attempts to use FU when none available 520system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.15% # attempts to use FU when none available 521system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.15% # attempts to use FU when none available 522system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.15% # attempts to use FU when none available 523system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.15% # attempts to use FU when none available 524system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.15% # attempts to use FU when none available 525system.cpu.iq.fu_full::MemRead 548005 53.27% 85.42% # attempts to use FU when none available 526system.cpu.iq.fu_full::MemWrite 150045 14.58% 100.00% # attempts to use FU when none available 527system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 528system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 529system.cpu.iq.FU_type_0::No_OpClass 308450 0.04% 0.04% # Type of FU issued 530system.cpu.iq.FU_type_0::IntAlu 796558014 96.63% 96.66% # Type of FU issued 531system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.66% # Type of FU issued 532system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.66% # Type of FU issued 533system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.66% # Type of FU issued 534system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.66% # Type of FU issued 535system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.66% # Type of FU issued 536system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.66% # Type of FU issued 537system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.66% # Type of FU issued 538system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.66% # Type of FU issued 539system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.66% # Type of FU issued 540system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.66% # Type of FU issued 541system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.66% # Type of FU issued 542system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.66% # Type of FU issued 543system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.66% # Type of FU issued 544system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.66% # Type of FU issued 545system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.66% # Type of FU issued 546system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.66% # Type of FU issued 547system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.66% # Type of FU issued 548system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.66% # Type of FU issued 549system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.66% # Type of FU issued 550system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.66% # Type of FU issued 551system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.66% # Type of FU issued 552system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.66% # Type of FU issued 553system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.66% # Type of FU issued 554system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.66% # Type of FU issued 555system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.66% # Type of FU issued 556system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.66% # Type of FU issued 557system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.66% # Type of FU issued 558system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.66% # Type of FU issued 559system.cpu.iq.FU_type_0::MemRead 18020026 2.19% 98.85% # Type of FU issued 560system.cpu.iq.FU_type_0::MemWrite 9476440 1.15% 100.00% # Type of FU issued 561system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 562system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 563system.cpu.iq.FU_type_0::total 824362930 # Type of FU issued 564system.cpu.iq.rate 1.769716 # Inst issue rate 565system.cpu.iq.fu_busy_cnt 1028786 # FU busy when requested 566system.cpu.iq.fu_busy_rate 0.001248 # FU busy rate (busy events/executed inst) 567system.cpu.iq.int_inst_queue_reads 1921889039 # Number of integer instruction queue reads 568system.cpu.iq.int_inst_queue_writes 855222885 # Number of integer instruction queue writes 569system.cpu.iq.int_inst_queue_wakeup_accesses 819729616 # Number of integer instruction queue wakeup accesses 570system.cpu.iq.fp_inst_queue_reads 209 # Number of floating instruction queue reads 571system.cpu.iq.fp_inst_queue_writes 260 # Number of floating instruction queue writes 572system.cpu.iq.fp_inst_queue_wakeup_accesses 52 # Number of floating instruction queue wakeup accesses 573system.cpu.iq.int_alu_accesses 825083173 # Number of integer alu accesses 574system.cpu.iq.fp_alu_accesses 93 # Number of floating point alu accesses 575system.cpu.iew.lsq.thread0.forwLoads 1659720 # Number of loads that had data forwarded from stores 576system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 577system.cpu.iew.lsq.thread0.squashedLoads 3372872 # Number of loads squashed 578system.cpu.iew.lsq.thread0.ignoredResponses 25465 # Number of memory responses ignored because the instruction is squashed 579system.cpu.iew.lsq.thread0.memOrderViolation 11865 # Number of memory ordering violations 580system.cpu.iew.lsq.thread0.squashedStores 1866399 # Number of stores squashed 581system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 582system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 583system.cpu.iew.lsq.thread0.rescheduledLoads 1917615 # Number of loads that were rescheduled 584system.cpu.iew.lsq.thread0.cacheBlocked 21790 # Number of times an access to memory failed due to the cache being blocked 585system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 586system.cpu.iew.iewSquashCycles 3887594 # Number of cycles IEW is squashing 587system.cpu.iew.iewBlockCycles 28830241 # Number of cycles IEW is blocking 588system.cpu.iew.iewUnblockCycles 2469402 # Number of cycles IEW is unblocking 589system.cpu.iew.iewDispatchedInsts 831240294 # Number of instructions dispatched to IQ 590system.cpu.iew.iewDispSquashedInsts 338803 # Number of squashed instructions skipped by dispatch 591system.cpu.iew.iewDispLoadInsts 17336278 # Number of dispatched load instructions 592system.cpu.iew.iewDispStoreInsts 10273791 # Number of dispatched store instructions 593system.cpu.iew.iewDispNonSpecInsts 725681 # Number of dispatched non-speculative instructions 594system.cpu.iew.iewIQFullEvents 1777576 # Number of times the IQ has become full, causing a stall 595system.cpu.iew.iewLSQFullEvents 17730 # Number of times the LSQ has become full, causing a stall 596system.cpu.iew.memOrderViolationEvents 11865 # Number of memory order violations 597system.cpu.iew.predictedTakenIncorrect 713088 # Number of branches that were predicted taken incorrectly 598system.cpu.iew.predictedNotTakenIncorrect 629130 # Number of branches that were predicted not taken incorrectly 599system.cpu.iew.branchMispredicts 1342218 # Number of branch mispredicts detected at execute 600system.cpu.iew.iewExecutedInsts 822392031 # Number of executed instructions 601system.cpu.iew.iewExecLoadInsts 17604275 # Number of load instructions executed 602system.cpu.iew.iewExecSquashedInsts 1970898 # Number of squashed instructions skipped in execute 603system.cpu.iew.exec_swp 0 # number of swp insts executed 604system.cpu.iew.exec_nop 0 # number of nop insts executed 605system.cpu.iew.exec_refs 26833761 # number of memory reference insts executed 606system.cpu.iew.exec_branches 83292230 # Number of branches executed 607system.cpu.iew.exec_stores 9229486 # Number of stores executed 608system.cpu.iew.exec_rate 1.765485 # Inst execution rate 609system.cpu.iew.wb_sent 821862423 # cumulative count of insts sent to commit 610system.cpu.iew.wb_count 819729668 # cumulative count of insts written-back 611system.cpu.iew.wb_producers 639700217 # num instructions producing a value 612system.cpu.iew.wb_consumers 1045258728 # num instructions consuming a value 613system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 614system.cpu.iew.wb_rate 1.759770 # insts written-back per cycle 615system.cpu.iew.wb_fanout 0.612002 # average fanout of values written-back 616system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 617system.cpu.commit.commitSquashedInsts 24883748 # The number of squashed insts skipped by commit 618system.cpu.commit.commitNonSpecStalls 1050106 # The number of times commit has been forced to stall to communicate backwards 619system.cpu.commit.branchMispredicts 1201289 # The number of times a branch was mispredicted 620system.cpu.commit.committed_per_cycle::samples 267943051 # Number of insts commited each cycle 621system.cpu.commit.committed_per_cycle::mean 3.009053 # Number of insts commited each cycle 622system.cpu.commit.committed_per_cycle::stdev 2.862554 # Number of insts commited each cycle 623system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 624system.cpu.commit.committed_per_cycle::0 95668224 35.70% 35.70% # Number of insts commited each cycle 625system.cpu.commit.committed_per_cycle::1 12347484 4.61% 40.31% # Number of insts commited each cycle 626system.cpu.commit.committed_per_cycle::2 3939395 1.47% 41.78% # Number of insts commited each cycle 627system.cpu.commit.committed_per_cycle::3 74898098 27.95% 69.74% # Number of insts commited each cycle 628system.cpu.commit.committed_per_cycle::4 2419496 0.90% 70.64% # Number of insts commited each cycle 629system.cpu.commit.committed_per_cycle::5 1554494 0.58% 71.22% # Number of insts commited each cycle 630system.cpu.commit.committed_per_cycle::6 1057385 0.39% 71.61% # Number of insts commited each cycle 631system.cpu.commit.committed_per_cycle::7 70928163 26.47% 98.09% # Number of insts commited each cycle 632system.cpu.commit.committed_per_cycle::8 5130312 1.91% 100.00% # Number of insts commited each cycle 633system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 634system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 635system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 636system.cpu.commit.committed_per_cycle::total 267943051 # Number of insts commited each cycle 637system.cpu.commit.committedInsts 407858031 # Number of instructions committed 638system.cpu.commit.committedOps 806254969 # Number of ops (including micro ops) committed 639system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 640system.cpu.commit.refs 22370795 # Number of memory references committed 641system.cpu.commit.loads 13963403 # Number of loads committed 642system.cpu.commit.membars 471705 # Number of memory barriers committed 643system.cpu.commit.branches 82181312 # Number of branches committed 644system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 645system.cpu.commit.int_insts 735195017 # Number of committed integer instructions. 646system.cpu.commit.function_calls 0 # Number of function calls committed. 647system.cpu.commit.bw_lim_events 5130312 # number cycles where commit BW limit reached 648system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 649system.cpu.rob.rob_reads 1093872885 # The number of ROB reads 650system.cpu.rob.rob_writes 1666184214 # The number of ROB writes 651system.cpu.timesIdled 1421273 # Number of times that the entire CPU went into an idle state and unscheduled itself 652system.cpu.idleCycles 194001244 # Total number of cycles that the CPU has spent unscheduled due to idling 653system.cpu.quiesceCycles 9862059849 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 654system.cpu.committedInsts 407858031 # Number of Instructions Simulated 655system.cpu.committedOps 806254969 # Number of Ops (including micro ops) Simulated 656system.cpu.committedInsts_total 407858031 # Number of Instructions Simulated 657system.cpu.cpi 1.142104 # CPI: Cycles Per Instruction 658system.cpu.cpi_total 1.142104 # CPI: Total CPI of All Threads 659system.cpu.ipc 0.875577 # IPC: Instructions Per Cycle 660system.cpu.ipc_total 0.875577 # IPC: Total IPC of All Threads 661system.cpu.int_regfile_reads 1508209791 # number of integer regfile reads 662system.cpu.int_regfile_writes 977816443 # number of integer regfile writes 663system.cpu.fp_regfile_reads 52 # number of floating regfile reads 664system.cpu.misc_regfile_reads 265196274 # number of misc regfile reads 665system.cpu.misc_regfile_writes 402502 # number of misc regfile writes 666system.cpu.icache.replacements 1071989 # number of replacements 667system.cpu.icache.tagsinuse 510.817098 # Cycle average of tags in use 668system.cpu.icache.total_refs 8149627 # Total number of references to valid blocks. 669system.cpu.icache.sampled_refs 1072501 # Sample count of references to valid blocks. 670system.cpu.icache.avg_refs 7.598713 # Average number of references to valid blocks. 671system.cpu.icache.warmup_cycle 147426882000 # Cycle when the warmup percentage was hit. 672system.cpu.icache.occ_blocks::cpu.inst 510.817098 # Average occupied blocks per requestor 673system.cpu.icache.occ_percent::cpu.inst 0.997690 # Average percentage of cache occupancy 674system.cpu.icache.occ_percent::total 0.997690 # Average percentage of cache occupancy 675system.cpu.icache.ReadReq_hits::cpu.inst 8149627 # number of ReadReq hits 676system.cpu.icache.ReadReq_hits::total 8149627 # number of ReadReq hits 677system.cpu.icache.demand_hits::cpu.inst 8149627 # number of demand (read+write) hits 678system.cpu.icache.demand_hits::total 8149627 # number of demand (read+write) hits 679system.cpu.icache.overall_hits::cpu.inst 8149627 # number of overall hits 680system.cpu.icache.overall_hits::total 8149627 # number of overall hits 681system.cpu.icache.ReadReq_misses::cpu.inst 1147113 # number of ReadReq misses 682system.cpu.icache.ReadReq_misses::total 1147113 # number of ReadReq misses 683system.cpu.icache.demand_misses::cpu.inst 1147113 # number of demand (read+write) misses 684system.cpu.icache.demand_misses::total 1147113 # number of demand (read+write) misses 685system.cpu.icache.overall_misses::cpu.inst 1147113 # number of overall misses 686system.cpu.icache.overall_misses::total 1147113 # number of overall misses 687system.cpu.icache.ReadReq_miss_latency::cpu.inst 18981109491 # number of ReadReq miss cycles 688system.cpu.icache.ReadReq_miss_latency::total 18981109491 # number of ReadReq miss cycles 689system.cpu.icache.demand_miss_latency::cpu.inst 18981109491 # number of demand (read+write) miss cycles 690system.cpu.icache.demand_miss_latency::total 18981109491 # number of demand (read+write) miss cycles 691system.cpu.icache.overall_miss_latency::cpu.inst 18981109491 # number of overall miss cycles 692system.cpu.icache.overall_miss_latency::total 18981109491 # number of overall miss cycles 693system.cpu.icache.ReadReq_accesses::cpu.inst 9296740 # number of ReadReq accesses(hits+misses) 694system.cpu.icache.ReadReq_accesses::total 9296740 # number of ReadReq accesses(hits+misses) 695system.cpu.icache.demand_accesses::cpu.inst 9296740 # number of demand (read+write) accesses 696system.cpu.icache.demand_accesses::total 9296740 # number of demand (read+write) accesses 697system.cpu.icache.overall_accesses::cpu.inst 9296740 # number of overall (read+write) accesses 698system.cpu.icache.overall_accesses::total 9296740 # number of overall (read+write) accesses 699system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123389 # miss rate for ReadReq accesses 700system.cpu.icache.ReadReq_miss_rate::total 0.123389 # miss rate for ReadReq accesses 701system.cpu.icache.demand_miss_rate::cpu.inst 0.123389 # miss rate for demand accesses 702system.cpu.icache.demand_miss_rate::total 0.123389 # miss rate for demand accesses 703system.cpu.icache.overall_miss_rate::cpu.inst 0.123389 # miss rate for overall accesses 704system.cpu.icache.overall_miss_rate::total 0.123389 # miss rate for overall accesses 705system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16546.852395 # average ReadReq miss latency 706system.cpu.icache.ReadReq_avg_miss_latency::total 16546.852395 # average ReadReq miss latency 707system.cpu.icache.demand_avg_miss_latency::cpu.inst 16546.852395 # average overall miss latency 708system.cpu.icache.demand_avg_miss_latency::total 16546.852395 # average overall miss latency 709system.cpu.icache.overall_avg_miss_latency::cpu.inst 16546.852395 # average overall miss latency 710system.cpu.icache.overall_avg_miss_latency::total 16546.852395 # average overall miss latency 711system.cpu.icache.blocked_cycles::no_mshrs 3167993 # number of cycles access was blocked 712system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 713system.cpu.icache.blocked::no_mshrs 401 # number of cycles access was blocked 714system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 715system.cpu.icache.avg_blocked_cycles::no_mshrs 7900.231920 # average number of cycles each access was blocked 716system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 717system.cpu.icache.fast_writes 0 # number of fast writes performed 718system.cpu.icache.cache_copies 0 # number of cache copies performed 719system.cpu.icache.ReadReq_mshr_hits::cpu.inst 72595 # number of ReadReq MSHR hits 720system.cpu.icache.ReadReq_mshr_hits::total 72595 # number of ReadReq MSHR hits 721system.cpu.icache.demand_mshr_hits::cpu.inst 72595 # number of demand (read+write) MSHR hits 722system.cpu.icache.demand_mshr_hits::total 72595 # number of demand (read+write) MSHR hits 723system.cpu.icache.overall_mshr_hits::cpu.inst 72595 # number of overall MSHR hits 724system.cpu.icache.overall_mshr_hits::total 72595 # number of overall MSHR hits 725system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1074518 # number of ReadReq MSHR misses 726system.cpu.icache.ReadReq_mshr_misses::total 1074518 # number of ReadReq MSHR misses 727system.cpu.icache.demand_mshr_misses::cpu.inst 1074518 # number of demand (read+write) MSHR misses 728system.cpu.icache.demand_mshr_misses::total 1074518 # number of demand (read+write) MSHR misses 729system.cpu.icache.overall_mshr_misses::cpu.inst 1074518 # number of overall MSHR misses 730system.cpu.icache.overall_mshr_misses::total 1074518 # number of overall MSHR misses 731system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14814669993 # number of ReadReq MSHR miss cycles 732system.cpu.icache.ReadReq_mshr_miss_latency::total 14814669993 # number of ReadReq MSHR miss cycles 733system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14814669993 # number of demand (read+write) MSHR miss cycles 734system.cpu.icache.demand_mshr_miss_latency::total 14814669993 # number of demand (read+write) MSHR miss cycles 735system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14814669993 # number of overall MSHR miss cycles 736system.cpu.icache.overall_mshr_miss_latency::total 14814669993 # number of overall MSHR miss cycles 737system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115580 # mshr miss rate for ReadReq accesses 738system.cpu.icache.ReadReq_mshr_miss_rate::total 0.115580 # mshr miss rate for ReadReq accesses 739system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115580 # mshr miss rate for demand accesses 740system.cpu.icache.demand_mshr_miss_rate::total 0.115580 # mshr miss rate for demand accesses 741system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115580 # mshr miss rate for overall accesses 742system.cpu.icache.overall_mshr_miss_rate::total 0.115580 # mshr miss rate for overall accesses 743system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13787.270193 # average ReadReq mshr miss latency 744system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13787.270193 # average ReadReq mshr miss latency 745system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13787.270193 # average overall mshr miss latency 746system.cpu.icache.demand_avg_mshr_miss_latency::total 13787.270193 # average overall mshr miss latency 747system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13787.270193 # average overall mshr miss latency 748system.cpu.icache.overall_avg_mshr_miss_latency::total 13787.270193 # average overall mshr miss latency 749system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 750system.cpu.itb_walker_cache.replacements 9931 # number of replacements 751system.cpu.itb_walker_cache.tagsinuse 6.048032 # Cycle average of tags in use 752system.cpu.itb_walker_cache.total_refs 33329 # Total number of references to valid blocks. 753system.cpu.itb_walker_cache.sampled_refs 9947 # Sample count of references to valid blocks. 754system.cpu.itb_walker_cache.avg_refs 3.350658 # Average number of references to valid blocks. 755system.cpu.itb_walker_cache.warmup_cycle 5125253660500 # Cycle when the warmup percentage was hit. 756system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.048032 # Average occupied blocks per requestor 757system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.378002 # Average percentage of cache occupancy 758system.cpu.itb_walker_cache.occ_percent::total 0.378002 # Average percentage of cache occupancy 759system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 33326 # number of ReadReq hits 760system.cpu.itb_walker_cache.ReadReq_hits::total 33326 # number of ReadReq hits 761system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits 762system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits 763system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 33329 # number of demand (read+write) hits 764system.cpu.itb_walker_cache.demand_hits::total 33329 # number of demand (read+write) hits 765system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 33329 # number of overall hits 766system.cpu.itb_walker_cache.overall_hits::total 33329 # number of overall hits 767system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 10825 # number of ReadReq misses 768system.cpu.itb_walker_cache.ReadReq_misses::total 10825 # number of ReadReq misses 769system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 10825 # number of demand (read+write) misses 770system.cpu.itb_walker_cache.demand_misses::total 10825 # number of demand (read+write) misses 771system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 10825 # number of overall misses 772system.cpu.itb_walker_cache.overall_misses::total 10825 # number of overall misses 773system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 178140000 # number of ReadReq miss cycles 774system.cpu.itb_walker_cache.ReadReq_miss_latency::total 178140000 # number of ReadReq miss cycles 775system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 178140000 # number of demand (read+write) miss cycles 776system.cpu.itb_walker_cache.demand_miss_latency::total 178140000 # number of demand (read+write) miss cycles 777system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 178140000 # number of overall miss cycles 778system.cpu.itb_walker_cache.overall_miss_latency::total 178140000 # number of overall miss cycles 779system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 44151 # number of ReadReq accesses(hits+misses) 780system.cpu.itb_walker_cache.ReadReq_accesses::total 44151 # number of ReadReq accesses(hits+misses) 781system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) 782system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 783system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 44154 # number of demand (read+write) accesses 784system.cpu.itb_walker_cache.demand_accesses::total 44154 # number of demand (read+write) accesses 785system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 44154 # number of overall (read+write) accesses 786system.cpu.itb_walker_cache.overall_accesses::total 44154 # number of overall (read+write) accesses 787system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.245181 # miss rate for ReadReq accesses 788system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.245181 # miss rate for ReadReq accesses 789system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.245165 # miss rate for demand accesses 790system.cpu.itb_walker_cache.demand_miss_rate::total 0.245165 # miss rate for demand accesses 791system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.245165 # miss rate for overall accesses 792system.cpu.itb_walker_cache.overall_miss_rate::total 0.245165 # miss rate for overall accesses 793system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 16456.351039 # average ReadReq miss latency 794system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 16456.351039 # average ReadReq miss latency 795system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 16456.351039 # average overall miss latency 796system.cpu.itb_walker_cache.demand_avg_miss_latency::total 16456.351039 # average overall miss latency 797system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 16456.351039 # average overall miss latency 798system.cpu.itb_walker_cache.overall_avg_miss_latency::total 16456.351039 # average overall miss latency 799system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 800system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 801system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 802system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 803system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 804system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 805system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 806system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 807system.cpu.itb_walker_cache.writebacks::writebacks 1872 # number of writebacks 808system.cpu.itb_walker_cache.writebacks::total 1872 # number of writebacks 809system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 10825 # number of ReadReq MSHR misses 810system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 10825 # number of ReadReq MSHR misses 811system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 10825 # number of demand (read+write) MSHR misses 812system.cpu.itb_walker_cache.demand_mshr_misses::total 10825 # number of demand (read+write) MSHR misses 813system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 10825 # number of overall MSHR misses 814system.cpu.itb_walker_cache.overall_mshr_misses::total 10825 # number of overall MSHR misses 815system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 145034027 # number of ReadReq MSHR miss cycles 816system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 145034027 # number of ReadReq MSHR miss cycles 817system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 145034027 # number of demand (read+write) MSHR miss cycles 818system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 145034027 # number of demand (read+write) MSHR miss cycles 819system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 145034027 # number of overall MSHR miss cycles 820system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 145034027 # number of overall MSHR miss cycles 821system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.245181 # mshr miss rate for ReadReq accesses 822system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.245181 # mshr miss rate for ReadReq accesses 823system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.245165 # mshr miss rate for demand accesses 824system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.245165 # mshr miss rate for demand accesses 825system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.245165 # mshr miss rate for overall accesses 826system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.245165 # mshr miss rate for overall accesses 827system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 13398.062540 # average ReadReq mshr miss latency 828system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 13398.062540 # average ReadReq mshr miss latency 829system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 13398.062540 # average overall mshr miss latency 830system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 13398.062540 # average overall mshr miss latency 831system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 13398.062540 # average overall mshr miss latency 832system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 13398.062540 # average overall mshr miss latency 833system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 834system.cpu.dtb_walker_cache.replacements 109056 # number of replacements 835system.cpu.dtb_walker_cache.tagsinuse 13.865602 # Cycle average of tags in use 836system.cpu.dtb_walker_cache.total_refs 139886 # Total number of references to valid blocks. 837system.cpu.dtb_walker_cache.sampled_refs 109072 # Sample count of references to valid blocks. 838system.cpu.dtb_walker_cache.avg_refs 1.282511 # Average number of references to valid blocks. 839system.cpu.dtb_walker_cache.warmup_cycle 5108962066000 # Cycle when the warmup percentage was hit. 840system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.865602 # Average occupied blocks per requestor 841system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.866600 # Average percentage of cache occupancy 842system.cpu.dtb_walker_cache.occ_percent::total 0.866600 # Average percentage of cache occupancy 843system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 139886 # number of ReadReq hits 844system.cpu.dtb_walker_cache.ReadReq_hits::total 139886 # number of ReadReq hits 845system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 139886 # number of demand (read+write) hits 846system.cpu.dtb_walker_cache.demand_hits::total 139886 # number of demand (read+write) hits 847system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 139886 # number of overall hits 848system.cpu.dtb_walker_cache.overall_hits::total 139886 # number of overall hits 849system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 110096 # number of ReadReq misses 850system.cpu.dtb_walker_cache.ReadReq_misses::total 110096 # number of ReadReq misses 851system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 110096 # number of demand (read+write) misses 852system.cpu.dtb_walker_cache.demand_misses::total 110096 # number of demand (read+write) misses 853system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 110096 # number of overall misses 854system.cpu.dtb_walker_cache.overall_misses::total 110096 # number of overall misses 855system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2001823500 # number of ReadReq miss cycles 856system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2001823500 # number of ReadReq miss cycles 857system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2001823500 # number of demand (read+write) miss cycles 858system.cpu.dtb_walker_cache.demand_miss_latency::total 2001823500 # number of demand (read+write) miss cycles 859system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2001823500 # number of overall miss cycles 860system.cpu.dtb_walker_cache.overall_miss_latency::total 2001823500 # number of overall miss cycles 861system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 249982 # number of ReadReq accesses(hits+misses) 862system.cpu.dtb_walker_cache.ReadReq_accesses::total 249982 # number of ReadReq accesses(hits+misses) 863system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 249982 # number of demand (read+write) accesses 864system.cpu.dtb_walker_cache.demand_accesses::total 249982 # number of demand (read+write) accesses 865system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 249982 # number of overall (read+write) accesses 866system.cpu.dtb_walker_cache.overall_accesses::total 249982 # number of overall (read+write) accesses 867system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.440416 # miss rate for ReadReq accesses 868system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.440416 # miss rate for ReadReq accesses 869system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.440416 # miss rate for demand accesses 870system.cpu.dtb_walker_cache.demand_miss_rate::total 0.440416 # miss rate for demand accesses 871system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.440416 # miss rate for overall accesses 872system.cpu.dtb_walker_cache.overall_miss_rate::total 0.440416 # miss rate for overall accesses 873system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 18182.527067 # average ReadReq miss latency 874system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 18182.527067 # average ReadReq miss latency 875system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 18182.527067 # average overall miss latency 876system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 18182.527067 # average overall miss latency 877system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 18182.527067 # average overall miss latency 878system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 18182.527067 # average overall miss latency 879system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 880system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 881system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 882system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 883system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 884system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 885system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 886system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 887system.cpu.dtb_walker_cache.writebacks::writebacks 35215 # number of writebacks 888system.cpu.dtb_walker_cache.writebacks::total 35215 # number of writebacks 889system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 110096 # number of ReadReq MSHR misses 890system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 110096 # number of ReadReq MSHR misses 891system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 110096 # number of demand (read+write) MSHR misses 892system.cpu.dtb_walker_cache.demand_mshr_misses::total 110096 # number of demand (read+write) MSHR misses 893system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 110096 # number of overall MSHR misses 894system.cpu.dtb_walker_cache.overall_mshr_misses::total 110096 # number of overall MSHR misses 895system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1668892003 # number of ReadReq MSHR miss cycles 896system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1668892003 # number of ReadReq MSHR miss cycles 897system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1668892003 # number of demand (read+write) MSHR miss cycles 898system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1668892003 # number of demand (read+write) MSHR miss cycles 899system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1668892003 # number of overall MSHR miss cycles 900system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1668892003 # number of overall MSHR miss cycles 901system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.440416 # mshr miss rate for ReadReq accesses 902system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.440416 # mshr miss rate for ReadReq accesses 903system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.440416 # mshr miss rate for demand accesses 904system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.440416 # mshr miss rate for demand accesses 905system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.440416 # mshr miss rate for overall accesses 906system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.440416 # mshr miss rate for overall accesses 907system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 15158.516231 # average ReadReq mshr miss latency 908system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 15158.516231 # average ReadReq mshr miss latency 909system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 15158.516231 # average overall mshr miss latency 910system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 15158.516231 # average overall mshr miss latency 911system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 15158.516231 # average overall mshr miss latency 912system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 15158.516231 # average overall mshr miss latency 913system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 914system.cpu.dcache.replacements 1672208 # number of replacements 915system.cpu.dcache.tagsinuse 511.998155 # Cycle average of tags in use 916system.cpu.dcache.total_refs 19212274 # Total number of references to valid blocks. 917system.cpu.dcache.sampled_refs 1672720 # Sample count of references to valid blocks. 918system.cpu.dcache.avg_refs 11.485649 # Average number of references to valid blocks. 919system.cpu.dcache.warmup_cycle 35774000 # Cycle when the warmup percentage was hit. 920system.cpu.dcache.occ_blocks::cpu.data 511.998155 # Average occupied blocks per requestor 921system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy 922system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy 923system.cpu.dcache.ReadReq_hits::cpu.data 11127928 # number of ReadReq hits 924system.cpu.dcache.ReadReq_hits::total 11127928 # number of ReadReq hits 925system.cpu.dcache.WriteReq_hits::cpu.data 8079547 # number of WriteReq hits 926system.cpu.dcache.WriteReq_hits::total 8079547 # number of WriteReq hits 927system.cpu.dcache.demand_hits::cpu.data 19207475 # number of demand (read+write) hits 928system.cpu.dcache.demand_hits::total 19207475 # number of demand (read+write) hits 929system.cpu.dcache.overall_hits::cpu.data 19207475 # number of overall hits 930system.cpu.dcache.overall_hits::total 19207475 # number of overall hits 931system.cpu.dcache.ReadReq_misses::cpu.data 2271021 # number of ReadReq misses 932system.cpu.dcache.ReadReq_misses::total 2271021 # number of ReadReq misses 933system.cpu.dcache.WriteReq_misses::cpu.data 318564 # number of WriteReq misses 934system.cpu.dcache.WriteReq_misses::total 318564 # number of WriteReq misses 935system.cpu.dcache.demand_misses::cpu.data 2589585 # number of demand (read+write) misses 936system.cpu.dcache.demand_misses::total 2589585 # number of demand (read+write) misses 937system.cpu.dcache.overall_misses::cpu.data 2589585 # number of overall misses 938system.cpu.dcache.overall_misses::total 2589585 # number of overall misses 939system.cpu.dcache.ReadReq_miss_latency::cpu.data 48812772000 # number of ReadReq miss cycles 940system.cpu.dcache.ReadReq_miss_latency::total 48812772000 # number of ReadReq miss cycles 941system.cpu.dcache.WriteReq_miss_latency::cpu.data 10760956984 # number of WriteReq miss cycles 942system.cpu.dcache.WriteReq_miss_latency::total 10760956984 # number of WriteReq miss cycles 943system.cpu.dcache.demand_miss_latency::cpu.data 59573728984 # number of demand (read+write) miss cycles 944system.cpu.dcache.demand_miss_latency::total 59573728984 # number of demand (read+write) miss cycles 945system.cpu.dcache.overall_miss_latency::cpu.data 59573728984 # number of overall miss cycles 946system.cpu.dcache.overall_miss_latency::total 59573728984 # number of overall miss cycles 947system.cpu.dcache.ReadReq_accesses::cpu.data 13398949 # number of ReadReq accesses(hits+misses) 948system.cpu.dcache.ReadReq_accesses::total 13398949 # number of ReadReq accesses(hits+misses) 949system.cpu.dcache.WriteReq_accesses::cpu.data 8398111 # number of WriteReq accesses(hits+misses) 950system.cpu.dcache.WriteReq_accesses::total 8398111 # number of WriteReq accesses(hits+misses) 951system.cpu.dcache.demand_accesses::cpu.data 21797060 # number of demand (read+write) accesses 952system.cpu.dcache.demand_accesses::total 21797060 # number of demand (read+write) accesses 953system.cpu.dcache.overall_accesses::cpu.data 21797060 # number of overall (read+write) accesses 954system.cpu.dcache.overall_accesses::total 21797060 # number of overall (read+write) accesses 955system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.169492 # miss rate for ReadReq accesses 956system.cpu.dcache.ReadReq_miss_rate::total 0.169492 # miss rate for ReadReq accesses 957system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037933 # miss rate for WriteReq accesses 958system.cpu.dcache.WriteReq_miss_rate::total 0.037933 # miss rate for WriteReq accesses 959system.cpu.dcache.demand_miss_rate::cpu.data 0.118804 # miss rate for demand accesses 960system.cpu.dcache.demand_miss_rate::total 0.118804 # miss rate for demand accesses 961system.cpu.dcache.overall_miss_rate::cpu.data 0.118804 # miss rate for overall accesses 962system.cpu.dcache.overall_miss_rate::total 0.118804 # miss rate for overall accesses 963system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21493.756333 # average ReadReq miss latency 964system.cpu.dcache.ReadReq_avg_miss_latency::total 21493.756333 # average ReadReq miss latency 965system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33779.576424 # average WriteReq miss latency 966system.cpu.dcache.WriteReq_avg_miss_latency::total 33779.576424 # average WriteReq miss latency 967system.cpu.dcache.demand_avg_miss_latency::cpu.data 23005.125912 # average overall miss latency 968system.cpu.dcache.demand_avg_miss_latency::total 23005.125912 # average overall miss latency 969system.cpu.dcache.overall_avg_miss_latency::cpu.data 23005.125912 # average overall miss latency 970system.cpu.dcache.overall_avg_miss_latency::total 23005.125912 # average overall miss latency 971system.cpu.dcache.blocked_cycles::no_mshrs 188289984 # number of cycles access was blocked 972system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 973system.cpu.dcache.blocked::no_mshrs 47618 # number of cycles access was blocked 974system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 975system.cpu.dcache.avg_blocked_cycles::no_mshrs 3954.176656 # average number of cycles each access was blocked 976system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 977system.cpu.dcache.fast_writes 0 # number of fast writes performed 978system.cpu.dcache.cache_copies 0 # number of cache copies performed 979system.cpu.dcache.writebacks::writebacks 1573408 # number of writebacks 980system.cpu.dcache.writebacks::total 1573408 # number of writebacks 981system.cpu.dcache.ReadReq_mshr_hits::cpu.data 886097 # number of ReadReq MSHR hits 982system.cpu.dcache.ReadReq_mshr_hits::total 886097 # number of ReadReq MSHR hits 983system.cpu.dcache.WriteReq_mshr_hits::cpu.data 26577 # number of WriteReq MSHR hits 984system.cpu.dcache.WriteReq_mshr_hits::total 26577 # number of WriteReq MSHR hits 985system.cpu.dcache.demand_mshr_hits::cpu.data 912674 # number of demand (read+write) MSHR hits 986system.cpu.dcache.demand_mshr_hits::total 912674 # number of demand (read+write) MSHR hits 987system.cpu.dcache.overall_mshr_hits::cpu.data 912674 # number of overall MSHR hits 988system.cpu.dcache.overall_mshr_hits::total 912674 # number of overall MSHR hits 989system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1384924 # number of ReadReq MSHR misses 990system.cpu.dcache.ReadReq_mshr_misses::total 1384924 # number of ReadReq MSHR misses 991system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291987 # number of WriteReq MSHR misses 992system.cpu.dcache.WriteReq_mshr_misses::total 291987 # number of WriteReq MSHR misses 993system.cpu.dcache.demand_mshr_misses::cpu.data 1676911 # number of demand (read+write) MSHR misses 994system.cpu.dcache.demand_mshr_misses::total 1676911 # number of demand (read+write) MSHR misses 995system.cpu.dcache.overall_mshr_misses::cpu.data 1676911 # number of overall MSHR misses 996system.cpu.dcache.overall_mshr_misses::total 1676911 # number of overall MSHR misses 997system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25980128023 # number of ReadReq MSHR miss cycles 998system.cpu.dcache.ReadReq_mshr_miss_latency::total 25980128023 # number of ReadReq MSHR miss cycles 999system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9456082986 # number of WriteReq MSHR miss cycles 1000system.cpu.dcache.WriteReq_mshr_miss_latency::total 9456082986 # number of WriteReq MSHR miss cycles 1001system.cpu.dcache.demand_mshr_miss_latency::cpu.data 35436211009 # number of demand (read+write) MSHR miss cycles 1002system.cpu.dcache.demand_mshr_miss_latency::total 35436211009 # number of demand (read+write) MSHR miss cycles 1003system.cpu.dcache.overall_mshr_miss_latency::cpu.data 35436211009 # number of overall MSHR miss cycles 1004system.cpu.dcache.overall_mshr_miss_latency::total 35436211009 # number of overall MSHR miss cycles 1005system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 96735395500 # number of ReadReq MSHR uncacheable cycles 1006system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 96735395500 # number of ReadReq MSHR uncacheable cycles 1007system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2475863500 # number of WriteReq MSHR uncacheable cycles 1008system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2475863500 # number of WriteReq MSHR uncacheable cycles 1009system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99211259000 # number of overall MSHR uncacheable cycles 1010system.cpu.dcache.overall_mshr_uncacheable_latency::total 99211259000 # number of overall MSHR uncacheable cycles 1011system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103361 # mshr miss rate for ReadReq accesses 1012system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103361 # mshr miss rate for ReadReq accesses 1013system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034768 # mshr miss rate for WriteReq accesses 1014system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034768 # mshr miss rate for WriteReq accesses 1015system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076933 # mshr miss rate for demand accesses 1016system.cpu.dcache.demand_mshr_miss_rate::total 0.076933 # mshr miss rate for demand accesses 1017system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076933 # mshr miss rate for overall accesses 1018system.cpu.dcache.overall_mshr_miss_rate::total 0.076933 # mshr miss rate for overall accesses 1019system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18759.244567 # average ReadReq mshr miss latency 1020system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18759.244567 # average ReadReq mshr miss latency 1021system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32385.287653 # average WriteReq mshr miss latency 1022system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32385.287653 # average WriteReq mshr miss latency 1023system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21131.837652 # average overall mshr miss latency 1024system.cpu.dcache.demand_avg_mshr_miss_latency::total 21131.837652 # average overall mshr miss latency 1025system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21131.837652 # average overall mshr miss latency 1026system.cpu.dcache.overall_avg_mshr_miss_latency::total 21131.837652 # average overall mshr miss latency 1027system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1028system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1029system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1030system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1031system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1032system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1033system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1034system.cpu.kern.inst.arm 0 # number of arm instructions executed 1035system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1036 1037---------- End Simulation Statistics ---------- 1038