stats.txt revision 9039:9a22621c741c
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.157514 # Number of seconds simulated 4sim_ticks 5157514159500 # Number of ticks simulated 5final_tick 5157514159500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 128842 # Simulator instruction rate (inst/s) 8host_op_rate 253899 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1558019011 # Simulator tick rate (ticks/s) 10host_mem_usage 389972 # Number of bytes of host memory used 11host_seconds 3310.30 # Real time elapsed on the host 12sim_insts 426506235 # Number of instructions simulated 13sim_ops 840483958 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 15959488 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 1257664 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 12050112 # Number of bytes written to this memory 17system.physmem.num_reads 249367 # Number of read requests responded to by this memory 18system.physmem.num_writes 188283 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 3094415 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 243851 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 2336419 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 5430833 # Total bandwidth to/from this memory (bytes/s) 24system.l2c.replacements 167142 # number of replacements 25system.l2c.tagsinuse 37816.689690 # Cycle average of tags in use 26system.l2c.total_refs 3843284 # Total number of references to valid blocks. 27system.l2c.sampled_refs 202399 # Sample count of references to valid blocks. 28system.l2c.avg_refs 18.988651 # Average number of references to valid blocks. 29system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. 30system.l2c.occ_blocks::writebacks 26702.073389 # Average occupied blocks per requestor 31system.l2c.occ_blocks::cpu.dtb.walker 8.025761 # Average occupied blocks per requestor 32system.l2c.occ_blocks::cpu.itb.walker 0.043125 # Average occupied blocks per requestor 33system.l2c.occ_blocks::cpu.inst 2426.285000 # Average occupied blocks per requestor 34system.l2c.occ_blocks::cpu.data 8680.262415 # Average occupied blocks per requestor 35system.l2c.occ_percent::writebacks 0.407441 # Average percentage of cache occupancy 36system.l2c.occ_percent::cpu.dtb.walker 0.000122 # Average percentage of cache occupancy 37system.l2c.occ_percent::cpu.itb.walker 0.000001 # Average percentage of cache occupancy 38system.l2c.occ_percent::cpu.inst 0.037022 # Average percentage of cache occupancy 39system.l2c.occ_percent::cpu.data 0.132450 # Average percentage of cache occupancy 40system.l2c.occ_percent::total 0.577037 # Average percentage of cache occupancy 41system.l2c.ReadReq_hits::cpu.dtb.walker 109565 # number of ReadReq hits 42system.l2c.ReadReq_hits::cpu.itb.walker 8804 # number of ReadReq hits 43system.l2c.ReadReq_hits::cpu.inst 1063948 # number of ReadReq hits 44system.l2c.ReadReq_hits::cpu.data 1334758 # number of ReadReq hits 45system.l2c.ReadReq_hits::total 2517075 # number of ReadReq hits 46system.l2c.Writeback_hits::writebacks 1600724 # number of Writeback hits 47system.l2c.Writeback_hits::total 1600724 # number of Writeback hits 48system.l2c.UpgradeReq_hits::cpu.data 336 # number of UpgradeReq hits 49system.l2c.UpgradeReq_hits::total 336 # number of UpgradeReq hits 50system.l2c.ReadExReq_hits::cpu.data 151728 # number of ReadExReq hits 51system.l2c.ReadExReq_hits::total 151728 # number of ReadExReq hits 52system.l2c.demand_hits::cpu.dtb.walker 109565 # number of demand (read+write) hits 53system.l2c.demand_hits::cpu.itb.walker 8804 # number of demand (read+write) hits 54system.l2c.demand_hits::cpu.inst 1063948 # number of demand (read+write) hits 55system.l2c.demand_hits::cpu.data 1486486 # number of demand (read+write) hits 56system.l2c.demand_hits::total 2668803 # number of demand (read+write) hits 57system.l2c.overall_hits::cpu.dtb.walker 109565 # number of overall hits 58system.l2c.overall_hits::cpu.itb.walker 8804 # number of overall hits 59system.l2c.overall_hits::cpu.inst 1063948 # number of overall hits 60system.l2c.overall_hits::cpu.data 1486486 # number of overall hits 61system.l2c.overall_hits::total 2668803 # number of overall hits 62system.l2c.ReadReq_misses::cpu.dtb.walker 105 # number of ReadReq misses 63system.l2c.ReadReq_misses::cpu.itb.walker 17 # number of ReadReq misses 64system.l2c.ReadReq_misses::cpu.inst 19652 # number of ReadReq misses 65system.l2c.ReadReq_misses::cpu.data 45660 # number of ReadReq misses 66system.l2c.ReadReq_misses::total 65434 # number of ReadReq misses 67system.l2c.UpgradeReq_misses::cpu.data 2521 # number of UpgradeReq misses 68system.l2c.UpgradeReq_misses::total 2521 # number of UpgradeReq misses 69system.l2c.ReadExReq_misses::cpu.data 141129 # number of ReadExReq misses 70system.l2c.ReadExReq_misses::total 141129 # number of ReadExReq misses 71system.l2c.demand_misses::cpu.dtb.walker 105 # number of demand (read+write) misses 72system.l2c.demand_misses::cpu.itb.walker 17 # number of demand (read+write) misses 73system.l2c.demand_misses::cpu.inst 19652 # number of demand (read+write) misses 74system.l2c.demand_misses::cpu.data 186789 # number of demand (read+write) misses 75system.l2c.demand_misses::total 206563 # number of demand (read+write) misses 76system.l2c.overall_misses::cpu.dtb.walker 105 # number of overall misses 77system.l2c.overall_misses::cpu.itb.walker 17 # number of overall misses 78system.l2c.overall_misses::cpu.inst 19652 # number of overall misses 79system.l2c.overall_misses::cpu.data 186789 # number of overall misses 80system.l2c.overall_misses::total 206563 # number of overall misses 81system.l2c.ReadReq_miss_latency::cpu.dtb.walker 5480500 # number of ReadReq miss cycles 82system.l2c.ReadReq_miss_latency::cpu.itb.walker 886000 # number of ReadReq miss cycles 83system.l2c.ReadReq_miss_latency::cpu.inst 1027000000 # number of ReadReq miss cycles 84system.l2c.ReadReq_miss_latency::cpu.data 2399872000 # number of ReadReq miss cycles 85system.l2c.ReadReq_miss_latency::total 3433238500 # number of ReadReq miss cycles 86system.l2c.UpgradeReq_miss_latency::cpu.data 39054500 # number of UpgradeReq miss cycles 87system.l2c.UpgradeReq_miss_latency::total 39054500 # number of UpgradeReq miss cycles 88system.l2c.ReadExReq_miss_latency::cpu.data 7349617000 # number of ReadExReq miss cycles 89system.l2c.ReadExReq_miss_latency::total 7349617000 # number of ReadExReq miss cycles 90system.l2c.demand_miss_latency::cpu.dtb.walker 5480500 # number of demand (read+write) miss cycles 91system.l2c.demand_miss_latency::cpu.itb.walker 886000 # number of demand (read+write) miss cycles 92system.l2c.demand_miss_latency::cpu.inst 1027000000 # number of demand (read+write) miss cycles 93system.l2c.demand_miss_latency::cpu.data 9749489000 # number of demand (read+write) miss cycles 94system.l2c.demand_miss_latency::total 10782855500 # number of demand (read+write) miss cycles 95system.l2c.overall_miss_latency::cpu.dtb.walker 5480500 # number of overall miss cycles 96system.l2c.overall_miss_latency::cpu.itb.walker 886000 # number of overall miss cycles 97system.l2c.overall_miss_latency::cpu.inst 1027000000 # number of overall miss cycles 98system.l2c.overall_miss_latency::cpu.data 9749489000 # number of overall miss cycles 99system.l2c.overall_miss_latency::total 10782855500 # number of overall miss cycles 100system.l2c.ReadReq_accesses::cpu.dtb.walker 109670 # number of ReadReq accesses(hits+misses) 101system.l2c.ReadReq_accesses::cpu.itb.walker 8821 # number of ReadReq accesses(hits+misses) 102system.l2c.ReadReq_accesses::cpu.inst 1083600 # number of ReadReq accesses(hits+misses) 103system.l2c.ReadReq_accesses::cpu.data 1380418 # number of ReadReq accesses(hits+misses) 104system.l2c.ReadReq_accesses::total 2582509 # number of ReadReq accesses(hits+misses) 105system.l2c.Writeback_accesses::writebacks 1600724 # number of Writeback accesses(hits+misses) 106system.l2c.Writeback_accesses::total 1600724 # number of Writeback accesses(hits+misses) 107system.l2c.UpgradeReq_accesses::cpu.data 2857 # number of UpgradeReq accesses(hits+misses) 108system.l2c.UpgradeReq_accesses::total 2857 # number of UpgradeReq accesses(hits+misses) 109system.l2c.ReadExReq_accesses::cpu.data 292857 # number of ReadExReq accesses(hits+misses) 110system.l2c.ReadExReq_accesses::total 292857 # number of ReadExReq accesses(hits+misses) 111system.l2c.demand_accesses::cpu.dtb.walker 109670 # number of demand (read+write) accesses 112system.l2c.demand_accesses::cpu.itb.walker 8821 # number of demand (read+write) accesses 113system.l2c.demand_accesses::cpu.inst 1083600 # number of demand (read+write) accesses 114system.l2c.demand_accesses::cpu.data 1673275 # number of demand (read+write) accesses 115system.l2c.demand_accesses::total 2875366 # number of demand (read+write) accesses 116system.l2c.overall_accesses::cpu.dtb.walker 109670 # number of overall (read+write) accesses 117system.l2c.overall_accesses::cpu.itb.walker 8821 # number of overall (read+write) accesses 118system.l2c.overall_accesses::cpu.inst 1083600 # number of overall (read+write) accesses 119system.l2c.overall_accesses::cpu.data 1673275 # number of overall (read+write) accesses 120system.l2c.overall_accesses::total 2875366 # number of overall (read+write) accesses 121system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000957 # miss rate for ReadReq accesses 122system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001927 # miss rate for ReadReq accesses 123system.l2c.ReadReq_miss_rate::cpu.inst 0.018136 # miss rate for ReadReq accesses 124system.l2c.ReadReq_miss_rate::cpu.data 0.033077 # miss rate for ReadReq accesses 125system.l2c.UpgradeReq_miss_rate::cpu.data 0.882394 # miss rate for UpgradeReq accesses 126system.l2c.ReadExReq_miss_rate::cpu.data 0.481904 # miss rate for ReadExReq accesses 127system.l2c.demand_miss_rate::cpu.dtb.walker 0.000957 # miss rate for demand accesses 128system.l2c.demand_miss_rate::cpu.itb.walker 0.001927 # miss rate for demand accesses 129system.l2c.demand_miss_rate::cpu.inst 0.018136 # miss rate for demand accesses 130system.l2c.demand_miss_rate::cpu.data 0.111631 # miss rate for demand accesses 131system.l2c.overall_miss_rate::cpu.dtb.walker 0.000957 # miss rate for overall accesses 132system.l2c.overall_miss_rate::cpu.itb.walker 0.001927 # miss rate for overall accesses 133system.l2c.overall_miss_rate::cpu.inst 0.018136 # miss rate for overall accesses 134system.l2c.overall_miss_rate::cpu.data 0.111631 # miss rate for overall accesses 135system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52195.238095 # average ReadReq miss latency 136system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52117.647059 # average ReadReq miss latency 137system.l2c.ReadReq_avg_miss_latency::cpu.inst 52259.312029 # average ReadReq miss latency 138system.l2c.ReadReq_avg_miss_latency::cpu.data 52559.614542 # average ReadReq miss latency 139system.l2c.UpgradeReq_avg_miss_latency::cpu.data 15491.669972 # average UpgradeReq miss latency 140system.l2c.ReadExReq_avg_miss_latency::cpu.data 52077.298075 # average ReadExReq miss latency 141system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52195.238095 # average overall miss latency 142system.l2c.demand_avg_miss_latency::cpu.itb.walker 52117.647059 # average overall miss latency 143system.l2c.demand_avg_miss_latency::cpu.inst 52259.312029 # average overall miss latency 144system.l2c.demand_avg_miss_latency::cpu.data 52195.198861 # average overall miss latency 145system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52195.238095 # average overall miss latency 146system.l2c.overall_avg_miss_latency::cpu.itb.walker 52117.647059 # average overall miss latency 147system.l2c.overall_avg_miss_latency::cpu.inst 52259.312029 # average overall miss latency 148system.l2c.overall_avg_miss_latency::cpu.data 52195.198861 # average overall miss latency 149system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 150system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 151system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 152system.l2c.blocked::no_targets 0 # number of cycles access was blocked 153system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 154system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 155system.l2c.fast_writes 0 # number of fast writes performed 156system.l2c.cache_copies 0 # number of cache copies performed 157system.l2c.writebacks::writebacks 141616 # number of writebacks 158system.l2c.writebacks::total 141616 # number of writebacks 159system.l2c.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 160system.l2c.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 161system.l2c.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits 162system.l2c.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 163system.l2c.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 164system.l2c.demand_mshr_hits::total 2 # number of demand (read+write) MSHR hits 165system.l2c.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 166system.l2c.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 167system.l2c.overall_mshr_hits::total 2 # number of overall MSHR hits 168system.l2c.ReadReq_mshr_misses::cpu.dtb.walker 105 # number of ReadReq MSHR misses 169system.l2c.ReadReq_mshr_misses::cpu.itb.walker 17 # number of ReadReq MSHR misses 170system.l2c.ReadReq_mshr_misses::cpu.inst 19651 # number of ReadReq MSHR misses 171system.l2c.ReadReq_mshr_misses::cpu.data 45659 # number of ReadReq MSHR misses 172system.l2c.ReadReq_mshr_misses::total 65432 # number of ReadReq MSHR misses 173system.l2c.UpgradeReq_mshr_misses::cpu.data 2521 # number of UpgradeReq MSHR misses 174system.l2c.UpgradeReq_mshr_misses::total 2521 # number of UpgradeReq MSHR misses 175system.l2c.ReadExReq_mshr_misses::cpu.data 141129 # number of ReadExReq MSHR misses 176system.l2c.ReadExReq_mshr_misses::total 141129 # number of ReadExReq MSHR misses 177system.l2c.demand_mshr_misses::cpu.dtb.walker 105 # number of demand (read+write) MSHR misses 178system.l2c.demand_mshr_misses::cpu.itb.walker 17 # number of demand (read+write) MSHR misses 179system.l2c.demand_mshr_misses::cpu.inst 19651 # number of demand (read+write) MSHR misses 180system.l2c.demand_mshr_misses::cpu.data 186788 # number of demand (read+write) MSHR misses 181system.l2c.demand_mshr_misses::total 206561 # number of demand (read+write) MSHR misses 182system.l2c.overall_mshr_misses::cpu.dtb.walker 105 # number of overall MSHR misses 183system.l2c.overall_mshr_misses::cpu.itb.walker 17 # number of overall MSHR misses 184system.l2c.overall_mshr_misses::cpu.inst 19651 # number of overall MSHR misses 185system.l2c.overall_mshr_misses::cpu.data 186788 # number of overall MSHR misses 186system.l2c.overall_mshr_misses::total 206561 # number of overall MSHR misses 187system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 4210000 # number of ReadReq MSHR miss cycles 188system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 680000 # number of ReadReq MSHR miss cycles 189system.l2c.ReadReq_mshr_miss_latency::cpu.inst 786943000 # number of ReadReq MSHR miss cycles 190system.l2c.ReadReq_mshr_miss_latency::cpu.data 1841762000 # number of ReadReq MSHR miss cycles 191system.l2c.ReadReq_mshr_miss_latency::total 2633595000 # number of ReadReq MSHR miss cycles 192system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 101204500 # number of UpgradeReq MSHR miss cycles 193system.l2c.UpgradeReq_mshr_miss_latency::total 101204500 # number of UpgradeReq MSHR miss cycles 194system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5646584500 # number of ReadExReq MSHR miss cycles 195system.l2c.ReadExReq_mshr_miss_latency::total 5646584500 # number of ReadExReq MSHR miss cycles 196system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 4210000 # number of demand (read+write) MSHR miss cycles 197system.l2c.demand_mshr_miss_latency::cpu.itb.walker 680000 # number of demand (read+write) MSHR miss cycles 198system.l2c.demand_mshr_miss_latency::cpu.inst 786943000 # number of demand (read+write) MSHR miss cycles 199system.l2c.demand_mshr_miss_latency::cpu.data 7488346500 # number of demand (read+write) MSHR miss cycles 200system.l2c.demand_mshr_miss_latency::total 8280179500 # number of demand (read+write) MSHR miss cycles 201system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 4210000 # number of overall MSHR miss cycles 202system.l2c.overall_mshr_miss_latency::cpu.itb.walker 680000 # number of overall MSHR miss cycles 203system.l2c.overall_mshr_miss_latency::cpu.inst 786943000 # number of overall MSHR miss cycles 204system.l2c.overall_mshr_miss_latency::cpu.data 7488346500 # number of overall MSHR miss cycles 205system.l2c.overall_mshr_miss_latency::total 8280179500 # number of overall MSHR miss cycles 206system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 59975402500 # number of ReadReq MSHR uncacheable cycles 207system.l2c.ReadReq_mshr_uncacheable_latency::total 59975402500 # number of ReadReq MSHR uncacheable cycles 208system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1229367500 # number of WriteReq MSHR uncacheable cycles 209system.l2c.WriteReq_mshr_uncacheable_latency::total 1229367500 # number of WriteReq MSHR uncacheable cycles 210system.l2c.overall_mshr_uncacheable_latency::cpu.data 61204770000 # number of overall MSHR uncacheable cycles 211system.l2c.overall_mshr_uncacheable_latency::total 61204770000 # number of overall MSHR uncacheable cycles 212system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000957 # mshr miss rate for ReadReq accesses 213system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001927 # mshr miss rate for ReadReq accesses 214system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.018135 # mshr miss rate for ReadReq accesses 215system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.033076 # mshr miss rate for ReadReq accesses 216system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.882394 # mshr miss rate for UpgradeReq accesses 217system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.481904 # mshr miss rate for ReadExReq accesses 218system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000957 # mshr miss rate for demand accesses 219system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001927 # mshr miss rate for demand accesses 220system.l2c.demand_mshr_miss_rate::cpu.inst 0.018135 # mshr miss rate for demand accesses 221system.l2c.demand_mshr_miss_rate::cpu.data 0.111630 # mshr miss rate for demand accesses 222system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000957 # mshr miss rate for overall accesses 223system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001927 # mshr miss rate for overall accesses 224system.l2c.overall_mshr_miss_rate::cpu.inst 0.018135 # mshr miss rate for overall accesses 225system.l2c.overall_mshr_miss_rate::cpu.data 0.111630 # mshr miss rate for overall accesses 226system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095 # average ReadReq mshr miss latency 227system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency 228system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.951860 # average ReadReq mshr miss latency 229system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40337.326704 # average ReadReq mshr miss latency 230system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40144.585482 # average UpgradeReq mshr miss latency 231system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40010.093602 # average ReadExReq mshr miss latency 232system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095 # average overall mshr miss latency 233system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 234system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40045.951860 # average overall mshr miss latency 235system.l2c.demand_avg_mshr_miss_latency::cpu.data 40090.083410 # average overall mshr miss latency 236system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40095.238095 # average overall mshr miss latency 237system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency 238system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40045.951860 # average overall mshr miss latency 239system.l2c.overall_avg_mshr_miss_latency::cpu.data 40090.083410 # average overall mshr miss latency 240system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 241system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 242system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 243system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 244system.iocache.replacements 47578 # number of replacements 245system.iocache.tagsinuse 0.166155 # Cycle average of tags in use 246system.iocache.total_refs 0 # Total number of references to valid blocks. 247system.iocache.sampled_refs 47594 # Sample count of references to valid blocks. 248system.iocache.avg_refs 0 # Average number of references to valid blocks. 249system.iocache.warmup_cycle 4996370640000 # Cycle when the warmup percentage was hit. 250system.iocache.occ_blocks::pc.south_bridge.ide 0.166155 # Average occupied blocks per requestor 251system.iocache.occ_percent::pc.south_bridge.ide 0.010385 # Average percentage of cache occupancy 252system.iocache.occ_percent::total 0.010385 # Average percentage of cache occupancy 253system.iocache.ReadReq_misses::pc.south_bridge.ide 913 # number of ReadReq misses 254system.iocache.ReadReq_misses::total 913 # number of ReadReq misses 255system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses 256system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses 257system.iocache.demand_misses::pc.south_bridge.ide 47633 # number of demand (read+write) misses 258system.iocache.demand_misses::total 47633 # number of demand (read+write) misses 259system.iocache.overall_misses::pc.south_bridge.ide 47633 # number of overall misses 260system.iocache.overall_misses::total 47633 # number of overall misses 261system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 114379932 # number of ReadReq miss cycles 262system.iocache.ReadReq_miss_latency::total 114379932 # number of ReadReq miss cycles 263system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6373400160 # number of WriteReq miss cycles 264system.iocache.WriteReq_miss_latency::total 6373400160 # number of WriteReq miss cycles 265system.iocache.demand_miss_latency::pc.south_bridge.ide 6487780092 # number of demand (read+write) miss cycles 266system.iocache.demand_miss_latency::total 6487780092 # number of demand (read+write) miss cycles 267system.iocache.overall_miss_latency::pc.south_bridge.ide 6487780092 # number of overall miss cycles 268system.iocache.overall_miss_latency::total 6487780092 # number of overall miss cycles 269system.iocache.ReadReq_accesses::pc.south_bridge.ide 913 # number of ReadReq accesses(hits+misses) 270system.iocache.ReadReq_accesses::total 913 # number of ReadReq accesses(hits+misses) 271system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses) 272system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses) 273system.iocache.demand_accesses::pc.south_bridge.ide 47633 # number of demand (read+write) accesses 274system.iocache.demand_accesses::total 47633 # number of demand (read+write) accesses 275system.iocache.overall_accesses::pc.south_bridge.ide 47633 # number of overall (read+write) accesses 276system.iocache.overall_accesses::total 47633 # number of overall (read+write) accesses 277system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 278system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses 279system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 280system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 281system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 125279.224535 # average ReadReq miss latency 282system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136416.955479 # average WriteReq miss latency 283system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136203.474314 # average overall miss latency 284system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136203.474314 # average overall miss latency 285system.iocache.blocked_cycles::no_mshrs 69025534 # number of cycles access was blocked 286system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 287system.iocache.blocked::no_mshrs 11269 # number of cycles access was blocked 288system.iocache.blocked::no_targets 0 # number of cycles access was blocked 289system.iocache.avg_blocked_cycles::no_mshrs 6125.258142 # average number of cycles each access was blocked 290system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 291system.iocache.fast_writes 0 # number of fast writes performed 292system.iocache.cache_copies 0 # number of cache copies performed 293system.iocache.writebacks::writebacks 46667 # number of writebacks 294system.iocache.writebacks::total 46667 # number of writebacks 295system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 913 # number of ReadReq MSHR misses 296system.iocache.ReadReq_mshr_misses::total 913 # number of ReadReq MSHR misses 297system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses 298system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses 299system.iocache.demand_mshr_misses::pc.south_bridge.ide 47633 # number of demand (read+write) MSHR misses 300system.iocache.demand_mshr_misses::total 47633 # number of demand (read+write) MSHR misses 301system.iocache.overall_mshr_misses::pc.south_bridge.ide 47633 # number of overall MSHR misses 302system.iocache.overall_mshr_misses::total 47633 # number of overall MSHR misses 303system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 66880982 # number of ReadReq MSHR miss cycles 304system.iocache.ReadReq_mshr_miss_latency::total 66880982 # number of ReadReq MSHR miss cycles 305system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 3943643878 # number of WriteReq MSHR miss cycles 306system.iocache.WriteReq_mshr_miss_latency::total 3943643878 # number of WriteReq MSHR miss cycles 307system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4010524860 # number of demand (read+write) MSHR miss cycles 308system.iocache.demand_mshr_miss_latency::total 4010524860 # number of demand (read+write) MSHR miss cycles 309system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4010524860 # number of overall MSHR miss cycles 310system.iocache.overall_mshr_miss_latency::total 4010524860 # number of overall MSHR miss cycles 311system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 312system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses 313system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 314system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 315system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 73254.087623 # average ReadReq mshr miss latency 316system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84410.185745 # average WriteReq mshr miss latency 317system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84196.352529 # average overall mshr miss latency 318system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84196.352529 # average overall mshr miss latency 319system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 320system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 321system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 322system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). 323system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 324system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 325system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 326system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 327system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 328system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 329system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 330system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 331system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 332system.cpu.numCycles 461333918 # number of cpu cycles simulated 333system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 334system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 335system.cpu.BPredUnit.lookups 90003796 # Number of BP lookups 336system.cpu.BPredUnit.condPredicted 90003796 # Number of conditional branches predicted 337system.cpu.BPredUnit.condIncorrect 1173183 # Number of conditional branches incorrect 338system.cpu.BPredUnit.BTBLookups 84315614 # Number of BTB lookups 339system.cpu.BPredUnit.BTBHits 81694619 # Number of BTB hits 340system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 341system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. 342system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. 343system.cpu.fetch.icacheStallCycles 29624871 # Number of cycles fetch is stalled on an Icache miss 344system.cpu.fetch.Insts 446885817 # Number of instructions fetch has processed 345system.cpu.fetch.Branches 90003796 # Number of branches that fetch encountered 346system.cpu.fetch.predictedBranches 81694619 # Number of branches that fetch has predicted taken 347system.cpu.fetch.Cycles 169759235 # Number of cycles fetch has run and was not squashing or blocked 348system.cpu.fetch.SquashCycles 5280537 # Number of cycles fetch has spent squashing 349system.cpu.fetch.TlbCycles 141697 # Number of cycles fetch has spent waiting for tlb 350system.cpu.fetch.BlockedCycles 98681847 # Number of cycles fetch has spent blocked 351system.cpu.fetch.MiscStallCycles 37486 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 352system.cpu.fetch.PendingTrapStallCycles 37869 # Number of stall cycles due to pending traps 353system.cpu.fetch.IcacheWaitRetryStallCycles 332 # Number of stall cycles due to full MSHR 354system.cpu.fetch.CacheLines 9366803 # Number of cache lines fetched 355system.cpu.fetch.IcacheSquashes 526850 # Number of outstanding Icache misses that were squashed 356system.cpu.fetch.ItlbSquashes 4968 # Number of outstanding ITLB misses that were squashed 357system.cpu.fetch.rateDist::samples 302354351 # Number of instructions fetched each cycle (Total) 358system.cpu.fetch.rateDist::mean 2.908315 # Number of instructions fetched each cycle (Total) 359system.cpu.fetch.rateDist::stdev 3.388599 # Number of instructions fetched each cycle (Total) 360system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 361system.cpu.fetch.rateDist::0 133032171 44.00% 44.00% # Number of instructions fetched each cycle (Total) 362system.cpu.fetch.rateDist::1 1767192 0.58% 44.58% # Number of instructions fetched each cycle (Total) 363system.cpu.fetch.rateDist::2 72774261 24.07% 68.65% # Number of instructions fetched each cycle (Total) 364system.cpu.fetch.rateDist::3 988290 0.33% 68.98% # Number of instructions fetched each cycle (Total) 365system.cpu.fetch.rateDist::4 1636300 0.54% 69.52% # Number of instructions fetched each cycle (Total) 366system.cpu.fetch.rateDist::5 3666710 1.21% 70.73% # Number of instructions fetched each cycle (Total) 367system.cpu.fetch.rateDist::6 1141173 0.38% 71.11% # Number of instructions fetched each cycle (Total) 368system.cpu.fetch.rateDist::7 1450765 0.48% 71.59% # Number of instructions fetched each cycle (Total) 369system.cpu.fetch.rateDist::8 85897489 28.41% 100.00% # Number of instructions fetched each cycle (Total) 370system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 371system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 372system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 373system.cpu.fetch.rateDist::total 302354351 # Number of instructions fetched each cycle (Total) 374system.cpu.fetch.branchRate 0.195095 # Number of branch fetches per cycle 375system.cpu.fetch.rate 0.968682 # Number of inst fetches per cycle 376system.cpu.decode.IdleCycles 34659888 # Number of cycles decode is idle 377system.cpu.decode.BlockedCycles 94852238 # Number of cycles decode is blocked 378system.cpu.decode.RunCycles 163950875 # Number of cycles decode is running 379system.cpu.decode.UnblockCycles 4820336 # Number of cycles decode is unblocking 380system.cpu.decode.SquashCycles 4071014 # Number of cycles decode is squashing 381system.cpu.decode.DecodedInsts 876062076 # Number of instructions handled by decode 382system.cpu.decode.SquashedInsts 946 # Number of squashed instructions handled by decode 383system.cpu.rename.SquashCycles 4071014 # Number of cycles rename is squashing 384system.cpu.rename.IdleCycles 38916721 # Number of cycles rename is idle 385system.cpu.rename.BlockCycles 39863124 # Number of cycles rename is blocking 386system.cpu.rename.serializeStallCycles 10415671 # count of cycles rename stalled for serializing inst 387system.cpu.rename.RunCycles 164017891 # Number of cycles rename is running 388system.cpu.rename.UnblockCycles 45069930 # Number of cycles rename is unblocking 389system.cpu.rename.RenamedInsts 872218550 # Number of instructions processed by rename 390system.cpu.rename.ROBFullEvents 9888 # Number of times rename has blocked due to ROB full 391system.cpu.rename.IQFullEvents 34551329 # Number of times rename has blocked due to IQ full 392system.cpu.rename.LSQFullEvents 3873333 # Number of times rename has blocked due to LSQ full 393system.cpu.rename.FullRegisterEvents 31844673 # Number of times there has been no free registers 394system.cpu.rename.RenamedOperands 1393807250 # Number of destination operands rename has renamed 395system.cpu.rename.RenameLookups 2487751490 # Number of register rename lookups that rename has made 396system.cpu.rename.int_rename_lookups 2487750754 # Number of integer rename lookups 397system.cpu.rename.fp_rename_lookups 736 # Number of floating rename lookups 398system.cpu.rename.CommittedMaps 1347499622 # Number of HB maps that are committed 399system.cpu.rename.UndoneMaps 46307621 # Number of HB maps that are undone due to squashing 400system.cpu.rename.serializingInsts 471559 # count of serializing insts renamed 401system.cpu.rename.tempSerializingInsts 478592 # count of temporary serializing insts renamed 402system.cpu.rename.skidInsts 46419855 # count of insts added to the skid buffer 403system.cpu.memDep0.insertedLoads 18887370 # Number of loads inserted to the mem dependence unit. 404system.cpu.memDep0.insertedStores 10441908 # Number of stores inserted to the mem dependence unit. 405system.cpu.memDep0.conflictingLoads 1295912 # Number of conflicting loads. 406system.cpu.memDep0.conflictingStores 1023550 # Number of conflicting stores. 407system.cpu.iq.iqInstsAdded 865497785 # Number of instructions added to the IQ (excludes non-spec) 408system.cpu.iq.iqNonSpecInstsAdded 1720774 # Number of non-speculative instructions added to the IQ 409system.cpu.iq.iqInstsIssued 864256485 # Number of instructions issued 410system.cpu.iq.iqSquashedInstsIssued 112298 # Number of squashed instructions issued 411system.cpu.iq.iqSquashedInstsExamined 25797308 # Number of squashed instructions iterated over during squash; mainly for profiling 412system.cpu.iq.iqSquashedOperandsExamined 52868100 # Number of squashed operands that are examined and possibly removed from graph 413system.cpu.iq.iqSquashedNonSpecRemoved 205226 # Number of squashed non-spec instructions that were removed 414system.cpu.iq.issued_per_cycle::samples 302354351 # Number of insts issued each cycle 415system.cpu.iq.issued_per_cycle::mean 2.858423 # Number of insts issued each cycle 416system.cpu.iq.issued_per_cycle::stdev 2.389396 # Number of insts issued each cycle 417system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 418system.cpu.iq.issued_per_cycle::0 95961753 31.74% 31.74% # Number of insts issued each cycle 419system.cpu.iq.issued_per_cycle::1 22210791 7.35% 39.08% # Number of insts issued each cycle 420system.cpu.iq.issued_per_cycle::2 18920489 6.26% 45.34% # Number of insts issued each cycle 421system.cpu.iq.issued_per_cycle::3 7861035 2.60% 47.94% # Number of insts issued each cycle 422system.cpu.iq.issued_per_cycle::4 80643891 26.67% 74.61% # Number of insts issued each cycle 423system.cpu.iq.issued_per_cycle::5 3288348 1.09% 75.70% # Number of insts issued each cycle 424system.cpu.iq.issued_per_cycle::6 72804040 24.08% 99.78% # Number of insts issued each cycle 425system.cpu.iq.issued_per_cycle::7 531965 0.18% 99.96% # Number of insts issued each cycle 426system.cpu.iq.issued_per_cycle::8 132039 0.04% 100.00% # Number of insts issued each cycle 427system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 428system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 429system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 430system.cpu.iq.issued_per_cycle::total 302354351 # Number of insts issued each cycle 431system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 432system.cpu.iq.fu_full::IntAlu 168781 8.00% 8.00% # attempts to use FU when none available 433system.cpu.iq.fu_full::IntMult 0 0.00% 8.00% # attempts to use FU when none available 434system.cpu.iq.fu_full::IntDiv 0 0.00% 8.00% # attempts to use FU when none available 435system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.00% # attempts to use FU when none available 436system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.00% # attempts to use FU when none available 437system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.00% # attempts to use FU when none available 438system.cpu.iq.fu_full::FloatMult 0 0.00% 8.00% # attempts to use FU when none available 439system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.00% # attempts to use FU when none available 440system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.00% # attempts to use FU when none available 441system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.00% # attempts to use FU when none available 442system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.00% # attempts to use FU when none available 443system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.00% # attempts to use FU when none available 444system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.00% # attempts to use FU when none available 445system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.00% # attempts to use FU when none available 446system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.00% # attempts to use FU when none available 447system.cpu.iq.fu_full::SimdMult 0 0.00% 8.00% # attempts to use FU when none available 448system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.00% # attempts to use FU when none available 449system.cpu.iq.fu_full::SimdShift 0 0.00% 8.00% # attempts to use FU when none available 450system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.00% # attempts to use FU when none available 451system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.00% # attempts to use FU when none available 452system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.00% # attempts to use FU when none available 453system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.00% # attempts to use FU when none available 454system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.00% # attempts to use FU when none available 455system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.00% # attempts to use FU when none available 456system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.00% # attempts to use FU when none available 457system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.00% # attempts to use FU when none available 458system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.00% # attempts to use FU when none available 459system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.00% # attempts to use FU when none available 460system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.00% # attempts to use FU when none available 461system.cpu.iq.fu_full::MemRead 1775830 84.20% 92.20% # attempts to use FU when none available 462system.cpu.iq.fu_full::MemWrite 164454 7.80% 100.00% # attempts to use FU when none available 463system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 464system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 465system.cpu.iq.FU_type_0::No_OpClass 295147 0.03% 0.03% # Type of FU issued 466system.cpu.iq.FU_type_0::IntAlu 829365416 95.96% 96.00% # Type of FU issued 467system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.00% # Type of FU issued 468system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.00% # Type of FU issued 469system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.00% # Type of FU issued 470system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.00% # Type of FU issued 471system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.00% # Type of FU issued 472system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.00% # Type of FU issued 473system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.00% # Type of FU issued 474system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.00% # Type of FU issued 475system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.00% # Type of FU issued 476system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.00% # Type of FU issued 477system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.00% # Type of FU issued 478system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.00% # Type of FU issued 479system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.00% # Type of FU issued 480system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.00% # Type of FU issued 481system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.00% # Type of FU issued 482system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.00% # Type of FU issued 483system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.00% # Type of FU issued 484system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.00% # Type of FU issued 485system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.00% # Type of FU issued 486system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.00% # Type of FU issued 487system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.00% # Type of FU issued 488system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.00% # Type of FU issued 489system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.00% # Type of FU issued 490system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.00% # Type of FU issued 491system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.00% # Type of FU issued 492system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.00% # Type of FU issued 493system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.00% # Type of FU issued 494system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.00% # Type of FU issued 495system.cpu.iq.FU_type_0::MemRead 25156928 2.91% 98.91% # Type of FU issued 496system.cpu.iq.FU_type_0::MemWrite 9438994 1.09% 100.00% # Type of FU issued 497system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 498system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 499system.cpu.iq.FU_type_0::total 864256485 # Type of FU issued 500system.cpu.iq.rate 1.873386 # Inst issue rate 501system.cpu.iq.fu_busy_cnt 2109065 # FU busy when requested 502system.cpu.iq.fu_busy_rate 0.002440 # FU busy rate (busy events/executed inst) 503system.cpu.iq.int_inst_queue_reads 2033227215 # Number of integer instruction queue reads 504system.cpu.iq.int_inst_queue_writes 893026339 # Number of integer instruction queue writes 505system.cpu.iq.int_inst_queue_wakeup_accesses 853844323 # Number of integer instruction queue wakeup accesses 506system.cpu.iq.fp_inst_queue_reads 314 # Number of floating instruction queue reads 507system.cpu.iq.fp_inst_queue_writes 348 # Number of floating instruction queue writes 508system.cpu.iq.fp_inst_queue_wakeup_accesses 80 # Number of floating instruction queue wakeup accesses 509system.cpu.iq.int_alu_accesses 866070258 # Number of integer alu accesses 510system.cpu.iq.fp_alu_accesses 145 # Number of floating point alu accesses 511system.cpu.iew.lsq.thread0.forwLoads 1582954 # Number of loads that had data forwarded from stores 512system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 513system.cpu.iew.lsq.thread0.squashedLoads 3588586 # Number of loads squashed 514system.cpu.iew.lsq.thread0.ignoredResponses 21998 # Number of memory responses ignored because the instruction is squashed 515system.cpu.iew.lsq.thread0.memOrderViolation 11829 # Number of memory ordering violations 516system.cpu.iew.lsq.thread0.squashedStores 2035325 # Number of stores squashed 517system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 518system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 519system.cpu.iew.lsq.thread0.rescheduledLoads 7821677 # Number of loads that were rescheduled 520system.cpu.iew.lsq.thread0.cacheBlocked 2614 # Number of times an access to memory failed due to the cache being blocked 521system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 522system.cpu.iew.iewSquashCycles 4071014 # Number of cycles IEW is squashing 523system.cpu.iew.iewBlockCycles 26002336 # Number of cycles IEW is blocking 524system.cpu.iew.iewUnblockCycles 1398631 # Number of cycles IEW is unblocking 525system.cpu.iew.iewDispatchedInsts 867218559 # Number of instructions dispatched to IQ 526system.cpu.iew.iewDispSquashedInsts 301512 # Number of squashed instructions skipped by dispatch 527system.cpu.iew.iewDispLoadInsts 18887370 # Number of dispatched load instructions 528system.cpu.iew.iewDispStoreInsts 10441908 # Number of dispatched store instructions 529system.cpu.iew.iewDispNonSpecInsts 882377 # Number of dispatched non-speculative instructions 530system.cpu.iew.iewIQFullEvents 699130 # Number of times the IQ has become full, causing a stall 531system.cpu.iew.iewLSQFullEvents 12813 # Number of times the LSQ has become full, causing a stall 532system.cpu.iew.memOrderViolationEvents 11829 # Number of memory order violations 533system.cpu.iew.predictedTakenIncorrect 701390 # Number of branches that were predicted taken incorrectly 534system.cpu.iew.predictedNotTakenIncorrect 622436 # Number of branches that were predicted not taken incorrectly 535system.cpu.iew.branchMispredicts 1323826 # Number of branch mispredicts detected at execute 536system.cpu.iew.iewExecutedInsts 862338984 # Number of executed instructions 537system.cpu.iew.iewExecLoadInsts 24725426 # Number of load instructions executed 538system.cpu.iew.iewExecSquashedInsts 1917500 # Number of squashed instructions skipped in execute 539system.cpu.iew.exec_swp 0 # number of swp insts executed 540system.cpu.iew.exec_nop 0 # number of nop insts executed 541system.cpu.iew.exec_refs 33920026 # number of memory reference insts executed 542system.cpu.iew.exec_branches 86488789 # Number of branches executed 543system.cpu.iew.exec_stores 9194600 # Number of stores executed 544system.cpu.iew.exec_rate 1.869230 # Inst execution rate 545system.cpu.iew.wb_sent 861878608 # cumulative count of insts sent to commit 546system.cpu.iew.wb_count 853844403 # cumulative count of insts written-back 547system.cpu.iew.wb_producers 669889230 # num instructions producing a value 548system.cpu.iew.wb_consumers 1919047361 # num instructions consuming a value 549system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 550system.cpu.iew.wb_rate 1.850816 # insts written-back per cycle 551system.cpu.iew.wb_fanout 0.349074 # average fanout of values written-back 552system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 553system.cpu.commit.commitCommittedInsts 426506235 # The number of committed instructions 554system.cpu.commit.commitCommittedOps 840483958 # The number of committed instructions 555system.cpu.commit.commitSquashedInsts 26630365 # The number of squashed insts skipped by commit 556system.cpu.commit.commitNonSpecStalls 1515546 # The number of times commit has been forced to stall to communicate backwards 557system.cpu.commit.branchMispredicts 1177301 # The number of times a branch was mispredicted 558system.cpu.commit.committed_per_cycle::samples 298298866 # Number of insts commited each cycle 559system.cpu.commit.committed_per_cycle::mean 2.817590 # Number of insts commited each cycle 560system.cpu.commit.committed_per_cycle::stdev 2.864095 # Number of insts commited each cycle 561system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 562system.cpu.commit.committed_per_cycle::0 117621447 39.43% 39.43% # Number of insts commited each cycle 563system.cpu.commit.committed_per_cycle::1 14371375 4.82% 44.25% # Number of insts commited each cycle 564system.cpu.commit.committed_per_cycle::2 4300832 1.44% 45.69% # Number of insts commited each cycle 565system.cpu.commit.committed_per_cycle::3 76665686 25.70% 71.39% # Number of insts commited each cycle 566system.cpu.commit.committed_per_cycle::4 3908070 1.31% 72.70% # Number of insts commited each cycle 567system.cpu.commit.committed_per_cycle::5 1784515 0.60% 73.30% # Number of insts commited each cycle 568system.cpu.commit.committed_per_cycle::6 1116090 0.37% 73.67% # Number of insts commited each cycle 569system.cpu.commit.committed_per_cycle::7 71984342 24.13% 97.81% # Number of insts commited each cycle 570system.cpu.commit.committed_per_cycle::8 6546509 2.19% 100.00% # Number of insts commited each cycle 571system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 572system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 573system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 574system.cpu.commit.committed_per_cycle::total 298298866 # Number of insts commited each cycle 575system.cpu.commit.committedInsts 426506235 # Number of instructions committed 576system.cpu.commit.committedOps 840483958 # Number of ops (including micro ops) committed 577system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 578system.cpu.commit.refs 23705364 # Number of memory references committed 579system.cpu.commit.loads 15298781 # Number of loads committed 580system.cpu.commit.membars 781557 # Number of memory barriers committed 581system.cpu.commit.branches 85502209 # Number of branches committed 582system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. 583system.cpu.commit.int_insts 768310964 # Number of committed integer instructions. 584system.cpu.commit.function_calls 0 # Number of function calls committed. 585system.cpu.commit.bw_lim_events 6546509 # number cycles where commit BW limit reached 586system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 587system.cpu.rob.rob_reads 1158787398 # The number of ROB reads 588system.cpu.rob.rob_writes 1738314967 # The number of ROB writes 589system.cpu.timesIdled 2905540 # Number of times that the entire CPU went into an idle state and unscheduled itself 590system.cpu.idleCycles 158979567 # Total number of cycles that the CPU has spent unscheduled due to idling 591system.cpu.quiesceCycles 9853691832 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 592system.cpu.committedInsts 426506235 # Number of Instructions Simulated 593system.cpu.committedOps 840483958 # Number of Ops (including micro ops) Simulated 594system.cpu.committedInsts_total 426506235 # Number of Instructions Simulated 595system.cpu.cpi 1.081658 # CPI: Cycles Per Instruction 596system.cpu.cpi_total 1.081658 # CPI: Total CPI of All Threads 597system.cpu.ipc 0.924507 # IPC: Instructions Per Cycle 598system.cpu.ipc_total 0.924507 # IPC: Total IPC of All Threads 599system.cpu.int_regfile_reads 2163093750 # number of integer regfile reads 600system.cpu.int_regfile_writes 1362601470 # number of integer regfile writes 601system.cpu.fp_regfile_reads 80 # number of floating regfile reads 602system.cpu.misc_regfile_reads 281025584 # number of misc regfile reads 603system.cpu.misc_regfile_writes 403474 # number of misc regfile writes 604system.cpu.icache.replacements 1083149 # number of replacements 605system.cpu.icache.tagsinuse 510.211811 # Cycle average of tags in use 606system.cpu.icache.total_refs 8213603 # Total number of references to valid blocks. 607system.cpu.icache.sampled_refs 1083661 # Sample count of references to valid blocks. 608system.cpu.icache.avg_refs 7.579495 # Average number of references to valid blocks. 609system.cpu.icache.warmup_cycle 56616978000 # Cycle when the warmup percentage was hit. 610system.cpu.icache.occ_blocks::cpu.inst 510.211811 # Average occupied blocks per requestor 611system.cpu.icache.occ_percent::cpu.inst 0.996507 # Average percentage of cache occupancy 612system.cpu.icache.occ_percent::total 0.996507 # Average percentage of cache occupancy 613system.cpu.icache.ReadReq_hits::cpu.inst 8213603 # number of ReadReq hits 614system.cpu.icache.ReadReq_hits::total 8213603 # number of ReadReq hits 615system.cpu.icache.demand_hits::cpu.inst 8213603 # number of demand (read+write) hits 616system.cpu.icache.demand_hits::total 8213603 # number of demand (read+write) hits 617system.cpu.icache.overall_hits::cpu.inst 8213603 # number of overall hits 618system.cpu.icache.overall_hits::total 8213603 # number of overall hits 619system.cpu.icache.ReadReq_misses::cpu.inst 1153196 # number of ReadReq misses 620system.cpu.icache.ReadReq_misses::total 1153196 # number of ReadReq misses 621system.cpu.icache.demand_misses::cpu.inst 1153196 # number of demand (read+write) misses 622system.cpu.icache.demand_misses::total 1153196 # number of demand (read+write) misses 623system.cpu.icache.overall_misses::cpu.inst 1153196 # number of overall misses 624system.cpu.icache.overall_misses::total 1153196 # number of overall misses 625system.cpu.icache.ReadReq_miss_latency::cpu.inst 17226505491 # number of ReadReq miss cycles 626system.cpu.icache.ReadReq_miss_latency::total 17226505491 # number of ReadReq miss cycles 627system.cpu.icache.demand_miss_latency::cpu.inst 17226505491 # number of demand (read+write) miss cycles 628system.cpu.icache.demand_miss_latency::total 17226505491 # number of demand (read+write) miss cycles 629system.cpu.icache.overall_miss_latency::cpu.inst 17226505491 # number of overall miss cycles 630system.cpu.icache.overall_miss_latency::total 17226505491 # number of overall miss cycles 631system.cpu.icache.ReadReq_accesses::cpu.inst 9366799 # number of ReadReq accesses(hits+misses) 632system.cpu.icache.ReadReq_accesses::total 9366799 # number of ReadReq accesses(hits+misses) 633system.cpu.icache.demand_accesses::cpu.inst 9366799 # number of demand (read+write) accesses 634system.cpu.icache.demand_accesses::total 9366799 # number of demand (read+write) accesses 635system.cpu.icache.overall_accesses::cpu.inst 9366799 # number of overall (read+write) accesses 636system.cpu.icache.overall_accesses::total 9366799 # number of overall (read+write) accesses 637system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.123115 # miss rate for ReadReq accesses 638system.cpu.icache.demand_miss_rate::cpu.inst 0.123115 # miss rate for demand accesses 639system.cpu.icache.overall_miss_rate::cpu.inst 0.123115 # miss rate for overall accesses 640system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14938.055188 # average ReadReq miss latency 641system.cpu.icache.demand_avg_miss_latency::cpu.inst 14938.055188 # average overall miss latency 642system.cpu.icache.overall_avg_miss_latency::cpu.inst 14938.055188 # average overall miss latency 643system.cpu.icache.blocked_cycles::no_mshrs 2912492 # number of cycles access was blocked 644system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 645system.cpu.icache.blocked::no_mshrs 289 # number of cycles access was blocked 646system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 647system.cpu.icache.avg_blocked_cycles::no_mshrs 10077.826990 # average number of cycles each access was blocked 648system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 649system.cpu.icache.fast_writes 0 # number of fast writes performed 650system.cpu.icache.cache_copies 0 # number of cache copies performed 651system.cpu.icache.writebacks::writebacks 1570 # number of writebacks 652system.cpu.icache.writebacks::total 1570 # number of writebacks 653system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68394 # number of ReadReq MSHR hits 654system.cpu.icache.ReadReq_mshr_hits::total 68394 # number of ReadReq MSHR hits 655system.cpu.icache.demand_mshr_hits::cpu.inst 68394 # number of demand (read+write) MSHR hits 656system.cpu.icache.demand_mshr_hits::total 68394 # number of demand (read+write) MSHR hits 657system.cpu.icache.overall_mshr_hits::cpu.inst 68394 # number of overall MSHR hits 658system.cpu.icache.overall_mshr_hits::total 68394 # number of overall MSHR hits 659system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1084802 # number of ReadReq MSHR misses 660system.cpu.icache.ReadReq_mshr_misses::total 1084802 # number of ReadReq MSHR misses 661system.cpu.icache.demand_mshr_misses::cpu.inst 1084802 # number of demand (read+write) MSHR misses 662system.cpu.icache.demand_mshr_misses::total 1084802 # number of demand (read+write) MSHR misses 663system.cpu.icache.overall_mshr_misses::cpu.inst 1084802 # number of overall MSHR misses 664system.cpu.icache.overall_mshr_misses::total 1084802 # number of overall MSHR misses 665system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13093471492 # number of ReadReq MSHR miss cycles 666system.cpu.icache.ReadReq_mshr_miss_latency::total 13093471492 # number of ReadReq MSHR miss cycles 667system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13093471492 # number of demand (read+write) MSHR miss cycles 668system.cpu.icache.demand_mshr_miss_latency::total 13093471492 # number of demand (read+write) MSHR miss cycles 669system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13093471492 # number of overall MSHR miss cycles 670system.cpu.icache.overall_mshr_miss_latency::total 13093471492 # number of overall MSHR miss cycles 671system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.115814 # mshr miss rate for ReadReq accesses 672system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.115814 # mshr miss rate for demand accesses 673system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.115814 # mshr miss rate for overall accesses 674system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12069.918282 # average ReadReq mshr miss latency 675system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12069.918282 # average overall mshr miss latency 676system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12069.918282 # average overall mshr miss latency 677system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 678system.cpu.itb_walker_cache.replacements 10825 # number of replacements 679system.cpu.itb_walker_cache.tagsinuse 6.011393 # Cycle average of tags in use 680system.cpu.itb_walker_cache.total_refs 27185 # Total number of references to valid blocks. 681system.cpu.itb_walker_cache.sampled_refs 10834 # Sample count of references to valid blocks. 682system.cpu.itb_walker_cache.avg_refs 2.509230 # Average number of references to valid blocks. 683system.cpu.itb_walker_cache.warmup_cycle 5135028893000 # Cycle when the warmup percentage was hit. 684system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.011393 # Average occupied blocks per requestor 685system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.375712 # Average percentage of cache occupancy 686system.cpu.itb_walker_cache.occ_percent::total 0.375712 # Average percentage of cache occupancy 687system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 27407 # number of ReadReq hits 688system.cpu.itb_walker_cache.ReadReq_hits::total 27407 # number of ReadReq hits 689system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits 690system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits 691system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 27410 # number of demand (read+write) hits 692system.cpu.itb_walker_cache.demand_hits::total 27410 # number of demand (read+write) hits 693system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 27410 # number of overall hits 694system.cpu.itb_walker_cache.overall_hits::total 27410 # number of overall hits 695system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 11687 # number of ReadReq misses 696system.cpu.itb_walker_cache.ReadReq_misses::total 11687 # number of ReadReq misses 697system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 11687 # number of demand (read+write) misses 698system.cpu.itb_walker_cache.demand_misses::total 11687 # number of demand (read+write) misses 699system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 11687 # number of overall misses 700system.cpu.itb_walker_cache.overall_misses::total 11687 # number of overall misses 701system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 148214000 # number of ReadReq miss cycles 702system.cpu.itb_walker_cache.ReadReq_miss_latency::total 148214000 # number of ReadReq miss cycles 703system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 148214000 # number of demand (read+write) miss cycles 704system.cpu.itb_walker_cache.demand_miss_latency::total 148214000 # number of demand (read+write) miss cycles 705system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 148214000 # number of overall miss cycles 706system.cpu.itb_walker_cache.overall_miss_latency::total 148214000 # number of overall miss cycles 707system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 39094 # number of ReadReq accesses(hits+misses) 708system.cpu.itb_walker_cache.ReadReq_accesses::total 39094 # number of ReadReq accesses(hits+misses) 709system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) 710system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 711system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 39097 # number of demand (read+write) accesses 712system.cpu.itb_walker_cache.demand_accesses::total 39097 # number of demand (read+write) accesses 713system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 39097 # number of overall (read+write) accesses 714system.cpu.itb_walker_cache.overall_accesses::total 39097 # number of overall (read+write) accesses 715system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.298946 # miss rate for ReadReq accesses 716system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.298923 # miss rate for demand accesses 717system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.298923 # miss rate for overall accesses 718system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12681.954308 # average ReadReq miss latency 719system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12681.954308 # average overall miss latency 720system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12681.954308 # average overall miss latency 721system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 722system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 723system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 724system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 725system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 726system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 727system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 728system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 729system.cpu.itb_walker_cache.writebacks::writebacks 1456 # number of writebacks 730system.cpu.itb_walker_cache.writebacks::total 1456 # number of writebacks 731system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 11687 # number of ReadReq MSHR misses 732system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 11687 # number of ReadReq MSHR misses 733system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 11687 # number of demand (read+write) MSHR misses 734system.cpu.itb_walker_cache.demand_mshr_misses::total 11687 # number of demand (read+write) MSHR misses 735system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 11687 # number of overall MSHR misses 736system.cpu.itb_walker_cache.overall_mshr_misses::total 11687 # number of overall MSHR misses 737system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 112719500 # number of ReadReq MSHR miss cycles 738system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 112719500 # number of ReadReq MSHR miss cycles 739system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 112719500 # number of demand (read+write) MSHR miss cycles 740system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 112719500 # number of demand (read+write) MSHR miss cycles 741system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 112719500 # number of overall MSHR miss cycles 742system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 112719500 # number of overall MSHR miss cycles 743system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.298946 # mshr miss rate for ReadReq accesses 744system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.298923 # mshr miss rate for demand accesses 745system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.298923 # mshr miss rate for overall accesses 746system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9644.861812 # average ReadReq mshr miss latency 747system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9644.861812 # average overall mshr miss latency 748system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9644.861812 # average overall mshr miss latency 749system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 750system.cpu.dtb_walker_cache.replacements 116553 # number of replacements 751system.cpu.dtb_walker_cache.tagsinuse 13.859632 # Cycle average of tags in use 752system.cpu.dtb_walker_cache.total_refs 135956 # Total number of references to valid blocks. 753system.cpu.dtb_walker_cache.sampled_refs 116568 # Sample count of references to valid blocks. 754system.cpu.dtb_walker_cache.avg_refs 1.166324 # Average number of references to valid blocks. 755system.cpu.dtb_walker_cache.warmup_cycle 5108641793000 # Cycle when the warmup percentage was hit. 756system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.859632 # Average occupied blocks per requestor 757system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.866227 # Average percentage of cache occupancy 758system.cpu.dtb_walker_cache.occ_percent::total 0.866227 # Average percentage of cache occupancy 759system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 135961 # number of ReadReq hits 760system.cpu.dtb_walker_cache.ReadReq_hits::total 135961 # number of ReadReq hits 761system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 135961 # number of demand (read+write) hits 762system.cpu.dtb_walker_cache.demand_hits::total 135961 # number of demand (read+write) hits 763system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 135961 # number of overall hits 764system.cpu.dtb_walker_cache.overall_hits::total 135961 # number of overall hits 765system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 117570 # number of ReadReq misses 766system.cpu.dtb_walker_cache.ReadReq_misses::total 117570 # number of ReadReq misses 767system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 117570 # number of demand (read+write) misses 768system.cpu.dtb_walker_cache.demand_misses::total 117570 # number of demand (read+write) misses 769system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 117570 # number of overall misses 770system.cpu.dtb_walker_cache.overall_misses::total 117570 # number of overall misses 771system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 1642151000 # number of ReadReq miss cycles 772system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 1642151000 # number of ReadReq miss cycles 773system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 1642151000 # number of demand (read+write) miss cycles 774system.cpu.dtb_walker_cache.demand_miss_latency::total 1642151000 # number of demand (read+write) miss cycles 775system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 1642151000 # number of overall miss cycles 776system.cpu.dtb_walker_cache.overall_miss_latency::total 1642151000 # number of overall miss cycles 777system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 253531 # number of ReadReq accesses(hits+misses) 778system.cpu.dtb_walker_cache.ReadReq_accesses::total 253531 # number of ReadReq accesses(hits+misses) 779system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 253531 # number of demand (read+write) accesses 780system.cpu.dtb_walker_cache.demand_accesses::total 253531 # number of demand (read+write) accesses 781system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 253531 # number of overall (read+write) accesses 782system.cpu.dtb_walker_cache.overall_accesses::total 253531 # number of overall (read+write) accesses 783system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.463730 # miss rate for ReadReq accesses 784system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.463730 # miss rate for demand accesses 785system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.463730 # miss rate for overall accesses 786system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 13967.432168 # average ReadReq miss latency 787system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 13967.432168 # average overall miss latency 788system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 13967.432168 # average overall miss latency 789system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 790system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 791system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 792system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 793system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 794system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 795system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 796system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 797system.cpu.dtb_walker_cache.writebacks::writebacks 36817 # number of writebacks 798system.cpu.dtb_walker_cache.writebacks::total 36817 # number of writebacks 799system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 117570 # number of ReadReq MSHR misses 800system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 117570 # number of ReadReq MSHR misses 801system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 117570 # number of demand (read+write) MSHR misses 802system.cpu.dtb_walker_cache.demand_mshr_misses::total 117570 # number of demand (read+write) MSHR misses 803system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 117570 # number of overall MSHR misses 804system.cpu.dtb_walker_cache.overall_mshr_misses::total 117570 # number of overall MSHR misses 805system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1286519500 # number of ReadReq MSHR miss cycles 806system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1286519500 # number of ReadReq MSHR miss cycles 807system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1286519500 # number of demand (read+write) MSHR miss cycles 808system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1286519500 # number of demand (read+write) MSHR miss cycles 809system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1286519500 # number of overall MSHR miss cycles 810system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1286519500 # number of overall MSHR miss cycles 811system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.463730 # mshr miss rate for ReadReq accesses 812system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.463730 # mshr miss rate for demand accesses 813system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.463730 # mshr miss rate for overall accesses 814system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142 # average ReadReq mshr miss latency 815system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142 # average overall mshr miss latency 816system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10942.583142 # average overall mshr miss latency 817system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 818system.cpu.dcache.replacements 1673290 # number of replacements 819system.cpu.dcache.tagsinuse 511.997033 # Cycle average of tags in use 820system.cpu.dcache.total_refs 19026186 # Total number of references to valid blocks. 821system.cpu.dcache.sampled_refs 1673802 # Sample count of references to valid blocks. 822system.cpu.dcache.avg_refs 11.367047 # Average number of references to valid blocks. 823system.cpu.dcache.warmup_cycle 34328000 # Cycle when the warmup percentage was hit. 824system.cpu.dcache.occ_blocks::cpu.data 511.997033 # Average occupied blocks per requestor 825system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy 826system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy 827system.cpu.dcache.ReadReq_hits::cpu.data 10943323 # number of ReadReq hits 828system.cpu.dcache.ReadReq_hits::total 10943323 # number of ReadReq hits 829system.cpu.dcache.WriteReq_hits::cpu.data 8079241 # number of WriteReq hits 830system.cpu.dcache.WriteReq_hits::total 8079241 # number of WriteReq hits 831system.cpu.dcache.demand_hits::cpu.data 19022564 # number of demand (read+write) hits 832system.cpu.dcache.demand_hits::total 19022564 # number of demand (read+write) hits 833system.cpu.dcache.overall_hits::cpu.data 19022564 # number of overall hits 834system.cpu.dcache.overall_hits::total 19022564 # number of overall hits 835system.cpu.dcache.ReadReq_misses::cpu.data 2411423 # number of ReadReq misses 836system.cpu.dcache.ReadReq_misses::total 2411423 # number of ReadReq misses 837system.cpu.dcache.WriteReq_misses::cpu.data 318003 # number of WriteReq misses 838system.cpu.dcache.WriteReq_misses::total 318003 # number of WriteReq misses 839system.cpu.dcache.demand_misses::cpu.data 2729426 # number of demand (read+write) misses 840system.cpu.dcache.demand_misses::total 2729426 # number of demand (read+write) misses 841system.cpu.dcache.overall_misses::cpu.data 2729426 # number of overall misses 842system.cpu.dcache.overall_misses::total 2729426 # number of overall misses 843system.cpu.dcache.ReadReq_miss_latency::cpu.data 36183001500 # number of ReadReq miss cycles 844system.cpu.dcache.ReadReq_miss_latency::total 36183001500 # number of ReadReq miss cycles 845system.cpu.dcache.WriteReq_miss_latency::cpu.data 10564799496 # number of WriteReq miss cycles 846system.cpu.dcache.WriteReq_miss_latency::total 10564799496 # number of WriteReq miss cycles 847system.cpu.dcache.demand_miss_latency::cpu.data 46747800996 # number of demand (read+write) miss cycles 848system.cpu.dcache.demand_miss_latency::total 46747800996 # number of demand (read+write) miss cycles 849system.cpu.dcache.overall_miss_latency::cpu.data 46747800996 # number of overall miss cycles 850system.cpu.dcache.overall_miss_latency::total 46747800996 # number of overall miss cycles 851system.cpu.dcache.ReadReq_accesses::cpu.data 13354746 # number of ReadReq accesses(hits+misses) 852system.cpu.dcache.ReadReq_accesses::total 13354746 # number of ReadReq accesses(hits+misses) 853system.cpu.dcache.WriteReq_accesses::cpu.data 8397244 # number of WriteReq accesses(hits+misses) 854system.cpu.dcache.WriteReq_accesses::total 8397244 # number of WriteReq accesses(hits+misses) 855system.cpu.dcache.demand_accesses::cpu.data 21751990 # number of demand (read+write) accesses 856system.cpu.dcache.demand_accesses::total 21751990 # number of demand (read+write) accesses 857system.cpu.dcache.overall_accesses::cpu.data 21751990 # number of overall (read+write) accesses 858system.cpu.dcache.overall_accesses::total 21751990 # number of overall (read+write) accesses 859system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180567 # miss rate for ReadReq accesses 860system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037870 # miss rate for WriteReq accesses 861system.cpu.dcache.demand_miss_rate::cpu.data 0.125479 # miss rate for demand accesses 862system.cpu.dcache.overall_miss_rate::cpu.data 0.125479 # miss rate for overall accesses 863system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15004.833868 # average ReadReq miss latency 864system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33222.326506 # average WriteReq miss latency 865system.cpu.dcache.demand_avg_miss_latency::cpu.data 17127.337761 # average overall miss latency 866system.cpu.dcache.overall_avg_miss_latency::cpu.data 17127.337761 # average overall miss latency 867system.cpu.dcache.blocked_cycles::no_mshrs 25105497 # number of cycles access was blocked 868system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 869system.cpu.dcache.blocked::no_mshrs 3680 # number of cycles access was blocked 870system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 871system.cpu.dcache.avg_blocked_cycles::no_mshrs 6822.145924 # average number of cycles each access was blocked 872system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 873system.cpu.dcache.fast_writes 0 # number of fast writes performed 874system.cpu.dcache.cache_copies 0 # number of cache copies performed 875system.cpu.dcache.writebacks::writebacks 1560881 # number of writebacks 876system.cpu.dcache.writebacks::total 1560881 # number of writebacks 877system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1029888 # number of ReadReq MSHR hits 878system.cpu.dcache.ReadReq_mshr_hits::total 1029888 # number of ReadReq MSHR hits 879system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22394 # number of WriteReq MSHR hits 880system.cpu.dcache.WriteReq_mshr_hits::total 22394 # number of WriteReq MSHR hits 881system.cpu.dcache.demand_mshr_hits::cpu.data 1052282 # number of demand (read+write) MSHR hits 882system.cpu.dcache.demand_mshr_hits::total 1052282 # number of demand (read+write) MSHR hits 883system.cpu.dcache.overall_mshr_hits::cpu.data 1052282 # number of overall MSHR hits 884system.cpu.dcache.overall_mshr_hits::total 1052282 # number of overall MSHR hits 885system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1381535 # number of ReadReq MSHR misses 886system.cpu.dcache.ReadReq_mshr_misses::total 1381535 # number of ReadReq MSHR misses 887system.cpu.dcache.WriteReq_mshr_misses::cpu.data 295609 # number of WriteReq MSHR misses 888system.cpu.dcache.WriteReq_mshr_misses::total 295609 # number of WriteReq MSHR misses 889system.cpu.dcache.demand_mshr_misses::cpu.data 1677144 # number of demand (read+write) MSHR misses 890system.cpu.dcache.demand_mshr_misses::total 1677144 # number of demand (read+write) MSHR misses 891system.cpu.dcache.overall_mshr_misses::cpu.data 1677144 # number of overall MSHR misses 892system.cpu.dcache.overall_mshr_misses::total 1677144 # number of overall MSHR misses 893system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18178804500 # number of ReadReq MSHR miss cycles 894system.cpu.dcache.ReadReq_mshr_miss_latency::total 18178804500 # number of ReadReq MSHR miss cycles 895system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9348322497 # number of WriteReq MSHR miss cycles 896system.cpu.dcache.WriteReq_mshr_miss_latency::total 9348322497 # number of WriteReq MSHR miss cycles 897system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27527126997 # number of demand (read+write) MSHR miss cycles 898system.cpu.dcache.demand_mshr_miss_latency::total 27527126997 # number of demand (read+write) MSHR miss cycles 899system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27527126997 # number of overall MSHR miss cycles 900system.cpu.dcache.overall_mshr_miss_latency::total 27527126997 # number of overall MSHR miss cycles 901system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85207754500 # number of ReadReq MSHR uncacheable cycles 902system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85207754500 # number of ReadReq MSHR uncacheable cycles 903system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1392930500 # number of WriteReq MSHR uncacheable cycles 904system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1392930500 # number of WriteReq MSHR uncacheable cycles 905system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86600685000 # number of overall MSHR uncacheable cycles 906system.cpu.dcache.overall_mshr_uncacheable_latency::total 86600685000 # number of overall MSHR uncacheable cycles 907system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103449 # mshr miss rate for ReadReq accesses 908system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035203 # mshr miss rate for WriteReq accesses 909system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077103 # mshr miss rate for demand accesses 910system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077103 # mshr miss rate for overall accesses 911system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13158.410391 # average ReadReq mshr miss latency 912system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31623.944119 # average WriteReq mshr miss latency 913system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16413.096906 # average overall mshr miss latency 914system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16413.096906 # average overall mshr miss latency 915system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 916system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 917system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 918system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 919system.cpu.kern.inst.arm 0 # number of arm instructions executed 920system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 921 922---------- End Simulation Statistics ---------- 923