stats.txt revision 10798:74e3c7359393
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 5.154240 # Number of seconds simulated 4sim_ticks 5154239928000 # Number of ticks simulated 5final_tick 5154239928000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 159835 # Simulator instruction rate (inst/s) 8host_op_rate 315937 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2019388964 # Simulator tick rate (ticks/s) 10host_mem_usage 759104 # Number of bytes of host memory used 11host_seconds 2552.38 # Real time elapsed on the host 12sim_insts 407959851 # Number of instructions simulated 13sim_ops 806389826 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 4224 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 1048832 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 10760128 # Number of bytes read from this memory 20system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory 21system.physmem.bytes_read::total 11841856 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 1048832 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 1048832 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 9579968 # Number of bytes written to this memory 25system.physmem.bytes_written::total 9579968 # Number of bytes written to this memory 26system.physmem.num_reads::cpu.dtb.walker 66 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.inst 16388 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.data 168127 # Number of read requests responded to by this memory 30system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory 31system.physmem.num_reads::total 185029 # Number of read requests responded to by this memory 32system.physmem.num_writes::writebacks 149687 # Number of write requests responded to by this memory 33system.physmem.num_writes::total 149687 # Number of write requests responded to by this memory 34system.physmem.bw_read::cpu.dtb.walker 820 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) 36system.physmem.bw_read::cpu.inst 203489 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.data 2087627 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::pc.south_bridge.ide 5501 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::total 2297498 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_inst_read::cpu.inst 203489 # Instruction read bandwidth from this memory (bytes/s) 41system.physmem.bw_inst_read::total 203489 # Instruction read bandwidth from this memory (bytes/s) 42system.physmem.bw_write::writebacks 1858658 # Write bandwidth from this memory (bytes/s) 43system.physmem.bw_write::total 1858658 # Write bandwidth from this memory (bytes/s) 44system.physmem.bw_total::writebacks 1858658 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::cpu.dtb.walker 820 # Total bandwidth to/from this memory (bytes/s) 46system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) 47system.physmem.bw_total::cpu.inst 203489 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.data 2087627 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::pc.south_bridge.ide 5501 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::total 4156156 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.readReqs 185029 # Number of read requests accepted 52system.physmem.writeReqs 196407 # Number of write requests accepted 53system.physmem.readBursts 185029 # Number of DRAM read bursts, including those serviced by the write queue 54system.physmem.writeBursts 196407 # Number of DRAM write bursts, including those merged in the write queue 55system.physmem.bytesReadDRAM 11835328 # Total number of bytes read from DRAM 56system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue 57system.physmem.bytesWritten 10911872 # Total number of bytes written to DRAM 58system.physmem.bytesReadSys 11841856 # Total read bytes from the system interface side 59system.physmem.bytesWrittenSys 12570048 # Total written bytes from the system interface side 60system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue 61system.physmem.mergedWrBursts 25884 # Number of DRAM write bursts merged with an existing one 62system.physmem.neitherReadNorWriteReqs 1735 # Number of requests that are neither read nor write 63system.physmem.perBankRdBursts::0 11576 # Per bank write bursts 64system.physmem.perBankRdBursts::1 11057 # Per bank write bursts 65system.physmem.perBankRdBursts::2 12153 # Per bank write bursts 66system.physmem.perBankRdBursts::3 11198 # Per bank write bursts 67system.physmem.perBankRdBursts::4 11802 # Per bank write bursts 68system.physmem.perBankRdBursts::5 11348 # Per bank write bursts 69system.physmem.perBankRdBursts::6 11143 # Per bank write bursts 70system.physmem.perBankRdBursts::7 11153 # Per bank write bursts 71system.physmem.perBankRdBursts::8 11425 # Per bank write bursts 72system.physmem.perBankRdBursts::9 11213 # Per bank write bursts 73system.physmem.perBankRdBursts::10 11332 # Per bank write bursts 74system.physmem.perBankRdBursts::11 11504 # Per bank write bursts 75system.physmem.perBankRdBursts::12 11762 # Per bank write bursts 76system.physmem.perBankRdBursts::13 12902 # Per bank write bursts 77system.physmem.perBankRdBursts::14 11974 # Per bank write bursts 78system.physmem.perBankRdBursts::15 11385 # Per bank write bursts 79system.physmem.perBankWrBursts::0 11439 # Per bank write bursts 80system.physmem.perBankWrBursts::1 10429 # Per bank write bursts 81system.physmem.perBankWrBursts::2 10485 # Per bank write bursts 82system.physmem.perBankWrBursts::3 9453 # Per bank write bursts 83system.physmem.perBankWrBursts::4 11713 # Per bank write bursts 84system.physmem.perBankWrBursts::5 11103 # Per bank write bursts 85system.physmem.perBankWrBursts::6 10277 # Per bank write bursts 86system.physmem.perBankWrBursts::7 10587 # Per bank write bursts 87system.physmem.perBankWrBursts::8 10639 # Per bank write bursts 88system.physmem.perBankWrBursts::9 10347 # Per bank write bursts 89system.physmem.perBankWrBursts::10 10880 # Per bank write bursts 90system.physmem.perBankWrBursts::11 10311 # Per bank write bursts 91system.physmem.perBankWrBursts::12 10712 # Per bank write bursts 92system.physmem.perBankWrBursts::13 11096 # Per bank write bursts 93system.physmem.perBankWrBursts::14 11110 # Per bank write bursts 94system.physmem.perBankWrBursts::15 9917 # Per bank write bursts 95system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 96system.physmem.numWrRetry 48 # Number of times write queue was full causing retry 97system.physmem.totGap 5154239876000 # Total gap between requests 98system.physmem.readPktSize::0 0 # Read request sizes (log2) 99system.physmem.readPktSize::1 0 # Read request sizes (log2) 100system.physmem.readPktSize::2 0 # Read request sizes (log2) 101system.physmem.readPktSize::3 0 # Read request sizes (log2) 102system.physmem.readPktSize::4 0 # Read request sizes (log2) 103system.physmem.readPktSize::5 0 # Read request sizes (log2) 104system.physmem.readPktSize::6 185029 # Read request sizes (log2) 105system.physmem.writePktSize::0 0 # Write request sizes (log2) 106system.physmem.writePktSize::1 0 # Write request sizes (log2) 107system.physmem.writePktSize::2 0 # Write request sizes (log2) 108system.physmem.writePktSize::3 0 # Write request sizes (log2) 109system.physmem.writePktSize::4 0 # Write request sizes (log2) 110system.physmem.writePktSize::5 0 # Write request sizes (log2) 111system.physmem.writePktSize::6 196407 # Write request sizes (log2) 112system.physmem.rdQLenPdf::0 170541 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::1 11600 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::2 1966 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::3 474 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::4 56 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::5 41 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::7 35 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::8 30 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::9 33 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 144system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::15 1636 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::16 1926 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::17 6237 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::18 6870 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::19 7193 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::20 7175 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::21 7339 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::22 7830 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::23 8415 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::24 7894 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::25 8094 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::26 9954 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::27 8496 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::28 7725 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::29 10840 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::30 8567 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::31 8107 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::32 7987 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::33 1631 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::34 1321 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::35 1459 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::36 2521 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::37 2967 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::38 2476 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::39 2901 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::40 3411 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::41 2551 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::42 2324 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::43 2194 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::44 2613 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::45 2036 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::46 1543 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::47 1490 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::48 1243 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::49 899 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::50 438 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::51 382 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::52 298 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::53 219 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::54 222 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::55 177 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::56 192 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::57 174 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::58 123 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::59 107 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::60 102 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::61 98 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::62 54 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::63 57 # What write queue length does an incoming req see 208system.physmem.bytesPerActivate::samples 73580 # Bytes accessed per row activation 209system.physmem.bytesPerActivate::mean 309.148356 # Bytes accessed per row activation 210system.physmem.bytesPerActivate::gmean 181.632665 # Bytes accessed per row activation 211system.physmem.bytesPerActivate::stdev 329.613307 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::0-127 27722 37.68% 37.68% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::128-255 17426 23.68% 61.36% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::256-383 7585 10.31% 71.67% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::384-511 4195 5.70% 77.37% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::512-639 2982 4.05% 81.42% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::640-767 2040 2.77% 84.19% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::768-895 1416 1.92% 86.12% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::896-1023 1303 1.77% 87.89% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::1024-1151 8911 12.11% 100.00% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::total 73580 # Bytes accessed per row activation 222system.physmem.rdPerTurnAround::samples 6767 # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::mean 27.326437 # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::stdev 584.974446 # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::0-2047 6766 99.99% 99.99% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::total 6767 # Reads before turning the bus around for writes 228system.physmem.wrPerTurnAround::samples 6767 # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::mean 25.195508 # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::gmean 18.700984 # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::stdev 42.210035 # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::16-31 6335 93.62% 93.62% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::32-47 84 1.24% 94.86% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::48-63 17 0.25% 95.11% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::64-79 17 0.25% 95.36% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::80-95 19 0.28% 95.64% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::96-111 20 0.30% 95.94% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::112-127 33 0.49% 96.42% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::128-143 32 0.47% 96.90% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::144-159 26 0.38% 97.28% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::160-175 8 0.12% 97.40% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::176-191 61 0.90% 98.30% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::192-207 50 0.74% 99.04% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::208-223 12 0.18% 99.22% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::224-239 1 0.01% 99.23% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::240-255 2 0.03% 99.26% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::272-287 3 0.04% 99.31% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::288-303 2 0.03% 99.34% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::304-319 2 0.03% 99.36% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::320-335 4 0.06% 99.42% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::336-351 9 0.13% 99.56% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::352-367 14 0.21% 99.76% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::368-383 6 0.09% 99.85% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::384-399 1 0.01% 99.87% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::400-415 1 0.01% 99.88% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::480-495 2 0.03% 99.91% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::528-543 1 0.01% 99.93% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::544-559 3 0.04% 99.97% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::560-575 2 0.03% 100.00% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::total 6767 # Writes before turning the bus around for reads 261system.physmem.totQLat 2002245948 # Total ticks spent queuing 262system.physmem.totMemAccLat 5469627198 # Total ticks spent from burst creation until serviced by the DRAM 263system.physmem.totBusLat 924635000 # Total ticks spent in databus transfers 264system.physmem.avgQLat 10827.22 # Average queueing delay per DRAM burst 265system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 266system.physmem.avgMemAccLat 29577.22 # Average memory access latency per DRAM burst 267system.physmem.avgRdBW 2.30 # Average DRAM read bandwidth in MiByte/s 268system.physmem.avgWrBW 2.12 # Average achieved write bandwidth in MiByte/s 269system.physmem.avgRdBWSys 2.30 # Average system read bandwidth in MiByte/s 270system.physmem.avgWrBWSys 2.44 # Average system write bandwidth in MiByte/s 271system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 272system.physmem.busUtil 0.03 # Data bus utilization in percentage 273system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 274system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 275system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing 276system.physmem.avgWrQLen 23.30 # Average write queue length when enqueuing 277system.physmem.readRowHits 151945 # Number of row buffer hits during reads 278system.physmem.writeRowHits 129899 # Number of row buffer hits during writes 279system.physmem.readRowHitRate 82.16 # Row buffer hit rate for reads 280system.physmem.writeRowHitRate 76.18 # Row buffer hit rate for writes 281system.physmem.avgGap 13512725.27 # Average gap between requests 282system.physmem.pageHitRate 79.29 # Row buffer hit rate, read and write combined 283system.physmem_0.actEnergy 271547640 # Energy for activate commands per rank (pJ) 284system.physmem_0.preEnergy 148165875 # Energy for precharge commands per rank (pJ) 285system.physmem_0.readEnergy 713146200 # Energy for read commands per rank (pJ) 286system.physmem_0.writeEnergy 553949280 # Energy for write commands per rank (pJ) 287system.physmem_0.refreshEnergy 336649428960 # Energy for refresh commands per rank (pJ) 288system.physmem_0.actBackEnergy 130302295830 # Energy for active background per rank (pJ) 289system.physmem_0.preBackEnergy 2978239548750 # Energy for precharge background per rank (pJ) 290system.physmem_0.totalEnergy 3446878082535 # Total energy per rank (pJ) 291system.physmem_0.averagePower 668.747042 # Core power per rank (mW) 292system.physmem_0.memoryStateTime::IDLE 4954509635136 # Time in different power states 293system.physmem_0.memoryStateTime::REF 172111160000 # Time in different power states 294system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 295system.physmem_0.memoryStateTime::ACT 27619022864 # Time in different power states 296system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 297system.physmem_1.actEnergy 284717160 # Energy for activate commands per rank (pJ) 298system.physmem_1.preEnergy 155351625 # Energy for precharge commands per rank (pJ) 299system.physmem_1.readEnergy 729276600 # Energy for read commands per rank (pJ) 300system.physmem_1.writeEnergy 550877760 # Energy for write commands per rank (pJ) 301system.physmem_1.refreshEnergy 336649428960 # Energy for refresh commands per rank (pJ) 302system.physmem_1.actBackEnergy 130834885590 # Energy for active background per rank (pJ) 303system.physmem_1.preBackEnergy 2977772364750 # Energy for precharge background per rank (pJ) 304system.physmem_1.totalEnergy 3446976902445 # Total energy per rank (pJ) 305system.physmem_1.averagePower 668.766215 # Core power per rank (mW) 306system.physmem_1.memoryStateTime::IDLE 4953723422640 # Time in different power states 307system.physmem_1.memoryStateTime::REF 172111160000 # Time in different power states 308system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 309system.physmem_1.memoryStateTime::ACT 28398444860 # Time in different power states 310system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 311system.cpu.branchPred.lookups 86886659 # Number of BP lookups 312system.cpu.branchPred.condPredicted 86886659 # Number of conditional branches predicted 313system.cpu.branchPred.condIncorrect 896606 # Number of conditional branches incorrect 314system.cpu.branchPred.BTBLookups 80012064 # Number of BTB lookups 315system.cpu.branchPred.BTBHits 78173158 # Number of BTB hits 316system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 317system.cpu.branchPred.BTBHitPct 97.701714 # BTB Hit Percentage 318system.cpu.branchPred.usedRAS 1555790 # Number of times the RAS was used to get a target. 319system.cpu.branchPred.RASInCorrect 180979 # Number of incorrect RAS predictions. 320system.cpu_clk_domain.clock 500 # Clock period in ticks 321system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks 322system.cpu.numCycles 452015949 # number of cpu cycles simulated 323system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 324system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 325system.cpu.fetch.icacheStallCycles 27708415 # Number of cycles fetch is stalled on an Icache miss 326system.cpu.fetch.Insts 429123541 # Number of instructions fetch has processed 327system.cpu.fetch.Branches 86886659 # Number of branches that fetch encountered 328system.cpu.fetch.predictedBranches 79728948 # Number of branches that fetch has predicted taken 329system.cpu.fetch.Cycles 420284778 # Number of cycles fetch has run and was not squashing or blocked 330system.cpu.fetch.SquashCycles 1879978 # Number of cycles fetch has spent squashing 331system.cpu.fetch.TlbCycles 144708 # Number of cycles fetch has spent waiting for tlb 332system.cpu.fetch.MiscStallCycles 58405 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 333system.cpu.fetch.PendingTrapStallCycles 207121 # Number of stall cycles due to pending traps 334system.cpu.fetch.PendingQuiesceStallCycles 57 # Number of stall cycles due to pending quiesce instructions 335system.cpu.fetch.IcacheWaitRetryStallCycles 651 # Number of stall cycles due to full MSHR 336system.cpu.fetch.CacheLines 9181144 # Number of cache lines fetched 337system.cpu.fetch.IcacheSquashes 450119 # Number of outstanding Icache misses that were squashed 338system.cpu.fetch.ItlbSquashes 5089 # Number of outstanding ITLB misses that were squashed 339system.cpu.fetch.rateDist::samples 449344124 # Number of instructions fetched each cycle (Total) 340system.cpu.fetch.rateDist::mean 1.884391 # Number of instructions fetched each cycle (Total) 341system.cpu.fetch.rateDist::stdev 3.047300 # Number of instructions fetched each cycle (Total) 342system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 343system.cpu.fetch.rateDist::0 283935319 63.19% 63.19% # Number of instructions fetched each cycle (Total) 344system.cpu.fetch.rateDist::1 2153229 0.48% 63.67% # Number of instructions fetched each cycle (Total) 345system.cpu.fetch.rateDist::2 72170843 16.06% 79.73% # Number of instructions fetched each cycle (Total) 346system.cpu.fetch.rateDist::3 1584001 0.35% 80.08% # Number of instructions fetched each cycle (Total) 347system.cpu.fetch.rateDist::4 2141625 0.48% 80.56% # Number of instructions fetched each cycle (Total) 348system.cpu.fetch.rateDist::5 2336888 0.52% 81.08% # Number of instructions fetched each cycle (Total) 349system.cpu.fetch.rateDist::6 1524270 0.34% 81.42% # Number of instructions fetched each cycle (Total) 350system.cpu.fetch.rateDist::7 1887238 0.42% 81.84% # Number of instructions fetched each cycle (Total) 351system.cpu.fetch.rateDist::8 81610711 18.16% 100.00% # Number of instructions fetched each cycle (Total) 352system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 353system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 354system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 355system.cpu.fetch.rateDist::total 449344124 # Number of instructions fetched each cycle (Total) 356system.cpu.fetch.branchRate 0.192220 # Number of branch fetches per cycle 357system.cpu.fetch.rate 0.949355 # Number of inst fetches per cycle 358system.cpu.decode.IdleCycles 23005123 # Number of cycles decode is idle 359system.cpu.decode.BlockedCycles 267198709 # Number of cycles decode is blocked 360system.cpu.decode.RunCycles 150742142 # Number of cycles decode is running 361system.cpu.decode.UnblockCycles 7458161 # Number of cycles decode is unblocking 362system.cpu.decode.SquashCycles 939989 # Number of cycles decode is squashing 363system.cpu.decode.DecodedInsts 838443104 # Number of instructions handled by decode 364system.cpu.rename.SquashCycles 939989 # Number of cycles rename is squashing 365system.cpu.rename.IdleCycles 25847202 # Number of cycles rename is idle 366system.cpu.rename.BlockCycles 224345308 # Number of cycles rename is blocking 367system.cpu.rename.serializeStallCycles 13466568 # count of cycles rename stalled for serializing inst 368system.cpu.rename.RunCycles 154654216 # Number of cycles rename is running 369system.cpu.rename.UnblockCycles 30090841 # Number of cycles rename is unblocking 370system.cpu.rename.RenamedInsts 834933758 # Number of instructions processed by rename 371system.cpu.rename.ROBFullEvents 459142 # Number of times rename has blocked due to ROB full 372system.cpu.rename.IQFullEvents 12335285 # Number of times rename has blocked due to IQ full 373system.cpu.rename.LQFullEvents 199811 # Number of times rename has blocked due to LQ full 374system.cpu.rename.SQFullEvents 14823013 # Number of times rename has blocked due to SQ full 375system.cpu.rename.RenamedOperands 997303578 # Number of destination operands rename has renamed 376system.cpu.rename.RenameLookups 1813575837 # Number of register rename lookups that rename has made 377system.cpu.rename.int_rename_lookups 1114848675 # Number of integer rename lookups 378system.cpu.rename.fp_rename_lookups 334 # Number of floating rename lookups 379system.cpu.rename.CommittedMaps 964352232 # Number of HB maps that are committed 380system.cpu.rename.UndoneMaps 32951344 # Number of HB maps that are undone due to squashing 381system.cpu.rename.serializingInsts 467055 # count of serializing insts renamed 382system.cpu.rename.tempSerializingInsts 470880 # count of temporary serializing insts renamed 383system.cpu.rename.skidInsts 38821668 # count of insts added to the skid buffer 384system.cpu.memDep0.insertedLoads 17323479 # Number of loads inserted to the mem dependence unit. 385system.cpu.memDep0.insertedStores 10180206 # Number of stores inserted to the mem dependence unit. 386system.cpu.memDep0.conflictingLoads 1295686 # Number of conflicting loads. 387system.cpu.memDep0.conflictingStores 1069829 # Number of conflicting stores. 388system.cpu.iq.iqInstsAdded 829469634 # Number of instructions added to the IQ (excludes non-spec) 389system.cpu.iq.iqNonSpecInstsAdded 1196558 # Number of non-speculative instructions added to the IQ 390system.cpu.iq.iqInstsIssued 824230120 # Number of instructions issued 391system.cpu.iq.iqSquashedInstsIssued 243416 # Number of squashed instructions issued 392system.cpu.iq.iqSquashedInstsExamined 24276361 # Number of squashed instructions iterated over during squash; mainly for profiling 393system.cpu.iq.iqSquashedOperandsExamined 36028466 # Number of squashed operands that are examined and possibly removed from graph 394system.cpu.iq.iqSquashedNonSpecRemoved 151024 # Number of squashed non-spec instructions that were removed 395system.cpu.iq.issued_per_cycle::samples 449344124 # Number of insts issued each cycle 396system.cpu.iq.issued_per_cycle::mean 1.834296 # Number of insts issued each cycle 397system.cpu.iq.issued_per_cycle::stdev 2.415438 # Number of insts issued each cycle 398system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::0 265024726 58.98% 58.98% # Number of insts issued each cycle 400system.cpu.iq.issued_per_cycle::1 14037592 3.12% 62.10% # Number of insts issued each cycle 401system.cpu.iq.issued_per_cycle::2 9914300 2.21% 64.31% # Number of insts issued each cycle 402system.cpu.iq.issued_per_cycle::3 7059540 1.57% 65.88% # Number of insts issued each cycle 403system.cpu.iq.issued_per_cycle::4 74309398 16.54% 82.42% # Number of insts issued each cycle 404system.cpu.iq.issued_per_cycle::5 4399488 0.98% 83.40% # Number of insts issued each cycle 405system.cpu.iq.issued_per_cycle::6 72817937 16.21% 99.60% # Number of insts issued each cycle 406system.cpu.iq.issued_per_cycle::7 1206490 0.27% 99.87% # Number of insts issued each cycle 407system.cpu.iq.issued_per_cycle::8 574653 0.13% 100.00% # Number of insts issued each cycle 408system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 409system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 410system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 411system.cpu.iq.issued_per_cycle::total 449344124 # Number of insts issued each cycle 412system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 413system.cpu.iq.fu_full::IntAlu 1987162 71.98% 71.98% # attempts to use FU when none available 414system.cpu.iq.fu_full::IntMult 137 0.00% 71.99% # attempts to use FU when none available 415system.cpu.iq.fu_full::IntDiv 645 0.02% 72.01% # attempts to use FU when none available 416system.cpu.iq.fu_full::FloatAdd 0 0.00% 72.01% # attempts to use FU when none available 417system.cpu.iq.fu_full::FloatCmp 0 0.00% 72.01% # attempts to use FU when none available 418system.cpu.iq.fu_full::FloatCvt 0 0.00% 72.01% # attempts to use FU when none available 419system.cpu.iq.fu_full::FloatMult 0 0.00% 72.01% # attempts to use FU when none available 420system.cpu.iq.fu_full::FloatDiv 0 0.00% 72.01% # attempts to use FU when none available 421system.cpu.iq.fu_full::FloatSqrt 0 0.00% 72.01% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdAdd 0 0.00% 72.01% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 72.01% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdAlu 0 0.00% 72.01% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdCmp 0 0.00% 72.01% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdCvt 0 0.00% 72.01% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdMisc 0 0.00% 72.01% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdMult 0 0.00% 72.01% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 72.01% # attempts to use FU when none available 430system.cpu.iq.fu_full::SimdShift 0 0.00% 72.01% # attempts to use FU when none available 431system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 72.01% # attempts to use FU when none available 432system.cpu.iq.fu_full::SimdSqrt 0 0.00% 72.01% # attempts to use FU when none available 433system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 72.01% # attempts to use FU when none available 434system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 72.01% # attempts to use FU when none available 435system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 72.01% # attempts to use FU when none available 436system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 72.01% # attempts to use FU when none available 437system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 72.01% # attempts to use FU when none available 438system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 72.01% # attempts to use FU when none available 439system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 72.01% # attempts to use FU when none available 440system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 72.01% # attempts to use FU when none available 441system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 72.01% # attempts to use FU when none available 442system.cpu.iq.fu_full::MemRead 611861 22.16% 94.18% # attempts to use FU when none available 443system.cpu.iq.fu_full::MemWrite 160804 5.82% 100.00% # attempts to use FU when none available 444system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 445system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 446system.cpu.iq.FU_type_0::No_OpClass 290308 0.04% 0.04% # Type of FU issued 447system.cpu.iq.FU_type_0::IntAlu 795868269 96.56% 96.59% # Type of FU issued 448system.cpu.iq.FU_type_0::IntMult 150766 0.02% 96.61% # Type of FU issued 449system.cpu.iq.FU_type_0::IntDiv 125160 0.02% 96.63% # Type of FU issued 450system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.63% # Type of FU issued 451system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.63% # Type of FU issued 452system.cpu.iq.FU_type_0::FloatCvt 92 0.00% 96.63% # Type of FU issued 453system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.63% # Type of FU issued 454system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.63% # Type of FU issued 455system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.63% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.63% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.63% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.63% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.63% # Type of FU issued 460system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.63% # Type of FU issued 461system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.63% # Type of FU issued 462system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.63% # Type of FU issued 463system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.63% # Type of FU issued 464system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.63% # Type of FU issued 465system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.63% # Type of FU issued 466system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.63% # Type of FU issued 467system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.63% # Type of FU issued 468system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.63% # Type of FU issued 469system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.63% # Type of FU issued 470system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.63% # Type of FU issued 471system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.63% # Type of FU issued 472system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.63% # Type of FU issued 473system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.63% # Type of FU issued 474system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.63% # Type of FU issued 475system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.63% # Type of FU issued 476system.cpu.iq.FU_type_0::MemRead 18401922 2.23% 98.86% # Type of FU issued 477system.cpu.iq.FU_type_0::MemWrite 9393603 1.14% 100.00% # Type of FU issued 478system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 479system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 480system.cpu.iq.FU_type_0::total 824230120 # Type of FU issued 481system.cpu.iq.rate 1.823454 # Inst issue rate 482system.cpu.iq.fu_busy_cnt 2760609 # FU busy when requested 483system.cpu.iq.fu_busy_rate 0.003349 # FU busy rate (busy events/executed inst) 484system.cpu.iq.int_inst_queue_reads 2100807897 # Number of integer instruction queue reads 485system.cpu.iq.int_inst_queue_writes 854954817 # Number of integer instruction queue writes 486system.cpu.iq.int_inst_queue_wakeup_accesses 819692227 # Number of integer instruction queue wakeup accesses 487system.cpu.iq.fp_inst_queue_reads 491 # Number of floating instruction queue reads 488system.cpu.iq.fp_inst_queue_writes 506 # Number of floating instruction queue writes 489system.cpu.iq.fp_inst_queue_wakeup_accesses 172 # Number of floating instruction queue wakeup accesses 490system.cpu.iq.int_alu_accesses 826700185 # Number of integer alu accesses 491system.cpu.iq.fp_alu_accesses 236 # Number of floating point alu accesses 492system.cpu.iew.lsq.thread0.forwLoads 1868049 # Number of loads that had data forwarded from stores 493system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 494system.cpu.iew.lsq.thread0.squashedLoads 3330814 # Number of loads squashed 495system.cpu.iew.lsq.thread0.ignoredResponses 14803 # Number of memory responses ignored because the instruction is squashed 496system.cpu.iew.lsq.thread0.memOrderViolation 14207 # Number of memory ordering violations 497system.cpu.iew.lsq.thread0.squashedStores 1754572 # Number of stores squashed 498system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 499system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 500system.cpu.iew.lsq.thread0.rescheduledLoads 2207477 # Number of loads that were rescheduled 501system.cpu.iew.lsq.thread0.cacheBlocked 74768 # Number of times an access to memory failed due to the cache being blocked 502system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 503system.cpu.iew.iewSquashCycles 939989 # Number of cycles IEW is squashing 504system.cpu.iew.iewBlockCycles 205903045 # Number of cycles IEW is blocking 505system.cpu.iew.iewUnblockCycles 10169335 # Number of cycles IEW is unblocking 506system.cpu.iew.iewDispatchedInsts 830666192 # Number of instructions dispatched to IQ 507system.cpu.iew.iewDispSquashedInsts 152285 # Number of squashed instructions skipped by dispatch 508system.cpu.iew.iewDispLoadInsts 17323479 # Number of dispatched load instructions 509system.cpu.iew.iewDispStoreInsts 10180206 # Number of dispatched store instructions 510system.cpu.iew.iewDispNonSpecInsts 703380 # Number of dispatched non-speculative instructions 511system.cpu.iew.iewIQFullEvents 416558 # Number of times the IQ has become full, causing a stall 512system.cpu.iew.iewLSQFullEvents 8857895 # Number of times the LSQ has become full, causing a stall 513system.cpu.iew.memOrderViolationEvents 14207 # Number of memory order violations 514system.cpu.iew.predictedTakenIncorrect 510302 # Number of branches that were predicted taken incorrectly 515system.cpu.iew.predictedNotTakenIncorrect 537060 # Number of branches that were predicted not taken incorrectly 516system.cpu.iew.branchMispredicts 1047362 # Number of branch mispredicts detected at execute 517system.cpu.iew.iewExecutedInsts 822616274 # Number of executed instructions 518system.cpu.iew.iewExecLoadInsts 18004247 # Number of load instructions executed 519system.cpu.iew.iewExecSquashedInsts 1478799 # Number of squashed instructions skipped in execute 520system.cpu.iew.exec_swp 0 # number of swp insts executed 521system.cpu.iew.exec_nop 0 # number of nop insts executed 522system.cpu.iew.exec_refs 27174393 # number of memory reference insts executed 523system.cpu.iew.exec_branches 83301836 # Number of branches executed 524system.cpu.iew.exec_stores 9170146 # Number of stores executed 525system.cpu.iew.exec_rate 1.819883 # Inst execution rate 526system.cpu.iew.wb_sent 822114086 # cumulative count of insts sent to commit 527system.cpu.iew.wb_count 819692399 # cumulative count of insts written-back 528system.cpu.iew.wb_producers 640992347 # num instructions producing a value 529system.cpu.iew.wb_consumers 1050518142 # num instructions consuming a value 530system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 531system.cpu.iew.wb_rate 1.813415 # insts written-back per cycle 532system.cpu.iew.wb_fanout 0.610168 # average fanout of values written-back 533system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 534system.cpu.commit.commitSquashedInsts 24149765 # The number of squashed insts skipped by commit 535system.cpu.commit.commitNonSpecStalls 1045534 # The number of times commit has been forced to stall to communicate backwards 536system.cpu.commit.branchMispredicts 907960 # The number of times a branch was mispredicted 537system.cpu.commit.committed_per_cycle::samples 445713409 # Number of insts commited each cycle 538system.cpu.commit.committed_per_cycle::mean 1.809212 # Number of insts commited each cycle 539system.cpu.commit.committed_per_cycle::stdev 2.671420 # Number of insts commited each cycle 540system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 541system.cpu.commit.committed_per_cycle::0 274913705 61.68% 61.68% # Number of insts commited each cycle 542system.cpu.commit.committed_per_cycle::1 11179565 2.51% 64.19% # Number of insts commited each cycle 543system.cpu.commit.committed_per_cycle::2 3571950 0.80% 64.99% # Number of insts commited each cycle 544system.cpu.commit.committed_per_cycle::3 74564778 16.73% 81.72% # Number of insts commited each cycle 545system.cpu.commit.committed_per_cycle::4 2421074 0.54% 82.26% # Number of insts commited each cycle 546system.cpu.commit.committed_per_cycle::5 1628213 0.37% 82.63% # Number of insts commited each cycle 547system.cpu.commit.committed_per_cycle::6 937027 0.21% 82.84% # Number of insts commited each cycle 548system.cpu.commit.committed_per_cycle::7 71052272 15.94% 98.78% # Number of insts commited each cycle 549system.cpu.commit.committed_per_cycle::8 5444825 1.22% 100.00% # Number of insts commited each cycle 550system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 551system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 552system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 553system.cpu.commit.committed_per_cycle::total 445713409 # Number of insts commited each cycle 554system.cpu.commit.committedInsts 407959851 # Number of instructions committed 555system.cpu.commit.committedOps 806389826 # Number of ops (including micro ops) committed 556system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 557system.cpu.commit.refs 22418298 # Number of memory references committed 558system.cpu.commit.loads 13992664 # Number of loads committed 559system.cpu.commit.membars 471797 # Number of memory barriers committed 560system.cpu.commit.branches 82198639 # Number of branches committed 561system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. 562system.cpu.commit.int_insts 735203522 # Number of committed integer instructions. 563system.cpu.commit.function_calls 1155963 # Number of function calls committed. 564system.cpu.commit.op_class_0::No_OpClass 171777 0.02% 0.02% # Class of committed instruction 565system.cpu.commit.op_class_0::IntAlu 783535872 97.17% 97.19% # Class of committed instruction 566system.cpu.commit.op_class_0::IntMult 144976 0.02% 97.21% # Class of committed instruction 567system.cpu.commit.op_class_0::IntDiv 121468 0.02% 97.22% # Class of committed instruction 568system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction 569system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction 570system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction 571system.cpu.commit.op_class_0::FloatMult 0 0.00% 97.22% # Class of committed instruction 572system.cpu.commit.op_class_0::FloatDiv 0 0.00% 97.22% # Class of committed instruction 573system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 97.22% # Class of committed instruction 574system.cpu.commit.op_class_0::SimdAdd 0 0.00% 97.22% # Class of committed instruction 575system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 97.22% # Class of committed instruction 576system.cpu.commit.op_class_0::SimdAlu 0 0.00% 97.22% # Class of committed instruction 577system.cpu.commit.op_class_0::SimdCmp 0 0.00% 97.22% # Class of committed instruction 578system.cpu.commit.op_class_0::SimdCvt 0 0.00% 97.22% # Class of committed instruction 579system.cpu.commit.op_class_0::SimdMisc 0 0.00% 97.22% # Class of committed instruction 580system.cpu.commit.op_class_0::SimdMult 0 0.00% 97.22% # Class of committed instruction 581system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 97.22% # Class of committed instruction 582system.cpu.commit.op_class_0::SimdShift 0 0.00% 97.22% # Class of committed instruction 583system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 97.22% # Class of committed instruction 584system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 97.22% # Class of committed instruction 585system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 97.22% # Class of committed instruction 586system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 97.22% # Class of committed instruction 587system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 97.22% # Class of committed instruction 588system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 97.22% # Class of committed instruction 589system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 97.22% # Class of committed instruction 590system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # Class of committed instruction 591system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction 592system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction 593system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction 594system.cpu.commit.op_class_0::MemRead 13990083 1.73% 98.96% # Class of committed instruction 595system.cpu.commit.op_class_0::MemWrite 8425634 1.04% 100.00% # Class of committed instruction 596system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 597system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 598system.cpu.commit.op_class_0::total 806389826 # Class of committed instruction 599system.cpu.commit.bw_lim_events 5444825 # number cycles where commit BW limit reached 600system.cpu.rob.rob_reads 1270729806 # The number of ROB reads 601system.cpu.rob.rob_writes 1664729387 # The number of ROB writes 602system.cpu.timesIdled 294275 # Number of times that the entire CPU went into an idle state and unscheduled itself 603system.cpu.idleCycles 2671825 # Total number of cycles that the CPU has spent unscheduled due to idling 604system.cpu.quiesceCycles 9856461520 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 605system.cpu.committedInsts 407959851 # Number of Instructions Simulated 606system.cpu.committedOps 806389826 # Number of Ops (including micro ops) Simulated 607system.cpu.cpi 1.107991 # CPI: Cycles Per Instruction 608system.cpu.cpi_total 1.107991 # CPI: Total CPI of All Threads 609system.cpu.ipc 0.902534 # IPC: Instructions Per Cycle 610system.cpu.ipc_total 0.902534 # IPC: Total IPC of All Threads 611system.cpu.int_regfile_reads 1092541258 # number of integer regfile reads 612system.cpu.int_regfile_writes 656084038 # number of integer regfile writes 613system.cpu.fp_regfile_reads 176 # number of floating regfile reads 614system.cpu.cc_regfile_reads 416293281 # number of cc regfile reads 615system.cpu.cc_regfile_writes 322054452 # number of cc regfile writes 616system.cpu.misc_regfile_reads 265591845 # number of misc regfile reads 617system.cpu.misc_regfile_writes 400328 # number of misc regfile writes 618system.cpu.dcache.tags.replacements 1659836 # number of replacements 619system.cpu.dcache.tags.tagsinuse 511.989699 # Cycle average of tags in use 620system.cpu.dcache.tags.total_refs 19130413 # Total number of references to valid blocks. 621system.cpu.dcache.tags.sampled_refs 1660348 # Sample count of references to valid blocks. 622system.cpu.dcache.tags.avg_refs 11.521930 # Average number of references to valid blocks. 623system.cpu.dcache.tags.warmup_cycle 41264250 # Cycle when the warmup percentage was hit. 624system.cpu.dcache.tags.occ_blocks::cpu.data 511.989699 # Average occupied blocks per requestor 625system.cpu.dcache.tags.occ_percent::cpu.data 0.999980 # Average percentage of cache occupancy 626system.cpu.dcache.tags.occ_percent::total 0.999980 # Average percentage of cache occupancy 627system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 628system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id 629system.cpu.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id 630system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id 631system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 632system.cpu.dcache.tags.tag_accesses 88364873 # Number of tag accesses 633system.cpu.dcache.tags.data_accesses 88364873 # Number of data accesses 634system.cpu.dcache.ReadReq_hits::cpu.data 10981747 # number of ReadReq hits 635system.cpu.dcache.ReadReq_hits::total 10981747 # number of ReadReq hits 636system.cpu.dcache.WriteReq_hits::cpu.data 8081553 # number of WriteReq hits 637system.cpu.dcache.WriteReq_hits::total 8081553 # number of WriteReq hits 638system.cpu.dcache.SoftPFReq_hits::cpu.data 64328 # number of SoftPFReq hits 639system.cpu.dcache.SoftPFReq_hits::total 64328 # number of SoftPFReq hits 640system.cpu.dcache.demand_hits::cpu.data 19063300 # number of demand (read+write) hits 641system.cpu.dcache.demand_hits::total 19063300 # number of demand (read+write) hits 642system.cpu.dcache.overall_hits::cpu.data 19127628 # number of overall hits 643system.cpu.dcache.overall_hits::total 19127628 # number of overall hits 644system.cpu.dcache.ReadReq_misses::cpu.data 1807734 # number of ReadReq misses 645system.cpu.dcache.ReadReq_misses::total 1807734 # number of ReadReq misses 646system.cpu.dcache.WriteReq_misses::cpu.data 334390 # number of WriteReq misses 647system.cpu.dcache.WriteReq_misses::total 334390 # number of WriteReq misses 648system.cpu.dcache.SoftPFReq_misses::cpu.data 406367 # number of SoftPFReq misses 649system.cpu.dcache.SoftPFReq_misses::total 406367 # number of SoftPFReq misses 650system.cpu.dcache.demand_misses::cpu.data 2142124 # number of demand (read+write) misses 651system.cpu.dcache.demand_misses::total 2142124 # number of demand (read+write) misses 652system.cpu.dcache.overall_misses::cpu.data 2548491 # number of overall misses 653system.cpu.dcache.overall_misses::total 2548491 # number of overall misses 654system.cpu.dcache.ReadReq_miss_latency::cpu.data 27237843437 # number of ReadReq miss cycles 655system.cpu.dcache.ReadReq_miss_latency::total 27237843437 # number of ReadReq miss cycles 656system.cpu.dcache.WriteReq_miss_latency::cpu.data 13894605384 # number of WriteReq miss cycles 657system.cpu.dcache.WriteReq_miss_latency::total 13894605384 # number of WriteReq miss cycles 658system.cpu.dcache.demand_miss_latency::cpu.data 41132448821 # number of demand (read+write) miss cycles 659system.cpu.dcache.demand_miss_latency::total 41132448821 # number of demand (read+write) miss cycles 660system.cpu.dcache.overall_miss_latency::cpu.data 41132448821 # number of overall miss cycles 661system.cpu.dcache.overall_miss_latency::total 41132448821 # number of overall miss cycles 662system.cpu.dcache.ReadReq_accesses::cpu.data 12789481 # number of ReadReq accesses(hits+misses) 663system.cpu.dcache.ReadReq_accesses::total 12789481 # number of ReadReq accesses(hits+misses) 664system.cpu.dcache.WriteReq_accesses::cpu.data 8415943 # number of WriteReq accesses(hits+misses) 665system.cpu.dcache.WriteReq_accesses::total 8415943 # number of WriteReq accesses(hits+misses) 666system.cpu.dcache.SoftPFReq_accesses::cpu.data 470695 # number of SoftPFReq accesses(hits+misses) 667system.cpu.dcache.SoftPFReq_accesses::total 470695 # number of SoftPFReq accesses(hits+misses) 668system.cpu.dcache.demand_accesses::cpu.data 21205424 # number of demand (read+write) accesses 669system.cpu.dcache.demand_accesses::total 21205424 # number of demand (read+write) accesses 670system.cpu.dcache.overall_accesses::cpu.data 21676119 # number of overall (read+write) accesses 671system.cpu.dcache.overall_accesses::total 21676119 # number of overall (read+write) accesses 672system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.141345 # miss rate for ReadReq accesses 673system.cpu.dcache.ReadReq_miss_rate::total 0.141345 # miss rate for ReadReq accesses 674system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039733 # miss rate for WriteReq accesses 675system.cpu.dcache.WriteReq_miss_rate::total 0.039733 # miss rate for WriteReq accesses 676system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.863334 # miss rate for SoftPFReq accesses 677system.cpu.dcache.SoftPFReq_miss_rate::total 0.863334 # miss rate for SoftPFReq accesses 678system.cpu.dcache.demand_miss_rate::cpu.data 0.101018 # miss rate for demand accesses 679system.cpu.dcache.demand_miss_rate::total 0.101018 # miss rate for demand accesses 680system.cpu.dcache.overall_miss_rate::cpu.data 0.117571 # miss rate for overall accesses 681system.cpu.dcache.overall_miss_rate::total 0.117571 # miss rate for overall accesses 682system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15067.395666 # average ReadReq miss latency 683system.cpu.dcache.ReadReq_avg_miss_latency::total 15067.395666 # average ReadReq miss latency 684system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41552.096008 # average WriteReq miss latency 685system.cpu.dcache.WriteReq_avg_miss_latency::total 41552.096008 # average WriteReq miss latency 686system.cpu.dcache.demand_avg_miss_latency::cpu.data 19201.712329 # average overall miss latency 687system.cpu.dcache.demand_avg_miss_latency::total 19201.712329 # average overall miss latency 688system.cpu.dcache.overall_avg_miss_latency::cpu.data 16139.923124 # average overall miss latency 689system.cpu.dcache.overall_avg_miss_latency::total 16139.923124 # average overall miss latency 690system.cpu.dcache.blocked_cycles::no_mshrs 413510 # number of cycles access was blocked 691system.cpu.dcache.blocked_cycles::no_targets 7 # number of cycles access was blocked 692system.cpu.dcache.blocked::no_mshrs 44186 # number of cycles access was blocked 693system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked 694system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.358394 # average number of cycles each access was blocked 695system.cpu.dcache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked 696system.cpu.dcache.fast_writes 0 # number of fast writes performed 697system.cpu.dcache.cache_copies 0 # number of cache copies performed 698system.cpu.dcache.writebacks::writebacks 1561658 # number of writebacks 699system.cpu.dcache.writebacks::total 1561658 # number of writebacks 700system.cpu.dcache.ReadReq_mshr_hits::cpu.data 837908 # number of ReadReq MSHR hits 701system.cpu.dcache.ReadReq_mshr_hits::total 837908 # number of ReadReq MSHR hits 702system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44444 # number of WriteReq MSHR hits 703system.cpu.dcache.WriteReq_mshr_hits::total 44444 # number of WriteReq MSHR hits 704system.cpu.dcache.demand_mshr_hits::cpu.data 882352 # number of demand (read+write) MSHR hits 705system.cpu.dcache.demand_mshr_hits::total 882352 # number of demand (read+write) MSHR hits 706system.cpu.dcache.overall_mshr_hits::cpu.data 882352 # number of overall MSHR hits 707system.cpu.dcache.overall_mshr_hits::total 882352 # number of overall MSHR hits 708system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969826 # number of ReadReq MSHR misses 709system.cpu.dcache.ReadReq_mshr_misses::total 969826 # number of ReadReq MSHR misses 710system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289946 # number of WriteReq MSHR misses 711system.cpu.dcache.WriteReq_mshr_misses::total 289946 # number of WriteReq MSHR misses 712system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402900 # number of SoftPFReq MSHR misses 713system.cpu.dcache.SoftPFReq_mshr_misses::total 402900 # number of SoftPFReq MSHR misses 714system.cpu.dcache.demand_mshr_misses::cpu.data 1259772 # number of demand (read+write) MSHR misses 715system.cpu.dcache.demand_mshr_misses::total 1259772 # number of demand (read+write) MSHR misses 716system.cpu.dcache.overall_mshr_misses::cpu.data 1662672 # number of overall MSHR misses 717system.cpu.dcache.overall_mshr_misses::total 1662672 # number of overall MSHR misses 718system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12862571524 # number of ReadReq MSHR miss cycles 719system.cpu.dcache.ReadReq_mshr_miss_latency::total 12862571524 # number of ReadReq MSHR miss cycles 720system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12285238213 # number of WriteReq MSHR miss cycles 721system.cpu.dcache.WriteReq_mshr_miss_latency::total 12285238213 # number of WriteReq MSHR miss cycles 722system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5938147500 # number of SoftPFReq MSHR miss cycles 723system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5938147500 # number of SoftPFReq MSHR miss cycles 724system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25147809737 # number of demand (read+write) MSHR miss cycles 725system.cpu.dcache.demand_mshr_miss_latency::total 25147809737 # number of demand (read+write) MSHR miss cycles 726system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31085957237 # number of overall MSHR miss cycles 727system.cpu.dcache.overall_mshr_miss_latency::total 31085957237 # number of overall MSHR miss cycles 728system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97453049000 # number of ReadReq MSHR uncacheable cycles 729system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97453049000 # number of ReadReq MSHR uncacheable cycles 730system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2592894500 # number of WriteReq MSHR uncacheable cycles 731system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2592894500 # number of WriteReq MSHR uncacheable cycles 732system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100045943500 # number of overall MSHR uncacheable cycles 733system.cpu.dcache.overall_mshr_uncacheable_latency::total 100045943500 # number of overall MSHR uncacheable cycles 734system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075830 # mshr miss rate for ReadReq accesses 735system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075830 # mshr miss rate for ReadReq accesses 736system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034452 # mshr miss rate for WriteReq accesses 737system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034452 # mshr miss rate for WriteReq accesses 738system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.855968 # mshr miss rate for SoftPFReq accesses 739system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.855968 # mshr miss rate for SoftPFReq accesses 740system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059408 # mshr miss rate for demand accesses 741system.cpu.dcache.demand_mshr_miss_rate::total 0.059408 # mshr miss rate for demand accesses 742system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076705 # mshr miss rate for overall accesses 743system.cpu.dcache.overall_mshr_miss_rate::total 0.076705 # mshr miss rate for overall accesses 744system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13262.762108 # average ReadReq mshr miss latency 745system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13262.762108 # average ReadReq mshr miss latency 746system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42370.780121 # average WriteReq mshr miss latency 747system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42370.780121 # average WriteReq mshr miss latency 748system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14738.514520 # average SoftPFReq mshr miss latency 749system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14738.514520 # average SoftPFReq mshr miss latency 750system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19962.191362 # average overall mshr miss latency 751system.cpu.dcache.demand_avg_mshr_miss_latency::total 19962.191362 # average overall mshr miss latency 752system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18696.385840 # average overall mshr miss latency 753system.cpu.dcache.overall_avg_mshr_miss_latency::total 18696.385840 # average overall mshr miss latency 754system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 755system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 756system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 757system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 758system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 759system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 760system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 761system.cpu.dtb_walker_cache.tags.replacements 73822 # number of replacements 762system.cpu.dtb_walker_cache.tags.tagsinuse 15.784353 # Cycle average of tags in use 763system.cpu.dtb_walker_cache.tags.total_refs 116295 # Total number of references to valid blocks. 764system.cpu.dtb_walker_cache.tags.sampled_refs 73836 # Sample count of references to valid blocks. 765system.cpu.dtb_walker_cache.tags.avg_refs 1.575045 # Average number of references to valid blocks. 766system.cpu.dtb_walker_cache.tags.warmup_cycle 194860088500 # Cycle when the warmup percentage was hit. 767system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.784353 # Average occupied blocks per requestor 768system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.986522 # Average percentage of cache occupancy 769system.cpu.dtb_walker_cache.tags.occ_percent::total 0.986522 # Average percentage of cache occupancy 770system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id 771system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id 772system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id 773system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 774system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id 775system.cpu.dtb_walker_cache.tags.tag_accesses 457427 # Number of tag accesses 776system.cpu.dtb_walker_cache.tags.data_accesses 457427 # Number of data accesses 777system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 116311 # number of ReadReq hits 778system.cpu.dtb_walker_cache.ReadReq_hits::total 116311 # number of ReadReq hits 779system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 116311 # number of demand (read+write) hits 780system.cpu.dtb_walker_cache.demand_hits::total 116311 # number of demand (read+write) hits 781system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 116311 # number of overall hits 782system.cpu.dtb_walker_cache.overall_hits::total 116311 # number of overall hits 783system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 74935 # number of ReadReq misses 784system.cpu.dtb_walker_cache.ReadReq_misses::total 74935 # number of ReadReq misses 785system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 74935 # number of demand (read+write) misses 786system.cpu.dtb_walker_cache.demand_misses::total 74935 # number of demand (read+write) misses 787system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 74935 # number of overall misses 788system.cpu.dtb_walker_cache.overall_misses::total 74935 # number of overall misses 789system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 914897711 # number of ReadReq miss cycles 790system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 914897711 # number of ReadReq miss cycles 791system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 914897711 # number of demand (read+write) miss cycles 792system.cpu.dtb_walker_cache.demand_miss_latency::total 914897711 # number of demand (read+write) miss cycles 793system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 914897711 # number of overall miss cycles 794system.cpu.dtb_walker_cache.overall_miss_latency::total 914897711 # number of overall miss cycles 795system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 191246 # number of ReadReq accesses(hits+misses) 796system.cpu.dtb_walker_cache.ReadReq_accesses::total 191246 # number of ReadReq accesses(hits+misses) 797system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 191246 # number of demand (read+write) accesses 798system.cpu.dtb_walker_cache.demand_accesses::total 191246 # number of demand (read+write) accesses 799system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 191246 # number of overall (read+write) accesses 800system.cpu.dtb_walker_cache.overall_accesses::total 191246 # number of overall (read+write) accesses 801system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.391825 # miss rate for ReadReq accesses 802system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.391825 # miss rate for ReadReq accesses 803system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.391825 # miss rate for demand accesses 804system.cpu.dtb_walker_cache.demand_miss_rate::total 0.391825 # miss rate for demand accesses 805system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.391825 # miss rate for overall accesses 806system.cpu.dtb_walker_cache.overall_miss_rate::total 0.391825 # miss rate for overall accesses 807system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12209.217468 # average ReadReq miss latency 808system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12209.217468 # average ReadReq miss latency 809system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12209.217468 # average overall miss latency 810system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12209.217468 # average overall miss latency 811system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12209.217468 # average overall miss latency 812system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12209.217468 # average overall miss latency 813system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 814system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 815system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 816system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 817system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 818system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 819system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed 820system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed 821system.cpu.dtb_walker_cache.writebacks::writebacks 20337 # number of writebacks 822system.cpu.dtb_walker_cache.writebacks::total 20337 # number of writebacks 823system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 74935 # number of ReadReq MSHR misses 824system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 74935 # number of ReadReq MSHR misses 825system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 74935 # number of demand (read+write) MSHR misses 826system.cpu.dtb_walker_cache.demand_mshr_misses::total 74935 # number of demand (read+write) MSHR misses 827system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 74935 # number of overall MSHR misses 828system.cpu.dtb_walker_cache.overall_mshr_misses::total 74935 # number of overall MSHR misses 829system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 802357975 # number of ReadReq MSHR miss cycles 830system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 802357975 # number of ReadReq MSHR miss cycles 831system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 802357975 # number of demand (read+write) MSHR miss cycles 832system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 802357975 # number of demand (read+write) MSHR miss cycles 833system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 802357975 # number of overall MSHR miss cycles 834system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 802357975 # number of overall MSHR miss cycles 835system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.391825 # mshr miss rate for ReadReq accesses 836system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.391825 # mshr miss rate for ReadReq accesses 837system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.391825 # mshr miss rate for demand accesses 838system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.391825 # mshr miss rate for demand accesses 839system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.391825 # mshr miss rate for overall accesses 840system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.391825 # mshr miss rate for overall accesses 841system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10707.386068 # average ReadReq mshr miss latency 842system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10707.386068 # average ReadReq mshr miss latency 843system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10707.386068 # average overall mshr miss latency 844system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10707.386068 # average overall mshr miss latency 845system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10707.386068 # average overall mshr miss latency 846system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10707.386068 # average overall mshr miss latency 847system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 848system.cpu.icache.tags.replacements 1000631 # number of replacements 849system.cpu.icache.tags.tagsinuse 508.729229 # Cycle average of tags in use 850system.cpu.icache.tags.total_refs 8114183 # Total number of references to valid blocks. 851system.cpu.icache.tags.sampled_refs 1001143 # Sample count of references to valid blocks. 852system.cpu.icache.tags.avg_refs 8.104919 # Average number of references to valid blocks. 853system.cpu.icache.tags.warmup_cycle 148026169000 # Cycle when the warmup percentage was hit. 854system.cpu.icache.tags.occ_blocks::cpu.inst 508.729229 # Average occupied blocks per requestor 855system.cpu.icache.tags.occ_percent::cpu.inst 0.993612 # Average percentage of cache occupancy 856system.cpu.icache.tags.occ_percent::total 0.993612 # Average percentage of cache occupancy 857system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 858system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 859system.cpu.icache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id 860system.cpu.icache.tags.age_task_id_blocks_1024::2 172 # Occupied blocks per task id 861system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 862system.cpu.icache.tags.tag_accesses 10182374 # Number of tag accesses 863system.cpu.icache.tags.data_accesses 10182374 # Number of data accesses 864system.cpu.icache.ReadReq_hits::cpu.inst 8114183 # number of ReadReq hits 865system.cpu.icache.ReadReq_hits::total 8114183 # number of ReadReq hits 866system.cpu.icache.demand_hits::cpu.inst 8114183 # number of demand (read+write) hits 867system.cpu.icache.demand_hits::total 8114183 # number of demand (read+write) hits 868system.cpu.icache.overall_hits::cpu.inst 8114183 # number of overall hits 869system.cpu.icache.overall_hits::total 8114183 # number of overall hits 870system.cpu.icache.ReadReq_misses::cpu.inst 1066954 # number of ReadReq misses 871system.cpu.icache.ReadReq_misses::total 1066954 # number of ReadReq misses 872system.cpu.icache.demand_misses::cpu.inst 1066954 # number of demand (read+write) misses 873system.cpu.icache.demand_misses::total 1066954 # number of demand (read+write) misses 874system.cpu.icache.overall_misses::cpu.inst 1066954 # number of overall misses 875system.cpu.icache.overall_misses::total 1066954 # number of overall misses 876system.cpu.icache.ReadReq_miss_latency::cpu.inst 14925731792 # number of ReadReq miss cycles 877system.cpu.icache.ReadReq_miss_latency::total 14925731792 # number of ReadReq miss cycles 878system.cpu.icache.demand_miss_latency::cpu.inst 14925731792 # number of demand (read+write) miss cycles 879system.cpu.icache.demand_miss_latency::total 14925731792 # number of demand (read+write) miss cycles 880system.cpu.icache.overall_miss_latency::cpu.inst 14925731792 # number of overall miss cycles 881system.cpu.icache.overall_miss_latency::total 14925731792 # number of overall miss cycles 882system.cpu.icache.ReadReq_accesses::cpu.inst 9181137 # number of ReadReq accesses(hits+misses) 883system.cpu.icache.ReadReq_accesses::total 9181137 # number of ReadReq accesses(hits+misses) 884system.cpu.icache.demand_accesses::cpu.inst 9181137 # number of demand (read+write) accesses 885system.cpu.icache.demand_accesses::total 9181137 # number of demand (read+write) accesses 886system.cpu.icache.overall_accesses::cpu.inst 9181137 # number of overall (read+write) accesses 887system.cpu.icache.overall_accesses::total 9181137 # number of overall (read+write) accesses 888system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116212 # miss rate for ReadReq accesses 889system.cpu.icache.ReadReq_miss_rate::total 0.116212 # miss rate for ReadReq accesses 890system.cpu.icache.demand_miss_rate::cpu.inst 0.116212 # miss rate for demand accesses 891system.cpu.icache.demand_miss_rate::total 0.116212 # miss rate for demand accesses 892system.cpu.icache.overall_miss_rate::cpu.inst 0.116212 # miss rate for overall accesses 893system.cpu.icache.overall_miss_rate::total 0.116212 # miss rate for overall accesses 894system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13989.105240 # average ReadReq miss latency 895system.cpu.icache.ReadReq_avg_miss_latency::total 13989.105240 # average ReadReq miss latency 896system.cpu.icache.demand_avg_miss_latency::cpu.inst 13989.105240 # average overall miss latency 897system.cpu.icache.demand_avg_miss_latency::total 13989.105240 # average overall miss latency 898system.cpu.icache.overall_avg_miss_latency::cpu.inst 13989.105240 # average overall miss latency 899system.cpu.icache.overall_avg_miss_latency::total 13989.105240 # average overall miss latency 900system.cpu.icache.blocked_cycles::no_mshrs 10002 # number of cycles access was blocked 901system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 902system.cpu.icache.blocked::no_mshrs 328 # number of cycles access was blocked 903system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 904system.cpu.icache.avg_blocked_cycles::no_mshrs 30.493902 # average number of cycles each access was blocked 905system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 906system.cpu.icache.fast_writes 0 # number of fast writes performed 907system.cpu.icache.cache_copies 0 # number of cache copies performed 908system.cpu.icache.ReadReq_mshr_hits::cpu.inst 65717 # number of ReadReq MSHR hits 909system.cpu.icache.ReadReq_mshr_hits::total 65717 # number of ReadReq MSHR hits 910system.cpu.icache.demand_mshr_hits::cpu.inst 65717 # number of demand (read+write) MSHR hits 911system.cpu.icache.demand_mshr_hits::total 65717 # number of demand (read+write) MSHR hits 912system.cpu.icache.overall_mshr_hits::cpu.inst 65717 # number of overall MSHR hits 913system.cpu.icache.overall_mshr_hits::total 65717 # number of overall MSHR hits 914system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1001237 # number of ReadReq MSHR misses 915system.cpu.icache.ReadReq_mshr_misses::total 1001237 # number of ReadReq MSHR misses 916system.cpu.icache.demand_mshr_misses::cpu.inst 1001237 # number of demand (read+write) MSHR misses 917system.cpu.icache.demand_mshr_misses::total 1001237 # number of demand (read+write) MSHR misses 918system.cpu.icache.overall_mshr_misses::cpu.inst 1001237 # number of overall MSHR misses 919system.cpu.icache.overall_mshr_misses::total 1001237 # number of overall MSHR misses 920system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12740674547 # number of ReadReq MSHR miss cycles 921system.cpu.icache.ReadReq_mshr_miss_latency::total 12740674547 # number of ReadReq MSHR miss cycles 922system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12740674547 # number of demand (read+write) MSHR miss cycles 923system.cpu.icache.demand_mshr_miss_latency::total 12740674547 # number of demand (read+write) MSHR miss cycles 924system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12740674547 # number of overall MSHR miss cycles 925system.cpu.icache.overall_mshr_miss_latency::total 12740674547 # number of overall MSHR miss cycles 926system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109054 # mshr miss rate for ReadReq accesses 927system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109054 # mshr miss rate for ReadReq accesses 928system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109054 # mshr miss rate for demand accesses 929system.cpu.icache.demand_mshr_miss_rate::total 0.109054 # mshr miss rate for demand accesses 930system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109054 # mshr miss rate for overall accesses 931system.cpu.icache.overall_mshr_miss_rate::total 0.109054 # mshr miss rate for overall accesses 932system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12724.933804 # average ReadReq mshr miss latency 933system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12724.933804 # average ReadReq mshr miss latency 934system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12724.933804 # average overall mshr miss latency 935system.cpu.icache.demand_avg_mshr_miss_latency::total 12724.933804 # average overall mshr miss latency 936system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12724.933804 # average overall mshr miss latency 937system.cpu.icache.overall_avg_mshr_miss_latency::total 12724.933804 # average overall mshr miss latency 938system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 939system.cpu.itb_walker_cache.tags.replacements 14933 # number of replacements 940system.cpu.itb_walker_cache.tags.tagsinuse 6.063651 # Cycle average of tags in use 941system.cpu.itb_walker_cache.tags.total_refs 25583 # Total number of references to valid blocks. 942system.cpu.itb_walker_cache.tags.sampled_refs 14948 # Sample count of references to valid blocks. 943system.cpu.itb_walker_cache.tags.avg_refs 1.711466 # Average number of references to valid blocks. 944system.cpu.itb_walker_cache.tags.warmup_cycle 5108134601500 # Cycle when the warmup percentage was hit. 945system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.063651 # Average occupied blocks per requestor 946system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.378978 # Average percentage of cache occupancy 947system.cpu.itb_walker_cache.tags.occ_percent::total 0.378978 # Average percentage of cache occupancy 948system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id 949system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id 950system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id 951system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id 952system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id 953system.cpu.itb_walker_cache.tags.tag_accesses 98613 # Number of tag accesses 954system.cpu.itb_walker_cache.tags.data_accesses 98613 # Number of data accesses 955system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25588 # number of ReadReq hits 956system.cpu.itb_walker_cache.ReadReq_hits::total 25588 # number of ReadReq hits 957system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits 958system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits 959system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25590 # number of demand (read+write) hits 960system.cpu.itb_walker_cache.demand_hits::total 25590 # number of demand (read+write) hits 961system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25590 # number of overall hits 962system.cpu.itb_walker_cache.overall_hits::total 25590 # number of overall hits 963system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 15811 # number of ReadReq misses 964system.cpu.itb_walker_cache.ReadReq_misses::total 15811 # number of ReadReq misses 965system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 15811 # number of demand (read+write) misses 966system.cpu.itb_walker_cache.demand_misses::total 15811 # number of demand (read+write) misses 967system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 15811 # number of overall misses 968system.cpu.itb_walker_cache.overall_misses::total 15811 # number of overall misses 969system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 183242996 # number of ReadReq miss cycles 970system.cpu.itb_walker_cache.ReadReq_miss_latency::total 183242996 # number of ReadReq miss cycles 971system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 183242996 # number of demand (read+write) miss cycles 972system.cpu.itb_walker_cache.demand_miss_latency::total 183242996 # number of demand (read+write) miss cycles 973system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 183242996 # number of overall miss cycles 974system.cpu.itb_walker_cache.overall_miss_latency::total 183242996 # number of overall miss cycles 975system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41399 # number of ReadReq accesses(hits+misses) 976system.cpu.itb_walker_cache.ReadReq_accesses::total 41399 # number of ReadReq accesses(hits+misses) 977system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) 978system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) 979system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41401 # number of demand (read+write) accesses 980system.cpu.itb_walker_cache.demand_accesses::total 41401 # number of demand (read+write) accesses 981system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41401 # number of overall (read+write) accesses 982system.cpu.itb_walker_cache.overall_accesses::total 41401 # number of overall (read+write) accesses 983system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.381917 # miss rate for ReadReq accesses 984system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.381917 # miss rate for ReadReq accesses 985system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.381899 # miss rate for demand accesses 986system.cpu.itb_walker_cache.demand_miss_rate::total 0.381899 # miss rate for demand accesses 987system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.381899 # miss rate for overall accesses 988system.cpu.itb_walker_cache.overall_miss_rate::total 0.381899 # miss rate for overall accesses 989system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11589.589273 # average ReadReq miss latency 990system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11589.589273 # average ReadReq miss latency 991system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11589.589273 # average overall miss latency 992system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11589.589273 # average overall miss latency 993system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11589.589273 # average overall miss latency 994system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11589.589273 # average overall miss latency 995system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 996system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 997system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked 998system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked 999system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1000system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1001system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed 1002system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed 1003system.cpu.itb_walker_cache.writebacks::writebacks 3310 # number of writebacks 1004system.cpu.itb_walker_cache.writebacks::total 3310 # number of writebacks 1005system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 15811 # number of ReadReq MSHR misses 1006system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 15811 # number of ReadReq MSHR misses 1007system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 15811 # number of demand (read+write) MSHR misses 1008system.cpu.itb_walker_cache.demand_mshr_misses::total 15811 # number of demand (read+write) MSHR misses 1009system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 15811 # number of overall MSHR misses 1010system.cpu.itb_walker_cache.overall_mshr_misses::total 15811 # number of overall MSHR misses 1011system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 159511522 # number of ReadReq MSHR miss cycles 1012system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 159511522 # number of ReadReq MSHR miss cycles 1013system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 159511522 # number of demand (read+write) MSHR miss cycles 1014system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 159511522 # number of demand (read+write) MSHR miss cycles 1015system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 159511522 # number of overall MSHR miss cycles 1016system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 159511522 # number of overall MSHR miss cycles 1017system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.381917 # mshr miss rate for ReadReq accesses 1018system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.381917 # mshr miss rate for ReadReq accesses 1019system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.381899 # mshr miss rate for demand accesses 1020system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.381899 # mshr miss rate for demand accesses 1021system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.381899 # mshr miss rate for overall accesses 1022system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.381899 # mshr miss rate for overall accesses 1023system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10088.642211 # average ReadReq mshr miss latency 1024system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10088.642211 # average ReadReq mshr miss latency 1025system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10088.642211 # average overall mshr miss latency 1026system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10088.642211 # average overall mshr miss latency 1027system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10088.642211 # average overall mshr miss latency 1028system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10088.642211 # average overall mshr miss latency 1029system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate 1030system.cpu.l2cache.tags.replacements 112684 # number of replacements 1031system.cpu.l2cache.tags.tagsinuse 64825.802499 # Cycle average of tags in use 1032system.cpu.l2cache.tags.total_refs 3846196 # Total number of references to valid blocks. 1033system.cpu.l2cache.tags.sampled_refs 176714 # Sample count of references to valid blocks. 1034system.cpu.l2cache.tags.avg_refs 21.765089 # Average number of references to valid blocks. 1035system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 1036system.cpu.l2cache.tags.occ_blocks::writebacks 50361.141250 # Average occupied blocks per requestor 1037system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 15.517179 # Average occupied blocks per requestor 1038system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.137228 # Average occupied blocks per requestor 1039system.cpu.l2cache.tags.occ_blocks::cpu.inst 3161.997282 # Average occupied blocks per requestor 1040system.cpu.l2cache.tags.occ_blocks::cpu.data 11287.009561 # Average occupied blocks per requestor 1041system.cpu.l2cache.tags.occ_percent::writebacks 0.768450 # Average percentage of cache occupancy 1042system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000237 # Average percentage of cache occupancy 1043system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy 1044system.cpu.l2cache.tags.occ_percent::cpu.inst 0.048248 # Average percentage of cache occupancy 1045system.cpu.l2cache.tags.occ_percent::cpu.data 0.172226 # Average percentage of cache occupancy 1046system.cpu.l2cache.tags.occ_percent::total 0.989163 # Average percentage of cache occupancy 1047system.cpu.l2cache.tags.occ_task_id_blocks::1024 64030 # Occupied blocks per task id 1048system.cpu.l2cache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id 1049system.cpu.l2cache.tags.age_task_id_blocks_1024::1 558 # Occupied blocks per task id 1050system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3484 # Occupied blocks per task id 1051system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5616 # Occupied blocks per task id 1052system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54343 # Occupied blocks per task id 1053system.cpu.l2cache.tags.occ_task_id_percent::1024 0.977020 # Percentage of cache occupancy per task id 1054system.cpu.l2cache.tags.tag_accesses 35101682 # Number of tag accesses 1055system.cpu.l2cache.tags.data_accesses 35101682 # Number of data accesses 1056system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 67331 # number of ReadReq hits 1057system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 13137 # number of ReadReq hits 1058system.cpu.l2cache.ReadReq_hits::cpu.inst 984666 # number of ReadReq hits 1059system.cpu.l2cache.ReadReq_hits::cpu.data 1336353 # number of ReadReq hits 1060system.cpu.l2cache.ReadReq_hits::total 2401487 # number of ReadReq hits 1061system.cpu.l2cache.Writeback_hits::writebacks 1585305 # number of Writeback hits 1062system.cpu.l2cache.Writeback_hits::total 1585305 # number of Writeback hits 1063system.cpu.l2cache.UpgradeReq_hits::cpu.data 326 # number of UpgradeReq hits 1064system.cpu.l2cache.UpgradeReq_hits::total 326 # number of UpgradeReq hits 1065system.cpu.l2cache.ReadExReq_hits::cpu.data 154346 # number of ReadExReq hits 1066system.cpu.l2cache.ReadExReq_hits::total 154346 # number of ReadExReq hits 1067system.cpu.l2cache.demand_hits::cpu.dtb.walker 67331 # number of demand (read+write) hits 1068system.cpu.l2cache.demand_hits::cpu.itb.walker 13137 # number of demand (read+write) hits 1069system.cpu.l2cache.demand_hits::cpu.inst 984666 # number of demand (read+write) hits 1070system.cpu.l2cache.demand_hits::cpu.data 1490699 # number of demand (read+write) hits 1071system.cpu.l2cache.demand_hits::total 2555833 # number of demand (read+write) hits 1072system.cpu.l2cache.overall_hits::cpu.dtb.walker 67331 # number of overall hits 1073system.cpu.l2cache.overall_hits::cpu.itb.walker 13137 # number of overall hits 1074system.cpu.l2cache.overall_hits::cpu.inst 984666 # number of overall hits 1075system.cpu.l2cache.overall_hits::cpu.data 1490699 # number of overall hits 1076system.cpu.l2cache.overall_hits::total 2555833 # number of overall hits 1077system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 66 # number of ReadReq misses 1078system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses 1079system.cpu.l2cache.ReadReq_misses::cpu.inst 16391 # number of ReadReq misses 1080system.cpu.l2cache.ReadReq_misses::cpu.data 35623 # number of ReadReq misses 1081system.cpu.l2cache.ReadReq_misses::total 52085 # number of ReadReq misses 1082system.cpu.l2cache.UpgradeReq_misses::cpu.data 1473 # number of UpgradeReq misses 1083system.cpu.l2cache.UpgradeReq_misses::total 1473 # number of UpgradeReq misses 1084system.cpu.l2cache.ReadExReq_misses::cpu.data 133459 # number of ReadExReq misses 1085system.cpu.l2cache.ReadExReq_misses::total 133459 # number of ReadExReq misses 1086system.cpu.l2cache.demand_misses::cpu.dtb.walker 66 # number of demand (read+write) misses 1087system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses 1088system.cpu.l2cache.demand_misses::cpu.inst 16391 # number of demand (read+write) misses 1089system.cpu.l2cache.demand_misses::cpu.data 169082 # number of demand (read+write) misses 1090system.cpu.l2cache.demand_misses::total 185544 # number of demand (read+write) misses 1091system.cpu.l2cache.overall_misses::cpu.dtb.walker 66 # number of overall misses 1092system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses 1093system.cpu.l2cache.overall_misses::cpu.inst 16391 # number of overall misses 1094system.cpu.l2cache.overall_misses::cpu.data 169082 # number of overall misses 1095system.cpu.l2cache.overall_misses::total 185544 # number of overall misses 1096system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6193250 # number of ReadReq miss cycles 1097system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 446000 # number of ReadReq miss cycles 1098system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1375483774 # number of ReadReq miss cycles 1099system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3059797000 # number of ReadReq miss cycles 1100system.cpu.l2cache.ReadReq_miss_latency::total 4441920024 # number of ReadReq miss cycles 1101system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22673320 # number of UpgradeReq miss cycles 1102system.cpu.l2cache.UpgradeReq_miss_latency::total 22673320 # number of UpgradeReq miss cycles 1103system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10319199473 # number of ReadExReq miss cycles 1104system.cpu.l2cache.ReadExReq_miss_latency::total 10319199473 # number of ReadExReq miss cycles 1105system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6193250 # number of demand (read+write) miss cycles 1106system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 446000 # number of demand (read+write) miss cycles 1107system.cpu.l2cache.demand_miss_latency::cpu.inst 1375483774 # number of demand (read+write) miss cycles 1108system.cpu.l2cache.demand_miss_latency::cpu.data 13378996473 # number of demand (read+write) miss cycles 1109system.cpu.l2cache.demand_miss_latency::total 14761119497 # number of demand (read+write) miss cycles 1110system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6193250 # number of overall miss cycles 1111system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 446000 # number of overall miss cycles 1112system.cpu.l2cache.overall_miss_latency::cpu.inst 1375483774 # number of overall miss cycles 1113system.cpu.l2cache.overall_miss_latency::cpu.data 13378996473 # number of overall miss cycles 1114system.cpu.l2cache.overall_miss_latency::total 14761119497 # number of overall miss cycles 1115system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 67397 # number of ReadReq accesses(hits+misses) 1116system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 13142 # number of ReadReq accesses(hits+misses) 1117system.cpu.l2cache.ReadReq_accesses::cpu.inst 1001057 # number of ReadReq accesses(hits+misses) 1118system.cpu.l2cache.ReadReq_accesses::cpu.data 1371976 # number of ReadReq accesses(hits+misses) 1119system.cpu.l2cache.ReadReq_accesses::total 2453572 # number of ReadReq accesses(hits+misses) 1120system.cpu.l2cache.Writeback_accesses::writebacks 1585305 # number of Writeback accesses(hits+misses) 1121system.cpu.l2cache.Writeback_accesses::total 1585305 # number of Writeback accesses(hits+misses) 1122system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1799 # number of UpgradeReq accesses(hits+misses) 1123system.cpu.l2cache.UpgradeReq_accesses::total 1799 # number of UpgradeReq accesses(hits+misses) 1124system.cpu.l2cache.ReadExReq_accesses::cpu.data 287805 # number of ReadExReq accesses(hits+misses) 1125system.cpu.l2cache.ReadExReq_accesses::total 287805 # number of ReadExReq accesses(hits+misses) 1126system.cpu.l2cache.demand_accesses::cpu.dtb.walker 67397 # number of demand (read+write) accesses 1127system.cpu.l2cache.demand_accesses::cpu.itb.walker 13142 # number of demand (read+write) accesses 1128system.cpu.l2cache.demand_accesses::cpu.inst 1001057 # number of demand (read+write) accesses 1129system.cpu.l2cache.demand_accesses::cpu.data 1659781 # number of demand (read+write) accesses 1130system.cpu.l2cache.demand_accesses::total 2741377 # number of demand (read+write) accesses 1131system.cpu.l2cache.overall_accesses::cpu.dtb.walker 67397 # number of overall (read+write) accesses 1132system.cpu.l2cache.overall_accesses::cpu.itb.walker 13142 # number of overall (read+write) accesses 1133system.cpu.l2cache.overall_accesses::cpu.inst 1001057 # number of overall (read+write) accesses 1134system.cpu.l2cache.overall_accesses::cpu.data 1659781 # number of overall (read+write) accesses 1135system.cpu.l2cache.overall_accesses::total 2741377 # number of overall (read+write) accesses 1136system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000979 # miss rate for ReadReq accesses 1137system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000380 # miss rate for ReadReq accesses 1138system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016374 # miss rate for ReadReq accesses 1139system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025965 # miss rate for ReadReq accesses 1140system.cpu.l2cache.ReadReq_miss_rate::total 0.021228 # miss rate for ReadReq accesses 1141system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.818788 # miss rate for UpgradeReq accesses 1142system.cpu.l2cache.UpgradeReq_miss_rate::total 0.818788 # miss rate for UpgradeReq accesses 1143system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.463713 # miss rate for ReadExReq accesses 1144system.cpu.l2cache.ReadExReq_miss_rate::total 0.463713 # miss rate for ReadExReq accesses 1145system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000979 # miss rate for demand accesses 1146system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000380 # miss rate for demand accesses 1147system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016374 # miss rate for demand accesses 1148system.cpu.l2cache.demand_miss_rate::cpu.data 0.101870 # miss rate for demand accesses 1149system.cpu.l2cache.demand_miss_rate::total 0.067683 # miss rate for demand accesses 1150system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000979 # miss rate for overall accesses 1151system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000380 # miss rate for overall accesses 1152system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016374 # miss rate for overall accesses 1153system.cpu.l2cache.overall_miss_rate::cpu.data 0.101870 # miss rate for overall accesses 1154system.cpu.l2cache.overall_miss_rate::total 0.067683 # miss rate for overall accesses 1155system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 93837.121212 # average ReadReq miss latency 1156system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 89200 # average ReadReq miss latency 1157system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83917.013849 # average ReadReq miss latency 1158system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85893.860708 # average ReadReq miss latency 1159system.cpu.l2cache.ReadReq_avg_miss_latency::total 85282.135432 # average ReadReq miss latency 1160system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15392.613714 # average UpgradeReq miss latency 1161system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15392.613714 # average UpgradeReq miss latency 1162system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77321.120891 # average ReadExReq miss latency 1163system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77321.120891 # average ReadExReq miss latency 1164system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 93837.121212 # average overall miss latency 1165system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 89200 # average overall miss latency 1166system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83917.013849 # average overall miss latency 1167system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79127.266492 # average overall miss latency 1168system.cpu.l2cache.demand_avg_miss_latency::total 79555.897776 # average overall miss latency 1169system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 93837.121212 # average overall miss latency 1170system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 89200 # average overall miss latency 1171system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83917.013849 # average overall miss latency 1172system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79127.266492 # average overall miss latency 1173system.cpu.l2cache.overall_avg_miss_latency::total 79555.897776 # average overall miss latency 1174system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1175system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1176system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1177system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1178system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1179system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1180system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1181system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1182system.cpu.l2cache.writebacks::writebacks 103019 # number of writebacks 1183system.cpu.l2cache.writebacks::total 103019 # number of writebacks 1184system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits 1185system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits 1186system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits 1187system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits 1188system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits 1189system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits 1190system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits 1191system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits 1192system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits 1193system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 66 # number of ReadReq MSHR misses 1194system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses 1195system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16388 # number of ReadReq MSHR misses 1196system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35622 # number of ReadReq MSHR misses 1197system.cpu.l2cache.ReadReq_mshr_misses::total 52081 # number of ReadReq MSHR misses 1198system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1473 # number of UpgradeReq MSHR misses 1199system.cpu.l2cache.UpgradeReq_mshr_misses::total 1473 # number of UpgradeReq MSHR misses 1200system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133459 # number of ReadExReq MSHR misses 1201system.cpu.l2cache.ReadExReq_mshr_misses::total 133459 # number of ReadExReq MSHR misses 1202system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 66 # number of demand (read+write) MSHR misses 1203system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses 1204system.cpu.l2cache.demand_mshr_misses::cpu.inst 16388 # number of demand (read+write) MSHR misses 1205system.cpu.l2cache.demand_mshr_misses::cpu.data 169081 # number of demand (read+write) MSHR misses 1206system.cpu.l2cache.demand_mshr_misses::total 185540 # number of demand (read+write) MSHR misses 1207system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 66 # number of overall MSHR misses 1208system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses 1209system.cpu.l2cache.overall_mshr_misses::cpu.inst 16388 # number of overall MSHR misses 1210system.cpu.l2cache.overall_mshr_misses::cpu.data 169081 # number of overall MSHR misses 1211system.cpu.l2cache.overall_mshr_misses::total 185540 # number of overall MSHR misses 1212system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5361750 # number of ReadReq MSHR miss cycles 1213system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 383000 # number of ReadReq MSHR miss cycles 1214system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1170197226 # number of ReadReq MSHR miss cycles 1215system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2615090750 # number of ReadReq MSHR miss cycles 1216system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3791032726 # number of ReadReq MSHR miss cycles 1217system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27003455 # number of UpgradeReq MSHR miss cycles 1218system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27003455 # number of UpgradeReq MSHR miss cycles 1219system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8650755527 # number of ReadExReq MSHR miss cycles 1220system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8650755527 # number of ReadExReq MSHR miss cycles 1221system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5361750 # number of demand (read+write) MSHR miss cycles 1222system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 383000 # number of demand (read+write) MSHR miss cycles 1223system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1170197226 # number of demand (read+write) MSHR miss cycles 1224system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11265846277 # number of demand (read+write) MSHR miss cycles 1225system.cpu.l2cache.demand_mshr_miss_latency::total 12441788253 # number of demand (read+write) MSHR miss cycles 1226system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5361750 # number of overall MSHR miss cycles 1227system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 383000 # number of overall MSHR miss cycles 1228system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1170197226 # number of overall MSHR miss cycles 1229system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11265846277 # number of overall MSHR miss cycles 1230system.cpu.l2cache.overall_mshr_miss_latency::total 12441788253 # number of overall MSHR miss cycles 1231system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 88987317500 # number of ReadReq MSHR uncacheable cycles 1232system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 88987317500 # number of ReadReq MSHR uncacheable cycles 1233system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2410942500 # number of WriteReq MSHR uncacheable cycles 1234system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2410942500 # number of WriteReq MSHR uncacheable cycles 1235system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91398260000 # number of overall MSHR uncacheable cycles 1236system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91398260000 # number of overall MSHR uncacheable cycles 1237system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000979 # mshr miss rate for ReadReq accesses 1238system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000380 # mshr miss rate for ReadReq accesses 1239system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016371 # mshr miss rate for ReadReq accesses 1240system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025964 # mshr miss rate for ReadReq accesses 1241system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021227 # mshr miss rate for ReadReq accesses 1242system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.818788 # mshr miss rate for UpgradeReq accesses 1243system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.818788 # mshr miss rate for UpgradeReq accesses 1244system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.463713 # mshr miss rate for ReadExReq accesses 1245system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.463713 # mshr miss rate for ReadExReq accesses 1246system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000979 # mshr miss rate for demand accesses 1247system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000380 # mshr miss rate for demand accesses 1248system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016371 # mshr miss rate for demand accesses 1249system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101869 # mshr miss rate for demand accesses 1250system.cpu.l2cache.demand_mshr_miss_rate::total 0.067681 # mshr miss rate for demand accesses 1251system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000979 # mshr miss rate for overall accesses 1252system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000380 # mshr miss rate for overall accesses 1253system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016371 # mshr miss rate for overall accesses 1254system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101869 # mshr miss rate for overall accesses 1255system.cpu.l2cache.overall_mshr_miss_rate::total 0.067681 # mshr miss rate for overall accesses 1256system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 81238.636364 # average ReadReq mshr miss latency 1257system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 76600 # average ReadReq mshr miss latency 1258system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71405.737491 # average ReadReq mshr miss latency 1259system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73412.238224 # average ReadReq mshr miss latency 1260system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72791.089380 # average ReadReq mshr miss latency 1261system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18332.284453 # average UpgradeReq mshr miss latency 1262system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18332.284453 # average UpgradeReq mshr miss latency 1263system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64819.574004 # average ReadExReq mshr miss latency 1264system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64819.574004 # average ReadExReq mshr miss latency 1265system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 81238.636364 # average overall mshr miss latency 1266system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 76600 # average overall mshr miss latency 1267system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71405.737491 # average overall mshr miss latency 1268system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66629.877260 # average overall mshr miss latency 1269system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67057.175019 # average overall mshr miss latency 1270system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 81238.636364 # average overall mshr miss latency 1271system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 76600 # average overall mshr miss latency 1272system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71405.737491 # average overall mshr miss latency 1273system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66629.877260 # average overall mshr miss latency 1274system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67057.175019 # average overall mshr miss latency 1275system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1276system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1277system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1278system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1279system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1280system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1281system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1282system.cpu.toL2Bus.trans_dist::ReadReq 3070183 # Transaction distribution 1283system.cpu.toL2Bus.trans_dist::ReadResp 3069642 # Transaction distribution 1284system.cpu.toL2Bus.trans_dist::WriteReq 13919 # Transaction distribution 1285system.cpu.toL2Bus.trans_dist::WriteResp 13919 # Transaction distribution 1286system.cpu.toL2Bus.trans_dist::Writeback 1585305 # Transaction distribution 1287system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46754 # Transaction distribution 1288system.cpu.toL2Bus.trans_dist::UpgradeReq 2280 # Transaction distribution 1289system.cpu.toL2Bus.trans_dist::UpgradeResp 2280 # Transaction distribution 1290system.cpu.toL2Bus.trans_dist::ReadExReq 287814 # Transaction distribution 1291system.cpu.toL2Bus.trans_dist::ReadExResp 287814 # Transaction distribution 1292system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution 1293system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2002294 # Packet count per connected master and slave (bytes) 1294system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6123530 # Packet count per connected master and slave (bytes) 1295system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 32263 # Packet count per connected master and slave (bytes) 1296system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 162669 # Packet count per connected master and slave (bytes) 1297system.cpu.toL2Bus.pkt_count::total 8320756 # Packet count per connected master and slave (bytes) 1298system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64067648 # Cumulative packet size per connected master and slave (bytes) 1299system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207974818 # Cumulative packet size per connected master and slave (bytes) 1300system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1052928 # Cumulative packet size per connected master and slave (bytes) 1301system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5614976 # Cumulative packet size per connected master and slave (bytes) 1302system.cpu.toL2Bus.pkt_size::total 278710370 # Cumulative packet size per connected master and slave (bytes) 1303system.cpu.toL2Bus.snoops 59545 # Total snoops (count) 1304system.cpu.toL2Bus.snoop_fanout::samples 4387643 # Request fanout histogram 1305system.cpu.toL2Bus.snoop_fanout::mean 3.010865 # Request fanout histogram 1306system.cpu.toL2Bus.snoop_fanout::stdev 0.103666 # Request fanout histogram 1307system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1308system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1309system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1310system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1311system.cpu.toL2Bus.snoop_fanout::3 4339973 98.91% 98.91% # Request fanout histogram 1312system.cpu.toL2Bus.snoop_fanout::4 47670 1.09% 100.00% # Request fanout histogram 1313system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1314system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1315system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1316system.cpu.toL2Bus.snoop_fanout::total 4387643 # Request fanout histogram 1317system.cpu.toL2Bus.reqLayer0.occupancy 4071571970 # Layer occupancy (ticks) 1318system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1319system.cpu.toL2Bus.snoopLayer0.occupancy 574500 # Layer occupancy (ticks) 1320system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1321system.cpu.toL2Bus.respLayer0.occupancy 1506228195 # Layer occupancy (ticks) 1322system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1323system.cpu.toL2Bus.respLayer1.occupancy 3139390437 # Layer occupancy (ticks) 1324system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 1325system.cpu.toL2Bus.respLayer2.occupancy 23723987 # Layer occupancy (ticks) 1326system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1327system.cpu.toL2Bus.respLayer3.occupancy 112471118 # Layer occupancy (ticks) 1328system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1329system.iobus.trans_dist::ReadReq 223900 # Transaction distribution 1330system.iobus.trans_dist::ReadResp 223900 # Transaction distribution 1331system.iobus.trans_dist::WriteReq 57738 # Transaction distribution 1332system.iobus.trans_dist::WriteResp 11018 # Transaction distribution 1333system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution 1334system.iobus.trans_dist::MessageReq 1650 # Transaction distribution 1335system.iobus.trans_dist::MessageResp 1650 # Transaction distribution 1336system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) 1337system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) 1338system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) 1339system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) 1340system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) 1341system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) 1342system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) 1343system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) 1344system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 423734 # Packet count per connected master and slave (bytes) 1345system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) 1346system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) 1347system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) 1348system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes) 1349system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) 1350system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) 1351system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) 1352system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) 1353system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) 1354system.iobus.pkt_count_system.bridge.master::total 468004 # Packet count per connected master and slave (bytes) 1355system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95272 # Packet count per connected master and slave (bytes) 1356system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95272 # Packet count per connected master and slave (bytes) 1357system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3300 # Packet count per connected master and slave (bytes) 1358system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3300 # Packet count per connected master and slave (bytes) 1359system.iobus.pkt_count::total 566576 # Packet count per connected master and slave (bytes) 1360system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) 1361system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) 1362system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) 1363system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) 1364system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) 1365system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) 1366system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) 1367system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) 1368system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 211867 # Cumulative packet size per connected master and slave (bytes) 1369system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) 1370system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) 1371system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) 1372system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes) 1373system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) 1374system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) 1375system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) 1376system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) 1377system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) 1378system.iobus.pkt_size_system.bridge.master::total 240285 # Cumulative packet size per connected master and slave (bytes) 1379system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027872 # Cumulative packet size per connected master and slave (bytes) 1380system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027872 # Cumulative packet size per connected master and slave (bytes) 1381system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6600 # Cumulative packet size per connected master and slave (bytes) 1382system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6600 # Cumulative packet size per connected master and slave (bytes) 1383system.iobus.pkt_size::total 3274757 # Cumulative packet size per connected master and slave (bytes) 1384system.iobus.reqLayer0.occupancy 3933000 # Layer occupancy (ticks) 1385system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1386system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) 1387system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1388system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) 1389system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1390system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks) 1391system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1392system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) 1393system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1394system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) 1395system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) 1396system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks) 1397system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 1398system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) 1399system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) 1400system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) 1401system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) 1402system.iobus.reqLayer9.occupancy 211868000 # Layer occupancy (ticks) 1403system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) 1404system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) 1405system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1406system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) 1407system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) 1408system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks) 1409system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1410system.iobus.reqLayer14.occupancy 20815000 # Layer occupancy (ticks) 1411system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1412system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) 1413system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1414system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) 1415system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1416system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) 1417system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1418system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) 1419system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) 1420system.iobus.reqLayer19.occupancy 257352407 # Layer occupancy (ticks) 1421system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) 1422system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) 1423system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) 1424system.iobus.respLayer0.occupancy 456986000 # Layer occupancy (ticks) 1425system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1426system.iobus.respLayer1.occupancy 50389253 # Layer occupancy (ticks) 1427system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 1428system.iobus.respLayer2.occupancy 1650000 # Layer occupancy (ticks) 1429system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) 1430system.iocache.tags.replacements 47582 # number of replacements 1431system.iocache.tags.tagsinuse 0.177916 # Cycle average of tags in use 1432system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 1433system.iocache.tags.sampled_refs 47598 # Sample count of references to valid blocks. 1434system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 1435system.iocache.tags.warmup_cycle 4993302485000 # Cycle when the warmup percentage was hit. 1436system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.177916 # Average occupied blocks per requestor 1437system.iocache.tags.occ_percent::pc.south_bridge.ide 0.011120 # Average percentage of cache occupancy 1438system.iocache.tags.occ_percent::total 0.011120 # Average percentage of cache occupancy 1439system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1440system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 1441system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1442system.iocache.tags.tag_accesses 428724 # Number of tag accesses 1443system.iocache.tags.data_accesses 428724 # Number of data accesses 1444system.iocache.ReadReq_misses::pc.south_bridge.ide 916 # number of ReadReq misses 1445system.iocache.ReadReq_misses::total 916 # number of ReadReq misses 1446system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses 1447system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses 1448system.iocache.demand_misses::pc.south_bridge.ide 916 # number of demand (read+write) misses 1449system.iocache.demand_misses::total 916 # number of demand (read+write) misses 1450system.iocache.overall_misses::pc.south_bridge.ide 916 # number of overall misses 1451system.iocache.overall_misses::total 916 # number of overall misses 1452system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144791938 # number of ReadReq miss cycles 1453system.iocache.ReadReq_miss_latency::total 144791938 # number of ReadReq miss cycles 1454system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 8565273216 # number of WriteInvalidateReq miss cycles 1455system.iocache.WriteInvalidateReq_miss_latency::total 8565273216 # number of WriteInvalidateReq miss cycles 1456system.iocache.demand_miss_latency::pc.south_bridge.ide 144791938 # number of demand (read+write) miss cycles 1457system.iocache.demand_miss_latency::total 144791938 # number of demand (read+write) miss cycles 1458system.iocache.overall_miss_latency::pc.south_bridge.ide 144791938 # number of overall miss cycles 1459system.iocache.overall_miss_latency::total 144791938 # number of overall miss cycles 1460system.iocache.ReadReq_accesses::pc.south_bridge.ide 916 # number of ReadReq accesses(hits+misses) 1461system.iocache.ReadReq_accesses::total 916 # number of ReadReq accesses(hits+misses) 1462system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) 1463system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) 1464system.iocache.demand_accesses::pc.south_bridge.ide 916 # number of demand (read+write) accesses 1465system.iocache.demand_accesses::total 916 # number of demand (read+write) accesses 1466system.iocache.overall_accesses::pc.south_bridge.ide 916 # number of overall (read+write) accesses 1467system.iocache.overall_accesses::total 916 # number of overall (read+write) accesses 1468system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses 1469system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1470system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses 1471system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 1472system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses 1473system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1474system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses 1475system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1476system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158069.801310 # average ReadReq miss latency 1477system.iocache.ReadReq_avg_miss_latency::total 158069.801310 # average ReadReq miss latency 1478system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 183332.046575 # average WriteInvalidateReq miss latency 1479system.iocache.WriteInvalidateReq_avg_miss_latency::total 183332.046575 # average WriteInvalidateReq miss latency 1480system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158069.801310 # average overall miss latency 1481system.iocache.demand_avg_miss_latency::total 158069.801310 # average overall miss latency 1482system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158069.801310 # average overall miss latency 1483system.iocache.overall_avg_miss_latency::total 158069.801310 # average overall miss latency 1484system.iocache.blocked_cycles::no_mshrs 29224 # number of cycles access was blocked 1485system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1486system.iocache.blocked::no_mshrs 4409 # number of cycles access was blocked 1487system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1488system.iocache.avg_blocked_cycles::no_mshrs 6.628260 # average number of cycles each access was blocked 1489system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1490system.iocache.fast_writes 0 # number of fast writes performed 1491system.iocache.cache_copies 0 # number of cache copies performed 1492system.iocache.writebacks::writebacks 46668 # number of writebacks 1493system.iocache.writebacks::total 46668 # number of writebacks 1494system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 916 # number of ReadReq MSHR misses 1495system.iocache.ReadReq_mshr_misses::total 916 # number of ReadReq MSHR misses 1496system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses 1497system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses 1498system.iocache.demand_mshr_misses::pc.south_bridge.ide 916 # number of demand (read+write) MSHR misses 1499system.iocache.demand_mshr_misses::total 916 # number of demand (read+write) MSHR misses 1500system.iocache.overall_mshr_misses::pc.south_bridge.ide 916 # number of overall MSHR misses 1501system.iocache.overall_mshr_misses::total 916 # number of overall MSHR misses 1502system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96734432 # number of ReadReq MSHR miss cycles 1503system.iocache.ReadReq_mshr_miss_latency::total 96734432 # number of ReadReq MSHR miss cycles 1504system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6135821228 # number of WriteInvalidateReq MSHR miss cycles 1505system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6135821228 # number of WriteInvalidateReq MSHR miss cycles 1506system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 96734432 # number of demand (read+write) MSHR miss cycles 1507system.iocache.demand_mshr_miss_latency::total 96734432 # number of demand (read+write) MSHR miss cycles 1508system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 96734432 # number of overall MSHR miss cycles 1509system.iocache.overall_mshr_miss_latency::total 96734432 # number of overall MSHR miss cycles 1510system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses 1511system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1512system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses 1513system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 1514system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses 1515system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1516system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses 1517system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1518system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105605.275109 # average ReadReq mshr miss latency 1519system.iocache.ReadReq_avg_mshr_miss_latency::total 105605.275109 # average ReadReq mshr miss latency 1520system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 131331.789983 # average WriteInvalidateReq mshr miss latency 1521system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131331.789983 # average WriteInvalidateReq mshr miss latency 1522system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 105605.275109 # average overall mshr miss latency 1523system.iocache.demand_avg_mshr_miss_latency::total 105605.275109 # average overall mshr miss latency 1524system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 105605.275109 # average overall mshr miss latency 1525system.iocache.overall_avg_mshr_miss_latency::total 105605.275109 # average overall mshr miss latency 1526system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1527system.membus.trans_dist::ReadReq 657690 # Transaction distribution 1528system.membus.trans_dist::ReadResp 657682 # Transaction distribution 1529system.membus.trans_dist::WriteReq 13919 # Transaction distribution 1530system.membus.trans_dist::WriteResp 13919 # Transaction distribution 1531system.membus.trans_dist::Writeback 149687 # Transaction distribution 1532system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution 1533system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution 1534system.membus.trans_dist::UpgradeReq 2233 # Transaction distribution 1535system.membus.trans_dist::UpgradeResp 1752 # Transaction distribution 1536system.membus.trans_dist::ReadExReq 133182 # Transaction distribution 1537system.membus.trans_dist::ReadExResp 133180 # Transaction distribution 1538system.membus.trans_dist::MessageReq 1650 # Transaction distribution 1539system.membus.trans_dist::MessageResp 1650 # Transaction distribution 1540system.membus.trans_dist::BadAddressError 8 # Transaction distribution 1541system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3300 # Packet count per connected master and slave (bytes) 1542system.membus.pkt_count_system.apicbridge.master::total 3300 # Packet count per connected master and slave (bytes) 1543system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 468004 # Packet count per connected master and slave (bytes) 1544system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769220 # Packet count per connected master and slave (bytes) 1545system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 476828 # Packet count per connected master and slave (bytes) 1546system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) 1547system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1714068 # Packet count per connected master and slave (bytes) 1548system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141467 # Packet count per connected master and slave (bytes) 1549system.membus.pkt_count_system.iocache.mem_side::total 141467 # Packet count per connected master and slave (bytes) 1550system.membus.pkt_count::total 1858835 # Packet count per connected master and slave (bytes) 1551system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6600 # Cumulative packet size per connected master and slave (bytes) 1552system.membus.pkt_size_system.apicbridge.master::total 6600 # Cumulative packet size per connected master and slave (bytes) 1553system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 240285 # Cumulative packet size per connected master and slave (bytes) 1554system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538437 # Cumulative packet size per connected master and slave (bytes) 1555system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18406720 # Cumulative packet size per connected master and slave (bytes) 1556system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20185442 # Cumulative packet size per connected master and slave (bytes) 1557system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005184 # Cumulative packet size per connected master and slave (bytes) 1558system.membus.pkt_size_system.iocache.mem_side::total 6005184 # Cumulative packet size per connected master and slave (bytes) 1559system.membus.pkt_size::total 26197226 # Cumulative packet size per connected master and slave (bytes) 1560system.membus.snoops 1640 # Total snoops (count) 1561system.membus.snoop_fanout::samples 384867 # Request fanout histogram 1562system.membus.snoop_fanout::mean 1 # Request fanout histogram 1563system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1564system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1565system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1566system.membus.snoop_fanout::1 384867 100.00% 100.00% # Request fanout histogram 1567system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1568system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1569system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1570system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1571system.membus.snoop_fanout::total 384867 # Request fanout histogram 1572system.membus.reqLayer0.occupancy 357799000 # Layer occupancy (ticks) 1573system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1574system.membus.reqLayer1.occupancy 388520500 # Layer occupancy (ticks) 1575system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1576system.membus.reqLayer2.occupancy 3300000 # Layer occupancy (ticks) 1577system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1578system.membus.reqLayer3.occupancy 1203232654 # Layer occupancy (ticks) 1579system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) 1580system.membus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) 1581system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) 1582system.membus.respLayer0.occupancy 1650000 # Layer occupancy (ticks) 1583system.membus.respLayer0.utilization 0.0 # Layer utilization (%) 1584system.membus.respLayer2.occupancy 2208381292 # Layer occupancy (ticks) 1585system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1586system.membus.respLayer4.occupancy 51518747 # Layer occupancy (ticks) 1587system.membus.respLayer4.utilization 0.0 # Layer utilization (%) 1588system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1589system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). 1590system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). 1591system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. 1592system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. 1593system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. 1594system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 1595system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 1596system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). 1597system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. 1598system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. 1599system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. 1600system.cpu.kern.inst.arm 0 # number of arm instructions executed 1601system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed 1602 1603---------- End Simulation Statistics ---------- 1604