xref: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.821872                       # Number of seconds simulated
sim_ticks                                51821872017500                       # Number of ticks simulated
final_tick                               51821872017500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                1130306                       # Simulator instruction rate (inst/s)
host_op_rate                                  1328204                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            68135685678                       # Simulator tick rate (ticks/s)
host_mem_usage                                 679252                       # Number of bytes of host memory used
host_seconds                                   760.57                       # Real time elapsed on the host
sim_insts                                   859675526                       # Number of instructions simulated
sim_ops                                    1010190283                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu.dtb.walker       215360                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker       217216                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           5027508                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          42852104                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        396352                       # Number of bytes read from this memory
system.physmem.bytes_read::total             48708540                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      5027508                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         5027508                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     69916032                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
system.physmem.bytes_written::total          69936612                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker         3365                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker         3394                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst             118962                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data             669577                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6193                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                801491                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1092438                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1095011                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           4156                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker           4192                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst                97015                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data               826912                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             7648                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                  939922                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst           97015                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total              97015                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1349161                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                 397                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1349558                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1349161                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          4156                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker          4192                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst               97015                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data              827309                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            7648                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2289480                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                        801491                       # Number of read requests accepted
system.physmem.writeReqs                      1095011                       # Number of write requests accepted
system.physmem.readBursts                      801491                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1095011                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 51258176                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     37248                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  69934720                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  48708540                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               69936612                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      582                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2264                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               50792                       # Per bank write bursts
system.physmem.perBankRdBursts::1               52585                       # Per bank write bursts
system.physmem.perBankRdBursts::2               45494                       # Per bank write bursts
system.physmem.perBankRdBursts::3               47583                       # Per bank write bursts
system.physmem.perBankRdBursts::4               47505                       # Per bank write bursts
system.physmem.perBankRdBursts::5               55338                       # Per bank write bursts
system.physmem.perBankRdBursts::6               45272                       # Per bank write bursts
system.physmem.perBankRdBursts::7               44194                       # Per bank write bursts
system.physmem.perBankRdBursts::8               47329                       # Per bank write bursts
system.physmem.perBankRdBursts::9               89850                       # Per bank write bursts
system.physmem.perBankRdBursts::10              47381                       # Per bank write bursts
system.physmem.perBankRdBursts::11              49509                       # Per bank write bursts
system.physmem.perBankRdBursts::12              42888                       # Per bank write bursts
system.physmem.perBankRdBursts::13              45239                       # Per bank write bursts
system.physmem.perBankRdBursts::14              44185                       # Per bank write bursts
system.physmem.perBankRdBursts::15              45765                       # Per bank write bursts
system.physmem.perBankWrBursts::0               68303                       # Per bank write bursts
system.physmem.perBankWrBursts::1               72266                       # Per bank write bursts
system.physmem.perBankWrBursts::2               69005                       # Per bank write bursts
system.physmem.perBankWrBursts::3               70230                       # Per bank write bursts
system.physmem.perBankWrBursts::4               67390                       # Per bank write bursts
system.physmem.perBankWrBursts::5               74059                       # Per bank write bursts
system.physmem.perBankWrBursts::6               66126                       # Per bank write bursts
system.physmem.perBankWrBursts::7               65521                       # Per bank write bursts
system.physmem.perBankWrBursts::8               69259                       # Per bank write bursts
system.physmem.perBankWrBursts::9               70740                       # Per bank write bursts
system.physmem.perBankWrBursts::10              68902                       # Per bank write bursts
system.physmem.perBankWrBursts::11              68447                       # Per bank write bursts
system.physmem.perBankWrBursts::12              64485                       # Per bank write bursts
system.physmem.perBankWrBursts::13              66687                       # Per bank write bursts
system.physmem.perBankWrBursts::14              65337                       # Per bank write bursts
system.physmem.perBankWrBursts::15              65973                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                         520                       # Number of times write queue was full causing retry
system.physmem.totGap                    51821869155500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                   43101                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                       2                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                  758375                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1092438                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    767476                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                     27687                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       514                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                       318                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       458                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       422                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       585                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                       474                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       927                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       560                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      272                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      285                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      188                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      149                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      121                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      108                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      104                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                       99                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       83                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       72                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        7                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    30627                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    35223                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    57744                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    61921                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    65097                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    62233                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    60629                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    62549                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    64813                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    63194                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    67249                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    66047                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    62409                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    60534                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    61342                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    60374                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    59104                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    58755                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     2399                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     1915                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     1595                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     1349                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     1180                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     1074                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     1043                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      852                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      821                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      854                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      798                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      853                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      796                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      786                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      758                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      811                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      936                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                     1000                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      837                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      851                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      761                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      822                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      850                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                     1161                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                     1037                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      797                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                     1136                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                     1468                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                     1603                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                      687                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                     1058                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       494423                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      245.119212                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     147.459226                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     287.994040                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         219027     44.30%     44.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       131709     26.64%     70.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        43564      8.81%     79.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        22937      4.64%     84.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        15466      3.13%     87.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767         9602      1.94%     89.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         7396      1.50%     90.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         5862      1.19%     92.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        38860      7.86%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         494423                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         57152                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        14.013543                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      134.391751                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023          57148     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047            2      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::20480-21503            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::23552-24575            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           57152                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         57152                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        19.119716                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       18.362666                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        8.513001                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           44632     78.09%     78.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23            9484     16.59%     94.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27             590      1.03%     95.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             287      0.50%     96.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35             876      1.53%     97.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             130      0.23%     97.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             106      0.19%     98.17% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              28      0.05%     98.22% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51              52      0.09%     98.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              20      0.03%     98.34% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              16      0.03%     98.37% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              48      0.08%     98.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             542      0.95%     99.40% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              77      0.13%     99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              52      0.09%     99.63% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79              79      0.14%     99.77% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83              35      0.06%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::84-87               1      0.00%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               2      0.00%     99.83% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::92-95               3      0.01%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               1      0.00%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             1      0.00%     99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::108-111            16      0.03%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             1      0.00%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             1      0.00%     99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             2      0.00%     99.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             9      0.02%     99.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            18      0.03%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             7      0.01%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.00%     99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143            11      0.02%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147             1      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             1      0.00%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             3      0.01%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::164-167             1      0.00%     99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::172-175             4      0.01%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::184-187             1      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::188-191             2      0.00%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             6      0.01%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::196-199             2      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::200-203             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           57152                       # Writes before turning the bus around for reads
system.physmem.totQLat                    29342800943                       # Total ticks spent queuing
system.physmem.totMemAccLat               44359844693                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   4004545000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       36636.87                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  55386.87                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           0.99                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.35                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        0.94                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.35                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.00                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        26.29                       # Average write queue length when enqueuing
system.physmem.readRowHits                     600164                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    799051                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   74.94                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  73.12                       # Row buffer hit rate for writes
system.physmem.avgGap                     27324974.69                       # Average gap between requests
system.physmem.pageHitRate                      73.89                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 1814238300                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  964290525                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                2775767820                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               2886138000                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           48823313760.000008                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            38608999590                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy             3011693280                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy       94024683450                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy       72592857120                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy       12330153384360                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy             12595677850665                       # Total energy per rank (pJ)
system.physmem_0.averagePower              243.057176                       # Core power per rank (mW)
system.physmem_0.totalIdleTime           51728729641480                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE     5702683750                       # Time in different power states
system.physmem_0.memoryStateTime::REF     20763204000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF   51334071775500                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 189043780464                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     66096536270                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 206194037516                       # Time in different power states
system.physmem_1.actEnergy                 1715949060                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  912044760                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                2942722440                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               2817912600                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           46334636400.000008                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            38117726280                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy             2754271680                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy       87558235230                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy       69416939040                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy       12335402832360                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy             12587993852010                       # Total energy per rank (pJ)
system.physmem_1.averagePower              242.908898                       # Core power per rank (mW)
system.physmem_1.totalIdleTime           51731061753764                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE     5083631742                       # Time in different power states
system.physmem_1.memoryStateTime::REF     19704542000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF   51358275119250                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 180773350699                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     66022048244                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 192013325565                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu.inst           96                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           132                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total           96                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             29                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst             2                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data             1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                3                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            2                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst            2                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               3                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.walker.walks                    196189                       # Table walker walks requested
system.cpu.dtb.walker.walksLong                196189                       # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2        13637                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksLongTerminationLevel::Level3       152377                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore           19                       # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples       196170                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean     0.152929                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev    48.843369                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-2047       196168    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::10240-12287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::16384-18431            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total       196170                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples       166033                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 23680.132865                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 19678.566540                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 19257.699461                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-65535       164361     98.99%     98.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-131071         1402      0.84%     99.84% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-196607           64      0.04%     99.88% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::196608-262143           64      0.04%     99.91% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-327679           59      0.04%     99.95% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-393215           17      0.01%     99.96% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::393216-458751            9      0.01%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::458752-524287            3      0.00%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::524288-589823            2      0.00%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::589824-655359           48      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::786432-851967            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total       166033                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples  -7075428332                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean     0.933158                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::stdev     0.249747                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0      -472932796      6.68%      6.68% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::1     -6602495536     93.32%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total  -7075428332                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K        152378     91.79%     91.79% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M         13637      8.21%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total       166015                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       196189                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total       196189                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       166015                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total       166015                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total       362204                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                    161617169                       # DTB read hits
system.cpu.dtb.read_misses                     145721                       # DTB read misses
system.cpu.dtb.write_hits                   146821389                       # DTB write hits
system.cpu.dtb.write_misses                     50468                       # DTB write misses
system.cpu.dtb.flush_tlb                           10                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid               40242                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                    1033                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                    72934                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                   7326                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                     19275                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                161762890                       # DTB read accesses
system.cpu.dtb.write_accesses               146871857                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                         308438558                       # DTB hits
system.cpu.dtb.misses                          196189                       # DTB misses
system.cpu.dtb.accesses                     308634747                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.cpu.itb.walker.walks                    120716                       # Table walker walks requested
system.cpu.itb.walker.walksLong                120716                       # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2         1119                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksLongTerminationLevel::Level3       108836                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walkWaitTime::samples       120716                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0          120716    100.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total       120716                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples       109955                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 27513.978446                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 23291.832317                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 24606.943327                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-65535       107988     98.21%     98.21% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-131071         1629      1.48%     99.69% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-196607           80      0.07%     99.77% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::196608-262143           85      0.08%     99.84% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::262144-327679           60      0.05%     99.90% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::327680-393215           20      0.02%     99.92% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::393216-458751           11      0.01%     99.93% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::458752-524287            2      0.00%     99.93% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::524288-589823            1      0.00%     99.93% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::589824-655359           77      0.07%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::655360-720895            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total       109955                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples   -556629296                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0      -556629296    100.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total   -556629296                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K        108836     98.98%     98.98% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M          1119      1.02%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total       109955                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       120716                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total       120716                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       109955                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total       109955                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total       230671                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                    860205714                       # ITB inst hits
system.cpu.itb.inst_misses                     120716                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           10                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid               40242                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                    1033                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                    52133                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                860326430                       # ITB inst accesses
system.cpu.itb.hits                         860205714                       # DTB hits
system.cpu.itb.misses                          120716                       # DTB misses
system.cpu.itb.accesses                     860326430                       # DTB accesses
system.cpu.numPwrStateTransitions               32324                       # Number of power state transitions
system.cpu.pwrStateClkGateDist::samples         16162                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::mean     3111484469.414615                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::stdev    60405660268.224297                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::underflows         6871     42.51%     42.51% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1000-5e+10         9256     57.27%     99.78% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::5e+10-1e+11            5      0.03%     99.81% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1e+11-1.5e+11            3      0.02%     99.83% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::1.5e+11-2e+11            1      0.01%     99.84% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2e+11-2.5e+11            2      0.01%     99.85% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::2.5e+11-3e+11            2      0.01%     99.86% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::3e+11-3.5e+11            1      0.01%     99.87% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::4.5e+11-5e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::7e+11-7.5e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::7.5e+11-8e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::overflows           18      0.11%    100.00% # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::max_value 1988775138696                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateClkGateDist::total           16162                       # Distribution of time spent in the clock gated state
system.cpu.pwrStateResidencyTicks::ON    1534060022821                       # Cumulative time (in ticks) in various power states
system.cpu.pwrStateResidencyTicks::CLK_GATED 50287811994679                       # Cumulative time (in ticks) in various power states
system.cpu.numCycles                     103643744035                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    16162                       # number of quiesce instructions executed
system.cpu.committedInsts                   859675526                       # Number of instructions committed
system.cpu.committedOps                    1010190283                       # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses             928076114                       # Number of integer alu accesses
system.cpu.num_fp_alu_accesses                 896946                       # Number of float alu accesses
system.cpu.num_func_calls                    51280324                       # number of times a function call or return occured
system.cpu.num_conditional_control_insts    130830869                       # number of instructions that are conditional controls
system.cpu.num_int_insts                    928076114                       # number of integer instructions
system.cpu.num_fp_insts                        896946                       # number of float instructions
system.cpu.num_int_register_reads          1348653813                       # number of times the integer registers were read
system.cpu.num_int_register_writes          735932841                       # number of times the integer registers were written
system.cpu.num_fp_register_reads              1446833                       # number of times the floating registers were read
system.cpu.num_fp_register_writes              759084                       # number of times the floating registers were written
system.cpu.num_cc_register_reads            224374440                       # number of times the CC registers were read
system.cpu.num_cc_register_writes           223774216                       # number of times the CC registers were written
system.cpu.num_mem_refs                     308419372                       # number of memory refs
system.cpu.num_load_insts                   161608555                       # Number of load instructions
system.cpu.num_store_insts                  146810817                       # Number of store instructions
system.cpu.num_idle_cycles               100575623989.356064                       # Number of idle cycles
system.cpu.num_busy_cycles               3068120045.643941                       # Number of busy cycles
system.cpu.not_idle_fraction                 0.029603                       # Percentage of non-idle cycles
system.cpu.idle_fraction                     0.970397                       # Percentage of idle cycles
system.cpu.Branches                         191908708                       # Number of branches fetched
system.cpu.op_class::No_OpClass                     1      0.00%      0.00% # Class of executed instruction
system.cpu.op_class::IntAlu                 699966855     69.25%     69.25% # Class of executed instruction
system.cpu.op_class::IntMult                  2168337      0.21%     69.47% # Class of executed instruction
system.cpu.op_class::IntDiv                     97451      0.01%     69.48% # Class of executed instruction
system.cpu.op_class::FloatAdd                       8      0.00%     69.48% # Class of executed instruction
system.cpu.op_class::FloatCmp                      13      0.00%     69.48% # Class of executed instruction
system.cpu.op_class::FloatCvt                      21      0.00%     69.48% # Class of executed instruction
system.cpu.op_class::FloatMult                      0      0.00%     69.48% # Class of executed instruction
system.cpu.op_class::FloatMultAcc                   0      0.00%     69.48% # Class of executed instruction
system.cpu.op_class::FloatDiv                       0      0.00%     69.48% # Class of executed instruction
system.cpu.op_class::FloatMisc                 111537      0.01%     69.49% # Class of executed instruction
system.cpu.op_class::FloatSqrt                      0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdAdd                        0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdAddAcc                     0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdAlu                        0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdCmp                        0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdCvt                        0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdMisc                       0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdMult                       0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdMultAcc                    0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdShift                      0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdShiftAcc                   0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdSqrt                       0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatAdd                   0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatAlu                   0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatCmp                   0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatCvt                   0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatDiv                   0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatMisc                  0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatMult                  0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc               0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt                  0      0.00%     69.49% # Class of executed instruction
system.cpu.op_class::MemRead                161496118     15.98%     85.46% # Class of executed instruction
system.cpu.op_class::MemWrite               146137887     14.46%     99.92% # Class of executed instruction
system.cpu.op_class::FloatMemRead              112437      0.01%     99.93% # Class of executed instruction
system.cpu.op_class::FloatMemWrite             672930      0.07%    100.00% # Class of executed instruction
system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
system.cpu.op_class::total                 1010763595                       # Class of executed instruction
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.replacements           9712819                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.962733                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           298526964                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           9713331                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             30.733737                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        3801165500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.962733                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999927                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999927                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           47                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          413                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           49                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3            3                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1243130616                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1243130616                       # Number of data accesses
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.ReadReq_hits::cpu.data    151166129                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       151166129                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    139372457                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      139372457                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       383388                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        383388                       # number of SoftPFReq hits
system.cpu.dcache.WriteLineReq_hits::cpu.data       333792                       # number of WriteLineReq hits
system.cpu.dcache.WriteLineReq_hits::total       333792                       # number of WriteLineReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      3475542                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      3475542                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      3766859                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      3766859                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     290872378                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        290872378                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    291255766                       # number of overall hits
system.cpu.dcache.overall_hits::total       291255766                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      5061632                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       5061632                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data      2072136                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total      2072136                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data      1203806                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total      1203806                       # number of SoftPFReq misses
system.cpu.dcache.WriteLineReq_misses::cpu.data      1225587                       # number of WriteLineReq misses
system.cpu.dcache.WriteLineReq_misses::total      1225587                       # number of WriteLineReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data       292986                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total       292986                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data      8359355                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total        8359355                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data      9563161                       # number of overall misses
system.cpu.dcache.overall_misses::total       9563161                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data  86410296000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total  86410296000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data  64078644000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total  64078644000                       # number of WriteReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  24971401500                       # number of WriteLineReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::total  24971401500                       # number of WriteLineReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   4471115500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total   4471115500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       167500                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       167500                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 175460341500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 175460341500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 175460341500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 175460341500                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    156227761                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    156227761                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    141444593                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    141444593                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data      1587194                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total      1587194                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::cpu.data      1559379                       # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::total      1559379                       # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3768528                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      3768528                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      3766861                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      3766861                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    299231733                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    299231733                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    300818927                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    300818927                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.032399                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.032399                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.014650                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.014650                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.758449                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.758449                       # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.785946                       # miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::total     0.785946                       # miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.077745                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.077745                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000001                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.027936                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.027936                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.031790                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.031790                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17071.627491                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17071.627491                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30923.956729                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 30923.956729                       # average WriteReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 20375.054158                       # average WriteLineReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::total 20375.054158                       # average WriteLineReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15260.509035                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15260.509035                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        83750                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        83750                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 20989.698547                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 20989.698547                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 18347.525625                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 18347.525625                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::writebacks      7496626                       # number of writebacks
system.cpu.dcache.writebacks::total           7496626                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        21661                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        21661                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        21294                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        21294                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data        70691                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total        70691                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data        42955                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total        42955                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data        42955                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total        42955                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5039971                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      5039971                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      2050842                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      2050842                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1203452                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total      1203452                       # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1225587                       # number of WriteLineReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::total      1225587                       # number of WriteLineReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       222295                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total       222295                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      8316400                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      8316400                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      9519852                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      9519852                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33706                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total        33706                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33710                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        33710                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67416                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        67416                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  80495651000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  80495651000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  61277537000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  61277537000                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  21572116000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  21572116000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  23745814500                       # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  23745814500                       # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3066936500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3066936500                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       165500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       165500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 165519002500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 165519002500                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187091118500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 187091118500                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6232858500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6232858500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   6232858500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total   6232858500                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032260                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032260                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014499                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014499                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.758226                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.758226                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.785946                       # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.785946                       # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.058987                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.058987                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.027793                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.027793                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.031646                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.031646                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15971.451225                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15971.451225                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29879.209125                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29879.209125                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17925.198512                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17925.198512                       # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 19375.054158                       # average WriteLineReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 19375.054158                       # average WriteLineReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13796.695832                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13796.695832                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        82750                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        82750                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19902.722632                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19902.722632                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19652.733940                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19652.733940                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184918.367650                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184918.367650                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92453.697935                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92453.697935                       # average overall mshr uncacheable latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.replacements          13486266                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.886684                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           846718931                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs          13486778                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             62.781409                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       32464203500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.886684                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.999779                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.999779                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           67                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          249                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          191                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            5                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         873692497                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        873692497                       # Number of data accesses
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.ReadReq_hits::cpu.inst    846718931                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       846718931                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     846718931                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        846718931                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    846718931                       # number of overall hits
system.cpu.icache.overall_hits::total       846718931                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst     13486783                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total      13486783                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst     13486783                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total       13486783                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst     13486783                       # number of overall misses
system.cpu.icache.overall_misses::total      13486783                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 183511474500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 183511474500                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 183511474500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 183511474500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 183511474500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 183511474500                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    860205714                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    860205714                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    860205714                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    860205714                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    860205714                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    860205714                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.015679                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.015679                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.015679                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.015679                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.015679                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.015679                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13606.764082                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13606.764082                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13606.764082                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13606.764082                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13606.764082                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13606.764082                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::writebacks     13486266                       # number of writebacks
system.cpu.icache.writebacks::total          13486266                       # number of writebacks
system.cpu.icache.ReadReq_mshr_misses::cpu.inst     13486783                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total     13486783                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst     13486783                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total     13486783                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst     13486783                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total     13486783                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        43125                       # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total        43125                       # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        43125                       # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total        43125                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170024691500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 170024691500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170024691500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 170024691500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170024691500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 170024691500                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   3557271000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   3557271000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   3557271000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total   3557271000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.015679                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.015679                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.015679                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.015679                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.015679                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.015679                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12606.764082                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12606.764082                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12606.764082                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12606.764082                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12606.764082                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12606.764082                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82487.443478                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82487.443478                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82487.443478                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82487.443478                       # average overall mshr uncacheable latency
system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.tags.replacements          1158711                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65407.211772                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           44429708                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1220523                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            36.402188                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle       6958052500                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 10958.963563                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   463.658135                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   540.023475                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  6661.801500                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 46782.765099                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.167221                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.007075                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.008240                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.101651                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.713848                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.998035                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023          301                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        61511                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4          301                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           31                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          241                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          815                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5756                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54668                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004593                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.938583                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        377726834                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       377726834                       # Number of data accesses
system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       307081                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       228330                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total         535411                       # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks      7496626                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      7496626                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks     13484674                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total     13484674                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data        24887                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total        24887                       # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1607168                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1607168                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     13410909                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total     13410909                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6209836                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      6209836                       # number of ReadSharedReq hits
system.cpu.l2cache.InvalidateReq_hits::cpu.data       727975                       # number of InvalidateReq hits
system.cpu.l2cache.InvalidateReq_hits::total       727975                       # number of InvalidateReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker       307081                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker       228330                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst     13410909                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      7817004                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total        21763324                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker       307081                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker       228330                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst     13410909                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      7817004                       # number of overall hits
system.cpu.l2cache.overall_hits::total       21763324                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         3365                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         3394                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         6759                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data         3908                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total         3908                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       414879                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       414879                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        75874                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        75874                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       255882                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       255882                       # number of ReadSharedReq misses
system.cpu.l2cache.InvalidateReq_misses::cpu.data       497612                       # number of InvalidateReq misses
system.cpu.l2cache.InvalidateReq_misses::total       497612                       # number of InvalidateReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker         3365                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker         3394                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        75874                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       670761                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        753394                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker         3365                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker         3394                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        75874                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       670761                       # number of overall misses
system.cpu.l2cache.overall_misses::total       753394                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    447362000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    421528500                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    868890500                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data     69021500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total     69021500                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       162500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total       162500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  40901099500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  40901099500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst   8709565500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total   8709565500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  30155420000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  30155420000                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    447362000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    421528500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst   8709565500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  71056519500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total  80634975500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    447362000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    421528500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst   8709565500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  71056519500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total  80634975500                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       310446                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       231724                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total       542170                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks      7496626                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      7496626                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks     13484674                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total     13484674                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data        28795                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total        28795                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      2022047                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      2022047                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     13486783                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total     13486783                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      6465718                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      6465718                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1225587                       # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::total      1225587                       # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker       310446                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker       231724                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst     13486783                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      8487765                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total     22516718                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker       310446                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker       231724                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst     13486783                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      8487765                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total     22516718                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.010839                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.014647                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.012467                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.135718                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.135718                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.205178                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.205178                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005626                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005626                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.039575                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.039575                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.406019                       # miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::total     0.406019                       # miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.010839                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.014647                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005626                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.079027                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.033459                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.010839                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.014647                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005626                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.079027                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.033459                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 132945.616642                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 124198.143783                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 128553.114366                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17661.591607                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17661.591607                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        81250                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        81250                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98585.610503                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98585.610503                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 114789.855550                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 114789.855550                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 117848.930366                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 117848.930366                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 132945.616642                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 124198.143783                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 114789.855550                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 105934.184456                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 107028.958951                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 132945.616642                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 124198.143783                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 114789.855550                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 105934.184456                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 107028.958951                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.writebacks::writebacks       985808                       # number of writebacks
system.cpu.l2cache.writebacks::total           985808                       # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         3365                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         3394                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         6759                       # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         3908                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total         3908                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       414879                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       414879                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        75874                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        75874                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       255882                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       255882                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       497612                       # number of InvalidateReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::total       497612                       # number of InvalidateReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         3365                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         3394                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        75874                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       670761                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       753394                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         3365                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         3394                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        75874                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       670761                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       753394                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        43125                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33706                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total        76831                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33710                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33710                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        43125                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67416                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total       110541                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    413712000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    387588500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    801300500                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     74391500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     74391500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       142500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       142500                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  36752309500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  36752309500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst   7950825500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total   7950825500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  27596583533                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  27596583533                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data   9287554000                       # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total   9287554000                       # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    413712000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    387588500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   7950825500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  64348893033                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  73101019033                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    413712000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    387588500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   7950825500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  64348893033                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  73101019033                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   3018208500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5810725500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8828934000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   3018208500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   5810725500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total   8828934000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.010839                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.014647                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.012467                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.135718                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.135718                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.205178                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.205178                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005626                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005626                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.039575                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.039575                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.406019                       # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.406019                       # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.010839                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.014647                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005626                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.079027                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.033459                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.010839                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.014647                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005626                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.079027                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.033459                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 122945.616642                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 114198.143783                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 118553.114366                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19035.696008                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19035.696008                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        71250                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        71250                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88585.610503                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88585.610503                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 104789.855550                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 104789.855550                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 107848.866012                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 107848.866012                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 18664.248451                       # average InvalidateReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 18664.248451                       # average InvalidateReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 122945.616642                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 114198.143783                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 104789.855550                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 95934.159906                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 97028.937094                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 122945.616642                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 114198.143783                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 104789.855550                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 95934.159906                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 97028.937094                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69987.443478                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172394.395657                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 114913.693691                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69987.443478                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86192.083482                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 79870.220099                       # average overall mshr uncacheable latency
system.cpu.toL2Bus.snoop_filter.tot_requests     46927036                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests     23726903                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests         1749                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         1976                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         1976                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.cpu.toL2Bus.trans_dist::ReadReq        1011319                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp      20964705                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         33710                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        33710                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty      8482434                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean     13486266                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict      2389096                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq        28798                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            2                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp        28800                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      2022047                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      2022047                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq     13486783                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      6468652                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq      1256381                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateResp      1225599                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     40546082                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     29332849                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       592477                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side       884181                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          71355589                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1726447636                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1023248134                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      1853792                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      2483568                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total         2754033130                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                     1585660                       # Total snoops (count)
system.cpu.toL2Bus.snoopTraffic              66286896                       # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples     25466403                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.019742                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.139111                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0           24963657     98.03%     98.03% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             502746      1.97%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       25466403                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    44736270000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy      1643382                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy   20273299500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   13409418464                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy     360753000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy     573735000                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                40342                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40342                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231042                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231042                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353826                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334600                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334600                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492520                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             42151500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                10500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               321500                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                11000                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                11000                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               11500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               17000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               11000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            25717000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            38602500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           569022926                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147802000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements               115502                       # number of replacements
system.iocache.tags.tagsinuse               10.457099                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115518                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13154766854000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     3.510741                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     6.946357                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.219421                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.434147                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.653569                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1040046                       # Number of tag accesses
system.iocache.tags.data_accesses             1040046                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8857                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8894                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide       115521                       # number of demand (read+write) misses
system.iocache.demand_misses::total            115561                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide       115521                       # number of overall misses
system.iocache.overall_misses::total           115561                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5086500                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   2023754150                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   2028840650                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13483489276                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13483489276                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5437500                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide  15507243426                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  15512680926                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5437500                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide  15507243426                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  15512680926                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8857                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8894                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide       115521                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total          115561                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide       115521                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total         115561                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137472.972973                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 228492.057130                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 228113.407915                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126410.872234                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 126410.872234                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 135937.500000                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 134237.441037                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 134238.029491                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 135937.500000                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 134237.441037                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 134238.029491                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         52159                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3349                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    15.574500                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks          106630                       # number of writebacks
system.iocache.writebacks::total               106630                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8857                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8894                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide       115521                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total       115561                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide       115521                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total       115561                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3236500                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1580904150                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1584140650                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8144739087                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   8144739087                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3437500                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   9725643237                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   9729080737                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3437500                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   9725643237                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   9729080737                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87472.972973                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 178492.057130                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 178113.407915                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76358.837912                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76358.837912                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85937.500000                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 84189.396188                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 84190.001272                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85937.500000                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 84189.396188                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 84190.001272                       # average overall mshr miss latency
system.membus.snoop_filter.tot_requests       2644146                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests      1308848                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests         3757                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               76831                       # Transaction distribution
system.membus.trans_dist::ReadResp             424240                       # Transaction distribution
system.membus.trans_dist::WriteReq              33710                       # Transaction distribution
system.membus.trans_dist::WriteResp             33710                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1092438                       # Transaction distribution
system.membus.trans_dist::CleanEvict           180711                       # Transaction distribution
system.membus.trans_dist::UpgradeReq             4469                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              2                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               8                       # Transaction distribution
system.membus.trans_dist::ReadExReq            414321                       # Transaction distribution
system.membus.trans_dist::ReadExResp           414321                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        347409                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        604276                       # Transaction distribution
system.membus.trans_dist::InvalidateResp        30630                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6942                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3256123                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3385827                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237256                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       237256                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                3623083                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          132                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13884                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    111424480                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total    111594330                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7220672                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7220672                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               118815002                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                            33993                       # Total snoops (count)
system.membus.snoopTraffic                     214720                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples           1481018                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.023235                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.150648                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 1446607     97.68%     97.68% # Request fanout histogram
system.membus.snoop_fanout::1                   34411      2.32%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             1481018                       # Request fanout histogram
system.membus.reqLayer0.occupancy           106898000                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               41500                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5816000                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          7183768776                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         4201020680                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           76902808                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             149                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              149                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500                       # Cumulative time (in ticks) in various power states

---------- End Simulation Statistics   ----------