stats.txt revision 11754
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.821872 # Number of seconds simulated 4sim_ticks 51821872017500 # Number of ticks simulated 5final_tick 51821872017500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1130306 # Simulator instruction rate (inst/s) 8host_op_rate 1328204 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 68135685678 # Simulator tick rate (ticks/s) 10host_mem_usage 679252 # Number of bytes of host memory used 11host_seconds 760.57 # Real time elapsed on the host 12sim_insts 859675526 # Number of instructions simulated 13sim_ops 1010190283 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 215360 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 217216 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 5027508 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 42852104 # Number of bytes read from this memory 21system.physmem.bytes_read::realview.ide 396352 # Number of bytes read from this memory 22system.physmem.bytes_read::total 48708540 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 5027508 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 5027508 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 69916032 # Number of bytes written to this memory 26system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 27system.physmem.bytes_written::total 69936612 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 3365 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 3394 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 118962 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 669577 # Number of read requests responded to by this memory 32system.physmem.num_reads::realview.ide 6193 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 801491 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 1092438 # Number of write requests responded to by this memory 35system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 36system.physmem.num_writes::total 1095011 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 4156 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 4192 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 97015 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 826912 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::realview.ide 7648 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::total 939922 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 97015 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 97015 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 1349161 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::total 1349558 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 1349161 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 4156 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 4192 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 97015 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 827309 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::realview.ide 7648 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::total 2289480 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.readReqs 801491 # Number of read requests accepted 56system.physmem.writeReqs 1095011 # Number of write requests accepted 57system.physmem.readBursts 801491 # Number of DRAM read bursts, including those serviced by the write queue 58system.physmem.writeBursts 1095011 # Number of DRAM write bursts, including those merged in the write queue 59system.physmem.bytesReadDRAM 51258176 # Total number of bytes read from DRAM 60system.physmem.bytesReadWrQ 37248 # Total number of bytes read from write queue 61system.physmem.bytesWritten 69934720 # Total number of bytes written to DRAM 62system.physmem.bytesReadSys 48708540 # Total read bytes from the system interface side 63system.physmem.bytesWrittenSys 69936612 # Total written bytes from the system interface side 64system.physmem.servicedByWrQ 582 # Number of DRAM read bursts serviced by the write queue 65system.physmem.mergedWrBursts 2264 # Number of DRAM write bursts merged with an existing one 66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 67system.physmem.perBankRdBursts::0 50792 # Per bank write bursts 68system.physmem.perBankRdBursts::1 52585 # Per bank write bursts 69system.physmem.perBankRdBursts::2 45494 # Per bank write bursts 70system.physmem.perBankRdBursts::3 47583 # Per bank write bursts 71system.physmem.perBankRdBursts::4 47505 # Per bank write bursts 72system.physmem.perBankRdBursts::5 55338 # Per bank write bursts 73system.physmem.perBankRdBursts::6 45272 # Per bank write bursts 74system.physmem.perBankRdBursts::7 44194 # Per bank write bursts 75system.physmem.perBankRdBursts::8 47329 # Per bank write bursts 76system.physmem.perBankRdBursts::9 89850 # Per bank write bursts 77system.physmem.perBankRdBursts::10 47381 # Per bank write bursts 78system.physmem.perBankRdBursts::11 49509 # Per bank write bursts 79system.physmem.perBankRdBursts::12 42888 # Per bank write bursts 80system.physmem.perBankRdBursts::13 45239 # Per bank write bursts 81system.physmem.perBankRdBursts::14 44185 # Per bank write bursts 82system.physmem.perBankRdBursts::15 45765 # Per bank write bursts 83system.physmem.perBankWrBursts::0 68303 # Per bank write bursts 84system.physmem.perBankWrBursts::1 72266 # Per bank write bursts 85system.physmem.perBankWrBursts::2 69005 # Per bank write bursts 86system.physmem.perBankWrBursts::3 70230 # Per bank write bursts 87system.physmem.perBankWrBursts::4 67390 # Per bank write bursts 88system.physmem.perBankWrBursts::5 74059 # Per bank write bursts 89system.physmem.perBankWrBursts::6 66126 # Per bank write bursts 90system.physmem.perBankWrBursts::7 65521 # Per bank write bursts 91system.physmem.perBankWrBursts::8 69259 # Per bank write bursts 92system.physmem.perBankWrBursts::9 70740 # Per bank write bursts 93system.physmem.perBankWrBursts::10 68902 # Per bank write bursts 94system.physmem.perBankWrBursts::11 68447 # Per bank write bursts 95system.physmem.perBankWrBursts::12 64485 # Per bank write bursts 96system.physmem.perBankWrBursts::13 66687 # Per bank write bursts 97system.physmem.perBankWrBursts::14 65337 # Per bank write bursts 98system.physmem.perBankWrBursts::15 65973 # Per bank write bursts 99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 100system.physmem.numWrRetry 520 # Number of times write queue was full causing retry 101system.physmem.totGap 51821869155500 # Total gap between requests 102system.physmem.readPktSize::0 0 # Read request sizes (log2) 103system.physmem.readPktSize::1 0 # Read request sizes (log2) 104system.physmem.readPktSize::2 43101 # Read request sizes (log2) 105system.physmem.readPktSize::3 13 # Read request sizes (log2) 106system.physmem.readPktSize::4 2 # Read request sizes (log2) 107system.physmem.readPktSize::5 0 # Read request sizes (log2) 108system.physmem.readPktSize::6 758375 # Read request sizes (log2) 109system.physmem.writePktSize::0 0 # Write request sizes (log2) 110system.physmem.writePktSize::1 0 # Write request sizes (log2) 111system.physmem.writePktSize::2 1 # Write request sizes (log2) 112system.physmem.writePktSize::3 2572 # Write request sizes (log2) 113system.physmem.writePktSize::4 0 # Write request sizes (log2) 114system.physmem.writePktSize::5 0 # Write request sizes (log2) 115system.physmem.writePktSize::6 1092438 # Write request sizes (log2) 116system.physmem.rdQLenPdf::0 767476 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 27687 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 514 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::3 318 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::4 458 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::5 422 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 585 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 474 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 927 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 560 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 272 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::11 285 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::12 188 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::13 149 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::14 121 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::15 108 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::17 99 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::18 83 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::19 72 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 148system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::15 30627 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::16 35223 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::17 57744 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::18 61921 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::19 65097 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::20 62233 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::21 60629 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::22 62549 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::23 64813 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::24 63194 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::25 67249 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::26 66047 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::27 62409 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::28 60534 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::29 61342 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::30 60374 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::31 59104 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::32 58755 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::33 2399 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::34 1915 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::35 1595 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::36 1349 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::37 1180 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::38 1074 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::39 1043 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::40 852 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::41 821 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::42 854 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::43 798 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::44 853 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::45 796 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::46 786 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::47 758 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::48 811 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::49 936 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::50 1000 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::51 837 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::52 851 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::53 761 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::54 822 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::55 850 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::56 1161 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::57 1037 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::58 797 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::59 1136 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::60 1468 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::61 1603 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::62 687 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::63 1058 # What write queue length does an incoming req see 212system.physmem.bytesPerActivate::samples 494423 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::mean 245.119212 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::gmean 147.459226 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::stdev 287.994040 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::0-127 219027 44.30% 44.30% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::128-255 131709 26.64% 70.94% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::256-383 43564 8.81% 79.75% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::384-511 22937 4.64% 84.39% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::512-639 15466 3.13% 87.52% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::640-767 9602 1.94% 89.46% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::768-895 7396 1.50% 90.95% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::896-1023 5862 1.19% 92.14% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1024-1151 38860 7.86% 100.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::total 494423 # Bytes accessed per row activation 226system.physmem.rdPerTurnAround::samples 57152 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::mean 14.013543 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::stdev 134.391751 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::0-1023 57148 99.99% 99.99% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 233system.physmem.rdPerTurnAround::total 57152 # Reads before turning the bus around for writes 234system.physmem.wrPerTurnAround::samples 57152 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::mean 19.119716 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::gmean 18.362666 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::stdev 8.513001 # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::16-19 44632 78.09% 78.09% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::20-23 9484 16.59% 94.69% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::24-27 590 1.03% 95.72% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::28-31 287 0.50% 96.22% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::32-35 876 1.53% 97.76% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::36-39 130 0.23% 97.98% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::40-43 106 0.19% 98.17% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::44-47 28 0.05% 98.22% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::48-51 52 0.09% 98.31% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::52-55 20 0.03% 98.34% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::56-59 16 0.03% 98.37% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::60-63 48 0.08% 98.45% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::64-67 542 0.95% 99.40% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::68-71 77 0.13% 99.54% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::72-75 52 0.09% 99.63% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::76-79 79 0.14% 99.77% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::80-83 35 0.06% 99.83% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::84-87 1 0.00% 99.83% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::88-91 2 0.00% 99.83% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::92-95 3 0.01% 99.84% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::96-99 1 0.00% 99.84% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::100-103 1 0.00% 99.84% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::108-111 16 0.03% 99.87% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::112-115 1 0.00% 99.87% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::116-119 1 0.00% 99.87% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::120-123 2 0.00% 99.88% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::124-127 9 0.02% 99.89% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::128-131 18 0.03% 99.92% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::132-135 7 0.01% 99.94% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::136-139 1 0.00% 99.94% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::140-143 11 0.02% 99.96% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::144-147 1 0.00% 99.96% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::148-151 1 0.00% 99.96% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::160-163 3 0.01% 99.97% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::164-167 1 0.00% 99.97% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::172-175 4 0.01% 99.98% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::180-183 2 0.00% 99.98% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::184-187 1 0.00% 99.98% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::188-191 2 0.00% 99.98% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::192-195 6 0.01% 99.99% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::196-199 2 0.00% 100.00% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::200-203 1 0.00% 100.00% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::total 57152 # Writes before turning the bus around for reads 281system.physmem.totQLat 29342800943 # Total ticks spent queuing 282system.physmem.totMemAccLat 44359844693 # Total ticks spent from burst creation until serviced by the DRAM 283system.physmem.totBusLat 4004545000 # Total ticks spent in databus transfers 284system.physmem.avgQLat 36636.87 # Average queueing delay per DRAM burst 285system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 286system.physmem.avgMemAccLat 55386.87 # Average memory access latency per DRAM burst 287system.physmem.avgRdBW 0.99 # Average DRAM read bandwidth in MiByte/s 288system.physmem.avgWrBW 1.35 # Average achieved write bandwidth in MiByte/s 289system.physmem.avgRdBWSys 0.94 # Average system read bandwidth in MiByte/s 290system.physmem.avgWrBWSys 1.35 # Average system write bandwidth in MiByte/s 291system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 292system.physmem.busUtil 0.02 # Data bus utilization in percentage 293system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 294system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 295system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 296system.physmem.avgWrQLen 26.29 # Average write queue length when enqueuing 297system.physmem.readRowHits 600164 # Number of row buffer hits during reads 298system.physmem.writeRowHits 799051 # Number of row buffer hits during writes 299system.physmem.readRowHitRate 74.94 # Row buffer hit rate for reads 300system.physmem.writeRowHitRate 73.12 # Row buffer hit rate for writes 301system.physmem.avgGap 27324974.69 # Average gap between requests 302system.physmem.pageHitRate 73.89 # Row buffer hit rate, read and write combined 303system.physmem_0.actEnergy 1814238300 # Energy for activate commands per rank (pJ) 304system.physmem_0.preEnergy 964290525 # Energy for precharge commands per rank (pJ) 305system.physmem_0.readEnergy 2775767820 # Energy for read commands per rank (pJ) 306system.physmem_0.writeEnergy 2886138000 # Energy for write commands per rank (pJ) 307system.physmem_0.refreshEnergy 48823313760.000008 # Energy for refresh commands per rank (pJ) 308system.physmem_0.actBackEnergy 38608999590 # Energy for active background per rank (pJ) 309system.physmem_0.preBackEnergy 3011693280 # Energy for precharge background per rank (pJ) 310system.physmem_0.actPowerDownEnergy 94024683450 # Energy for active power-down per rank (pJ) 311system.physmem_0.prePowerDownEnergy 72592857120 # Energy for precharge power-down per rank (pJ) 312system.physmem_0.selfRefreshEnergy 12330153384360 # Energy for self refresh per rank (pJ) 313system.physmem_0.totalEnergy 12595677850665 # Total energy per rank (pJ) 314system.physmem_0.averagePower 243.057176 # Core power per rank (mW) 315system.physmem_0.totalIdleTime 51728729641480 # Total Idle time Per DRAM Rank 316system.physmem_0.memoryStateTime::IDLE 5702683750 # Time in different power states 317system.physmem_0.memoryStateTime::REF 20763204000 # Time in different power states 318system.physmem_0.memoryStateTime::SREF 51334071775500 # Time in different power states 319system.physmem_0.memoryStateTime::PRE_PDN 189043780464 # Time in different power states 320system.physmem_0.memoryStateTime::ACT 66096536270 # Time in different power states 321system.physmem_0.memoryStateTime::ACT_PDN 206194037516 # Time in different power states 322system.physmem_1.actEnergy 1715949060 # Energy for activate commands per rank (pJ) 323system.physmem_1.preEnergy 912044760 # Energy for precharge commands per rank (pJ) 324system.physmem_1.readEnergy 2942722440 # Energy for read commands per rank (pJ) 325system.physmem_1.writeEnergy 2817912600 # Energy for write commands per rank (pJ) 326system.physmem_1.refreshEnergy 46334636400.000008 # Energy for refresh commands per rank (pJ) 327system.physmem_1.actBackEnergy 38117726280 # Energy for active background per rank (pJ) 328system.physmem_1.preBackEnergy 2754271680 # Energy for precharge background per rank (pJ) 329system.physmem_1.actPowerDownEnergy 87558235230 # Energy for active power-down per rank (pJ) 330system.physmem_1.prePowerDownEnergy 69416939040 # Energy for precharge power-down per rank (pJ) 331system.physmem_1.selfRefreshEnergy 12335402832360 # Energy for self refresh per rank (pJ) 332system.physmem_1.totalEnergy 12587993852010 # Total energy per rank (pJ) 333system.physmem_1.averagePower 242.908898 # Core power per rank (mW) 334system.physmem_1.totalIdleTime 51731061753764 # Total Idle time Per DRAM Rank 335system.physmem_1.memoryStateTime::IDLE 5083631742 # Time in different power states 336system.physmem_1.memoryStateTime::REF 19704542000 # Time in different power states 337system.physmem_1.memoryStateTime::SREF 51358275119250 # Time in different power states 338system.physmem_1.memoryStateTime::PRE_PDN 180773350699 # Time in different power states 339system.physmem_1.memoryStateTime::ACT 66022048244 # Time in different power states 340system.physmem_1.memoryStateTime::ACT_PDN 192013325565 # Time in different power states 341system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 342system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory 343system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 344system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory 345system.realview.nvmem.bytes_inst_read::cpu.inst 96 # Number of instructions bytes read from this memory 346system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory 347system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory 348system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 349system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory 350system.realview.nvmem.bw_read::cpu.inst 2 # Total read bandwidth from this memory (bytes/s) 351system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 352system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) 353system.realview.nvmem.bw_inst_read::cpu.inst 2 # Instruction read bandwidth from this memory (bytes/s) 354system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) 355system.realview.nvmem.bw_total::cpu.inst 2 # Total bandwidth to/from this memory (bytes/s) 356system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 357system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) 358system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 359system.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 360system.bridge.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 361system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 362system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 363system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 364system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 365system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 366system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 367system.cpu_clk_domain.clock 500 # Clock period in ticks 368system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 369system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 370system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 371system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 372system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 373system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 374system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 375system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 376system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 377system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 378system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 379system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 380system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 381system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 382system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 383system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 384system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 385system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 386system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 387system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 388system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 389system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 390system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 391system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 392system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 393system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 394system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 395system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 396system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 397system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 398system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 399system.cpu.dtb.walker.walks 196189 # Table walker walks requested 400system.cpu.dtb.walker.walksLong 196189 # Table walker walks initiated with long descriptors 401system.cpu.dtb.walker.walksLongTerminationLevel::Level2 13637 # Level at which table walker walks with long descriptors terminate 402system.cpu.dtb.walker.walksLongTerminationLevel::Level3 152377 # Level at which table walker walks with long descriptors terminate 403system.cpu.dtb.walker.walksSquashedBefore 19 # Table walks squashed before starting 404system.cpu.dtb.walker.walkWaitTime::samples 196170 # Table walker wait (enqueue to first request) latency 405system.cpu.dtb.walker.walkWaitTime::mean 0.152929 # Table walker wait (enqueue to first request) latency 406system.cpu.dtb.walker.walkWaitTime::stdev 48.843369 # Table walker wait (enqueue to first request) latency 407system.cpu.dtb.walker.walkWaitTime::0-2047 196168 100.00% 100.00% # Table walker wait (enqueue to first request) latency 408system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 409system.cpu.dtb.walker.walkWaitTime::16384-18431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 410system.cpu.dtb.walker.walkWaitTime::total 196170 # Table walker wait (enqueue to first request) latency 411system.cpu.dtb.walker.walkCompletionTime::samples 166033 # Table walker service (enqueue to completion) latency 412system.cpu.dtb.walker.walkCompletionTime::mean 23680.132865 # Table walker service (enqueue to completion) latency 413system.cpu.dtb.walker.walkCompletionTime::gmean 19678.566540 # Table walker service (enqueue to completion) latency 414system.cpu.dtb.walker.walkCompletionTime::stdev 19257.699461 # Table walker service (enqueue to completion) latency 415system.cpu.dtb.walker.walkCompletionTime::0-65535 164361 98.99% 98.99% # Table walker service (enqueue to completion) latency 416system.cpu.dtb.walker.walkCompletionTime::65536-131071 1402 0.84% 99.84% # Table walker service (enqueue to completion) latency 417system.cpu.dtb.walker.walkCompletionTime::131072-196607 64 0.04% 99.88% # Table walker service (enqueue to completion) latency 418system.cpu.dtb.walker.walkCompletionTime::196608-262143 64 0.04% 99.91% # Table walker service (enqueue to completion) latency 419system.cpu.dtb.walker.walkCompletionTime::262144-327679 59 0.04% 99.95% # Table walker service (enqueue to completion) latency 420system.cpu.dtb.walker.walkCompletionTime::327680-393215 17 0.01% 99.96% # Table walker service (enqueue to completion) latency 421system.cpu.dtb.walker.walkCompletionTime::393216-458751 9 0.01% 99.97% # Table walker service (enqueue to completion) latency 422system.cpu.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 99.97% # Table walker service (enqueue to completion) latency 423system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.97% # Table walker service (enqueue to completion) latency 424system.cpu.dtb.walker.walkCompletionTime::589824-655359 48 0.03% 100.00% # Table walker service (enqueue to completion) latency 425system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 426system.cpu.dtb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 427system.cpu.dtb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 428system.cpu.dtb.walker.walkCompletionTime::total 166033 # Table walker service (enqueue to completion) latency 429system.cpu.dtb.walker.walksPending::samples -7075428332 # Table walker pending requests distribution 430system.cpu.dtb.walker.walksPending::mean 0.933158 # Table walker pending requests distribution 431system.cpu.dtb.walker.walksPending::stdev 0.249747 # Table walker pending requests distribution 432system.cpu.dtb.walker.walksPending::0 -472932796 6.68% 6.68% # Table walker pending requests distribution 433system.cpu.dtb.walker.walksPending::1 -6602495536 93.32% 100.00% # Table walker pending requests distribution 434system.cpu.dtb.walker.walksPending::total -7075428332 # Table walker pending requests distribution 435system.cpu.dtb.walker.walkPageSizes::4K 152378 91.79% 91.79% # Table walker page sizes translated 436system.cpu.dtb.walker.walkPageSizes::2M 13637 8.21% 100.00% # Table walker page sizes translated 437system.cpu.dtb.walker.walkPageSizes::total 166015 # Table walker page sizes translated 438system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 196189 # Table walker requests started/completed, data/inst 439system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 440system.cpu.dtb.walker.walkRequestOrigin_Requested::total 196189 # Table walker requests started/completed, data/inst 441system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 166015 # Table walker requests started/completed, data/inst 442system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 443system.cpu.dtb.walker.walkRequestOrigin_Completed::total 166015 # Table walker requests started/completed, data/inst 444system.cpu.dtb.walker.walkRequestOrigin::total 362204 # Table walker requests started/completed, data/inst 445system.cpu.dtb.inst_hits 0 # ITB inst hits 446system.cpu.dtb.inst_misses 0 # ITB inst misses 447system.cpu.dtb.read_hits 161617169 # DTB read hits 448system.cpu.dtb.read_misses 145721 # DTB read misses 449system.cpu.dtb.write_hits 146821389 # DTB write hits 450system.cpu.dtb.write_misses 50468 # DTB write misses 451system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed 452system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 453system.cpu.dtb.flush_tlb_mva_asid 40242 # Number of times TLB was flushed by MVA & ASID 454system.cpu.dtb.flush_tlb_asid 1033 # Number of times TLB was flushed by ASID 455system.cpu.dtb.flush_entries 72934 # Number of entries that have been flushed from TLB 456system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 457system.cpu.dtb.prefetch_faults 7326 # Number of TLB faults due to prefetch 458system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 459system.cpu.dtb.perms_faults 19275 # Number of TLB faults due to permissions restrictions 460system.cpu.dtb.read_accesses 161762890 # DTB read accesses 461system.cpu.dtb.write_accesses 146871857 # DTB write accesses 462system.cpu.dtb.inst_accesses 0 # ITB inst accesses 463system.cpu.dtb.hits 308438558 # DTB hits 464system.cpu.dtb.misses 196189 # DTB misses 465system.cpu.dtb.accesses 308634747 # DTB accesses 466system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 467system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 468system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 469system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 470system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 471system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 472system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 473system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 474system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 475system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 476system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 477system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 478system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 479system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 480system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 481system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 482system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 483system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 484system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 485system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 486system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 487system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 488system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 489system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 490system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 491system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 492system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 493system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 494system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 495system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 496system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 497system.cpu.itb.walker.walks 120716 # Table walker walks requested 498system.cpu.itb.walker.walksLong 120716 # Table walker walks initiated with long descriptors 499system.cpu.itb.walker.walksLongTerminationLevel::Level2 1119 # Level at which table walker walks with long descriptors terminate 500system.cpu.itb.walker.walksLongTerminationLevel::Level3 108836 # Level at which table walker walks with long descriptors terminate 501system.cpu.itb.walker.walkWaitTime::samples 120716 # Table walker wait (enqueue to first request) latency 502system.cpu.itb.walker.walkWaitTime::0 120716 100.00% 100.00% # Table walker wait (enqueue to first request) latency 503system.cpu.itb.walker.walkWaitTime::total 120716 # Table walker wait (enqueue to first request) latency 504system.cpu.itb.walker.walkCompletionTime::samples 109955 # Table walker service (enqueue to completion) latency 505system.cpu.itb.walker.walkCompletionTime::mean 27513.978446 # Table walker service (enqueue to completion) latency 506system.cpu.itb.walker.walkCompletionTime::gmean 23291.832317 # Table walker service (enqueue to completion) latency 507system.cpu.itb.walker.walkCompletionTime::stdev 24606.943327 # Table walker service (enqueue to completion) latency 508system.cpu.itb.walker.walkCompletionTime::0-65535 107988 98.21% 98.21% # Table walker service (enqueue to completion) latency 509system.cpu.itb.walker.walkCompletionTime::65536-131071 1629 1.48% 99.69% # Table walker service (enqueue to completion) latency 510system.cpu.itb.walker.walkCompletionTime::131072-196607 80 0.07% 99.77% # Table walker service (enqueue to completion) latency 511system.cpu.itb.walker.walkCompletionTime::196608-262143 85 0.08% 99.84% # Table walker service (enqueue to completion) latency 512system.cpu.itb.walker.walkCompletionTime::262144-327679 60 0.05% 99.90% # Table walker service (enqueue to completion) latency 513system.cpu.itb.walker.walkCompletionTime::327680-393215 20 0.02% 99.92% # Table walker service (enqueue to completion) latency 514system.cpu.itb.walker.walkCompletionTime::393216-458751 11 0.01% 99.93% # Table walker service (enqueue to completion) latency 515system.cpu.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.93% # Table walker service (enqueue to completion) latency 516system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.93% # Table walker service (enqueue to completion) latency 517system.cpu.itb.walker.walkCompletionTime::589824-655359 77 0.07% 100.00% # Table walker service (enqueue to completion) latency 518system.cpu.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 519system.cpu.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 520system.cpu.itb.walker.walkCompletionTime::total 109955 # Table walker service (enqueue to completion) latency 521system.cpu.itb.walker.walksPending::samples -556629296 # Table walker pending requests distribution 522system.cpu.itb.walker.walksPending::0 -556629296 100.00% 100.00% # Table walker pending requests distribution 523system.cpu.itb.walker.walksPending::total -556629296 # Table walker pending requests distribution 524system.cpu.itb.walker.walkPageSizes::4K 108836 98.98% 98.98% # Table walker page sizes translated 525system.cpu.itb.walker.walkPageSizes::2M 1119 1.02% 100.00% # Table walker page sizes translated 526system.cpu.itb.walker.walkPageSizes::total 109955 # Table walker page sizes translated 527system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 528system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 120716 # Table walker requests started/completed, data/inst 529system.cpu.itb.walker.walkRequestOrigin_Requested::total 120716 # Table walker requests started/completed, data/inst 530system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 531system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 109955 # Table walker requests started/completed, data/inst 532system.cpu.itb.walker.walkRequestOrigin_Completed::total 109955 # Table walker requests started/completed, data/inst 533system.cpu.itb.walker.walkRequestOrigin::total 230671 # Table walker requests started/completed, data/inst 534system.cpu.itb.inst_hits 860205714 # ITB inst hits 535system.cpu.itb.inst_misses 120716 # ITB inst misses 536system.cpu.itb.read_hits 0 # DTB read hits 537system.cpu.itb.read_misses 0 # DTB read misses 538system.cpu.itb.write_hits 0 # DTB write hits 539system.cpu.itb.write_misses 0 # DTB write misses 540system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed 541system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 542system.cpu.itb.flush_tlb_mva_asid 40242 # Number of times TLB was flushed by MVA & ASID 543system.cpu.itb.flush_tlb_asid 1033 # Number of times TLB was flushed by ASID 544system.cpu.itb.flush_entries 52133 # Number of entries that have been flushed from TLB 545system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 546system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 547system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 548system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 549system.cpu.itb.read_accesses 0 # DTB read accesses 550system.cpu.itb.write_accesses 0 # DTB write accesses 551system.cpu.itb.inst_accesses 860326430 # ITB inst accesses 552system.cpu.itb.hits 860205714 # DTB hits 553system.cpu.itb.misses 120716 # DTB misses 554system.cpu.itb.accesses 860326430 # DTB accesses 555system.cpu.numPwrStateTransitions 32324 # Number of power state transitions 556system.cpu.pwrStateClkGateDist::samples 16162 # Distribution of time spent in the clock gated state 557system.cpu.pwrStateClkGateDist::mean 3111484469.414615 # Distribution of time spent in the clock gated state 558system.cpu.pwrStateClkGateDist::stdev 60405660268.224297 # Distribution of time spent in the clock gated state 559system.cpu.pwrStateClkGateDist::underflows 6871 42.51% 42.51% # Distribution of time spent in the clock gated state 560system.cpu.pwrStateClkGateDist::1000-5e+10 9256 57.27% 99.78% # Distribution of time spent in the clock gated state 561system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.81% # Distribution of time spent in the clock gated state 562system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.83% # Distribution of time spent in the clock gated state 563system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state 564system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.85% # Distribution of time spent in the clock gated state 565system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state 566system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 567system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 568system.cpu.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 569system.cpu.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 570system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state 571system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 572system.cpu.pwrStateClkGateDist::max_value 1988775138696 # Distribution of time spent in the clock gated state 573system.cpu.pwrStateClkGateDist::total 16162 # Distribution of time spent in the clock gated state 574system.cpu.pwrStateResidencyTicks::ON 1534060022821 # Cumulative time (in ticks) in various power states 575system.cpu.pwrStateResidencyTicks::CLK_GATED 50287811994679 # Cumulative time (in ticks) in various power states 576system.cpu.numCycles 103643744035 # number of cpu cycles simulated 577system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 578system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 579system.cpu.kern.inst.arm 0 # number of arm instructions executed 580system.cpu.kern.inst.quiesce 16162 # number of quiesce instructions executed 581system.cpu.committedInsts 859675526 # Number of instructions committed 582system.cpu.committedOps 1010190283 # Number of ops (including micro ops) committed 583system.cpu.num_int_alu_accesses 928076114 # Number of integer alu accesses 584system.cpu.num_fp_alu_accesses 896946 # Number of float alu accesses 585system.cpu.num_func_calls 51280324 # number of times a function call or return occured 586system.cpu.num_conditional_control_insts 130830869 # number of instructions that are conditional controls 587system.cpu.num_int_insts 928076114 # number of integer instructions 588system.cpu.num_fp_insts 896946 # number of float instructions 589system.cpu.num_int_register_reads 1348653813 # number of times the integer registers were read 590system.cpu.num_int_register_writes 735932841 # number of times the integer registers were written 591system.cpu.num_fp_register_reads 1446833 # number of times the floating registers were read 592system.cpu.num_fp_register_writes 759084 # number of times the floating registers were written 593system.cpu.num_cc_register_reads 224374440 # number of times the CC registers were read 594system.cpu.num_cc_register_writes 223774216 # number of times the CC registers were written 595system.cpu.num_mem_refs 308419372 # number of memory refs 596system.cpu.num_load_insts 161608555 # Number of load instructions 597system.cpu.num_store_insts 146810817 # Number of store instructions 598system.cpu.num_idle_cycles 100575623989.356064 # Number of idle cycles 599system.cpu.num_busy_cycles 3068120045.643941 # Number of busy cycles 600system.cpu.not_idle_fraction 0.029603 # Percentage of non-idle cycles 601system.cpu.idle_fraction 0.970397 # Percentage of idle cycles 602system.cpu.Branches 191908708 # Number of branches fetched 603system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 604system.cpu.op_class::IntAlu 699966855 69.25% 69.25% # Class of executed instruction 605system.cpu.op_class::IntMult 2168337 0.21% 69.47% # Class of executed instruction 606system.cpu.op_class::IntDiv 97451 0.01% 69.48% # Class of executed instruction 607system.cpu.op_class::FloatAdd 8 0.00% 69.48% # Class of executed instruction 608system.cpu.op_class::FloatCmp 13 0.00% 69.48% # Class of executed instruction 609system.cpu.op_class::FloatCvt 21 0.00% 69.48% # Class of executed instruction 610system.cpu.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction 611system.cpu.op_class::FloatMultAcc 0 0.00% 69.48% # Class of executed instruction 612system.cpu.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction 613system.cpu.op_class::FloatMisc 111537 0.01% 69.49% # Class of executed instruction 614system.cpu.op_class::FloatSqrt 0 0.00% 69.49% # Class of executed instruction 615system.cpu.op_class::SimdAdd 0 0.00% 69.49% # Class of executed instruction 616system.cpu.op_class::SimdAddAcc 0 0.00% 69.49% # Class of executed instruction 617system.cpu.op_class::SimdAlu 0 0.00% 69.49% # Class of executed instruction 618system.cpu.op_class::SimdCmp 0 0.00% 69.49% # Class of executed instruction 619system.cpu.op_class::SimdCvt 0 0.00% 69.49% # Class of executed instruction 620system.cpu.op_class::SimdMisc 0 0.00% 69.49% # Class of executed instruction 621system.cpu.op_class::SimdMult 0 0.00% 69.49% # Class of executed instruction 622system.cpu.op_class::SimdMultAcc 0 0.00% 69.49% # Class of executed instruction 623system.cpu.op_class::SimdShift 0 0.00% 69.49% # Class of executed instruction 624system.cpu.op_class::SimdShiftAcc 0 0.00% 69.49% # Class of executed instruction 625system.cpu.op_class::SimdSqrt 0 0.00% 69.49% # Class of executed instruction 626system.cpu.op_class::SimdFloatAdd 0 0.00% 69.49% # Class of executed instruction 627system.cpu.op_class::SimdFloatAlu 0 0.00% 69.49% # Class of executed instruction 628system.cpu.op_class::SimdFloatCmp 0 0.00% 69.49% # Class of executed instruction 629system.cpu.op_class::SimdFloatCvt 0 0.00% 69.49% # Class of executed instruction 630system.cpu.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction 631system.cpu.op_class::SimdFloatMisc 0 0.00% 69.49% # Class of executed instruction 632system.cpu.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction 633system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction 634system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction 635system.cpu.op_class::MemRead 161496118 15.98% 85.46% # Class of executed instruction 636system.cpu.op_class::MemWrite 146137887 14.46% 99.92% # Class of executed instruction 637system.cpu.op_class::FloatMemRead 112437 0.01% 99.93% # Class of executed instruction 638system.cpu.op_class::FloatMemWrite 672930 0.07% 100.00% # Class of executed instruction 639system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 640system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 641system.cpu.op_class::total 1010763595 # Class of executed instruction 642system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 643system.cpu.dcache.tags.replacements 9712819 # number of replacements 644system.cpu.dcache.tags.tagsinuse 511.962733 # Cycle average of tags in use 645system.cpu.dcache.tags.total_refs 298526964 # Total number of references to valid blocks. 646system.cpu.dcache.tags.sampled_refs 9713331 # Sample count of references to valid blocks. 647system.cpu.dcache.tags.avg_refs 30.733737 # Average number of references to valid blocks. 648system.cpu.dcache.tags.warmup_cycle 3801165500 # Cycle when the warmup percentage was hit. 649system.cpu.dcache.tags.occ_blocks::cpu.data 511.962733 # Average occupied blocks per requestor 650system.cpu.dcache.tags.occ_percent::cpu.data 0.999927 # Average percentage of cache occupancy 651system.cpu.dcache.tags.occ_percent::total 0.999927 # Average percentage of cache occupancy 652system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 653system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id 654system.cpu.dcache.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id 655system.cpu.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id 656system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id 657system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 658system.cpu.dcache.tags.tag_accesses 1243130616 # Number of tag accesses 659system.cpu.dcache.tags.data_accesses 1243130616 # Number of data accesses 660system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 661system.cpu.dcache.ReadReq_hits::cpu.data 151166129 # number of ReadReq hits 662system.cpu.dcache.ReadReq_hits::total 151166129 # number of ReadReq hits 663system.cpu.dcache.WriteReq_hits::cpu.data 139372457 # number of WriteReq hits 664system.cpu.dcache.WriteReq_hits::total 139372457 # number of WriteReq hits 665system.cpu.dcache.SoftPFReq_hits::cpu.data 383388 # number of SoftPFReq hits 666system.cpu.dcache.SoftPFReq_hits::total 383388 # number of SoftPFReq hits 667system.cpu.dcache.WriteLineReq_hits::cpu.data 333792 # number of WriteLineReq hits 668system.cpu.dcache.WriteLineReq_hits::total 333792 # number of WriteLineReq hits 669system.cpu.dcache.LoadLockedReq_hits::cpu.data 3475542 # number of LoadLockedReq hits 670system.cpu.dcache.LoadLockedReq_hits::total 3475542 # number of LoadLockedReq hits 671system.cpu.dcache.StoreCondReq_hits::cpu.data 3766859 # number of StoreCondReq hits 672system.cpu.dcache.StoreCondReq_hits::total 3766859 # number of StoreCondReq hits 673system.cpu.dcache.demand_hits::cpu.data 290872378 # number of demand (read+write) hits 674system.cpu.dcache.demand_hits::total 290872378 # number of demand (read+write) hits 675system.cpu.dcache.overall_hits::cpu.data 291255766 # number of overall hits 676system.cpu.dcache.overall_hits::total 291255766 # number of overall hits 677system.cpu.dcache.ReadReq_misses::cpu.data 5061632 # number of ReadReq misses 678system.cpu.dcache.ReadReq_misses::total 5061632 # number of ReadReq misses 679system.cpu.dcache.WriteReq_misses::cpu.data 2072136 # number of WriteReq misses 680system.cpu.dcache.WriteReq_misses::total 2072136 # number of WriteReq misses 681system.cpu.dcache.SoftPFReq_misses::cpu.data 1203806 # number of SoftPFReq misses 682system.cpu.dcache.SoftPFReq_misses::total 1203806 # number of SoftPFReq misses 683system.cpu.dcache.WriteLineReq_misses::cpu.data 1225587 # number of WriteLineReq misses 684system.cpu.dcache.WriteLineReq_misses::total 1225587 # number of WriteLineReq misses 685system.cpu.dcache.LoadLockedReq_misses::cpu.data 292986 # number of LoadLockedReq misses 686system.cpu.dcache.LoadLockedReq_misses::total 292986 # number of LoadLockedReq misses 687system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 688system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 689system.cpu.dcache.demand_misses::cpu.data 8359355 # number of demand (read+write) misses 690system.cpu.dcache.demand_misses::total 8359355 # number of demand (read+write) misses 691system.cpu.dcache.overall_misses::cpu.data 9563161 # number of overall misses 692system.cpu.dcache.overall_misses::total 9563161 # number of overall misses 693system.cpu.dcache.ReadReq_miss_latency::cpu.data 86410296000 # number of ReadReq miss cycles 694system.cpu.dcache.ReadReq_miss_latency::total 86410296000 # number of ReadReq miss cycles 695system.cpu.dcache.WriteReq_miss_latency::cpu.data 64078644000 # number of WriteReq miss cycles 696system.cpu.dcache.WriteReq_miss_latency::total 64078644000 # number of WriteReq miss cycles 697system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 24971401500 # number of WriteLineReq miss cycles 698system.cpu.dcache.WriteLineReq_miss_latency::total 24971401500 # number of WriteLineReq miss cycles 699system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4471115500 # number of LoadLockedReq miss cycles 700system.cpu.dcache.LoadLockedReq_miss_latency::total 4471115500 # number of LoadLockedReq miss cycles 701system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 167500 # number of StoreCondReq miss cycles 702system.cpu.dcache.StoreCondReq_miss_latency::total 167500 # number of StoreCondReq miss cycles 703system.cpu.dcache.demand_miss_latency::cpu.data 175460341500 # number of demand (read+write) miss cycles 704system.cpu.dcache.demand_miss_latency::total 175460341500 # number of demand (read+write) miss cycles 705system.cpu.dcache.overall_miss_latency::cpu.data 175460341500 # number of overall miss cycles 706system.cpu.dcache.overall_miss_latency::total 175460341500 # number of overall miss cycles 707system.cpu.dcache.ReadReq_accesses::cpu.data 156227761 # number of ReadReq accesses(hits+misses) 708system.cpu.dcache.ReadReq_accesses::total 156227761 # number of ReadReq accesses(hits+misses) 709system.cpu.dcache.WriteReq_accesses::cpu.data 141444593 # number of WriteReq accesses(hits+misses) 710system.cpu.dcache.WriteReq_accesses::total 141444593 # number of WriteReq accesses(hits+misses) 711system.cpu.dcache.SoftPFReq_accesses::cpu.data 1587194 # number of SoftPFReq accesses(hits+misses) 712system.cpu.dcache.SoftPFReq_accesses::total 1587194 # number of SoftPFReq accesses(hits+misses) 713system.cpu.dcache.WriteLineReq_accesses::cpu.data 1559379 # number of WriteLineReq accesses(hits+misses) 714system.cpu.dcache.WriteLineReq_accesses::total 1559379 # number of WriteLineReq accesses(hits+misses) 715system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3768528 # number of LoadLockedReq accesses(hits+misses) 716system.cpu.dcache.LoadLockedReq_accesses::total 3768528 # number of LoadLockedReq accesses(hits+misses) 717system.cpu.dcache.StoreCondReq_accesses::cpu.data 3766861 # number of StoreCondReq accesses(hits+misses) 718system.cpu.dcache.StoreCondReq_accesses::total 3766861 # number of StoreCondReq accesses(hits+misses) 719system.cpu.dcache.demand_accesses::cpu.data 299231733 # number of demand (read+write) accesses 720system.cpu.dcache.demand_accesses::total 299231733 # number of demand (read+write) accesses 721system.cpu.dcache.overall_accesses::cpu.data 300818927 # number of overall (read+write) accesses 722system.cpu.dcache.overall_accesses::total 300818927 # number of overall (read+write) accesses 723system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032399 # miss rate for ReadReq accesses 724system.cpu.dcache.ReadReq_miss_rate::total 0.032399 # miss rate for ReadReq accesses 725system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.014650 # miss rate for WriteReq accesses 726system.cpu.dcache.WriteReq_miss_rate::total 0.014650 # miss rate for WriteReq accesses 727system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758449 # miss rate for SoftPFReq accesses 728system.cpu.dcache.SoftPFReq_miss_rate::total 0.758449 # miss rate for SoftPFReq accesses 729system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.785946 # miss rate for WriteLineReq accesses 730system.cpu.dcache.WriteLineReq_miss_rate::total 0.785946 # miss rate for WriteLineReq accesses 731system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.077745 # miss rate for LoadLockedReq accesses 732system.cpu.dcache.LoadLockedReq_miss_rate::total 0.077745 # miss rate for LoadLockedReq accesses 733system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses 734system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses 735system.cpu.dcache.demand_miss_rate::cpu.data 0.027936 # miss rate for demand accesses 736system.cpu.dcache.demand_miss_rate::total 0.027936 # miss rate for demand accesses 737system.cpu.dcache.overall_miss_rate::cpu.data 0.031790 # miss rate for overall accesses 738system.cpu.dcache.overall_miss_rate::total 0.031790 # miss rate for overall accesses 739system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17071.627491 # average ReadReq miss latency 740system.cpu.dcache.ReadReq_avg_miss_latency::total 17071.627491 # average ReadReq miss latency 741system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30923.956729 # average WriteReq miss latency 742system.cpu.dcache.WriteReq_avg_miss_latency::total 30923.956729 # average WriteReq miss latency 743system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 20375.054158 # average WriteLineReq miss latency 744system.cpu.dcache.WriteLineReq_avg_miss_latency::total 20375.054158 # average WriteLineReq miss latency 745system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15260.509035 # average LoadLockedReq miss latency 746system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15260.509035 # average LoadLockedReq miss latency 747system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83750 # average StoreCondReq miss latency 748system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83750 # average StoreCondReq miss latency 749system.cpu.dcache.demand_avg_miss_latency::cpu.data 20989.698547 # average overall miss latency 750system.cpu.dcache.demand_avg_miss_latency::total 20989.698547 # average overall miss latency 751system.cpu.dcache.overall_avg_miss_latency::cpu.data 18347.525625 # average overall miss latency 752system.cpu.dcache.overall_avg_miss_latency::total 18347.525625 # average overall miss latency 753system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 754system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 755system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 756system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 757system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 758system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 759system.cpu.dcache.writebacks::writebacks 7496626 # number of writebacks 760system.cpu.dcache.writebacks::total 7496626 # number of writebacks 761system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21661 # number of ReadReq MSHR hits 762system.cpu.dcache.ReadReq_mshr_hits::total 21661 # number of ReadReq MSHR hits 763system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21294 # number of WriteReq MSHR hits 764system.cpu.dcache.WriteReq_mshr_hits::total 21294 # number of WriteReq MSHR hits 765system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70691 # number of LoadLockedReq MSHR hits 766system.cpu.dcache.LoadLockedReq_mshr_hits::total 70691 # number of LoadLockedReq MSHR hits 767system.cpu.dcache.demand_mshr_hits::cpu.data 42955 # number of demand (read+write) MSHR hits 768system.cpu.dcache.demand_mshr_hits::total 42955 # number of demand (read+write) MSHR hits 769system.cpu.dcache.overall_mshr_hits::cpu.data 42955 # number of overall MSHR hits 770system.cpu.dcache.overall_mshr_hits::total 42955 # number of overall MSHR hits 771system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5039971 # number of ReadReq MSHR misses 772system.cpu.dcache.ReadReq_mshr_misses::total 5039971 # number of ReadReq MSHR misses 773system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2050842 # number of WriteReq MSHR misses 774system.cpu.dcache.WriteReq_mshr_misses::total 2050842 # number of WriteReq MSHR misses 775system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1203452 # number of SoftPFReq MSHR misses 776system.cpu.dcache.SoftPFReq_mshr_misses::total 1203452 # number of SoftPFReq MSHR misses 777system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1225587 # number of WriteLineReq MSHR misses 778system.cpu.dcache.WriteLineReq_mshr_misses::total 1225587 # number of WriteLineReq MSHR misses 779system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 222295 # number of LoadLockedReq MSHR misses 780system.cpu.dcache.LoadLockedReq_mshr_misses::total 222295 # number of LoadLockedReq MSHR misses 781system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 782system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 783system.cpu.dcache.demand_mshr_misses::cpu.data 8316400 # number of demand (read+write) MSHR misses 784system.cpu.dcache.demand_mshr_misses::total 8316400 # number of demand (read+write) MSHR misses 785system.cpu.dcache.overall_mshr_misses::cpu.data 9519852 # number of overall MSHR misses 786system.cpu.dcache.overall_mshr_misses::total 9519852 # number of overall MSHR misses 787system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable 788system.cpu.dcache.ReadReq_mshr_uncacheable::total 33706 # number of ReadReq MSHR uncacheable 789system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable 790system.cpu.dcache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable 791system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses 792system.cpu.dcache.overall_mshr_uncacheable_misses::total 67416 # number of overall MSHR uncacheable misses 793system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 80495651000 # number of ReadReq MSHR miss cycles 794system.cpu.dcache.ReadReq_mshr_miss_latency::total 80495651000 # number of ReadReq MSHR miss cycles 795system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 61277537000 # number of WriteReq MSHR miss cycles 796system.cpu.dcache.WriteReq_mshr_miss_latency::total 61277537000 # number of WriteReq MSHR miss cycles 797system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 21572116000 # number of SoftPFReq MSHR miss cycles 798system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 21572116000 # number of SoftPFReq MSHR miss cycles 799system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 23745814500 # number of WriteLineReq MSHR miss cycles 800system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 23745814500 # number of WriteLineReq MSHR miss cycles 801system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3066936500 # number of LoadLockedReq MSHR miss cycles 802system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3066936500 # number of LoadLockedReq MSHR miss cycles 803system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 165500 # number of StoreCondReq MSHR miss cycles 804system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 165500 # number of StoreCondReq MSHR miss cycles 805system.cpu.dcache.demand_mshr_miss_latency::cpu.data 165519002500 # number of demand (read+write) MSHR miss cycles 806system.cpu.dcache.demand_mshr_miss_latency::total 165519002500 # number of demand (read+write) MSHR miss cycles 807system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187091118500 # number of overall MSHR miss cycles 808system.cpu.dcache.overall_mshr_miss_latency::total 187091118500 # number of overall MSHR miss cycles 809system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6232858500 # number of ReadReq MSHR uncacheable cycles 810system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6232858500 # number of ReadReq MSHR uncacheable cycles 811system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6232858500 # number of overall MSHR uncacheable cycles 812system.cpu.dcache.overall_mshr_uncacheable_latency::total 6232858500 # number of overall MSHR uncacheable cycles 813system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032260 # mshr miss rate for ReadReq accesses 814system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032260 # mshr miss rate for ReadReq accesses 815system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014499 # mshr miss rate for WriteReq accesses 816system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014499 # mshr miss rate for WriteReq accesses 817system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.758226 # mshr miss rate for SoftPFReq accesses 818system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.758226 # mshr miss rate for SoftPFReq accesses 819system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.785946 # mshr miss rate for WriteLineReq accesses 820system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.785946 # mshr miss rate for WriteLineReq accesses 821system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058987 # mshr miss rate for LoadLockedReq accesses 822system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058987 # mshr miss rate for LoadLockedReq accesses 823system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses 824system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses 825system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027793 # mshr miss rate for demand accesses 826system.cpu.dcache.demand_mshr_miss_rate::total 0.027793 # mshr miss rate for demand accesses 827system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031646 # mshr miss rate for overall accesses 828system.cpu.dcache.overall_mshr_miss_rate::total 0.031646 # mshr miss rate for overall accesses 829system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15971.451225 # average ReadReq mshr miss latency 830system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15971.451225 # average ReadReq mshr miss latency 831system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29879.209125 # average WriteReq mshr miss latency 832system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29879.209125 # average WriteReq mshr miss latency 833system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17925.198512 # average SoftPFReq mshr miss latency 834system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17925.198512 # average SoftPFReq mshr miss latency 835system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 19375.054158 # average WriteLineReq mshr miss latency 836system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 19375.054158 # average WriteLineReq mshr miss latency 837system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13796.695832 # average LoadLockedReq mshr miss latency 838system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13796.695832 # average LoadLockedReq mshr miss latency 839system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82750 # average StoreCondReq mshr miss latency 840system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82750 # average StoreCondReq mshr miss latency 841system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19902.722632 # average overall mshr miss latency 842system.cpu.dcache.demand_avg_mshr_miss_latency::total 19902.722632 # average overall mshr miss latency 843system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19652.733940 # average overall mshr miss latency 844system.cpu.dcache.overall_avg_mshr_miss_latency::total 19652.733940 # average overall mshr miss latency 845system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184918.367650 # average ReadReq mshr uncacheable latency 846system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184918.367650 # average ReadReq mshr uncacheable latency 847system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92453.697935 # average overall mshr uncacheable latency 848system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92453.697935 # average overall mshr uncacheable latency 849system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 850system.cpu.icache.tags.replacements 13486266 # number of replacements 851system.cpu.icache.tags.tagsinuse 511.886684 # Cycle average of tags in use 852system.cpu.icache.tags.total_refs 846718931 # Total number of references to valid blocks. 853system.cpu.icache.tags.sampled_refs 13486778 # Sample count of references to valid blocks. 854system.cpu.icache.tags.avg_refs 62.781409 # Average number of references to valid blocks. 855system.cpu.icache.tags.warmup_cycle 32464203500 # Cycle when the warmup percentage was hit. 856system.cpu.icache.tags.occ_blocks::cpu.inst 511.886684 # Average occupied blocks per requestor 857system.cpu.icache.tags.occ_percent::cpu.inst 0.999779 # Average percentage of cache occupancy 858system.cpu.icache.tags.occ_percent::total 0.999779 # Average percentage of cache occupancy 859system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 860system.cpu.icache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id 861system.cpu.icache.tags.age_task_id_blocks_1024::1 249 # Occupied blocks per task id 862system.cpu.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id 863system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id 864system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 865system.cpu.icache.tags.tag_accesses 873692497 # Number of tag accesses 866system.cpu.icache.tags.data_accesses 873692497 # Number of data accesses 867system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 868system.cpu.icache.ReadReq_hits::cpu.inst 846718931 # number of ReadReq hits 869system.cpu.icache.ReadReq_hits::total 846718931 # number of ReadReq hits 870system.cpu.icache.demand_hits::cpu.inst 846718931 # number of demand (read+write) hits 871system.cpu.icache.demand_hits::total 846718931 # number of demand (read+write) hits 872system.cpu.icache.overall_hits::cpu.inst 846718931 # number of overall hits 873system.cpu.icache.overall_hits::total 846718931 # number of overall hits 874system.cpu.icache.ReadReq_misses::cpu.inst 13486783 # number of ReadReq misses 875system.cpu.icache.ReadReq_misses::total 13486783 # number of ReadReq misses 876system.cpu.icache.demand_misses::cpu.inst 13486783 # number of demand (read+write) misses 877system.cpu.icache.demand_misses::total 13486783 # number of demand (read+write) misses 878system.cpu.icache.overall_misses::cpu.inst 13486783 # number of overall misses 879system.cpu.icache.overall_misses::total 13486783 # number of overall misses 880system.cpu.icache.ReadReq_miss_latency::cpu.inst 183511474500 # number of ReadReq miss cycles 881system.cpu.icache.ReadReq_miss_latency::total 183511474500 # number of ReadReq miss cycles 882system.cpu.icache.demand_miss_latency::cpu.inst 183511474500 # number of demand (read+write) miss cycles 883system.cpu.icache.demand_miss_latency::total 183511474500 # number of demand (read+write) miss cycles 884system.cpu.icache.overall_miss_latency::cpu.inst 183511474500 # number of overall miss cycles 885system.cpu.icache.overall_miss_latency::total 183511474500 # number of overall miss cycles 886system.cpu.icache.ReadReq_accesses::cpu.inst 860205714 # number of ReadReq accesses(hits+misses) 887system.cpu.icache.ReadReq_accesses::total 860205714 # number of ReadReq accesses(hits+misses) 888system.cpu.icache.demand_accesses::cpu.inst 860205714 # number of demand (read+write) accesses 889system.cpu.icache.demand_accesses::total 860205714 # number of demand (read+write) accesses 890system.cpu.icache.overall_accesses::cpu.inst 860205714 # number of overall (read+write) accesses 891system.cpu.icache.overall_accesses::total 860205714 # number of overall (read+write) accesses 892system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015679 # miss rate for ReadReq accesses 893system.cpu.icache.ReadReq_miss_rate::total 0.015679 # miss rate for ReadReq accesses 894system.cpu.icache.demand_miss_rate::cpu.inst 0.015679 # miss rate for demand accesses 895system.cpu.icache.demand_miss_rate::total 0.015679 # miss rate for demand accesses 896system.cpu.icache.overall_miss_rate::cpu.inst 0.015679 # miss rate for overall accesses 897system.cpu.icache.overall_miss_rate::total 0.015679 # miss rate for overall accesses 898system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13606.764082 # average ReadReq miss latency 899system.cpu.icache.ReadReq_avg_miss_latency::total 13606.764082 # average ReadReq miss latency 900system.cpu.icache.demand_avg_miss_latency::cpu.inst 13606.764082 # average overall miss latency 901system.cpu.icache.demand_avg_miss_latency::total 13606.764082 # average overall miss latency 902system.cpu.icache.overall_avg_miss_latency::cpu.inst 13606.764082 # average overall miss latency 903system.cpu.icache.overall_avg_miss_latency::total 13606.764082 # average overall miss latency 904system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 905system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 906system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 907system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 908system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 909system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 910system.cpu.icache.writebacks::writebacks 13486266 # number of writebacks 911system.cpu.icache.writebacks::total 13486266 # number of writebacks 912system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13486783 # number of ReadReq MSHR misses 913system.cpu.icache.ReadReq_mshr_misses::total 13486783 # number of ReadReq MSHR misses 914system.cpu.icache.demand_mshr_misses::cpu.inst 13486783 # number of demand (read+write) MSHR misses 915system.cpu.icache.demand_mshr_misses::total 13486783 # number of demand (read+write) MSHR misses 916system.cpu.icache.overall_mshr_misses::cpu.inst 13486783 # number of overall MSHR misses 917system.cpu.icache.overall_mshr_misses::total 13486783 # number of overall MSHR misses 918system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable 919system.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 920system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses 921system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses 922system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170024691500 # number of ReadReq MSHR miss cycles 923system.cpu.icache.ReadReq_mshr_miss_latency::total 170024691500 # number of ReadReq MSHR miss cycles 924system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170024691500 # number of demand (read+write) MSHR miss cycles 925system.cpu.icache.demand_mshr_miss_latency::total 170024691500 # number of demand (read+write) MSHR miss cycles 926system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170024691500 # number of overall MSHR miss cycles 927system.cpu.icache.overall_mshr_miss_latency::total 170024691500 # number of overall MSHR miss cycles 928system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3557271000 # number of ReadReq MSHR uncacheable cycles 929system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3557271000 # number of ReadReq MSHR uncacheable cycles 930system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3557271000 # number of overall MSHR uncacheable cycles 931system.cpu.icache.overall_mshr_uncacheable_latency::total 3557271000 # number of overall MSHR uncacheable cycles 932system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015679 # mshr miss rate for ReadReq accesses 933system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015679 # mshr miss rate for ReadReq accesses 934system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015679 # mshr miss rate for demand accesses 935system.cpu.icache.demand_mshr_miss_rate::total 0.015679 # mshr miss rate for demand accesses 936system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015679 # mshr miss rate for overall accesses 937system.cpu.icache.overall_mshr_miss_rate::total 0.015679 # mshr miss rate for overall accesses 938system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12606.764082 # average ReadReq mshr miss latency 939system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12606.764082 # average ReadReq mshr miss latency 940system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12606.764082 # average overall mshr miss latency 941system.cpu.icache.demand_avg_mshr_miss_latency::total 12606.764082 # average overall mshr miss latency 942system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12606.764082 # average overall mshr miss latency 943system.cpu.icache.overall_avg_mshr_miss_latency::total 12606.764082 # average overall mshr miss latency 944system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 82487.443478 # average ReadReq mshr uncacheable latency 945system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 82487.443478 # average ReadReq mshr uncacheable latency 946system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 82487.443478 # average overall mshr uncacheable latency 947system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 82487.443478 # average overall mshr uncacheable latency 948system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 949system.cpu.l2cache.tags.replacements 1158711 # number of replacements 950system.cpu.l2cache.tags.tagsinuse 65407.211772 # Cycle average of tags in use 951system.cpu.l2cache.tags.total_refs 44429708 # Total number of references to valid blocks. 952system.cpu.l2cache.tags.sampled_refs 1220523 # Sample count of references to valid blocks. 953system.cpu.l2cache.tags.avg_refs 36.402188 # Average number of references to valid blocks. 954system.cpu.l2cache.tags.warmup_cycle 6958052500 # Cycle when the warmup percentage was hit. 955system.cpu.l2cache.tags.occ_blocks::writebacks 10958.963563 # Average occupied blocks per requestor 956system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 463.658135 # Average occupied blocks per requestor 957system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 540.023475 # Average occupied blocks per requestor 958system.cpu.l2cache.tags.occ_blocks::cpu.inst 6661.801500 # Average occupied blocks per requestor 959system.cpu.l2cache.tags.occ_blocks::cpu.data 46782.765099 # Average occupied blocks per requestor 960system.cpu.l2cache.tags.occ_percent::writebacks 0.167221 # Average percentage of cache occupancy 961system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.007075 # Average percentage of cache occupancy 962system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.008240 # Average percentage of cache occupancy 963system.cpu.l2cache.tags.occ_percent::cpu.inst 0.101651 # Average percentage of cache occupancy 964system.cpu.l2cache.tags.occ_percent::cpu.data 0.713848 # Average percentage of cache occupancy 965system.cpu.l2cache.tags.occ_percent::total 0.998035 # Average percentage of cache occupancy 966system.cpu.l2cache.tags.occ_task_id_blocks::1023 301 # Occupied blocks per task id 967system.cpu.l2cache.tags.occ_task_id_blocks::1024 61511 # Occupied blocks per task id 968system.cpu.l2cache.tags.age_task_id_blocks_1023::4 301 # Occupied blocks per task id 969system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 970system.cpu.l2cache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id 971system.cpu.l2cache.tags.age_task_id_blocks_1024::2 815 # Occupied blocks per task id 972system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5756 # Occupied blocks per task id 973system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54668 # Occupied blocks per task id 974system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004593 # Percentage of cache occupancy per task id 975system.cpu.l2cache.tags.occ_task_id_percent::1024 0.938583 # Percentage of cache occupancy per task id 976system.cpu.l2cache.tags.tag_accesses 377726834 # Number of tag accesses 977system.cpu.l2cache.tags.data_accesses 377726834 # Number of data accesses 978system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 979system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 307081 # number of ReadReq hits 980system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 228330 # number of ReadReq hits 981system.cpu.l2cache.ReadReq_hits::total 535411 # number of ReadReq hits 982system.cpu.l2cache.WritebackDirty_hits::writebacks 7496626 # number of WritebackDirty hits 983system.cpu.l2cache.WritebackDirty_hits::total 7496626 # number of WritebackDirty hits 984system.cpu.l2cache.WritebackClean_hits::writebacks 13484674 # number of WritebackClean hits 985system.cpu.l2cache.WritebackClean_hits::total 13484674 # number of WritebackClean hits 986system.cpu.l2cache.UpgradeReq_hits::cpu.data 24887 # number of UpgradeReq hits 987system.cpu.l2cache.UpgradeReq_hits::total 24887 # number of UpgradeReq hits 988system.cpu.l2cache.ReadExReq_hits::cpu.data 1607168 # number of ReadExReq hits 989system.cpu.l2cache.ReadExReq_hits::total 1607168 # number of ReadExReq hits 990system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 13410909 # number of ReadCleanReq hits 991system.cpu.l2cache.ReadCleanReq_hits::total 13410909 # number of ReadCleanReq hits 992system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6209836 # number of ReadSharedReq hits 993system.cpu.l2cache.ReadSharedReq_hits::total 6209836 # number of ReadSharedReq hits 994system.cpu.l2cache.InvalidateReq_hits::cpu.data 727975 # number of InvalidateReq hits 995system.cpu.l2cache.InvalidateReq_hits::total 727975 # number of InvalidateReq hits 996system.cpu.l2cache.demand_hits::cpu.dtb.walker 307081 # number of demand (read+write) hits 997system.cpu.l2cache.demand_hits::cpu.itb.walker 228330 # number of demand (read+write) hits 998system.cpu.l2cache.demand_hits::cpu.inst 13410909 # number of demand (read+write) hits 999system.cpu.l2cache.demand_hits::cpu.data 7817004 # number of demand (read+write) hits 1000system.cpu.l2cache.demand_hits::total 21763324 # number of demand (read+write) hits 1001system.cpu.l2cache.overall_hits::cpu.dtb.walker 307081 # number of overall hits 1002system.cpu.l2cache.overall_hits::cpu.itb.walker 228330 # number of overall hits 1003system.cpu.l2cache.overall_hits::cpu.inst 13410909 # number of overall hits 1004system.cpu.l2cache.overall_hits::cpu.data 7817004 # number of overall hits 1005system.cpu.l2cache.overall_hits::total 21763324 # number of overall hits 1006system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3365 # number of ReadReq misses 1007system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3394 # number of ReadReq misses 1008system.cpu.l2cache.ReadReq_misses::total 6759 # number of ReadReq misses 1009system.cpu.l2cache.UpgradeReq_misses::cpu.data 3908 # number of UpgradeReq misses 1010system.cpu.l2cache.UpgradeReq_misses::total 3908 # number of UpgradeReq misses 1011system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses 1012system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses 1013system.cpu.l2cache.ReadExReq_misses::cpu.data 414879 # number of ReadExReq misses 1014system.cpu.l2cache.ReadExReq_misses::total 414879 # number of ReadExReq misses 1015system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 75874 # number of ReadCleanReq misses 1016system.cpu.l2cache.ReadCleanReq_misses::total 75874 # number of ReadCleanReq misses 1017system.cpu.l2cache.ReadSharedReq_misses::cpu.data 255882 # number of ReadSharedReq misses 1018system.cpu.l2cache.ReadSharedReq_misses::total 255882 # number of ReadSharedReq misses 1019system.cpu.l2cache.InvalidateReq_misses::cpu.data 497612 # number of InvalidateReq misses 1020system.cpu.l2cache.InvalidateReq_misses::total 497612 # number of InvalidateReq misses 1021system.cpu.l2cache.demand_misses::cpu.dtb.walker 3365 # number of demand (read+write) misses 1022system.cpu.l2cache.demand_misses::cpu.itb.walker 3394 # number of demand (read+write) misses 1023system.cpu.l2cache.demand_misses::cpu.inst 75874 # number of demand (read+write) misses 1024system.cpu.l2cache.demand_misses::cpu.data 670761 # number of demand (read+write) misses 1025system.cpu.l2cache.demand_misses::total 753394 # number of demand (read+write) misses 1026system.cpu.l2cache.overall_misses::cpu.dtb.walker 3365 # number of overall misses 1027system.cpu.l2cache.overall_misses::cpu.itb.walker 3394 # number of overall misses 1028system.cpu.l2cache.overall_misses::cpu.inst 75874 # number of overall misses 1029system.cpu.l2cache.overall_misses::cpu.data 670761 # number of overall misses 1030system.cpu.l2cache.overall_misses::total 753394 # number of overall misses 1031system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 447362000 # number of ReadReq miss cycles 1032system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 421528500 # number of ReadReq miss cycles 1033system.cpu.l2cache.ReadReq_miss_latency::total 868890500 # number of ReadReq miss cycles 1034system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 69021500 # number of UpgradeReq miss cycles 1035system.cpu.l2cache.UpgradeReq_miss_latency::total 69021500 # number of UpgradeReq miss cycles 1036system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 162500 # number of SCUpgradeReq miss cycles 1037system.cpu.l2cache.SCUpgradeReq_miss_latency::total 162500 # number of SCUpgradeReq miss cycles 1038system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40901099500 # number of ReadExReq miss cycles 1039system.cpu.l2cache.ReadExReq_miss_latency::total 40901099500 # number of ReadExReq miss cycles 1040system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 8709565500 # number of ReadCleanReq miss cycles 1041system.cpu.l2cache.ReadCleanReq_miss_latency::total 8709565500 # number of ReadCleanReq miss cycles 1042system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30155420000 # number of ReadSharedReq miss cycles 1043system.cpu.l2cache.ReadSharedReq_miss_latency::total 30155420000 # number of ReadSharedReq miss cycles 1044system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 447362000 # number of demand (read+write) miss cycles 1045system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 421528500 # number of demand (read+write) miss cycles 1046system.cpu.l2cache.demand_miss_latency::cpu.inst 8709565500 # number of demand (read+write) miss cycles 1047system.cpu.l2cache.demand_miss_latency::cpu.data 71056519500 # number of demand (read+write) miss cycles 1048system.cpu.l2cache.demand_miss_latency::total 80634975500 # number of demand (read+write) miss cycles 1049system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 447362000 # number of overall miss cycles 1050system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 421528500 # number of overall miss cycles 1051system.cpu.l2cache.overall_miss_latency::cpu.inst 8709565500 # number of overall miss cycles 1052system.cpu.l2cache.overall_miss_latency::cpu.data 71056519500 # number of overall miss cycles 1053system.cpu.l2cache.overall_miss_latency::total 80634975500 # number of overall miss cycles 1054system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 310446 # number of ReadReq accesses(hits+misses) 1055system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 231724 # number of ReadReq accesses(hits+misses) 1056system.cpu.l2cache.ReadReq_accesses::total 542170 # number of ReadReq accesses(hits+misses) 1057system.cpu.l2cache.WritebackDirty_accesses::writebacks 7496626 # number of WritebackDirty accesses(hits+misses) 1058system.cpu.l2cache.WritebackDirty_accesses::total 7496626 # number of WritebackDirty accesses(hits+misses) 1059system.cpu.l2cache.WritebackClean_accesses::writebacks 13484674 # number of WritebackClean accesses(hits+misses) 1060system.cpu.l2cache.WritebackClean_accesses::total 13484674 # number of WritebackClean accesses(hits+misses) 1061system.cpu.l2cache.UpgradeReq_accesses::cpu.data 28795 # number of UpgradeReq accesses(hits+misses) 1062system.cpu.l2cache.UpgradeReq_accesses::total 28795 # number of UpgradeReq accesses(hits+misses) 1063system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 1064system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 1065system.cpu.l2cache.ReadExReq_accesses::cpu.data 2022047 # number of ReadExReq accesses(hits+misses) 1066system.cpu.l2cache.ReadExReq_accesses::total 2022047 # number of ReadExReq accesses(hits+misses) 1067system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 13486783 # number of ReadCleanReq accesses(hits+misses) 1068system.cpu.l2cache.ReadCleanReq_accesses::total 13486783 # number of ReadCleanReq accesses(hits+misses) 1069system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6465718 # number of ReadSharedReq accesses(hits+misses) 1070system.cpu.l2cache.ReadSharedReq_accesses::total 6465718 # number of ReadSharedReq accesses(hits+misses) 1071system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1225587 # number of InvalidateReq accesses(hits+misses) 1072system.cpu.l2cache.InvalidateReq_accesses::total 1225587 # number of InvalidateReq accesses(hits+misses) 1073system.cpu.l2cache.demand_accesses::cpu.dtb.walker 310446 # number of demand (read+write) accesses 1074system.cpu.l2cache.demand_accesses::cpu.itb.walker 231724 # number of demand (read+write) accesses 1075system.cpu.l2cache.demand_accesses::cpu.inst 13486783 # number of demand (read+write) accesses 1076system.cpu.l2cache.demand_accesses::cpu.data 8487765 # number of demand (read+write) accesses 1077system.cpu.l2cache.demand_accesses::total 22516718 # number of demand (read+write) accesses 1078system.cpu.l2cache.overall_accesses::cpu.dtb.walker 310446 # number of overall (read+write) accesses 1079system.cpu.l2cache.overall_accesses::cpu.itb.walker 231724 # number of overall (read+write) accesses 1080system.cpu.l2cache.overall_accesses::cpu.inst 13486783 # number of overall (read+write) accesses 1081system.cpu.l2cache.overall_accesses::cpu.data 8487765 # number of overall (read+write) accesses 1082system.cpu.l2cache.overall_accesses::total 22516718 # number of overall (read+write) accesses 1083system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.010839 # miss rate for ReadReq accesses 1084system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.014647 # miss rate for ReadReq accesses 1085system.cpu.l2cache.ReadReq_miss_rate::total 0.012467 # miss rate for ReadReq accesses 1086system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.135718 # miss rate for UpgradeReq accesses 1087system.cpu.l2cache.UpgradeReq_miss_rate::total 0.135718 # miss rate for UpgradeReq accesses 1088system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 1089system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1090system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.205178 # miss rate for ReadExReq accesses 1091system.cpu.l2cache.ReadExReq_miss_rate::total 0.205178 # miss rate for ReadExReq accesses 1092system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005626 # miss rate for ReadCleanReq accesses 1093system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005626 # miss rate for ReadCleanReq accesses 1094system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.039575 # miss rate for ReadSharedReq accesses 1095system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.039575 # miss rate for ReadSharedReq accesses 1096system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.406019 # miss rate for InvalidateReq accesses 1097system.cpu.l2cache.InvalidateReq_miss_rate::total 0.406019 # miss rate for InvalidateReq accesses 1098system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.010839 # miss rate for demand accesses 1099system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.014647 # miss rate for demand accesses 1100system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005626 # miss rate for demand accesses 1101system.cpu.l2cache.demand_miss_rate::cpu.data 0.079027 # miss rate for demand accesses 1102system.cpu.l2cache.demand_miss_rate::total 0.033459 # miss rate for demand accesses 1103system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.010839 # miss rate for overall accesses 1104system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.014647 # miss rate for overall accesses 1105system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005626 # miss rate for overall accesses 1106system.cpu.l2cache.overall_miss_rate::cpu.data 0.079027 # miss rate for overall accesses 1107system.cpu.l2cache.overall_miss_rate::total 0.033459 # miss rate for overall accesses 1108system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 132945.616642 # average ReadReq miss latency 1109system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 124198.143783 # average ReadReq miss latency 1110system.cpu.l2cache.ReadReq_avg_miss_latency::total 128553.114366 # average ReadReq miss latency 1111system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 17661.591607 # average UpgradeReq miss latency 1112system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 17661.591607 # average UpgradeReq miss latency 1113system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 81250 # average SCUpgradeReq miss latency 1114system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 81250 # average SCUpgradeReq miss latency 1115system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98585.610503 # average ReadExReq miss latency 1116system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98585.610503 # average ReadExReq miss latency 1117system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 114789.855550 # average ReadCleanReq miss latency 1118system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 114789.855550 # average ReadCleanReq miss latency 1119system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 117848.930366 # average ReadSharedReq miss latency 1120system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 117848.930366 # average ReadSharedReq miss latency 1121system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 132945.616642 # average overall miss latency 1122system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 124198.143783 # average overall miss latency 1123system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 114789.855550 # average overall miss latency 1124system.cpu.l2cache.demand_avg_miss_latency::cpu.data 105934.184456 # average overall miss latency 1125system.cpu.l2cache.demand_avg_miss_latency::total 107028.958951 # average overall miss latency 1126system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 132945.616642 # average overall miss latency 1127system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 124198.143783 # average overall miss latency 1128system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 114789.855550 # average overall miss latency 1129system.cpu.l2cache.overall_avg_miss_latency::cpu.data 105934.184456 # average overall miss latency 1130system.cpu.l2cache.overall_avg_miss_latency::total 107028.958951 # average overall miss latency 1131system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1132system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1133system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1134system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1135system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1136system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1137system.cpu.l2cache.writebacks::writebacks 985808 # number of writebacks 1138system.cpu.l2cache.writebacks::total 985808 # number of writebacks 1139system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3365 # number of ReadReq MSHR misses 1140system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3394 # number of ReadReq MSHR misses 1141system.cpu.l2cache.ReadReq_mshr_misses::total 6759 # number of ReadReq MSHR misses 1142system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3908 # number of UpgradeReq MSHR misses 1143system.cpu.l2cache.UpgradeReq_mshr_misses::total 3908 # number of UpgradeReq MSHR misses 1144system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses 1145system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses 1146system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 414879 # number of ReadExReq MSHR misses 1147system.cpu.l2cache.ReadExReq_mshr_misses::total 414879 # number of ReadExReq MSHR misses 1148system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 75874 # number of ReadCleanReq MSHR misses 1149system.cpu.l2cache.ReadCleanReq_mshr_misses::total 75874 # number of ReadCleanReq MSHR misses 1150system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 255882 # number of ReadSharedReq MSHR misses 1151system.cpu.l2cache.ReadSharedReq_mshr_misses::total 255882 # number of ReadSharedReq MSHR misses 1152system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 497612 # number of InvalidateReq MSHR misses 1153system.cpu.l2cache.InvalidateReq_mshr_misses::total 497612 # number of InvalidateReq MSHR misses 1154system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3365 # number of demand (read+write) MSHR misses 1155system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3394 # number of demand (read+write) MSHR misses 1156system.cpu.l2cache.demand_mshr_misses::cpu.inst 75874 # number of demand (read+write) MSHR misses 1157system.cpu.l2cache.demand_mshr_misses::cpu.data 670761 # number of demand (read+write) MSHR misses 1158system.cpu.l2cache.demand_mshr_misses::total 753394 # number of demand (read+write) MSHR misses 1159system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3365 # number of overall MSHR misses 1160system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3394 # number of overall MSHR misses 1161system.cpu.l2cache.overall_mshr_misses::cpu.inst 75874 # number of overall MSHR misses 1162system.cpu.l2cache.overall_mshr_misses::cpu.data 670761 # number of overall MSHR misses 1163system.cpu.l2cache.overall_mshr_misses::total 753394 # number of overall MSHR misses 1164system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable 1165system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable 1166system.cpu.l2cache.ReadReq_mshr_uncacheable::total 76831 # number of ReadReq MSHR uncacheable 1167system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable 1168system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable 1169system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses 1170system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses 1171system.cpu.l2cache.overall_mshr_uncacheable_misses::total 110541 # number of overall MSHR uncacheable misses 1172system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 413712000 # number of ReadReq MSHR miss cycles 1173system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 387588500 # number of ReadReq MSHR miss cycles 1174system.cpu.l2cache.ReadReq_mshr_miss_latency::total 801300500 # number of ReadReq MSHR miss cycles 1175system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 74391500 # number of UpgradeReq MSHR miss cycles 1176system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 74391500 # number of UpgradeReq MSHR miss cycles 1177system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 142500 # number of SCUpgradeReq MSHR miss cycles 1178system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 142500 # number of SCUpgradeReq MSHR miss cycles 1179system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 36752309500 # number of ReadExReq MSHR miss cycles 1180system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 36752309500 # number of ReadExReq MSHR miss cycles 1181system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 7950825500 # number of ReadCleanReq MSHR miss cycles 1182system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 7950825500 # number of ReadCleanReq MSHR miss cycles 1183system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 27596583533 # number of ReadSharedReq MSHR miss cycles 1184system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 27596583533 # number of ReadSharedReq MSHR miss cycles 1185system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 9287554000 # number of InvalidateReq MSHR miss cycles 1186system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 9287554000 # number of InvalidateReq MSHR miss cycles 1187system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 413712000 # number of demand (read+write) MSHR miss cycles 1188system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 387588500 # number of demand (read+write) MSHR miss cycles 1189system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7950825500 # number of demand (read+write) MSHR miss cycles 1190system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 64348893033 # number of demand (read+write) MSHR miss cycles 1191system.cpu.l2cache.demand_mshr_miss_latency::total 73101019033 # number of demand (read+write) MSHR miss cycles 1192system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 413712000 # number of overall MSHR miss cycles 1193system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 387588500 # number of overall MSHR miss cycles 1194system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7950825500 # number of overall MSHR miss cycles 1195system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 64348893033 # number of overall MSHR miss cycles 1196system.cpu.l2cache.overall_mshr_miss_latency::total 73101019033 # number of overall MSHR miss cycles 1197system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 3018208500 # number of ReadReq MSHR uncacheable cycles 1198system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5810725500 # number of ReadReq MSHR uncacheable cycles 1199system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8828934000 # number of ReadReq MSHR uncacheable cycles 1200system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3018208500 # number of overall MSHR uncacheable cycles 1201system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5810725500 # number of overall MSHR uncacheable cycles 1202system.cpu.l2cache.overall_mshr_uncacheable_latency::total 8828934000 # number of overall MSHR uncacheable cycles 1203system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.010839 # mshr miss rate for ReadReq accesses 1204system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.014647 # mshr miss rate for ReadReq accesses 1205system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.012467 # mshr miss rate for ReadReq accesses 1206system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.135718 # mshr miss rate for UpgradeReq accesses 1207system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.135718 # mshr miss rate for UpgradeReq accesses 1208system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1209system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1210system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.205178 # mshr miss rate for ReadExReq accesses 1211system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.205178 # mshr miss rate for ReadExReq accesses 1212system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005626 # mshr miss rate for ReadCleanReq accesses 1213system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005626 # mshr miss rate for ReadCleanReq accesses 1214system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.039575 # mshr miss rate for ReadSharedReq accesses 1215system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.039575 # mshr miss rate for ReadSharedReq accesses 1216system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.406019 # mshr miss rate for InvalidateReq accesses 1217system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.406019 # mshr miss rate for InvalidateReq accesses 1218system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.010839 # mshr miss rate for demand accesses 1219system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.014647 # mshr miss rate for demand accesses 1220system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005626 # mshr miss rate for demand accesses 1221system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.079027 # mshr miss rate for demand accesses 1222system.cpu.l2cache.demand_mshr_miss_rate::total 0.033459 # mshr miss rate for demand accesses 1223system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.010839 # mshr miss rate for overall accesses 1224system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.014647 # mshr miss rate for overall accesses 1225system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005626 # mshr miss rate for overall accesses 1226system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.079027 # mshr miss rate for overall accesses 1227system.cpu.l2cache.overall_mshr_miss_rate::total 0.033459 # mshr miss rate for overall accesses 1228system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 122945.616642 # average ReadReq mshr miss latency 1229system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 114198.143783 # average ReadReq mshr miss latency 1230system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 118553.114366 # average ReadReq mshr miss latency 1231system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19035.696008 # average UpgradeReq mshr miss latency 1232system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19035.696008 # average UpgradeReq mshr miss latency 1233system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71250 # average SCUpgradeReq mshr miss latency 1234system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71250 # average SCUpgradeReq mshr miss latency 1235system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88585.610503 # average ReadExReq mshr miss latency 1236system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88585.610503 # average ReadExReq mshr miss latency 1237system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 104789.855550 # average ReadCleanReq mshr miss latency 1238system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 104789.855550 # average ReadCleanReq mshr miss latency 1239system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 107848.866012 # average ReadSharedReq mshr miss latency 1240system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 107848.866012 # average ReadSharedReq mshr miss latency 1241system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 18664.248451 # average InvalidateReq mshr miss latency 1242system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 18664.248451 # average InvalidateReq mshr miss latency 1243system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 122945.616642 # average overall mshr miss latency 1244system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 114198.143783 # average overall mshr miss latency 1245system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 104789.855550 # average overall mshr miss latency 1246system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 95934.159906 # average overall mshr miss latency 1247system.cpu.l2cache.demand_avg_mshr_miss_latency::total 97028.937094 # average overall mshr miss latency 1248system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 122945.616642 # average overall mshr miss latency 1249system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 114198.143783 # average overall mshr miss latency 1250system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 104789.855550 # average overall mshr miss latency 1251system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 95934.159906 # average overall mshr miss latency 1252system.cpu.l2cache.overall_avg_mshr_miss_latency::total 97028.937094 # average overall mshr miss latency 1253system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69987.443478 # average ReadReq mshr uncacheable latency 1254system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172394.395657 # average ReadReq mshr uncacheable latency 1255system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 114913.693691 # average ReadReq mshr uncacheable latency 1256system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69987.443478 # average overall mshr uncacheable latency 1257system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86192.083482 # average overall mshr uncacheable latency 1258system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 79870.220099 # average overall mshr uncacheable latency 1259system.cpu.toL2Bus.snoop_filter.tot_requests 46927036 # Total number of requests made to the snoop filter. 1260system.cpu.toL2Bus.snoop_filter.hit_single_requests 23726903 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1261system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1749 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1262system.cpu.toL2Bus.snoop_filter.tot_snoops 1976 # Total number of snoops made to the snoop filter. 1263system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1976 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1264system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1265system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1266system.cpu.toL2Bus.trans_dist::ReadReq 1011319 # Transaction distribution 1267system.cpu.toL2Bus.trans_dist::ReadResp 20964705 # Transaction distribution 1268system.cpu.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution 1269system.cpu.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution 1270system.cpu.toL2Bus.trans_dist::WritebackDirty 8482434 # Transaction distribution 1271system.cpu.toL2Bus.trans_dist::WritebackClean 13486266 # Transaction distribution 1272system.cpu.toL2Bus.trans_dist::CleanEvict 2389096 # Transaction distribution 1273system.cpu.toL2Bus.trans_dist::UpgradeReq 28798 # Transaction distribution 1274system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1275system.cpu.toL2Bus.trans_dist::UpgradeResp 28800 # Transaction distribution 1276system.cpu.toL2Bus.trans_dist::ReadExReq 2022047 # Transaction distribution 1277system.cpu.toL2Bus.trans_dist::ReadExResp 2022047 # Transaction distribution 1278system.cpu.toL2Bus.trans_dist::ReadCleanReq 13486783 # Transaction distribution 1279system.cpu.toL2Bus.trans_dist::ReadSharedReq 6468652 # Transaction distribution 1280system.cpu.toL2Bus.trans_dist::InvalidateReq 1256381 # Transaction distribution 1281system.cpu.toL2Bus.trans_dist::InvalidateResp 1225599 # Transaction distribution 1282system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40546082 # Packet count per connected master and slave (bytes) 1283system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29332849 # Packet count per connected master and slave (bytes) 1284system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 592477 # Packet count per connected master and slave (bytes) 1285system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 884181 # Packet count per connected master and slave (bytes) 1286system.cpu.toL2Bus.pkt_count::total 71355589 # Packet count per connected master and slave (bytes) 1287system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1726447636 # Cumulative packet size per connected master and slave (bytes) 1288system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1023248134 # Cumulative packet size per connected master and slave (bytes) 1289system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 1853792 # Cumulative packet size per connected master and slave (bytes) 1290system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2483568 # Cumulative packet size per connected master and slave (bytes) 1291system.cpu.toL2Bus.pkt_size::total 2754033130 # Cumulative packet size per connected master and slave (bytes) 1292system.cpu.toL2Bus.snoops 1585660 # Total snoops (count) 1293system.cpu.toL2Bus.snoopTraffic 66286896 # Total snoop traffic (bytes) 1294system.cpu.toL2Bus.snoop_fanout::samples 25466403 # Request fanout histogram 1295system.cpu.toL2Bus.snoop_fanout::mean 0.019742 # Request fanout histogram 1296system.cpu.toL2Bus.snoop_fanout::stdev 0.139111 # Request fanout histogram 1297system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1298system.cpu.toL2Bus.snoop_fanout::0 24963657 98.03% 98.03% # Request fanout histogram 1299system.cpu.toL2Bus.snoop_fanout::1 502746 1.97% 100.00% # Request fanout histogram 1300system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1301system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1302system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1303system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1304system.cpu.toL2Bus.snoop_fanout::total 25466403 # Request fanout histogram 1305system.cpu.toL2Bus.reqLayer0.occupancy 44736270000 # Layer occupancy (ticks) 1306system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1307system.cpu.toL2Bus.snoopLayer0.occupancy 1643382 # Layer occupancy (ticks) 1308system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1309system.cpu.toL2Bus.respLayer0.occupancy 20273299500 # Layer occupancy (ticks) 1310system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1311system.cpu.toL2Bus.respLayer1.occupancy 13409418464 # Layer occupancy (ticks) 1312system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1313system.cpu.toL2Bus.respLayer2.occupancy 360753000 # Layer occupancy (ticks) 1314system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1315system.cpu.toL2Bus.respLayer3.occupancy 573735000 # Layer occupancy (ticks) 1316system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1317system.iobus.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1318system.iobus.trans_dist::ReadReq 40342 # Transaction distribution 1319system.iobus.trans_dist::ReadResp 40342 # Transaction distribution 1320system.iobus.trans_dist::WriteReq 136571 # Transaction distribution 1321system.iobus.trans_dist::WriteResp 136571 # Transaction distribution 1322system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 1323system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1324system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1325system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1326system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1327system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1328system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1329system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1330system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1331system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1332system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1333system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 1334system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1335system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) 1336system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231042 # Packet count per connected master and slave (bytes) 1337system.iobus.pkt_count_system.realview.ide.dma::total 231042 # Packet count per connected master and slave (bytes) 1338system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1339system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 1340system.iobus.pkt_count::total 353826 # Packet count per connected master and slave (bytes) 1341system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 1342system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1343system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 1344system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1345system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1346system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1347system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1348system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1349system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1350system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1351system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1352system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 1353system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1354system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) 1355system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334600 # Cumulative packet size per connected master and slave (bytes) 1356system.iobus.pkt_size_system.realview.ide.dma::total 7334600 # Cumulative packet size per connected master and slave (bytes) 1357system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1358system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 1359system.iobus.pkt_size::total 7492520 # Cumulative packet size per connected master and slave (bytes) 1360system.iobus.reqLayer0.occupancy 42151500 # Layer occupancy (ticks) 1361system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1362system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) 1363system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1364system.iobus.reqLayer2.occupancy 321500 # Layer occupancy (ticks) 1365system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1366system.iobus.reqLayer3.occupancy 11000 # Layer occupancy (ticks) 1367system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1368system.iobus.reqLayer4.occupancy 11000 # Layer occupancy (ticks) 1369system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1370system.iobus.reqLayer10.occupancy 11000 # Layer occupancy (ticks) 1371system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1372system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) 1373system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1374system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) 1375system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1376system.iobus.reqLayer15.occupancy 11000 # Layer occupancy (ticks) 1377system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1378system.iobus.reqLayer16.occupancy 17000 # Layer occupancy (ticks) 1379system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1380system.iobus.reqLayer17.occupancy 11000 # Layer occupancy (ticks) 1381system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1382system.iobus.reqLayer23.occupancy 25717000 # Layer occupancy (ticks) 1383system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1384system.iobus.reqLayer24.occupancy 38602500 # Layer occupancy (ticks) 1385system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1386system.iobus.reqLayer25.occupancy 569022926 # Layer occupancy (ticks) 1387system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1388system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 1389system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1390system.iobus.respLayer3.occupancy 147802000 # Layer occupancy (ticks) 1391system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1392system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 1393system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 1394system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1395system.iocache.tags.replacements 115502 # number of replacements 1396system.iocache.tags.tagsinuse 10.457099 # Cycle average of tags in use 1397system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 1398system.iocache.tags.sampled_refs 115518 # Sample count of references to valid blocks. 1399system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1400system.iocache.tags.warmup_cycle 13154766854000 # Cycle when the warmup percentage was hit. 1401system.iocache.tags.occ_blocks::realview.ethernet 3.510741 # Average occupied blocks per requestor 1402system.iocache.tags.occ_blocks::realview.ide 6.946357 # Average occupied blocks per requestor 1403system.iocache.tags.occ_percent::realview.ethernet 0.219421 # Average percentage of cache occupancy 1404system.iocache.tags.occ_percent::realview.ide 0.434147 # Average percentage of cache occupancy 1405system.iocache.tags.occ_percent::total 0.653569 # Average percentage of cache occupancy 1406system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1407system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1408system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1409system.iocache.tags.tag_accesses 1040046 # Number of tag accesses 1410system.iocache.tags.data_accesses 1040046 # Number of data accesses 1411system.iocache.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1412system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1413system.iocache.ReadReq_misses::realview.ide 8857 # number of ReadReq misses 1414system.iocache.ReadReq_misses::total 8894 # number of ReadReq misses 1415system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1416system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1417system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1418system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1419system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 1420system.iocache.demand_misses::realview.ide 115521 # number of demand (read+write) misses 1421system.iocache.demand_misses::total 115561 # number of demand (read+write) misses 1422system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 1423system.iocache.overall_misses::realview.ide 115521 # number of overall misses 1424system.iocache.overall_misses::total 115561 # number of overall misses 1425system.iocache.ReadReq_miss_latency::realview.ethernet 5086500 # number of ReadReq miss cycles 1426system.iocache.ReadReq_miss_latency::realview.ide 2023754150 # number of ReadReq miss cycles 1427system.iocache.ReadReq_miss_latency::total 2028840650 # number of ReadReq miss cycles 1428system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 1429system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 1430system.iocache.WriteLineReq_miss_latency::realview.ide 13483489276 # number of WriteLineReq miss cycles 1431system.iocache.WriteLineReq_miss_latency::total 13483489276 # number of WriteLineReq miss cycles 1432system.iocache.demand_miss_latency::realview.ethernet 5437500 # number of demand (read+write) miss cycles 1433system.iocache.demand_miss_latency::realview.ide 15507243426 # number of demand (read+write) miss cycles 1434system.iocache.demand_miss_latency::total 15512680926 # number of demand (read+write) miss cycles 1435system.iocache.overall_miss_latency::realview.ethernet 5437500 # number of overall miss cycles 1436system.iocache.overall_miss_latency::realview.ide 15507243426 # number of overall miss cycles 1437system.iocache.overall_miss_latency::total 15512680926 # number of overall miss cycles 1438system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1439system.iocache.ReadReq_accesses::realview.ide 8857 # number of ReadReq accesses(hits+misses) 1440system.iocache.ReadReq_accesses::total 8894 # number of ReadReq accesses(hits+misses) 1441system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1442system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1443system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 1444system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 1445system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 1446system.iocache.demand_accesses::realview.ide 115521 # number of demand (read+write) accesses 1447system.iocache.demand_accesses::total 115561 # number of demand (read+write) accesses 1448system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 1449system.iocache.overall_accesses::realview.ide 115521 # number of overall (read+write) accesses 1450system.iocache.overall_accesses::total 115561 # number of overall (read+write) accesses 1451system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1452system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1453system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1454system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1455system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1456system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1457system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1458system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1459system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1460system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1461system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1462system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1463system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1464system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137472.972973 # average ReadReq miss latency 1465system.iocache.ReadReq_avg_miss_latency::realview.ide 228492.057130 # average ReadReq miss latency 1466system.iocache.ReadReq_avg_miss_latency::total 228113.407915 # average ReadReq miss latency 1467system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 1468system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 1469system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126410.872234 # average WriteLineReq miss latency 1470system.iocache.WriteLineReq_avg_miss_latency::total 126410.872234 # average WriteLineReq miss latency 1471system.iocache.demand_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency 1472system.iocache.demand_avg_miss_latency::realview.ide 134237.441037 # average overall miss latency 1473system.iocache.demand_avg_miss_latency::total 134238.029491 # average overall miss latency 1474system.iocache.overall_avg_miss_latency::realview.ethernet 135937.500000 # average overall miss latency 1475system.iocache.overall_avg_miss_latency::realview.ide 134237.441037 # average overall miss latency 1476system.iocache.overall_avg_miss_latency::total 134238.029491 # average overall miss latency 1477system.iocache.blocked_cycles::no_mshrs 52159 # number of cycles access was blocked 1478system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1479system.iocache.blocked::no_mshrs 3349 # number of cycles access was blocked 1480system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1481system.iocache.avg_blocked_cycles::no_mshrs 15.574500 # average number of cycles each access was blocked 1482system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1483system.iocache.writebacks::writebacks 106630 # number of writebacks 1484system.iocache.writebacks::total 106630 # number of writebacks 1485system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 1486system.iocache.ReadReq_mshr_misses::realview.ide 8857 # number of ReadReq MSHR misses 1487system.iocache.ReadReq_mshr_misses::total 8894 # number of ReadReq MSHR misses 1488system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1489system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1490system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 1491system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 1492system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 1493system.iocache.demand_mshr_misses::realview.ide 115521 # number of demand (read+write) MSHR misses 1494system.iocache.demand_mshr_misses::total 115561 # number of demand (read+write) MSHR misses 1495system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 1496system.iocache.overall_mshr_misses::realview.ide 115521 # number of overall MSHR misses 1497system.iocache.overall_mshr_misses::total 115561 # number of overall MSHR misses 1498system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236500 # number of ReadReq MSHR miss cycles 1499system.iocache.ReadReq_mshr_miss_latency::realview.ide 1580904150 # number of ReadReq MSHR miss cycles 1500system.iocache.ReadReq_mshr_miss_latency::total 1584140650 # number of ReadReq MSHR miss cycles 1501system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 1502system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 1503system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8144739087 # number of WriteLineReq MSHR miss cycles 1504system.iocache.WriteLineReq_mshr_miss_latency::total 8144739087 # number of WriteLineReq MSHR miss cycles 1505system.iocache.demand_mshr_miss_latency::realview.ethernet 3437500 # number of demand (read+write) MSHR miss cycles 1506system.iocache.demand_mshr_miss_latency::realview.ide 9725643237 # number of demand (read+write) MSHR miss cycles 1507system.iocache.demand_mshr_miss_latency::total 9729080737 # number of demand (read+write) MSHR miss cycles 1508system.iocache.overall_mshr_miss_latency::realview.ethernet 3437500 # number of overall MSHR miss cycles 1509system.iocache.overall_mshr_miss_latency::realview.ide 9725643237 # number of overall MSHR miss cycles 1510system.iocache.overall_mshr_miss_latency::total 9729080737 # number of overall MSHR miss cycles 1511system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1512system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1513system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1514system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1515system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1516system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1517system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1518system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 1519system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1520system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1521system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 1522system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1523system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1524system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87472.972973 # average ReadReq mshr miss latency 1525system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 178492.057130 # average ReadReq mshr miss latency 1526system.iocache.ReadReq_avg_mshr_miss_latency::total 178113.407915 # average ReadReq mshr miss latency 1527system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 1528system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 1529system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76358.837912 # average WriteLineReq mshr miss latency 1530system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76358.837912 # average WriteLineReq mshr miss latency 1531system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency 1532system.iocache.demand_avg_mshr_miss_latency::realview.ide 84189.396188 # average overall mshr miss latency 1533system.iocache.demand_avg_mshr_miss_latency::total 84190.001272 # average overall mshr miss latency 1534system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85937.500000 # average overall mshr miss latency 1535system.iocache.overall_avg_mshr_miss_latency::realview.ide 84189.396188 # average overall mshr miss latency 1536system.iocache.overall_avg_mshr_miss_latency::total 84190.001272 # average overall mshr miss latency 1537system.membus.snoop_filter.tot_requests 2644146 # Total number of requests made to the snoop filter. 1538system.membus.snoop_filter.hit_single_requests 1308848 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1539system.membus.snoop_filter.hit_multi_requests 3757 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1540system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1541system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1542system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1543system.membus.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1544system.membus.trans_dist::ReadReq 76831 # Transaction distribution 1545system.membus.trans_dist::ReadResp 424240 # Transaction distribution 1546system.membus.trans_dist::WriteReq 33710 # Transaction distribution 1547system.membus.trans_dist::WriteResp 33710 # Transaction distribution 1548system.membus.trans_dist::WritebackDirty 1092438 # Transaction distribution 1549system.membus.trans_dist::CleanEvict 180711 # Transaction distribution 1550system.membus.trans_dist::UpgradeReq 4469 # Transaction distribution 1551system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution 1552system.membus.trans_dist::UpgradeResp 8 # Transaction distribution 1553system.membus.trans_dist::ReadExReq 414321 # Transaction distribution 1554system.membus.trans_dist::ReadExResp 414321 # Transaction distribution 1555system.membus.trans_dist::ReadSharedReq 347409 # Transaction distribution 1556system.membus.trans_dist::InvalidateReq 604276 # Transaction distribution 1557system.membus.trans_dist::InvalidateResp 30630 # Transaction distribution 1558system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 1559system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) 1560system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) 1561system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3256123 # Packet count per connected master and slave (bytes) 1562system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3385827 # Packet count per connected master and slave (bytes) 1563system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237256 # Packet count per connected master and slave (bytes) 1564system.membus.pkt_count_system.iocache.mem_side::total 237256 # Packet count per connected master and slave (bytes) 1565system.membus.pkt_count::total 3623083 # Packet count per connected master and slave (bytes) 1566system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 1567system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) 1568system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) 1569system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 111424480 # Cumulative packet size per connected master and slave (bytes) 1570system.membus.pkt_size_system.cpu.l2cache.mem_side::total 111594330 # Cumulative packet size per connected master and slave (bytes) 1571system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7220672 # Cumulative packet size per connected master and slave (bytes) 1572system.membus.pkt_size_system.iocache.mem_side::total 7220672 # Cumulative packet size per connected master and slave (bytes) 1573system.membus.pkt_size::total 118815002 # Cumulative packet size per connected master and slave (bytes) 1574system.membus.snoops 33993 # Total snoops (count) 1575system.membus.snoopTraffic 214720 # Total snoop traffic (bytes) 1576system.membus.snoop_fanout::samples 1481018 # Request fanout histogram 1577system.membus.snoop_fanout::mean 0.023235 # Request fanout histogram 1578system.membus.snoop_fanout::stdev 0.150648 # Request fanout histogram 1579system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1580system.membus.snoop_fanout::0 1446607 97.68% 97.68% # Request fanout histogram 1581system.membus.snoop_fanout::1 34411 2.32% 100.00% # Request fanout histogram 1582system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1583system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1584system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1585system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1586system.membus.snoop_fanout::total 1481018 # Request fanout histogram 1587system.membus.reqLayer0.occupancy 106898000 # Layer occupancy (ticks) 1588system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1589system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) 1590system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1591system.membus.reqLayer2.occupancy 5816000 # Layer occupancy (ticks) 1592system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1593system.membus.reqLayer5.occupancy 7183768776 # Layer occupancy (ticks) 1594system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1595system.membus.respLayer2.occupancy 4201020680 # Layer occupancy (ticks) 1596system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1597system.membus.respLayer3.occupancy 76902808 # Layer occupancy (ticks) 1598system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1599system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1600system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1601system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1602system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1603system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1604system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1605system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1606system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1607system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1608system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1609system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1610system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1611system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1612system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1613system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1614system.realview.ethernet.txBytes 966 # Bytes Transmitted 1615system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1616system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1617system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1618system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1619system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1620system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1621system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1622system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1623system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) 1624system.realview.ethernet.totPackets 3 # Total Packets 1625system.realview.ethernet.totBytes 966 # Total Bytes 1626system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 1627system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) 1628system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 1629system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1630system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 1631system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1632system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1633system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 1634system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1635system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1636system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 1637system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1638system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1639system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 1640system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1641system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1642system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 1643system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1644system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1645system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 1646system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1647system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1648system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1649system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1650system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1651system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1652system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1653system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1654system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1655system.realview.ethernet.droppedPackets 0 # number of packets dropped 1656system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1657system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1658system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1659system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1660system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1661system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1662system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1663system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1664system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1665system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1666system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1667system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1668system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1669system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1670system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1671system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1672system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1673system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1674system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1675system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1676system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1677system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1678system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51821872017500 # Cumulative time (in ticks) in various power states 1679 1680---------- End Simulation Statistics ---------- 1681