xref: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 51.331525                       # Number of seconds simulated
sim_ticks                                51331524771000                       # Number of ticks simulated
final_tick                               51331524771000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 185259                       # Simulator instruction rate (inst/s)
host_op_rate                                   217677                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                            11233724737                       # Simulator tick rate (ticks/s)
host_mem_usage                                 689476                       # Number of bytes of host memory used
host_seconds                                  4569.41                       # Real time elapsed on the host
sim_insts                                   846524467                       # Number of instructions simulated
sim_ops                                     994654061                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.dtb.walker       205568                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker       197440                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst           5696288                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data          72187912                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        428288                       # Number of bytes read from this memory
system.physmem.bytes_read::total             78715496                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst      5696288                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         5696288                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     67280640                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data          20580                       # Number of bytes written to this memory
system.physmem.bytes_written::total          67301220                       # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker         3212                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker         3085                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst             104957                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data            1127949                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6692                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1245895                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1051260                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data              2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1053833                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker           4005                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker           3846                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst               110971                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1406308                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             8344                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1533473                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst          110971                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             110971                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1310708                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data                 401                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1311109                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1310708                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker          4005                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker          3846                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst              110971                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1406708                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            8344                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                2844582                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1245895                       # Number of read requests accepted
system.physmem.writeReqs                      1053833                       # Number of write requests accepted
system.physmem.readBursts                     1245895                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1053833                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 79684928                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     52352                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  67299776                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  78715496                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               67301220                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      818                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2246                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               74822                       # Per bank write bursts
system.physmem.perBankRdBursts::1               82180                       # Per bank write bursts
system.physmem.perBankRdBursts::2               80987                       # Per bank write bursts
system.physmem.perBankRdBursts::3               75462                       # Per bank write bursts
system.physmem.perBankRdBursts::4               75477                       # Per bank write bursts
system.physmem.perBankRdBursts::5               80130                       # Per bank write bursts
system.physmem.perBankRdBursts::6               74577                       # Per bank write bursts
system.physmem.perBankRdBursts::7               72890                       # Per bank write bursts
system.physmem.perBankRdBursts::8               72311                       # Per bank write bursts
system.physmem.perBankRdBursts::9              102827                       # Per bank write bursts
system.physmem.perBankRdBursts::10              78128                       # Per bank write bursts
system.physmem.perBankRdBursts::11              79408                       # Per bank write bursts
system.physmem.perBankRdBursts::12              72963                       # Per bank write bursts
system.physmem.perBankRdBursts::13              76387                       # Per bank write bursts
system.physmem.perBankRdBursts::14              73944                       # Per bank write bursts
system.physmem.perBankRdBursts::15              72584                       # Per bank write bursts
system.physmem.perBankWrBursts::0               62047                       # Per bank write bursts
system.physmem.perBankWrBursts::1               68427                       # Per bank write bursts
system.physmem.perBankWrBursts::2               68519                       # Per bank write bursts
system.physmem.perBankWrBursts::3               66050                       # Per bank write bursts
system.physmem.perBankWrBursts::4               65357                       # Per bank write bursts
system.physmem.perBankWrBursts::5               67435                       # Per bank write bursts
system.physmem.perBankWrBursts::6               63960                       # Per bank write bursts
system.physmem.perBankWrBursts::7               63937                       # Per bank write bursts
system.physmem.perBankWrBursts::8               63039                       # Per bank write bursts
system.physmem.perBankWrBursts::9               70105                       # Per bank write bursts
system.physmem.perBankWrBursts::10              66227                       # Per bank write bursts
system.physmem.perBankWrBursts::11              68082                       # Per bank write bursts
system.physmem.perBankWrBursts::12              64306                       # Per bank write bursts
system.physmem.perBankWrBursts::13              66291                       # Per bank write bursts
system.physmem.perBankWrBursts::14              64522                       # Per bank write bursts
system.physmem.perBankWrBursts::15              63255                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                          38                       # Number of times write queue was full causing retry
system.physmem.totGap                    51331523357500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      13                       # Read request sizes (log2)
system.physmem.readPktSize::4                   21272                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1224610                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      1                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1051260                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    635913                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    326498                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    150136                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                    126962                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                       653                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                       548                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                       549                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                      1209                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                       762                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                       332                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                      367                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                      192                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                      170                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                      133                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      125                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      133                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      111                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      110                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                       86                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                       71                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       10                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        2                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    11720                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    15352                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    33279                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    44422                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    54389                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    61870                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    62052                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    63406                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    64510                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    63581                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    65005                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    68339                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    65443                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    80751                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    86913                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    66052                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    69586                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    62814                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     2950                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                      981                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                      731                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                      548                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                      563                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                      453                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                      371                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                      380                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                      355                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                      337                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                      297                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                      291                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                      329                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                      273                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                      323                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                      265                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                      252                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                      297                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                      210                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                      278                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                      193                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                      215                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                      142                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                      148                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                      116                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                      157                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                      117                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                      142                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                      209                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                       72                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                       93                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples       477001                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      308.142583                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     177.284446                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     336.100691                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         186993     39.20%     39.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       111432     23.36%     62.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        45372      9.51%     72.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        23464      4.92%     76.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        18197      3.81%     80.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        11652      2.44%     83.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895        10522      2.21%     85.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         8218      1.72%     87.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        61151     12.82%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total         477001                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         59594                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        20.891952                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev      270.280066                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-2047          59591     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-12287            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::63488-65535            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           59594                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         59594                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        17.645384                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       16.994879                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev        7.954134                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16-19           56960     95.58%     95.58% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20-23             905      1.52%     97.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27              37      0.06%     97.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31             115      0.19%     97.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35              18      0.03%     97.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39             110      0.18%     97.57% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43             195      0.33%     97.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47              24      0.04%     97.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51             355      0.60%     98.53% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::52-55              71      0.12%     98.65% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59              24      0.04%     98.69% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63              56      0.09%     98.79% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67             280      0.47%     99.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71              26      0.04%     99.30% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75              33      0.06%     99.35% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79             125      0.21%     99.56% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::80-83             203      0.34%     99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::88-91               2      0.00%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99               3      0.01%     99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::100-103             2      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107             1      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::112-115             2      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::116-119             1      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123             1      0.00%     99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127             1      0.00%     99.93% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131            13      0.02%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135             1      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::136-139             1      0.00%     99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143             8      0.01%     99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147            11      0.02%     99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::148-151             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::156-159             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::160-163             2      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179             1      0.00%     99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::180-183             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192-195             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::208-211             1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           59594                       # Writes before turning the bus around for reads
system.physmem.totQLat                    31834686171                       # Total ticks spent queuing
system.physmem.totMemAccLat               55179879921                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   6225385000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       25568.45                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  44318.45                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.55                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.31                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.53                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.31                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.02                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.05                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        26.63                       # Average write queue length when enqueuing
system.physmem.readRowHits                    1023243                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    796390                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   82.18                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  75.73                       # Row buffer hit rate for writes
system.physmem.avgGap                     22320693.30                       # Average gap between requests
system.physmem.pageHitRate                      79.23                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 1817907840                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                  991914000                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                4808848200                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3406743360                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           3352725536160                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy           1236862065645                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy           29713947077250                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy             34314560092455                       # Total energy per rank (pJ)
system.physmem_0.averagePower              668.489031                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE   49431665045810                       # Time in different power states
system.physmem_0.memoryStateTime::REF    1714072360000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT    185786732190                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                 1788219720                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                  975715125                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                4902705600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3407358960                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           3352725536160                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy           1238749464465                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy           29712291456000                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy             34314840456030                       # Total energy per rank (pJ)
system.physmem_1.averagePower              668.494493                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE   49428877758086                       # Time in different power states
system.physmem_1.memoryStateTime::REF    1714072360000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT    188572884414                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst          384                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           420                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst          384                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          384                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst           24                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             29                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst             7                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu.data             1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total                8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total            7                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst            7                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total               8                       # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1666                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6826496                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1669                       # Number of DMA write transactions.
system.cpu.branchPred.lookups               223870317                       # Number of BP lookups
system.cpu.branchPred.condPredicted         149571742                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect          12183866                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups            157933845                       # Number of BTB lookups
system.cpu.branchPred.BTBHits               103250874                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             65.376028                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                30780710                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect             342883                       # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                    937088                       # Table walker walks requested
system.cpu.dtb.walker.walksLong                937088                       # Table walker walks initiated with long descriptors
system.cpu.dtb.walker.walksLongTerminationLevel::Level2        15029                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksLongTerminationLevel::Level3       154587                       # Level at which table walker walks with long descriptors terminate
system.cpu.dtb.walker.walksSquashedBefore       427394                       # Table walks squashed before starting
system.cpu.dtb.walker.walkWaitTime::samples       509694                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::mean  2223.932399                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::stdev 14616.246492                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::0-65535       506310     99.34%     99.34% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::65536-131071         1920      0.38%     99.71% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::131072-196607          988      0.19%     99.91% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::196608-262143          199      0.04%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::262144-327679          148      0.03%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::327680-393215           28      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::393216-458751           46      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::458752-524287           49      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::524288-589823            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkWaitTime::total       509694                       # Table walker wait (enqueue to first request) latency
system.cpu.dtb.walker.walkCompletionTime::samples       474748                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::mean 23018.407660                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::gmean 18045.301329                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::stdev 20477.097679                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::0-65535       463839     97.70%     97.70% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::65536-131071         7714      1.62%     99.33% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::131072-196607         2286      0.48%     99.81% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::196608-262143          175      0.04%     99.85% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::262144-327679          504      0.11%     99.95% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::327680-393215           86      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::393216-458751           94      0.02%     99.99% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::458752-524287           30      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::524288-589823           10      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::589824-655359            8      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::720896-786431            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::total       474748                       # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 784053971876                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::mean     0.725342                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::stdev     0.519550                       # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0-1  781854829876     99.72%     99.72% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::2-3    1175747000      0.15%     99.87% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::4-5     476309500      0.06%     99.93% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::6-7     200437500      0.03%     99.96% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::8-9     146602500      0.02%     99.97% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::10-11    120332500      0.02%     99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::12-13     25999000      0.00%     99.99% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::14-15     51086000      0.01%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::16-17      2628000      0.00%    100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 784053971876                       # Table walker pending requests distribution
system.cpu.dtb.walker.walkPageSizes::4K        154588     91.14%     91.14% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::2M         15029      8.86%    100.00% # Table walker page sizes translated
system.cpu.dtb.walker.walkPageSizes::total       169617                       # Table walker page sizes translated
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data       937088                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total       937088                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data       169617                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total       169617                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total      1106705                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                    169133397                       # DTB read hits
system.cpu.dtb.read_misses                     670096                       # DTB read misses
system.cpu.dtb.write_hits                   147221017                       # DTB write hits
system.cpu.dtb.write_misses                    266992                       # DTB write misses
system.cpu.dtb.flush_tlb                           10                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid               39151                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                    1017                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                    71818                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                        99                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                   9972                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                     69741                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                169803493                       # DTB read accesses
system.cpu.dtb.write_accesses               147488009                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                         316354414                       # DTB hits
system.cpu.dtb.misses                          937088                       # DTB misses
system.cpu.dtb.accesses                     317291502                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                    160983                       # Table walker walks requested
system.cpu.itb.walker.walksLong                160983                       # Table walker walks initiated with long descriptors
system.cpu.itb.walker.walksLongTerminationLevel::Level2         1438                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksLongTerminationLevel::Level3       121478                       # Level at which table walker walks with long descriptors terminate
system.cpu.itb.walker.walksSquashedBefore        17520                       # Table walks squashed before starting
system.cpu.itb.walker.walkWaitTime::samples       143463                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::mean  1273.722144                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::stdev  9463.659088                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::0-32767       142472     99.31%     99.31% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::32768-65535          574      0.40%     99.71% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::65536-98303           44      0.03%     99.74% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::98304-131071           82      0.06%     99.80% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::131072-163839          231      0.16%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::163840-196607           26      0.02%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::196608-229375            2      0.00%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::229376-262143            4      0.00%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::262144-294911           15      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::294912-327679            5      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::327680-360447            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::360448-393215            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::393216-425983            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::425984-458751            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkWaitTime::total       143463                       # Table walker wait (enqueue to first request) latency
system.cpu.itb.walker.walkCompletionTime::samples       140436                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::mean 29061.341109                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::gmean 24320.215707                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::stdev 22395.663440                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::0-65535       137485     97.90%     97.90% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::65536-131071          845      0.60%     98.50% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::131072-196607         1830      1.30%     99.80% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::196608-262143           92      0.07%     99.87% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::262144-327679          113      0.08%     99.95% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::327680-393215           31      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::393216-458751           34      0.02%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::458752-524287            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::524288-589823            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::589824-655359            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::total       140436                       # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples 672381692680                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::mean     0.944059                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::stdev     0.230149                       # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0     37665306856      5.60%      5.60% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::1    634665708824     94.39%     99.99% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::2        49644500      0.01%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::3         1013500      0.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::4           19000      0.00%    100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 672381692680                       # Table walker pending requests distribution
system.cpu.itb.walker.walkPageSizes::4K        121478     98.83%     98.83% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::2M          1438      1.17%    100.00% # Table walker page sizes translated
system.cpu.itb.walker.walkPageSizes::total       122916                       # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst       160983                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total       160983                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst       122916                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total       122916                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total       283899                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                    355891670                       # ITB inst hits
system.cpu.itb.inst_misses                     160983                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                           10                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid               39151                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                    1017                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                    52900                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                    368990                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                356052653                       # ITB inst accesses
system.cpu.itb.hits                         355891670                       # DTB hits
system.cpu.itb.misses                          160983                       # DTB misses
system.cpu.itb.accesses                     356052653                       # DTB accesses
system.cpu.numCycles                       1641618102                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles          643295277                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      998912988                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                   223870317                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches          134031584                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     911548920                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                26021190                       # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles                    3814569                       # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles                28072                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles       9294541                       # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles      1045994                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles          928                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                 355505947                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes               6091455                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes                   48555                       # Number of outstanding ITLB misses that were squashed
system.cpu.fetch.rateDist::samples         1582038896                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              0.739816                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.145969                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0               1026150412     64.86%     64.86% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                213368743     13.49%     78.35% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 70509493      4.46%     82.81% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                272010248     17.19%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total           1582038896                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.136372                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        0.608493                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                523526038                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles             567332242                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 432225078                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles              49743606                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                9211932                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             33585206                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred               3858658                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts             1082487330                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts              28953315                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                9211932                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                568013928                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                68659821                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles      370106883                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 437449183                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles             128597149                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts             1062778939                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts               6765759                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents               5100330                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 330196                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                 669001                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents               77613497                       # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents            20248                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands          1010589647                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1636490834                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups       1256895335                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups           1474103                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             945145868                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                 65443776                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts           26770566                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts       23114475                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                 102068123                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads            173157157                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores           150776419                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           9868164                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          9014634                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                 1027918827                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded            27065451                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                1043272281                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           3272960                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        60330213                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined     33600804                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved         313388                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples    1582038896                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         0.659448                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        0.917899                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0           936232713     59.18%     59.18% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1           333194737     21.06%     80.24% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2           234236353     14.81%     95.05% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            71914703      4.55%     99.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             6441221      0.41%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5               19169      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total      1582038896                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                57633129     35.05%     35.05% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                 100179      0.06%     35.11% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                   26746      0.02%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd                 0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp                 0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt                 0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv                 0      0.00%     35.12% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc              783      0.00%     35.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult                0      0.00%     35.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             0      0.00%     35.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     35.13% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               44218992     26.89%     62.02% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite              62461837     37.98%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                21      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             718385578     68.86%     68.86% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult              2533352      0.24%     69.10% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                122770      0.01%     69.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                 382      0.00%     69.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     69.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     69.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     69.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     69.11% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     69.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     69.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     69.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     69.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     69.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     69.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     69.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     69.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     69.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     69.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     69.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     69.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd               8      0.00%     69.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     69.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp              15      0.00%     69.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt              23      0.00%     69.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv               0      0.00%     69.11% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc         121248      0.01%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult              0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt              0      0.00%     69.13% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead            173007895     16.58%     85.71% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite           149100989     14.29%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total             1043272281                       # Type of FU issued
system.cpu.iq.rate                           0.635515                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                   164441666                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.157621                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads         3833820592                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes        1114508942                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses   1025374913                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads             2477491                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes             947894                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses       909947                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses             1206157308                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                 1556618                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          4301219                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads     13765356                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses        14482                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation       143653                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      6293913                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads      2526650                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked       1543650                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                9211932                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 6884950                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles               9078435                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts          1055205514                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts             173157157                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts            150776419                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts           22691259                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                  56491                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents               8949926                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents         143653                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        3653003                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      5096400                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              8749403                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts            1032130630                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts             169121119                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts          10215406                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                        221236                       # number of nop insts executed
system.cpu.iew.exec_refs                    316337352                       # number of memory reference insts executed
system.cpu.iew.exec_branches                195829859                       # Number of branches executed
system.cpu.iew.exec_stores                  147216233                       # Number of stores executed
system.cpu.iew.exec_rate                     0.628728                       # Inst execution rate
system.cpu.iew.wb_sent                     1027090277                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                    1026284860                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 436833707                       # num instructions producing a value
system.cpu.iew.wb_consumers                 706462159                       # num instructions consuming a value
system.cpu.iew.wb_rate                       0.625167                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.618340                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts        51246502                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls        26752063                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           8385203                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples   1570087734                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     0.633502                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.269814                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0   1059518127     67.48%     67.48% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1    287046411     18.28%     85.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2    120236472      7.66%     93.42% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3     36451838      2.32%     95.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4     28385212      1.81%     97.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5     13987217      0.89%     98.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      8615612      0.55%     98.99% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      4166173      0.27%     99.26% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8     11680672      0.74%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total   1570087734                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            846524467                       # Number of instructions committed
system.cpu.commit.committedOps              994654061                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                      303874306                       # Number of memory references committed
system.cpu.commit.loads                     159391800                       # Number of loads committed
system.cpu.commit.membars                     6909679                       # Number of memory barriers committed
system.cpu.commit.branches                  188935778                       # Number of branches committed
system.cpu.commit.fp_insts                     896706                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 913907111                       # Number of committed integer instructions.
system.cpu.commit.function_calls             25250179                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        688421836     69.21%     69.21% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult         2147861      0.22%     69.43% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv            98019      0.01%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd            8      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp           13      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt           21      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv            0      0.00%     69.44% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc       111997      0.01%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult            0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.45% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead       159391800     16.02%     85.47% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite      144482506     14.53%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         994654061                       # Class of committed instruction
system.cpu.commit.bw_lim_events              11680672                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                   2596784081                       # The number of ROB reads
system.cpu.rob.rob_writes                  2103659595                       # The number of ROB writes
system.cpu.timesIdled                         8144337                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                        59579206                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles                 101021431570                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts                   846524467                       # Number of Instructions Simulated
system.cpu.committedOps                     994654061                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               1.939245                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         1.939245                       # CPI: Total CPI of All Threads
system.cpu.ipc                               0.515665                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         0.515665                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads               1221742987                       # number of integer regfile reads
system.cpu.int_regfile_writes               729786392                       # number of integer regfile writes
system.cpu.fp_regfile_reads                   1462559                       # number of floating regfile reads
system.cpu.fp_regfile_writes                   782552                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 224594796                       # number of cc regfile reads
system.cpu.cc_regfile_writes                225242859                       # number of cc regfile writes
system.cpu.misc_regfile_reads              2567204891                       # number of misc regfile reads
system.cpu.misc_regfile_writes               26785378                       # number of misc regfile writes
system.cpu.dcache.tags.replacements           9653571                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.972798                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs           282643774                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs           9654083                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs             29.277123                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle        2743199500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.972798                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.999947                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.999947                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           94                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          381                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2           37                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses        1234280358                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses       1234280358                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data    146896386                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total       146896386                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data    128038519                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total      128038519                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data       377527                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total        377527                       # number of SoftPFReq hits
system.cpu.dcache.WriteLineReq_hits::cpu.data       324244                       # number of WriteLineReq hits
system.cpu.dcache.WriteLineReq_hits::total       324244                       # number of WriteLineReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data      3284324                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total      3284324                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data      3679077                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total      3679077                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data     274934905                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total        274934905                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data    275312432                       # number of overall hits
system.cpu.dcache.overall_hits::total       275312432                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data      9519580                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total       9519580                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data     11197407                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total     11197407                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data      1162034                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total      1162034                       # number of SoftPFReq misses
system.cpu.dcache.WriteLineReq_misses::cpu.data      1231431                       # number of WriteLineReq misses
system.cpu.dcache.WriteLineReq_misses::total      1231431                       # number of WriteLineReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data       446029                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total       446029                       # number of LoadLockedReq misses
system.cpu.dcache.StoreCondReq_misses::cpu.data            5                       # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total            5                       # number of StoreCondReq misses
system.cpu.dcache.demand_misses::cpu.data     20716987                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total       20716987                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data     21879021                       # number of overall misses
system.cpu.dcache.overall_misses::total      21879021                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 166239076000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 166239076000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 434694643757                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 434694643757                       # number of WriteReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::cpu.data  89167821376                       # number of WriteLineReq miss cycles
system.cpu.dcache.WriteLineReq_miss_latency::total  89167821376                       # number of WriteLineReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data   6826466500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total   6826466500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       272500                       # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total       272500                       # number of StoreCondReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 600933719757                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 600933719757                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 600933719757                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 600933719757                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data    156415966                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total    156415966                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data    139235926                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total    139235926                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data      1539561                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total      1539561                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::cpu.data      1555675                       # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.WriteLineReq_accesses::total      1555675                       # number of WriteLineReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data      3730353                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total      3730353                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data      3679082                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total      3679082                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data    295651892                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total    295651892                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data    297191453                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total    297191453                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.060861                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.060861                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.080420                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.080420                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.754783                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.754783                       # miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::cpu.data     0.791573                       # miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_miss_rate::total     0.791573                       # miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.119568                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.119568                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000001                       # miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_miss_rate::total     0.000001                       # miss rate for StoreCondReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.070072                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.070072                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.073619                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.073619                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17462.858235                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 17462.858235                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38821.009521                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 38821.009521                       # average WriteReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 72409.920959                       # average WriteLineReq miss latency
system.cpu.dcache.WriteLineReq_avg_miss_latency::total 72409.920959                       # average WriteLineReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15304.983532                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15304.983532                       # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        54500                       # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total        54500                       # average StoreCondReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 29006.810679                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 29006.810679                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 27466.207001                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 27466.207001                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs     49612844                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs           1593346                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs    31.137521                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks      7472245                       # number of writebacks
system.cpu.dcache.writebacks::total           7472245                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data      4426093                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total      4426093                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data      9200570                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total      9200570                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data         7004                       # number of WriteLineReq MSHR hits
system.cpu.dcache.WriteLineReq_mshr_hits::total         7004                       # number of WriteLineReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data       218758                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total       218758                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data     13626663                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total     13626663                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data     13626663                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total     13626663                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data      5093487                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total      5093487                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1996837                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total      1996837                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data      1155229                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total      1155229                       # number of SoftPFReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data      1224427                       # number of WriteLineReq MSHR misses
system.cpu.dcache.WriteLineReq_mshr_misses::total      1224427                       # number of WriteLineReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data       227271                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total       227271                       # number of LoadLockedReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            5                       # number of StoreCondReq MSHR misses
system.cpu.dcache.StoreCondReq_mshr_misses::total            5                       # number of StoreCondReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data      7090324                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total      7090324                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data      8245553                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total      8245553                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.ReadReq_mshr_uncacheable::total        33678                       # number of ReadReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data        33696                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data        67374                       # number of overall MSHR uncacheable misses
system.cpu.dcache.overall_mshr_uncacheable_misses::total        67374                       # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  84024978000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total  84024978000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  76144562086                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total  76144562086                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data  22952152500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total  22952152500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data  87564866876                       # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.WriteLineReq_mshr_miss_latency::total  87564866876                       # number of WriteLineReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data   3184481000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total   3184481000                       # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       267500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       267500                       # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160169540086                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 160169540086                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 183121692586                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 183121692586                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   6191871000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   6191871000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   6228308464                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   6228308464                       # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  12420179464                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total  12420179464                       # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.032564                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.032564                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.014341                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.014341                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.750363                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.750363                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data     0.787071                       # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.WriteLineReq_mshr_miss_rate::total     0.787071                       # mshr miss rate for WriteLineReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.060925                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.060925                       # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000001                       # mshr miss rate for StoreCondReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.023982                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.023982                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.027745                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.027745                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16496.552951                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16496.552951                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38132.587730                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38132.587730                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19868.054299                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19868.054299                       # average SoftPFReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 71514.975475                       # average WriteLineReq mshr miss latency
system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 71514.975475                       # average WriteLineReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14011.822890                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14011.822890                       # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        53500                       # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        53500                       # average StoreCondReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22589.876018                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 22589.876018                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22208.539874                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 22208.539874                       # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183855.068591                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183855.068591                       # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184838.214150                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184838.214150                       # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184346.772702                       # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184346.772702                       # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements          15015869                       # number of replacements
system.cpu.icache.tags.tagsinuse           511.916858                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs           339700335                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs          15016381                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             22.621984                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       24730722500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   511.916858                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.999838                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.999838                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0          117                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          294                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          101                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         370501257                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        370501257                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst    339700335                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total       339700335                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst     339700335                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total        339700335                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst    339700335                       # number of overall hits
system.cpu.icache.overall_hits::total       339700335                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst     15784316                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total      15784316                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst     15784316                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total       15784316                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst     15784316                       # number of overall misses
system.cpu.icache.overall_misses::total      15784316                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 213513378383                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 213513378383                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 213513378383                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 213513378383                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 213513378383                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 213513378383                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst    355484651                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total    355484651                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst    355484651                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total    355484651                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst    355484651                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total    355484651                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.044402                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.044402                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.044402                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.044402                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.044402                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.044402                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13526.932582                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13526.932582                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13526.932582                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13526.932582                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13526.932582                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13526.932582                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        23493                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs              1429                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    16.440168                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks     15015869                       # number of writebacks
system.cpu.icache.writebacks::total          15015869                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst       767710                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total       767710                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst       767710                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total       767710                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst       767710                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total       767710                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst     15016606                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total     15016606                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst     15016606                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total     15016606                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst     15016606                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total     15016606                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst        21294                       # number of ReadReq MSHR uncacheable
system.cpu.icache.ReadReq_mshr_uncacheable::total        21294                       # number of ReadReq MSHR uncacheable
system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst        21294                       # number of overall MSHR uncacheable misses
system.cpu.icache.overall_mshr_uncacheable_misses::total        21294                       # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191214569892                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 191214569892                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191214569892                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 191214569892                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191214569892                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 191214569892                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst   2684938000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total   2684938000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst   2684938000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total   2684938000                       # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.042243                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.042243                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.042243                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.042243                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.042243                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.042243                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12733.541114                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12733.541114                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12733.541114                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12733.541114                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12733.541114                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12733.541114                       # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.945243                       # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.945243                       # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.945243                       # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.945243                       # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements          1125252                       # number of replacements
system.cpu.l2cache.tags.tagsinuse        65288.718100                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs           45967246                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs          1186784                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            38.732614                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle      22908442500                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 37194.464747                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker   291.486399                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker   421.983765                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst  7890.372010                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 19490.411179                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.567542                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.004448                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.006439                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst     0.120398                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data     0.297400                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.996227                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1023          288                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024        61244                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1023::4          288                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           63                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          554                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2         2686                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3         5116                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4        52825                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1023     0.004395                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.934509                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses        408147650                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses       408147650                       # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker       779679                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker       299256                       # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total        1078935                       # number of ReadReq hits
system.cpu.l2cache.WritebackDirty_hits::writebacks      7472245                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total      7472245                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks     15013335                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total     15013335                       # number of WritebackClean hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data         9316                       # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total         9316                       # number of UpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::cpu.data            2                       # number of SCUpgradeReq hits
system.cpu.l2cache.SCUpgradeReq_hits::total            2                       # number of SCUpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data      1569994                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total      1569994                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst     14932694                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total     14932694                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data      6224430                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total      6224430                       # number of ReadSharedReq hits
system.cpu.l2cache.InvalidateReq_hits::cpu.data       730294                       # number of InvalidateReq hits
system.cpu.l2cache.InvalidateReq_hits::total       730294                       # number of InvalidateReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker       779679                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker       299256                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst     14932694                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data      7794424                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total        23806053                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker       779679                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker       299256                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst     14932694                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data      7794424                       # number of overall hits
system.cpu.l2cache.overall_hits::total       23806053                       # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker         3212                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker         3085                       # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total         6297                       # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data        33834                       # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total        33834                       # number of UpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::cpu.data            3                       # number of SCUpgradeReq misses
system.cpu.l2cache.SCUpgradeReq_misses::total            3                       # number of SCUpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data       386835                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total       386835                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst        83701                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total        83701                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data       248420                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total       248420                       # number of ReadSharedReq misses
system.cpu.l2cache.InvalidateReq_misses::cpu.data       494133                       # number of InvalidateReq misses
system.cpu.l2cache.InvalidateReq_misses::total       494133                       # number of InvalidateReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker         3212                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker         3085                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst        83701                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data       635255                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total        725253                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker         3212                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker         3085                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst        83701                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data       635255                       # number of overall misses
system.cpu.l2cache.overall_misses::total       725253                       # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker    442122000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker    426004000                       # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total    868126000                       # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data   1354898000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total   1354898000                       # number of UpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data       160500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.SCUpgradeReq_miss_latency::total       160500                       # number of SCUpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  53636618000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total  53636618000                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst  11266586500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total  11266586500                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data  34501509500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total  34501509500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data  76602045500                       # number of InvalidateReq miss cycles
system.cpu.l2cache.InvalidateReq_miss_latency::total  76602045500                       # number of InvalidateReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker    442122000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker    426004000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst  11266586500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data  88138127500                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 100272840000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker    442122000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker    426004000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst  11266586500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data  88138127500                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 100272840000                       # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker       782891                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker       302341                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total      1085232                       # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::writebacks      7472245                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total      7472245                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks     15013335                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total     15013335                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data        43150                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total        43150                       # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data            5                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.SCUpgradeReq_accesses::total            5                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data      1956829                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total      1956829                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst     15016395                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total     15016395                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data      6472850                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total      6472850                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::cpu.data      1224427                       # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.InvalidateReq_accesses::total      1224427                       # number of InvalidateReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker       782891                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker       302341                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst     15016395                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data      8429679                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total     24531306                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker       782891                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker       302341                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst     15016395                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data      8429679                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total     24531306                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.004103                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker     0.010204                       # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total     0.005802                       # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.784102                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total     0.784102                       # miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data     0.600000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_miss_rate::total     0.600000                       # miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.197685                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.197685                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.005574                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.005574                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.038379                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.038379                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data     0.403563                       # miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_miss_rate::total     0.403563                       # miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.004103                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker     0.010204                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.005574                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.075359                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.029564                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker     0.004103                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker     0.010204                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.005574                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.075359                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.029564                       # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137646.948941                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 138088.816856                       # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 137863.427029                       # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 40045.457232                       # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 40045.457232                       # average UpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        53500                       # average SCUpgradeReq miss latency
system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total        53500                       # average SCUpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 138655.028630                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 138655.028630                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134605.160034                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134605.160034                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 138883.783512                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 138883.783512                       # average ReadSharedReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 155023.132436                       # average InvalidateReq miss latency
system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 155023.132436                       # average InvalidateReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137646.948941                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 138088.816856                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134605.160034                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 138744.484498                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 138259.117853                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137646.948941                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 138088.816856                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134605.160034                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 138744.484498                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 138259.117853                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks       944630                       # number of writebacks
system.cpu.l2cache.writebacks::total           944630                       # number of writebacks
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data           20                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total           20                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           20                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           20                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           20                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           20                       # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker         3212                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker         3085                       # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total         6297                       # number of ReadReq MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::writebacks            1                       # number of CleanEvict MSHR misses
system.cpu.l2cache.CleanEvict_mshr_misses::total            1                       # number of CleanEvict MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data        33834                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total        33834                       # number of UpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            3                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            3                       # number of SCUpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       386835                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total       386835                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst        83701                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total        83701                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data       248400                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total       248400                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data       494133                       # number of InvalidateReq MSHR misses
system.cpu.l2cache.InvalidateReq_mshr_misses::total       494133                       # number of InvalidateReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker         3212                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker         3085                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst        83701                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data       635235                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total       725233                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker         3212                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker         3085                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst        83701                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data       635235                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total       725233                       # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst        21294                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data        33678                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.ReadReq_mshr_uncacheable::total        54972                       # number of ReadReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data        33696                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.WriteReq_mshr_uncacheable::total        33696                       # number of WriteReq MSHR uncacheable
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst        21294                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data        67374                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.overall_mshr_uncacheable_misses::total        88668                       # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker    410001501                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker    395154000                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total    805155501                       # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   2301104500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   2301104500                       # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       209000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       209000                       # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  49768267002                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  49768267002                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst  10429576500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total  10429576500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data  32015340500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total  32015340500                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data  71660712011                       # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total  71660712011                       # number of InvalidateReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker    410001501                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker    395154000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst  10429576500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  81783607502                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total  93018339503                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker    410001501                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker    395154000                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst  10429576500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  81783607502                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total  93018339503                       # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   2418763000                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5770735500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   8189498500                       # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   5836278000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   5836278000                       # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   2418763000                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data  11607013500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total  14025776500                       # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.004103                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.010204                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.005802                       # mshr miss rate for ReadReq accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.784102                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.784102                       # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data     0.600000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.600000                       # mshr miss rate for SCUpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.197685                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.197685                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.005574                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.005574                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.038376                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.038376                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data     0.403563                       # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total     0.403563                       # mshr miss rate for InvalidateReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.004103                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.010204                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.005574                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.075357                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.029564                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.004103                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.010204                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.005574                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.075357                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.029564                       # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127646.793587                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 128088.816856                       # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127863.347785                       # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68011.600757                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68011.600757                       # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69666.666667                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69666.666667                       # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128655.026050                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128655.026050                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124605.160034                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124605.160034                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 128886.233897                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 128886.233897                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 145023.125375                       # average InvalidateReq mshr miss latency
system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145023.125375                       # average InvalidateReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127646.793587                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 128088.816856                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124605.160034                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 128745.436731                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128259.937845                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127646.793587                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 128088.816856                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124605.160034                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 128745.436731                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128259.937845                       # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.945243                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171350.302868                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148975.814960                       # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173203.881766                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173203.881766                       # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.945243                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172277.339923                       # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158183.070555                       # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests     50072876                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests     25402191                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3486                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops         2165                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         2165                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadReq        1616472                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp      23106705                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq         33696                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp        33696                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty      8523542                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean     15015869                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict      2370764                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq        43153                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq            5                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp        43158                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq      1956829                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp      1956829                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq     15016606                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq      6481683                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateReq      1331091                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::InvalidateResp      1224427                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side     45091458                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side     29183621                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side       729593                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      1917139                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total          76921811                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side   1922405600                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side   1017963166                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side      2418728                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side      6263128                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total         2949050622                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                     1833494                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples     27720270                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.025088                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.156393                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0           27024822     97.49%     97.49% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1             695448      2.51%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total       27720270                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy    48021701496                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy      1471889                       # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy   22555136481                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy   13331758520                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy     427610263                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy    1134604242                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.trans_dist::ReadReq                40281                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40281                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136571                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136571                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47822                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29548                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122704                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       230920                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       230920                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353704                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47842                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17558                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155834                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7334112                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7334112                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7492032                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             41869500                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                12000                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               342000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                 9500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                 9500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy                9500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               14500                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            25153000                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            36496500                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           567170357                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92800000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147680000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.replacements               115446                       # number of replacements
system.iocache.tags.tagsinuse               10.422236                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115462                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         13103145496000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     5.903254                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     4.518982                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.368953                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.282436                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.651390                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1039497                       # Number of tag accesses
system.iocache.tags.data_accesses             1039497                       # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8796                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8833                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106664                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106664                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide         8796                       # number of demand (read+write) misses
system.iocache.demand_misses::total              8836                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide         8796                       # number of overall misses
system.iocache.overall_misses::total             8836                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5069500                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1678447047                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1683516547                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       351000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       351000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13410212810                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13410212810                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5420500                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide   1678447047                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total   1683867547                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5420500                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide   1678447047                       # number of overall miss cycles
system.iocache.overall_miss_latency::total   1683867547                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8796                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8833                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106664                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide         8796                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total            8836                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide         8796                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total           8836                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 190819.355048                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 190593.971131                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       117000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       117000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125723.888191                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 125723.888191                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 190819.355048                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 190568.984495                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 190819.355048                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 190568.984495                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         34452                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3448                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs     9.991879                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.fast_writes                          0                       # number of fast writes performed
system.iocache.cache_copies                         0                       # number of cache copies performed
system.iocache.writebacks::writebacks          106630                       # number of writebacks
system.iocache.writebacks::total               106630                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8796                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8833                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106664                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106664                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide         8796                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total         8836                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide         8796                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total         8836                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3219500                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1238647047                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1241866547                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       201000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   8071956842                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   8071956842                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3420500                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   1238647047                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   1242067547                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3420500                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   1238647047                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   1242067547                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140819.355048                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 140593.971131                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        67000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        67000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75676.487306                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75676.487306                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 140819.355048                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 140568.984495                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 140819.355048                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 140568.984495                       # average overall mshr miss latency
system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq               54972                       # Transaction distribution
system.membus.trans_dist::ReadResp             402203                       # Transaction distribution
system.membus.trans_dist::WriteReq              33696                       # Transaction distribution
system.membus.trans_dist::WriteResp             33696                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1051260                       # Transaction distribution
system.membus.trans_dist::CleanEvict           188377                       # Transaction distribution
system.membus.trans_dist::UpgradeReq            34626                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq              3                       # Transaction distribution
system.membus.trans_dist::UpgradeResp               8                       # Transaction distribution
system.membus.trans_dist::ReadExReq            880179                       # Transaction distribution
system.membus.trans_dist::ReadExResp           880179                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq        347231                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        106664                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave       122704                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port           58                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio         6858                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port      3643028                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total      3772648                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       237638                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       237638                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                4010286                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave       155834                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port          420                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio        13716                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port    138764108                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total    138934078                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7252608                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7252608                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               146186686                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                             2808                       # Total snoops (count)
system.membus.snoop_fanout::samples           2697046                       # Request fanout histogram
system.membus.snoop_fanout::mean                    1                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                       0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::1                 2697046    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               1                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             2697046                       # Request fanout histogram
system.membus.reqLayer0.occupancy           103954500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               32000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy             5466500                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          7139670905                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         6571001988                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           44720417                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             151                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              151                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
system.cpu.kern.inst.quiesce                    16102                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------