stats.txt revision 11336
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.331525 # Number of seconds simulated 4sim_ticks 51331524771000 # Number of ticks simulated 5final_tick 51331524771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 185259 # Simulator instruction rate (inst/s) 8host_op_rate 217677 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 11233724737 # Simulator tick rate (ticks/s) 10host_mem_usage 689476 # Number of bytes of host memory used 11host_seconds 4569.41 # Real time elapsed on the host 12sim_insts 846524467 # Number of instructions simulated 13sim_ops 994654061 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 205568 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 197440 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 5696288 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 72187912 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 428288 # Number of bytes read from this memory 21system.physmem.bytes_read::total 78715496 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 5696288 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 5696288 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 67280640 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 26system.physmem.bytes_written::total 67301220 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 3212 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 3085 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 104957 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 1127949 # Number of read requests responded to by this memory 31system.physmem.num_reads::realview.ide 6692 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 1245895 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 1051260 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 1053833 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 4005 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 3846 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 110971 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 1406308 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 8344 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 1533473 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 110971 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 110971 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1310708 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 1311109 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1310708 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 4005 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 3846 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 110971 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 1406708 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 8344 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 2844582 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 1245895 # Number of read requests accepted 55system.physmem.writeReqs 1053833 # Number of write requests accepted 56system.physmem.readBursts 1245895 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 1053833 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 79684928 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 52352 # Total number of bytes read from write queue 60system.physmem.bytesWritten 67299776 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 78715496 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 67301220 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 818 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 74822 # Per bank write bursts 67system.physmem.perBankRdBursts::1 82180 # Per bank write bursts 68system.physmem.perBankRdBursts::2 80987 # Per bank write bursts 69system.physmem.perBankRdBursts::3 75462 # Per bank write bursts 70system.physmem.perBankRdBursts::4 75477 # Per bank write bursts 71system.physmem.perBankRdBursts::5 80130 # Per bank write bursts 72system.physmem.perBankRdBursts::6 74577 # Per bank write bursts 73system.physmem.perBankRdBursts::7 72890 # Per bank write bursts 74system.physmem.perBankRdBursts::8 72311 # Per bank write bursts 75system.physmem.perBankRdBursts::9 102827 # Per bank write bursts 76system.physmem.perBankRdBursts::10 78128 # Per bank write bursts 77system.physmem.perBankRdBursts::11 79408 # Per bank write bursts 78system.physmem.perBankRdBursts::12 72963 # Per bank write bursts 79system.physmem.perBankRdBursts::13 76387 # Per bank write bursts 80system.physmem.perBankRdBursts::14 73944 # Per bank write bursts 81system.physmem.perBankRdBursts::15 72584 # Per bank write bursts 82system.physmem.perBankWrBursts::0 62047 # Per bank write bursts 83system.physmem.perBankWrBursts::1 68427 # Per bank write bursts 84system.physmem.perBankWrBursts::2 68519 # Per bank write bursts 85system.physmem.perBankWrBursts::3 66050 # Per bank write bursts 86system.physmem.perBankWrBursts::4 65357 # Per bank write bursts 87system.physmem.perBankWrBursts::5 67435 # Per bank write bursts 88system.physmem.perBankWrBursts::6 63960 # Per bank write bursts 89system.physmem.perBankWrBursts::7 63937 # Per bank write bursts 90system.physmem.perBankWrBursts::8 63039 # Per bank write bursts 91system.physmem.perBankWrBursts::9 70105 # Per bank write bursts 92system.physmem.perBankWrBursts::10 66227 # Per bank write bursts 93system.physmem.perBankWrBursts::11 68082 # Per bank write bursts 94system.physmem.perBankWrBursts::12 64306 # Per bank write bursts 95system.physmem.perBankWrBursts::13 66291 # Per bank write bursts 96system.physmem.perBankWrBursts::14 64522 # Per bank write bursts 97system.physmem.perBankWrBursts::15 63255 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 38 # Number of times write queue was full causing retry 100system.physmem.totGap 51331523357500 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 0 # Read request sizes (log2) 104system.physmem.readPktSize::3 13 # Read request sizes (log2) 105system.physmem.readPktSize::4 21272 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 1224610 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 1 # Write request sizes (log2) 111system.physmem.writePktSize::3 2572 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 1051260 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 635913 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 326498 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 150136 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 126962 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 653 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 548 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 549 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1209 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 762 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 332 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 367 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 192 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 170 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 133 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 125 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 133 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 110 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 86 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 71 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 11720 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 15352 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 33279 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 44422 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 54389 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 61870 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 62052 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 63406 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 64510 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 63581 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 65005 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 68339 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 65443 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 80751 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 86913 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 66052 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 69586 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 62814 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 2950 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 981 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 731 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 548 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 563 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 453 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 371 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 380 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 355 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 337 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 297 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 291 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 329 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 273 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 323 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 265 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 252 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 297 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 210 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 278 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 193 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 215 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 142 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 148 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 116 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 157 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 117 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 142 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 209 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 72 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 93 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 477001 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 308.142583 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 177.284446 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 336.100691 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 186993 39.20% 39.20% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 111432 23.36% 62.56% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 45372 9.51% 72.07% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 23464 4.92% 76.99% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 18197 3.81% 80.81% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 11652 2.44% 83.25% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 10522 2.21% 85.46% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 8218 1.72% 87.18% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 61151 12.82% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 477001 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 59594 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 20.891952 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 270.280066 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-2047 59591 99.99% 99.99% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::2048-4095 1 0.00% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::10240-12287 1 0.00% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::63488-65535 1 0.00% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::total 59594 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 59594 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 17.645384 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 16.994879 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 7.954134 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16-19 56960 95.58% 95.58% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::20-23 905 1.52% 97.10% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::24-27 37 0.06% 97.16% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::28-31 115 0.19% 97.35% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::32-35 18 0.03% 97.38% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::36-39 110 0.18% 97.57% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::40-43 195 0.33% 97.90% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::44-47 24 0.04% 97.94% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::48-51 355 0.60% 98.53% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::52-55 71 0.12% 98.65% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::56-59 24 0.04% 98.69% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::60-63 56 0.09% 98.79% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::64-67 280 0.47% 99.25% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::68-71 26 0.04% 99.30% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::72-75 33 0.06% 99.35% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::76-79 125 0.21% 99.56% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::80-83 203 0.34% 99.90% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::88-91 2 0.00% 99.91% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::96-99 3 0.01% 99.91% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::100-103 2 0.00% 99.92% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::104-107 1 0.00% 99.92% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::112-115 2 0.00% 99.92% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::116-119 1 0.00% 99.92% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::120-123 1 0.00% 99.92% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::124-127 1 0.00% 99.93% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::128-131 13 0.02% 99.95% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::132-135 1 0.00% 99.95% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::136-139 1 0.00% 99.95% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::140-143 8 0.01% 99.96% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::144-147 11 0.02% 99.98% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::148-151 2 0.00% 99.99% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::160-163 2 0.00% 99.99% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::176-179 1 0.00% 99.99% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::180-183 1 0.00% 100.00% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::192-195 1 0.00% 100.00% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::208-211 1 0.00% 100.00% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::total 59594 # Writes before turning the bus around for reads 275system.physmem.totQLat 31834686171 # Total ticks spent queuing 276system.physmem.totMemAccLat 55179879921 # Total ticks spent from burst creation until serviced by the DRAM 277system.physmem.totBusLat 6225385000 # Total ticks spent in databus transfers 278system.physmem.avgQLat 25568.45 # Average queueing delay per DRAM burst 279system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 280system.physmem.avgMemAccLat 44318.45 # Average memory access latency per DRAM burst 281system.physmem.avgRdBW 1.55 # Average DRAM read bandwidth in MiByte/s 282system.physmem.avgWrBW 1.31 # Average achieved write bandwidth in MiByte/s 283system.physmem.avgRdBWSys 1.53 # Average system read bandwidth in MiByte/s 284system.physmem.avgWrBWSys 1.31 # Average system write bandwidth in MiByte/s 285system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 286system.physmem.busUtil 0.02 # Data bus utilization in percentage 287system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 288system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 289system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing 290system.physmem.avgWrQLen 26.63 # Average write queue length when enqueuing 291system.physmem.readRowHits 1023243 # Number of row buffer hits during reads 292system.physmem.writeRowHits 796390 # Number of row buffer hits during writes 293system.physmem.readRowHitRate 82.18 # Row buffer hit rate for reads 294system.physmem.writeRowHitRate 75.73 # Row buffer hit rate for writes 295system.physmem.avgGap 22320693.30 # Average gap between requests 296system.physmem.pageHitRate 79.23 # Row buffer hit rate, read and write combined 297system.physmem_0.actEnergy 1817907840 # Energy for activate commands per rank (pJ) 298system.physmem_0.preEnergy 991914000 # Energy for precharge commands per rank (pJ) 299system.physmem_0.readEnergy 4808848200 # Energy for read commands per rank (pJ) 300system.physmem_0.writeEnergy 3406743360 # Energy for write commands per rank (pJ) 301system.physmem_0.refreshEnergy 3352725536160 # Energy for refresh commands per rank (pJ) 302system.physmem_0.actBackEnergy 1236862065645 # Energy for active background per rank (pJ) 303system.physmem_0.preBackEnergy 29713947077250 # Energy for precharge background per rank (pJ) 304system.physmem_0.totalEnergy 34314560092455 # Total energy per rank (pJ) 305system.physmem_0.averagePower 668.489031 # Core power per rank (mW) 306system.physmem_0.memoryStateTime::IDLE 49431665045810 # Time in different power states 307system.physmem_0.memoryStateTime::REF 1714072360000 # Time in different power states 308system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 309system.physmem_0.memoryStateTime::ACT 185786732190 # Time in different power states 310system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 311system.physmem_1.actEnergy 1788219720 # Energy for activate commands per rank (pJ) 312system.physmem_1.preEnergy 975715125 # Energy for precharge commands per rank (pJ) 313system.physmem_1.readEnergy 4902705600 # Energy for read commands per rank (pJ) 314system.physmem_1.writeEnergy 3407358960 # Energy for write commands per rank (pJ) 315system.physmem_1.refreshEnergy 3352725536160 # Energy for refresh commands per rank (pJ) 316system.physmem_1.actBackEnergy 1238749464465 # Energy for active background per rank (pJ) 317system.physmem_1.preBackEnergy 29712291456000 # Energy for precharge background per rank (pJ) 318system.physmem_1.totalEnergy 34314840456030 # Total energy per rank (pJ) 319system.physmem_1.averagePower 668.494493 # Core power per rank (mW) 320system.physmem_1.memoryStateTime::IDLE 49428877758086 # Time in different power states 321system.physmem_1.memoryStateTime::REF 1714072360000 # Time in different power states 322system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 323system.physmem_1.memoryStateTime::ACT 188572884414 # Time in different power states 324system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 325system.realview.nvmem.bytes_read::cpu.inst 384 # Number of bytes read from this memory 326system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 327system.realview.nvmem.bytes_read::total 420 # Number of bytes read from this memory 328system.realview.nvmem.bytes_inst_read::cpu.inst 384 # Number of instructions bytes read from this memory 329system.realview.nvmem.bytes_inst_read::total 384 # Number of instructions bytes read from this memory 330system.realview.nvmem.num_reads::cpu.inst 24 # Number of read requests responded to by this memory 331system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 332system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory 333system.realview.nvmem.bw_read::cpu.inst 7 # Total read bandwidth from this memory (bytes/s) 334system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 335system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) 336system.realview.nvmem.bw_inst_read::cpu.inst 7 # Instruction read bandwidth from this memory (bytes/s) 337system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) 338system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s) 339system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 340system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) 341system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 342system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 343system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 344system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 345system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 346system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 347system.cpu.branchPred.lookups 223870317 # Number of BP lookups 348system.cpu.branchPred.condPredicted 149571742 # Number of conditional branches predicted 349system.cpu.branchPred.condIncorrect 12183866 # Number of conditional branches incorrect 350system.cpu.branchPred.BTBLookups 157933845 # Number of BTB lookups 351system.cpu.branchPred.BTBHits 103250874 # Number of BTB hits 352system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 353system.cpu.branchPred.BTBHitPct 65.376028 # BTB Hit Percentage 354system.cpu.branchPred.usedRAS 30780710 # Number of times the RAS was used to get a target. 355system.cpu.branchPred.RASInCorrect 342883 # Number of incorrect RAS predictions. 356system.cpu_clk_domain.clock 500 # Clock period in ticks 357system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 358system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 359system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 360system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 361system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 362system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 363system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 364system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 365system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 366system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 367system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 368system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 369system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 370system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 371system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 372system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 373system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 374system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 375system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 376system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 377system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 378system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 379system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 380system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 381system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 382system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 383system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 384system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 385system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 386system.cpu.dtb.walker.walks 937088 # Table walker walks requested 387system.cpu.dtb.walker.walksLong 937088 # Table walker walks initiated with long descriptors 388system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15029 # Level at which table walker walks with long descriptors terminate 389system.cpu.dtb.walker.walksLongTerminationLevel::Level3 154587 # Level at which table walker walks with long descriptors terminate 390system.cpu.dtb.walker.walksSquashedBefore 427394 # Table walks squashed before starting 391system.cpu.dtb.walker.walkWaitTime::samples 509694 # Table walker wait (enqueue to first request) latency 392system.cpu.dtb.walker.walkWaitTime::mean 2223.932399 # Table walker wait (enqueue to first request) latency 393system.cpu.dtb.walker.walkWaitTime::stdev 14616.246492 # Table walker wait (enqueue to first request) latency 394system.cpu.dtb.walker.walkWaitTime::0-65535 506310 99.34% 99.34% # Table walker wait (enqueue to first request) latency 395system.cpu.dtb.walker.walkWaitTime::65536-131071 1920 0.38% 99.71% # Table walker wait (enqueue to first request) latency 396system.cpu.dtb.walker.walkWaitTime::131072-196607 988 0.19% 99.91% # Table walker wait (enqueue to first request) latency 397system.cpu.dtb.walker.walkWaitTime::196608-262143 199 0.04% 99.95% # Table walker wait (enqueue to first request) latency 398system.cpu.dtb.walker.walkWaitTime::262144-327679 148 0.03% 99.97% # Table walker wait (enqueue to first request) latency 399system.cpu.dtb.walker.walkWaitTime::327680-393215 28 0.01% 99.98% # Table walker wait (enqueue to first request) latency 400system.cpu.dtb.walker.walkWaitTime::393216-458751 46 0.01% 99.99% # Table walker wait (enqueue to first request) latency 401system.cpu.dtb.walker.walkWaitTime::458752-524287 49 0.01% 100.00% # Table walker wait (enqueue to first request) latency 402system.cpu.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency 403system.cpu.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 404system.cpu.dtb.walker.walkWaitTime::total 509694 # Table walker wait (enqueue to first request) latency 405system.cpu.dtb.walker.walkCompletionTime::samples 474748 # Table walker service (enqueue to completion) latency 406system.cpu.dtb.walker.walkCompletionTime::mean 23018.407660 # Table walker service (enqueue to completion) latency 407system.cpu.dtb.walker.walkCompletionTime::gmean 18045.301329 # Table walker service (enqueue to completion) latency 408system.cpu.dtb.walker.walkCompletionTime::stdev 20477.097679 # Table walker service (enqueue to completion) latency 409system.cpu.dtb.walker.walkCompletionTime::0-65535 463839 97.70% 97.70% # Table walker service (enqueue to completion) latency 410system.cpu.dtb.walker.walkCompletionTime::65536-131071 7714 1.62% 99.33% # Table walker service (enqueue to completion) latency 411system.cpu.dtb.walker.walkCompletionTime::131072-196607 2286 0.48% 99.81% # Table walker service (enqueue to completion) latency 412system.cpu.dtb.walker.walkCompletionTime::196608-262143 175 0.04% 99.85% # Table walker service (enqueue to completion) latency 413system.cpu.dtb.walker.walkCompletionTime::262144-327679 504 0.11% 99.95% # Table walker service (enqueue to completion) latency 414system.cpu.dtb.walker.walkCompletionTime::327680-393215 86 0.02% 99.97% # Table walker service (enqueue to completion) latency 415system.cpu.dtb.walker.walkCompletionTime::393216-458751 94 0.02% 99.99% # Table walker service (enqueue to completion) latency 416system.cpu.dtb.walker.walkCompletionTime::458752-524287 30 0.01% 100.00% # Table walker service (enqueue to completion) latency 417system.cpu.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 100.00% # Table walker service (enqueue to completion) latency 418system.cpu.dtb.walker.walkCompletionTime::589824-655359 8 0.00% 100.00% # Table walker service (enqueue to completion) latency 419system.cpu.dtb.walker.walkCompletionTime::720896-786431 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 420system.cpu.dtb.walker.walkCompletionTime::total 474748 # Table walker service (enqueue to completion) latency 421system.cpu.dtb.walker.walksPending::samples 784053971876 # Table walker pending requests distribution 422system.cpu.dtb.walker.walksPending::mean 0.725342 # Table walker pending requests distribution 423system.cpu.dtb.walker.walksPending::stdev 0.519550 # Table walker pending requests distribution 424system.cpu.dtb.walker.walksPending::0-1 781854829876 99.72% 99.72% # Table walker pending requests distribution 425system.cpu.dtb.walker.walksPending::2-3 1175747000 0.15% 99.87% # Table walker pending requests distribution 426system.cpu.dtb.walker.walksPending::4-5 476309500 0.06% 99.93% # Table walker pending requests distribution 427system.cpu.dtb.walker.walksPending::6-7 200437500 0.03% 99.96% # Table walker pending requests distribution 428system.cpu.dtb.walker.walksPending::8-9 146602500 0.02% 99.97% # Table walker pending requests distribution 429system.cpu.dtb.walker.walksPending::10-11 120332500 0.02% 99.99% # Table walker pending requests distribution 430system.cpu.dtb.walker.walksPending::12-13 25999000 0.00% 99.99% # Table walker pending requests distribution 431system.cpu.dtb.walker.walksPending::14-15 51086000 0.01% 100.00% # Table walker pending requests distribution 432system.cpu.dtb.walker.walksPending::16-17 2628000 0.00% 100.00% # Table walker pending requests distribution 433system.cpu.dtb.walker.walksPending::total 784053971876 # Table walker pending requests distribution 434system.cpu.dtb.walker.walkPageSizes::4K 154588 91.14% 91.14% # Table walker page sizes translated 435system.cpu.dtb.walker.walkPageSizes::2M 15029 8.86% 100.00% # Table walker page sizes translated 436system.cpu.dtb.walker.walkPageSizes::total 169617 # Table walker page sizes translated 437system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 937088 # Table walker requests started/completed, data/inst 438system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 439system.cpu.dtb.walker.walkRequestOrigin_Requested::total 937088 # Table walker requests started/completed, data/inst 440system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 169617 # Table walker requests started/completed, data/inst 441system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 442system.cpu.dtb.walker.walkRequestOrigin_Completed::total 169617 # Table walker requests started/completed, data/inst 443system.cpu.dtb.walker.walkRequestOrigin::total 1106705 # Table walker requests started/completed, data/inst 444system.cpu.dtb.inst_hits 0 # ITB inst hits 445system.cpu.dtb.inst_misses 0 # ITB inst misses 446system.cpu.dtb.read_hits 169133397 # DTB read hits 447system.cpu.dtb.read_misses 670096 # DTB read misses 448system.cpu.dtb.write_hits 147221017 # DTB write hits 449system.cpu.dtb.write_misses 266992 # DTB write misses 450system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed 451system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 452system.cpu.dtb.flush_tlb_mva_asid 39151 # Number of times TLB was flushed by MVA & ASID 453system.cpu.dtb.flush_tlb_asid 1017 # Number of times TLB was flushed by ASID 454system.cpu.dtb.flush_entries 71818 # Number of entries that have been flushed from TLB 455system.cpu.dtb.align_faults 99 # Number of TLB faults due to alignment restrictions 456system.cpu.dtb.prefetch_faults 9972 # Number of TLB faults due to prefetch 457system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 458system.cpu.dtb.perms_faults 69741 # Number of TLB faults due to permissions restrictions 459system.cpu.dtb.read_accesses 169803493 # DTB read accesses 460system.cpu.dtb.write_accesses 147488009 # DTB write accesses 461system.cpu.dtb.inst_accesses 0 # ITB inst accesses 462system.cpu.dtb.hits 316354414 # DTB hits 463system.cpu.dtb.misses 937088 # DTB misses 464system.cpu.dtb.accesses 317291502 # DTB accesses 465system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 466system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 467system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 468system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 469system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 470system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 471system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 472system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 473system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 474system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 475system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 476system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 477system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 478system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 479system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 480system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 481system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 482system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 483system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 484system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 485system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 486system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 487system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 488system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 489system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 490system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 491system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 492system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 493system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 494system.cpu.itb.walker.walks 160983 # Table walker walks requested 495system.cpu.itb.walker.walksLong 160983 # Table walker walks initiated with long descriptors 496system.cpu.itb.walker.walksLongTerminationLevel::Level2 1438 # Level at which table walker walks with long descriptors terminate 497system.cpu.itb.walker.walksLongTerminationLevel::Level3 121478 # Level at which table walker walks with long descriptors terminate 498system.cpu.itb.walker.walksSquashedBefore 17520 # Table walks squashed before starting 499system.cpu.itb.walker.walkWaitTime::samples 143463 # Table walker wait (enqueue to first request) latency 500system.cpu.itb.walker.walkWaitTime::mean 1273.722144 # Table walker wait (enqueue to first request) latency 501system.cpu.itb.walker.walkWaitTime::stdev 9463.659088 # Table walker wait (enqueue to first request) latency 502system.cpu.itb.walker.walkWaitTime::0-32767 142472 99.31% 99.31% # Table walker wait (enqueue to first request) latency 503system.cpu.itb.walker.walkWaitTime::32768-65535 574 0.40% 99.71% # Table walker wait (enqueue to first request) latency 504system.cpu.itb.walker.walkWaitTime::65536-98303 44 0.03% 99.74% # Table walker wait (enqueue to first request) latency 505system.cpu.itb.walker.walkWaitTime::98304-131071 82 0.06% 99.80% # Table walker wait (enqueue to first request) latency 506system.cpu.itb.walker.walkWaitTime::131072-163839 231 0.16% 99.96% # Table walker wait (enqueue to first request) latency 507system.cpu.itb.walker.walkWaitTime::163840-196607 26 0.02% 99.98% # Table walker wait (enqueue to first request) latency 508system.cpu.itb.walker.walkWaitTime::196608-229375 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency 509system.cpu.itb.walker.walkWaitTime::229376-262143 4 0.00% 99.98% # Table walker wait (enqueue to first request) latency 510system.cpu.itb.walker.walkWaitTime::262144-294911 15 0.01% 99.99% # Table walker wait (enqueue to first request) latency 511system.cpu.itb.walker.walkWaitTime::294912-327679 5 0.00% 99.99% # Table walker wait (enqueue to first request) latency 512system.cpu.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 513system.cpu.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 514system.cpu.itb.walker.walkWaitTime::393216-425983 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 515system.cpu.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 516system.cpu.itb.walker.walkWaitTime::total 143463 # Table walker wait (enqueue to first request) latency 517system.cpu.itb.walker.walkCompletionTime::samples 140436 # Table walker service (enqueue to completion) latency 518system.cpu.itb.walker.walkCompletionTime::mean 29061.341109 # Table walker service (enqueue to completion) latency 519system.cpu.itb.walker.walkCompletionTime::gmean 24320.215707 # Table walker service (enqueue to completion) latency 520system.cpu.itb.walker.walkCompletionTime::stdev 22395.663440 # Table walker service (enqueue to completion) latency 521system.cpu.itb.walker.walkCompletionTime::0-65535 137485 97.90% 97.90% # Table walker service (enqueue to completion) latency 522system.cpu.itb.walker.walkCompletionTime::65536-131071 845 0.60% 98.50% # Table walker service (enqueue to completion) latency 523system.cpu.itb.walker.walkCompletionTime::131072-196607 1830 1.30% 99.80% # Table walker service (enqueue to completion) latency 524system.cpu.itb.walker.walkCompletionTime::196608-262143 92 0.07% 99.87% # Table walker service (enqueue to completion) latency 525system.cpu.itb.walker.walkCompletionTime::262144-327679 113 0.08% 99.95% # Table walker service (enqueue to completion) latency 526system.cpu.itb.walker.walkCompletionTime::327680-393215 31 0.02% 99.97% # Table walker service (enqueue to completion) latency 527system.cpu.itb.walker.walkCompletionTime::393216-458751 34 0.02% 100.00% # Table walker service (enqueue to completion) latency 528system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 529system.cpu.itb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 530system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 531system.cpu.itb.walker.walkCompletionTime::total 140436 # Table walker service (enqueue to completion) latency 532system.cpu.itb.walker.walksPending::samples 672381692680 # Table walker pending requests distribution 533system.cpu.itb.walker.walksPending::mean 0.944059 # Table walker pending requests distribution 534system.cpu.itb.walker.walksPending::stdev 0.230149 # Table walker pending requests distribution 535system.cpu.itb.walker.walksPending::0 37665306856 5.60% 5.60% # Table walker pending requests distribution 536system.cpu.itb.walker.walksPending::1 634665708824 94.39% 99.99% # Table walker pending requests distribution 537system.cpu.itb.walker.walksPending::2 49644500 0.01% 100.00% # Table walker pending requests distribution 538system.cpu.itb.walker.walksPending::3 1013500 0.00% 100.00% # Table walker pending requests distribution 539system.cpu.itb.walker.walksPending::4 19000 0.00% 100.00% # Table walker pending requests distribution 540system.cpu.itb.walker.walksPending::total 672381692680 # Table walker pending requests distribution 541system.cpu.itb.walker.walkPageSizes::4K 121478 98.83% 98.83% # Table walker page sizes translated 542system.cpu.itb.walker.walkPageSizes::2M 1438 1.17% 100.00% # Table walker page sizes translated 543system.cpu.itb.walker.walkPageSizes::total 122916 # Table walker page sizes translated 544system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 545system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 160983 # Table walker requests started/completed, data/inst 546system.cpu.itb.walker.walkRequestOrigin_Requested::total 160983 # Table walker requests started/completed, data/inst 547system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 548system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 122916 # Table walker requests started/completed, data/inst 549system.cpu.itb.walker.walkRequestOrigin_Completed::total 122916 # Table walker requests started/completed, data/inst 550system.cpu.itb.walker.walkRequestOrigin::total 283899 # Table walker requests started/completed, data/inst 551system.cpu.itb.inst_hits 355891670 # ITB inst hits 552system.cpu.itb.inst_misses 160983 # ITB inst misses 553system.cpu.itb.read_hits 0 # DTB read hits 554system.cpu.itb.read_misses 0 # DTB read misses 555system.cpu.itb.write_hits 0 # DTB write hits 556system.cpu.itb.write_misses 0 # DTB write misses 557system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed 558system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 559system.cpu.itb.flush_tlb_mva_asid 39151 # Number of times TLB was flushed by MVA & ASID 560system.cpu.itb.flush_tlb_asid 1017 # Number of times TLB was flushed by ASID 561system.cpu.itb.flush_entries 52900 # Number of entries that have been flushed from TLB 562system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 563system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 564system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 565system.cpu.itb.perms_faults 368990 # Number of TLB faults due to permissions restrictions 566system.cpu.itb.read_accesses 0 # DTB read accesses 567system.cpu.itb.write_accesses 0 # DTB write accesses 568system.cpu.itb.inst_accesses 356052653 # ITB inst accesses 569system.cpu.itb.hits 355891670 # DTB hits 570system.cpu.itb.misses 160983 # DTB misses 571system.cpu.itb.accesses 356052653 # DTB accesses 572system.cpu.numCycles 1641618102 # number of cpu cycles simulated 573system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 574system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 575system.cpu.fetch.icacheStallCycles 643295277 # Number of cycles fetch is stalled on an Icache miss 576system.cpu.fetch.Insts 998912988 # Number of instructions fetch has processed 577system.cpu.fetch.Branches 223870317 # Number of branches that fetch encountered 578system.cpu.fetch.predictedBranches 134031584 # Number of branches that fetch has predicted taken 579system.cpu.fetch.Cycles 911548920 # Number of cycles fetch has run and was not squashing or blocked 580system.cpu.fetch.SquashCycles 26021190 # Number of cycles fetch has spent squashing 581system.cpu.fetch.TlbCycles 3814569 # Number of cycles fetch has spent waiting for tlb 582system.cpu.fetch.MiscStallCycles 28072 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 583system.cpu.fetch.PendingTrapStallCycles 9294541 # Number of stall cycles due to pending traps 584system.cpu.fetch.PendingQuiesceStallCycles 1045994 # Number of stall cycles due to pending quiesce instructions 585system.cpu.fetch.IcacheWaitRetryStallCycles 928 # Number of stall cycles due to full MSHR 586system.cpu.fetch.CacheLines 355505947 # Number of cache lines fetched 587system.cpu.fetch.IcacheSquashes 6091455 # Number of outstanding Icache misses that were squashed 588system.cpu.fetch.ItlbSquashes 48555 # Number of outstanding ITLB misses that were squashed 589system.cpu.fetch.rateDist::samples 1582038896 # Number of instructions fetched each cycle (Total) 590system.cpu.fetch.rateDist::mean 0.739816 # Number of instructions fetched each cycle (Total) 591system.cpu.fetch.rateDist::stdev 1.145969 # Number of instructions fetched each cycle (Total) 592system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 593system.cpu.fetch.rateDist::0 1026150412 64.86% 64.86% # Number of instructions fetched each cycle (Total) 594system.cpu.fetch.rateDist::1 213368743 13.49% 78.35% # Number of instructions fetched each cycle (Total) 595system.cpu.fetch.rateDist::2 70509493 4.46% 82.81% # Number of instructions fetched each cycle (Total) 596system.cpu.fetch.rateDist::3 272010248 17.19% 100.00% # Number of instructions fetched each cycle (Total) 597system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 598system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 599system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 600system.cpu.fetch.rateDist::total 1582038896 # Number of instructions fetched each cycle (Total) 601system.cpu.fetch.branchRate 0.136372 # Number of branch fetches per cycle 602system.cpu.fetch.rate 0.608493 # Number of inst fetches per cycle 603system.cpu.decode.IdleCycles 523526038 # Number of cycles decode is idle 604system.cpu.decode.BlockedCycles 567332242 # Number of cycles decode is blocked 605system.cpu.decode.RunCycles 432225078 # Number of cycles decode is running 606system.cpu.decode.UnblockCycles 49743606 # Number of cycles decode is unblocking 607system.cpu.decode.SquashCycles 9211932 # Number of cycles decode is squashing 608system.cpu.decode.BranchResolved 33585206 # Number of times decode resolved a branch 609system.cpu.decode.BranchMispred 3858658 # Number of times decode detected a branch misprediction 610system.cpu.decode.DecodedInsts 1082487330 # Number of instructions handled by decode 611system.cpu.decode.SquashedInsts 28953315 # Number of squashed instructions handled by decode 612system.cpu.rename.SquashCycles 9211932 # Number of cycles rename is squashing 613system.cpu.rename.IdleCycles 568013928 # Number of cycles rename is idle 614system.cpu.rename.BlockCycles 68659821 # Number of cycles rename is blocking 615system.cpu.rename.serializeStallCycles 370106883 # count of cycles rename stalled for serializing inst 616system.cpu.rename.RunCycles 437449183 # Number of cycles rename is running 617system.cpu.rename.UnblockCycles 128597149 # Number of cycles rename is unblocking 618system.cpu.rename.RenamedInsts 1062778939 # Number of instructions processed by rename 619system.cpu.rename.SquashedInsts 6765759 # Number of squashed instructions processed by rename 620system.cpu.rename.ROBFullEvents 5100330 # Number of times rename has blocked due to ROB full 621system.cpu.rename.IQFullEvents 330196 # Number of times rename has blocked due to IQ full 622system.cpu.rename.LQFullEvents 669001 # Number of times rename has blocked due to LQ full 623system.cpu.rename.SQFullEvents 77613497 # Number of times rename has blocked due to SQ full 624system.cpu.rename.FullRegisterEvents 20248 # Number of times there has been no free registers 625system.cpu.rename.RenamedOperands 1010589647 # Number of destination operands rename has renamed 626system.cpu.rename.RenameLookups 1636490834 # Number of register rename lookups that rename has made 627system.cpu.rename.int_rename_lookups 1256895335 # Number of integer rename lookups 628system.cpu.rename.fp_rename_lookups 1474103 # Number of floating rename lookups 629system.cpu.rename.CommittedMaps 945145868 # Number of HB maps that are committed 630system.cpu.rename.UndoneMaps 65443776 # Number of HB maps that are undone due to squashing 631system.cpu.rename.serializingInsts 26770566 # count of serializing insts renamed 632system.cpu.rename.tempSerializingInsts 23114475 # count of temporary serializing insts renamed 633system.cpu.rename.skidInsts 102068123 # count of insts added to the skid buffer 634system.cpu.memDep0.insertedLoads 173157157 # Number of loads inserted to the mem dependence unit. 635system.cpu.memDep0.insertedStores 150776419 # Number of stores inserted to the mem dependence unit. 636system.cpu.memDep0.conflictingLoads 9868164 # Number of conflicting loads. 637system.cpu.memDep0.conflictingStores 9014634 # Number of conflicting stores. 638system.cpu.iq.iqInstsAdded 1027918827 # Number of instructions added to the IQ (excludes non-spec) 639system.cpu.iq.iqNonSpecInstsAdded 27065451 # Number of non-speculative instructions added to the IQ 640system.cpu.iq.iqInstsIssued 1043272281 # Number of instructions issued 641system.cpu.iq.iqSquashedInstsIssued 3272960 # Number of squashed instructions issued 642system.cpu.iq.iqSquashedInstsExamined 60330213 # Number of squashed instructions iterated over during squash; mainly for profiling 643system.cpu.iq.iqSquashedOperandsExamined 33600804 # Number of squashed operands that are examined and possibly removed from graph 644system.cpu.iq.iqSquashedNonSpecRemoved 313388 # Number of squashed non-spec instructions that were removed 645system.cpu.iq.issued_per_cycle::samples 1582038896 # Number of insts issued each cycle 646system.cpu.iq.issued_per_cycle::mean 0.659448 # Number of insts issued each cycle 647system.cpu.iq.issued_per_cycle::stdev 0.917899 # Number of insts issued each cycle 648system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 649system.cpu.iq.issued_per_cycle::0 936232713 59.18% 59.18% # Number of insts issued each cycle 650system.cpu.iq.issued_per_cycle::1 333194737 21.06% 80.24% # Number of insts issued each cycle 651system.cpu.iq.issued_per_cycle::2 234236353 14.81% 95.05% # Number of insts issued each cycle 652system.cpu.iq.issued_per_cycle::3 71914703 4.55% 99.59% # Number of insts issued each cycle 653system.cpu.iq.issued_per_cycle::4 6441221 0.41% 100.00% # Number of insts issued each cycle 654system.cpu.iq.issued_per_cycle::5 19169 0.00% 100.00% # Number of insts issued each cycle 655system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 656system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 657system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 658system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 659system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 660system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 661system.cpu.iq.issued_per_cycle::total 1582038896 # Number of insts issued each cycle 662system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 663system.cpu.iq.fu_full::IntAlu 57633129 35.05% 35.05% # attempts to use FU when none available 664system.cpu.iq.fu_full::IntMult 100179 0.06% 35.11% # attempts to use FU when none available 665system.cpu.iq.fu_full::IntDiv 26746 0.02% 35.12% # attempts to use FU when none available 666system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.12% # attempts to use FU when none available 667system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.12% # attempts to use FU when none available 668system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.12% # attempts to use FU when none available 669system.cpu.iq.fu_full::FloatMult 0 0.00% 35.12% # attempts to use FU when none available 670system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.12% # attempts to use FU when none available 671system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.12% # attempts to use FU when none available 672system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.12% # attempts to use FU when none available 673system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.12% # attempts to use FU when none available 674system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.12% # attempts to use FU when none available 675system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.12% # attempts to use FU when none available 676system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.12% # attempts to use FU when none available 677system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.12% # attempts to use FU when none available 678system.cpu.iq.fu_full::SimdMult 0 0.00% 35.12% # attempts to use FU when none available 679system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.12% # attempts to use FU when none available 680system.cpu.iq.fu_full::SimdShift 0 0.00% 35.12% # attempts to use FU when none available 681system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.12% # attempts to use FU when none available 682system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.12% # attempts to use FU when none available 683system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.12% # attempts to use FU when none available 684system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.12% # attempts to use FU when none available 685system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.12% # attempts to use FU when none available 686system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.12% # attempts to use FU when none available 687system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.12% # attempts to use FU when none available 688system.cpu.iq.fu_full::SimdFloatMisc 783 0.00% 35.13% # attempts to use FU when none available 689system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.13% # attempts to use FU when none available 690system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.13% # attempts to use FU when none available 691system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.13% # attempts to use FU when none available 692system.cpu.iq.fu_full::MemRead 44218992 26.89% 62.02% # attempts to use FU when none available 693system.cpu.iq.fu_full::MemWrite 62461837 37.98% 100.00% # attempts to use FU when none available 694system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 695system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 696system.cpu.iq.FU_type_0::No_OpClass 21 0.00% 0.00% # Type of FU issued 697system.cpu.iq.FU_type_0::IntAlu 718385578 68.86% 68.86% # Type of FU issued 698system.cpu.iq.FU_type_0::IntMult 2533352 0.24% 69.10% # Type of FU issued 699system.cpu.iq.FU_type_0::IntDiv 122770 0.01% 69.11% # Type of FU issued 700system.cpu.iq.FU_type_0::FloatAdd 382 0.00% 69.11% # Type of FU issued 701system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.11% # Type of FU issued 702system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.11% # Type of FU issued 703system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.11% # Type of FU issued 704system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 69.11% # Type of FU issued 705system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 69.11% # Type of FU issued 706system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 69.11% # Type of FU issued 707system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 69.11% # Type of FU issued 708system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 69.11% # Type of FU issued 709system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 69.11% # Type of FU issued 710system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 69.11% # Type of FU issued 711system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 69.11% # Type of FU issued 712system.cpu.iq.FU_type_0::SimdMult 0 0.00% 69.11% # Type of FU issued 713system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 69.11% # Type of FU issued 714system.cpu.iq.FU_type_0::SimdShift 0 0.00% 69.11% # Type of FU issued 715system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.11% # Type of FU issued 716system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 69.11% # Type of FU issued 717system.cpu.iq.FU_type_0::SimdFloatAdd 8 0.00% 69.11% # Type of FU issued 718system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.11% # Type of FU issued 719system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.11% # Type of FU issued 720system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.11% # Type of FU issued 721system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.11% # Type of FU issued 722system.cpu.iq.FU_type_0::SimdFloatMisc 121248 0.01% 69.13% # Type of FU issued 723system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued 724system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued 725system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued 726system.cpu.iq.FU_type_0::MemRead 173007895 16.58% 85.71% # Type of FU issued 727system.cpu.iq.FU_type_0::MemWrite 149100989 14.29% 100.00% # Type of FU issued 728system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 729system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 730system.cpu.iq.FU_type_0::total 1043272281 # Type of FU issued 731system.cpu.iq.rate 0.635515 # Inst issue rate 732system.cpu.iq.fu_busy_cnt 164441666 # FU busy when requested 733system.cpu.iq.fu_busy_rate 0.157621 # FU busy rate (busy events/executed inst) 734system.cpu.iq.int_inst_queue_reads 3833820592 # Number of integer instruction queue reads 735system.cpu.iq.int_inst_queue_writes 1114508942 # Number of integer instruction queue writes 736system.cpu.iq.int_inst_queue_wakeup_accesses 1025374913 # Number of integer instruction queue wakeup accesses 737system.cpu.iq.fp_inst_queue_reads 2477491 # Number of floating instruction queue reads 738system.cpu.iq.fp_inst_queue_writes 947894 # Number of floating instruction queue writes 739system.cpu.iq.fp_inst_queue_wakeup_accesses 909947 # Number of floating instruction queue wakeup accesses 740system.cpu.iq.int_alu_accesses 1206157308 # Number of integer alu accesses 741system.cpu.iq.fp_alu_accesses 1556618 # Number of floating point alu accesses 742system.cpu.iew.lsq.thread0.forwLoads 4301219 # Number of loads that had data forwarded from stores 743system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 744system.cpu.iew.lsq.thread0.squashedLoads 13765356 # Number of loads squashed 745system.cpu.iew.lsq.thread0.ignoredResponses 14482 # Number of memory responses ignored because the instruction is squashed 746system.cpu.iew.lsq.thread0.memOrderViolation 143653 # Number of memory ordering violations 747system.cpu.iew.lsq.thread0.squashedStores 6293913 # Number of stores squashed 748system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 749system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 750system.cpu.iew.lsq.thread0.rescheduledLoads 2526650 # Number of loads that were rescheduled 751system.cpu.iew.lsq.thread0.cacheBlocked 1543650 # Number of times an access to memory failed due to the cache being blocked 752system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 753system.cpu.iew.iewSquashCycles 9211932 # Number of cycles IEW is squashing 754system.cpu.iew.iewBlockCycles 6884950 # Number of cycles IEW is blocking 755system.cpu.iew.iewUnblockCycles 9078435 # Number of cycles IEW is unblocking 756system.cpu.iew.iewDispatchedInsts 1055205514 # Number of instructions dispatched to IQ 757system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 758system.cpu.iew.iewDispLoadInsts 173157157 # Number of dispatched load instructions 759system.cpu.iew.iewDispStoreInsts 150776419 # Number of dispatched store instructions 760system.cpu.iew.iewDispNonSpecInsts 22691259 # Number of dispatched non-speculative instructions 761system.cpu.iew.iewIQFullEvents 56491 # Number of times the IQ has become full, causing a stall 762system.cpu.iew.iewLSQFullEvents 8949926 # Number of times the LSQ has become full, causing a stall 763system.cpu.iew.memOrderViolationEvents 143653 # Number of memory order violations 764system.cpu.iew.predictedTakenIncorrect 3653003 # Number of branches that were predicted taken incorrectly 765system.cpu.iew.predictedNotTakenIncorrect 5096400 # Number of branches that were predicted not taken incorrectly 766system.cpu.iew.branchMispredicts 8749403 # Number of branch mispredicts detected at execute 767system.cpu.iew.iewExecutedInsts 1032130630 # Number of executed instructions 768system.cpu.iew.iewExecLoadInsts 169121119 # Number of load instructions executed 769system.cpu.iew.iewExecSquashedInsts 10215406 # Number of squashed instructions skipped in execute 770system.cpu.iew.exec_swp 0 # number of swp insts executed 771system.cpu.iew.exec_nop 221236 # number of nop insts executed 772system.cpu.iew.exec_refs 316337352 # number of memory reference insts executed 773system.cpu.iew.exec_branches 195829859 # Number of branches executed 774system.cpu.iew.exec_stores 147216233 # Number of stores executed 775system.cpu.iew.exec_rate 0.628728 # Inst execution rate 776system.cpu.iew.wb_sent 1027090277 # cumulative count of insts sent to commit 777system.cpu.iew.wb_count 1026284860 # cumulative count of insts written-back 778system.cpu.iew.wb_producers 436833707 # num instructions producing a value 779system.cpu.iew.wb_consumers 706462159 # num instructions consuming a value 780system.cpu.iew.wb_rate 0.625167 # insts written-back per cycle 781system.cpu.iew.wb_fanout 0.618340 # average fanout of values written-back 782system.cpu.commit.commitSquashedInsts 51246502 # The number of squashed insts skipped by commit 783system.cpu.commit.commitNonSpecStalls 26752063 # The number of times commit has been forced to stall to communicate backwards 784system.cpu.commit.branchMispredicts 8385203 # The number of times a branch was mispredicted 785system.cpu.commit.committed_per_cycle::samples 1570087734 # Number of insts commited each cycle 786system.cpu.commit.committed_per_cycle::mean 0.633502 # Number of insts commited each cycle 787system.cpu.commit.committed_per_cycle::stdev 1.269814 # Number of insts commited each cycle 788system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 789system.cpu.commit.committed_per_cycle::0 1059518127 67.48% 67.48% # Number of insts commited each cycle 790system.cpu.commit.committed_per_cycle::1 287046411 18.28% 85.76% # Number of insts commited each cycle 791system.cpu.commit.committed_per_cycle::2 120236472 7.66% 93.42% # Number of insts commited each cycle 792system.cpu.commit.committed_per_cycle::3 36451838 2.32% 95.74% # Number of insts commited each cycle 793system.cpu.commit.committed_per_cycle::4 28385212 1.81% 97.55% # Number of insts commited each cycle 794system.cpu.commit.committed_per_cycle::5 13987217 0.89% 98.44% # Number of insts commited each cycle 795system.cpu.commit.committed_per_cycle::6 8615612 0.55% 98.99% # Number of insts commited each cycle 796system.cpu.commit.committed_per_cycle::7 4166173 0.27% 99.26% # Number of insts commited each cycle 797system.cpu.commit.committed_per_cycle::8 11680672 0.74% 100.00% # Number of insts commited each cycle 798system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 799system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 800system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 801system.cpu.commit.committed_per_cycle::total 1570087734 # Number of insts commited each cycle 802system.cpu.commit.committedInsts 846524467 # Number of instructions committed 803system.cpu.commit.committedOps 994654061 # Number of ops (including micro ops) committed 804system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 805system.cpu.commit.refs 303874306 # Number of memory references committed 806system.cpu.commit.loads 159391800 # Number of loads committed 807system.cpu.commit.membars 6909679 # Number of memory barriers committed 808system.cpu.commit.branches 188935778 # Number of branches committed 809system.cpu.commit.fp_insts 896706 # Number of committed floating point instructions. 810system.cpu.commit.int_insts 913907111 # Number of committed integer instructions. 811system.cpu.commit.function_calls 25250179 # Number of function calls committed. 812system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 813system.cpu.commit.op_class_0::IntAlu 688421836 69.21% 69.21% # Class of committed instruction 814system.cpu.commit.op_class_0::IntMult 2147861 0.22% 69.43% # Class of committed instruction 815system.cpu.commit.op_class_0::IntDiv 98019 0.01% 69.44% # Class of committed instruction 816system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.44% # Class of committed instruction 817system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.44% # Class of committed instruction 818system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.44% # Class of committed instruction 819system.cpu.commit.op_class_0::FloatMult 0 0.00% 69.44% # Class of committed instruction 820system.cpu.commit.op_class_0::FloatDiv 0 0.00% 69.44% # Class of committed instruction 821system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 69.44% # Class of committed instruction 822system.cpu.commit.op_class_0::SimdAdd 0 0.00% 69.44% # Class of committed instruction 823system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 69.44% # Class of committed instruction 824system.cpu.commit.op_class_0::SimdAlu 0 0.00% 69.44% # Class of committed instruction 825system.cpu.commit.op_class_0::SimdCmp 0 0.00% 69.44% # Class of committed instruction 826system.cpu.commit.op_class_0::SimdCvt 0 0.00% 69.44% # Class of committed instruction 827system.cpu.commit.op_class_0::SimdMisc 0 0.00% 69.44% # Class of committed instruction 828system.cpu.commit.op_class_0::SimdMult 0 0.00% 69.44% # Class of committed instruction 829system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 69.44% # Class of committed instruction 830system.cpu.commit.op_class_0::SimdShift 0 0.00% 69.44% # Class of committed instruction 831system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 69.44% # Class of committed instruction 832system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 69.44% # Class of committed instruction 833system.cpu.commit.op_class_0::SimdFloatAdd 8 0.00% 69.44% # Class of committed instruction 834system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.44% # Class of committed instruction 835system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.44% # Class of committed instruction 836system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.44% # Class of committed instruction 837system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.44% # Class of committed instruction 838system.cpu.commit.op_class_0::SimdFloatMisc 111997 0.01% 69.45% # Class of committed instruction 839system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.45% # Class of committed instruction 840system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.45% # Class of committed instruction 841system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.45% # Class of committed instruction 842system.cpu.commit.op_class_0::MemRead 159391800 16.02% 85.47% # Class of committed instruction 843system.cpu.commit.op_class_0::MemWrite 144482506 14.53% 100.00% # Class of committed instruction 844system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 845system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 846system.cpu.commit.op_class_0::total 994654061 # Class of committed instruction 847system.cpu.commit.bw_lim_events 11680672 # number cycles where commit BW limit reached 848system.cpu.rob.rob_reads 2596784081 # The number of ROB reads 849system.cpu.rob.rob_writes 2103659595 # The number of ROB writes 850system.cpu.timesIdled 8144337 # Number of times that the entire CPU went into an idle state and unscheduled itself 851system.cpu.idleCycles 59579206 # Total number of cycles that the CPU has spent unscheduled due to idling 852system.cpu.quiesceCycles 101021431570 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 853system.cpu.committedInsts 846524467 # Number of Instructions Simulated 854system.cpu.committedOps 994654061 # Number of Ops (including micro ops) Simulated 855system.cpu.cpi 1.939245 # CPI: Cycles Per Instruction 856system.cpu.cpi_total 1.939245 # CPI: Total CPI of All Threads 857system.cpu.ipc 0.515665 # IPC: Instructions Per Cycle 858system.cpu.ipc_total 0.515665 # IPC: Total IPC of All Threads 859system.cpu.int_regfile_reads 1221742987 # number of integer regfile reads 860system.cpu.int_regfile_writes 729786392 # number of integer regfile writes 861system.cpu.fp_regfile_reads 1462559 # number of floating regfile reads 862system.cpu.fp_regfile_writes 782552 # number of floating regfile writes 863system.cpu.cc_regfile_reads 224594796 # number of cc regfile reads 864system.cpu.cc_regfile_writes 225242859 # number of cc regfile writes 865system.cpu.misc_regfile_reads 2567204891 # number of misc regfile reads 866system.cpu.misc_regfile_writes 26785378 # number of misc regfile writes 867system.cpu.dcache.tags.replacements 9653571 # number of replacements 868system.cpu.dcache.tags.tagsinuse 511.972798 # Cycle average of tags in use 869system.cpu.dcache.tags.total_refs 282643774 # Total number of references to valid blocks. 870system.cpu.dcache.tags.sampled_refs 9654083 # Sample count of references to valid blocks. 871system.cpu.dcache.tags.avg_refs 29.277123 # Average number of references to valid blocks. 872system.cpu.dcache.tags.warmup_cycle 2743199500 # Cycle when the warmup percentage was hit. 873system.cpu.dcache.tags.occ_blocks::cpu.data 511.972798 # Average occupied blocks per requestor 874system.cpu.dcache.tags.occ_percent::cpu.data 0.999947 # Average percentage of cache occupancy 875system.cpu.dcache.tags.occ_percent::total 0.999947 # Average percentage of cache occupancy 876system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 877system.cpu.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id 878system.cpu.dcache.tags.age_task_id_blocks_1024::1 381 # Occupied blocks per task id 879system.cpu.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id 880system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 881system.cpu.dcache.tags.tag_accesses 1234280358 # Number of tag accesses 882system.cpu.dcache.tags.data_accesses 1234280358 # Number of data accesses 883system.cpu.dcache.ReadReq_hits::cpu.data 146896386 # number of ReadReq hits 884system.cpu.dcache.ReadReq_hits::total 146896386 # number of ReadReq hits 885system.cpu.dcache.WriteReq_hits::cpu.data 128038519 # number of WriteReq hits 886system.cpu.dcache.WriteReq_hits::total 128038519 # number of WriteReq hits 887system.cpu.dcache.SoftPFReq_hits::cpu.data 377527 # number of SoftPFReq hits 888system.cpu.dcache.SoftPFReq_hits::total 377527 # number of SoftPFReq hits 889system.cpu.dcache.WriteLineReq_hits::cpu.data 324244 # number of WriteLineReq hits 890system.cpu.dcache.WriteLineReq_hits::total 324244 # number of WriteLineReq hits 891system.cpu.dcache.LoadLockedReq_hits::cpu.data 3284324 # number of LoadLockedReq hits 892system.cpu.dcache.LoadLockedReq_hits::total 3284324 # number of LoadLockedReq hits 893system.cpu.dcache.StoreCondReq_hits::cpu.data 3679077 # number of StoreCondReq hits 894system.cpu.dcache.StoreCondReq_hits::total 3679077 # number of StoreCondReq hits 895system.cpu.dcache.demand_hits::cpu.data 274934905 # number of demand (read+write) hits 896system.cpu.dcache.demand_hits::total 274934905 # number of demand (read+write) hits 897system.cpu.dcache.overall_hits::cpu.data 275312432 # number of overall hits 898system.cpu.dcache.overall_hits::total 275312432 # number of overall hits 899system.cpu.dcache.ReadReq_misses::cpu.data 9519580 # number of ReadReq misses 900system.cpu.dcache.ReadReq_misses::total 9519580 # number of ReadReq misses 901system.cpu.dcache.WriteReq_misses::cpu.data 11197407 # number of WriteReq misses 902system.cpu.dcache.WriteReq_misses::total 11197407 # number of WriteReq misses 903system.cpu.dcache.SoftPFReq_misses::cpu.data 1162034 # number of SoftPFReq misses 904system.cpu.dcache.SoftPFReq_misses::total 1162034 # number of SoftPFReq misses 905system.cpu.dcache.WriteLineReq_misses::cpu.data 1231431 # number of WriteLineReq misses 906system.cpu.dcache.WriteLineReq_misses::total 1231431 # number of WriteLineReq misses 907system.cpu.dcache.LoadLockedReq_misses::cpu.data 446029 # number of LoadLockedReq misses 908system.cpu.dcache.LoadLockedReq_misses::total 446029 # number of LoadLockedReq misses 909system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses 910system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses 911system.cpu.dcache.demand_misses::cpu.data 20716987 # number of demand (read+write) misses 912system.cpu.dcache.demand_misses::total 20716987 # number of demand (read+write) misses 913system.cpu.dcache.overall_misses::cpu.data 21879021 # number of overall misses 914system.cpu.dcache.overall_misses::total 21879021 # number of overall misses 915system.cpu.dcache.ReadReq_miss_latency::cpu.data 166239076000 # number of ReadReq miss cycles 916system.cpu.dcache.ReadReq_miss_latency::total 166239076000 # number of ReadReq miss cycles 917system.cpu.dcache.WriteReq_miss_latency::cpu.data 434694643757 # number of WriteReq miss cycles 918system.cpu.dcache.WriteReq_miss_latency::total 434694643757 # number of WriteReq miss cycles 919system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 89167821376 # number of WriteLineReq miss cycles 920system.cpu.dcache.WriteLineReq_miss_latency::total 89167821376 # number of WriteLineReq miss cycles 921system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6826466500 # number of LoadLockedReq miss cycles 922system.cpu.dcache.LoadLockedReq_miss_latency::total 6826466500 # number of LoadLockedReq miss cycles 923system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 272500 # number of StoreCondReq miss cycles 924system.cpu.dcache.StoreCondReq_miss_latency::total 272500 # number of StoreCondReq miss cycles 925system.cpu.dcache.demand_miss_latency::cpu.data 600933719757 # number of demand (read+write) miss cycles 926system.cpu.dcache.demand_miss_latency::total 600933719757 # number of demand (read+write) miss cycles 927system.cpu.dcache.overall_miss_latency::cpu.data 600933719757 # number of overall miss cycles 928system.cpu.dcache.overall_miss_latency::total 600933719757 # number of overall miss cycles 929system.cpu.dcache.ReadReq_accesses::cpu.data 156415966 # number of ReadReq accesses(hits+misses) 930system.cpu.dcache.ReadReq_accesses::total 156415966 # number of ReadReq accesses(hits+misses) 931system.cpu.dcache.WriteReq_accesses::cpu.data 139235926 # number of WriteReq accesses(hits+misses) 932system.cpu.dcache.WriteReq_accesses::total 139235926 # number of WriteReq accesses(hits+misses) 933system.cpu.dcache.SoftPFReq_accesses::cpu.data 1539561 # number of SoftPFReq accesses(hits+misses) 934system.cpu.dcache.SoftPFReq_accesses::total 1539561 # number of SoftPFReq accesses(hits+misses) 935system.cpu.dcache.WriteLineReq_accesses::cpu.data 1555675 # number of WriteLineReq accesses(hits+misses) 936system.cpu.dcache.WriteLineReq_accesses::total 1555675 # number of WriteLineReq accesses(hits+misses) 937system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3730353 # number of LoadLockedReq accesses(hits+misses) 938system.cpu.dcache.LoadLockedReq_accesses::total 3730353 # number of LoadLockedReq accesses(hits+misses) 939system.cpu.dcache.StoreCondReq_accesses::cpu.data 3679082 # number of StoreCondReq accesses(hits+misses) 940system.cpu.dcache.StoreCondReq_accesses::total 3679082 # number of StoreCondReq accesses(hits+misses) 941system.cpu.dcache.demand_accesses::cpu.data 295651892 # number of demand (read+write) accesses 942system.cpu.dcache.demand_accesses::total 295651892 # number of demand (read+write) accesses 943system.cpu.dcache.overall_accesses::cpu.data 297191453 # number of overall (read+write) accesses 944system.cpu.dcache.overall_accesses::total 297191453 # number of overall (read+write) accesses 945system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060861 # miss rate for ReadReq accesses 946system.cpu.dcache.ReadReq_miss_rate::total 0.060861 # miss rate for ReadReq accesses 947system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080420 # miss rate for WriteReq accesses 948system.cpu.dcache.WriteReq_miss_rate::total 0.080420 # miss rate for WriteReq accesses 949system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.754783 # miss rate for SoftPFReq accesses 950system.cpu.dcache.SoftPFReq_miss_rate::total 0.754783 # miss rate for SoftPFReq accesses 951system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.791573 # miss rate for WriteLineReq accesses 952system.cpu.dcache.WriteLineReq_miss_rate::total 0.791573 # miss rate for WriteLineReq accesses 953system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119568 # miss rate for LoadLockedReq accesses 954system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119568 # miss rate for LoadLockedReq accesses 955system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses 956system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses 957system.cpu.dcache.demand_miss_rate::cpu.data 0.070072 # miss rate for demand accesses 958system.cpu.dcache.demand_miss_rate::total 0.070072 # miss rate for demand accesses 959system.cpu.dcache.overall_miss_rate::cpu.data 0.073619 # miss rate for overall accesses 960system.cpu.dcache.overall_miss_rate::total 0.073619 # miss rate for overall accesses 961system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17462.858235 # average ReadReq miss latency 962system.cpu.dcache.ReadReq_avg_miss_latency::total 17462.858235 # average ReadReq miss latency 963system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38821.009521 # average WriteReq miss latency 964system.cpu.dcache.WriteReq_avg_miss_latency::total 38821.009521 # average WriteReq miss latency 965system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 72409.920959 # average WriteLineReq miss latency 966system.cpu.dcache.WriteLineReq_avg_miss_latency::total 72409.920959 # average WriteLineReq miss latency 967system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15304.983532 # average LoadLockedReq miss latency 968system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15304.983532 # average LoadLockedReq miss latency 969system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 54500 # average StoreCondReq miss latency 970system.cpu.dcache.StoreCondReq_avg_miss_latency::total 54500 # average StoreCondReq miss latency 971system.cpu.dcache.demand_avg_miss_latency::cpu.data 29006.810679 # average overall miss latency 972system.cpu.dcache.demand_avg_miss_latency::total 29006.810679 # average overall miss latency 973system.cpu.dcache.overall_avg_miss_latency::cpu.data 27466.207001 # average overall miss latency 974system.cpu.dcache.overall_avg_miss_latency::total 27466.207001 # average overall miss latency 975system.cpu.dcache.blocked_cycles::no_mshrs 49612844 # number of cycles access was blocked 976system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 977system.cpu.dcache.blocked::no_mshrs 1593346 # number of cycles access was blocked 978system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 979system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.137521 # average number of cycles each access was blocked 980system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 981system.cpu.dcache.fast_writes 0 # number of fast writes performed 982system.cpu.dcache.cache_copies 0 # number of cache copies performed 983system.cpu.dcache.writebacks::writebacks 7472245 # number of writebacks 984system.cpu.dcache.writebacks::total 7472245 # number of writebacks 985system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4426093 # number of ReadReq MSHR hits 986system.cpu.dcache.ReadReq_mshr_hits::total 4426093 # number of ReadReq MSHR hits 987system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9200570 # number of WriteReq MSHR hits 988system.cpu.dcache.WriteReq_mshr_hits::total 9200570 # number of WriteReq MSHR hits 989system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 7004 # number of WriteLineReq MSHR hits 990system.cpu.dcache.WriteLineReq_mshr_hits::total 7004 # number of WriteLineReq MSHR hits 991system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 218758 # number of LoadLockedReq MSHR hits 992system.cpu.dcache.LoadLockedReq_mshr_hits::total 218758 # number of LoadLockedReq MSHR hits 993system.cpu.dcache.demand_mshr_hits::cpu.data 13626663 # number of demand (read+write) MSHR hits 994system.cpu.dcache.demand_mshr_hits::total 13626663 # number of demand (read+write) MSHR hits 995system.cpu.dcache.overall_mshr_hits::cpu.data 13626663 # number of overall MSHR hits 996system.cpu.dcache.overall_mshr_hits::total 13626663 # number of overall MSHR hits 997system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5093487 # number of ReadReq MSHR misses 998system.cpu.dcache.ReadReq_mshr_misses::total 5093487 # number of ReadReq MSHR misses 999system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1996837 # number of WriteReq MSHR misses 1000system.cpu.dcache.WriteReq_mshr_misses::total 1996837 # number of WriteReq MSHR misses 1001system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1155229 # number of SoftPFReq MSHR misses 1002system.cpu.dcache.SoftPFReq_mshr_misses::total 1155229 # number of SoftPFReq MSHR misses 1003system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1224427 # number of WriteLineReq MSHR misses 1004system.cpu.dcache.WriteLineReq_mshr_misses::total 1224427 # number of WriteLineReq MSHR misses 1005system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 227271 # number of LoadLockedReq MSHR misses 1006system.cpu.dcache.LoadLockedReq_mshr_misses::total 227271 # number of LoadLockedReq MSHR misses 1007system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses 1008system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses 1009system.cpu.dcache.demand_mshr_misses::cpu.data 7090324 # number of demand (read+write) MSHR misses 1010system.cpu.dcache.demand_mshr_misses::total 7090324 # number of demand (read+write) MSHR misses 1011system.cpu.dcache.overall_mshr_misses::cpu.data 8245553 # number of overall MSHR misses 1012system.cpu.dcache.overall_mshr_misses::total 8245553 # number of overall MSHR misses 1013system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable 1014system.cpu.dcache.ReadReq_mshr_uncacheable::total 33678 # number of ReadReq MSHR uncacheable 1015system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable 1016system.cpu.dcache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable 1017system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67374 # number of overall MSHR uncacheable misses 1018system.cpu.dcache.overall_mshr_uncacheable_misses::total 67374 # number of overall MSHR uncacheable misses 1019system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84024978000 # number of ReadReq MSHR miss cycles 1020system.cpu.dcache.ReadReq_mshr_miss_latency::total 84024978000 # number of ReadReq MSHR miss cycles 1021system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 76144562086 # number of WriteReq MSHR miss cycles 1022system.cpu.dcache.WriteReq_mshr_miss_latency::total 76144562086 # number of WriteReq MSHR miss cycles 1023system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 22952152500 # number of SoftPFReq MSHR miss cycles 1024system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 22952152500 # number of SoftPFReq MSHR miss cycles 1025system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 87564866876 # number of WriteLineReq MSHR miss cycles 1026system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 87564866876 # number of WriteLineReq MSHR miss cycles 1027system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3184481000 # number of LoadLockedReq MSHR miss cycles 1028system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3184481000 # number of LoadLockedReq MSHR miss cycles 1029system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 267500 # number of StoreCondReq MSHR miss cycles 1030system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 267500 # number of StoreCondReq MSHR miss cycles 1031system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160169540086 # number of demand (read+write) MSHR miss cycles 1032system.cpu.dcache.demand_mshr_miss_latency::total 160169540086 # number of demand (read+write) MSHR miss cycles 1033system.cpu.dcache.overall_mshr_miss_latency::cpu.data 183121692586 # number of overall MSHR miss cycles 1034system.cpu.dcache.overall_mshr_miss_latency::total 183121692586 # number of overall MSHR miss cycles 1035system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6191871000 # number of ReadReq MSHR uncacheable cycles 1036system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6191871000 # number of ReadReq MSHR uncacheable cycles 1037system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 6228308464 # number of WriteReq MSHR uncacheable cycles 1038system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 6228308464 # number of WriteReq MSHR uncacheable cycles 1039system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 12420179464 # number of overall MSHR uncacheable cycles 1040system.cpu.dcache.overall_mshr_uncacheable_latency::total 12420179464 # number of overall MSHR uncacheable cycles 1041system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032564 # mshr miss rate for ReadReq accesses 1042system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032564 # mshr miss rate for ReadReq accesses 1043system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014341 # mshr miss rate for WriteReq accesses 1044system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014341 # mshr miss rate for WriteReq accesses 1045system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.750363 # mshr miss rate for SoftPFReq accesses 1046system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.750363 # mshr miss rate for SoftPFReq accesses 1047system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787071 # mshr miss rate for WriteLineReq accesses 1048system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787071 # mshr miss rate for WriteLineReq accesses 1049system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060925 # mshr miss rate for LoadLockedReq accesses 1050system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060925 # mshr miss rate for LoadLockedReq accesses 1051system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses 1052system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses 1053system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.023982 # mshr miss rate for demand accesses 1054system.cpu.dcache.demand_mshr_miss_rate::total 0.023982 # mshr miss rate for demand accesses 1055system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027745 # mshr miss rate for overall accesses 1056system.cpu.dcache.overall_mshr_miss_rate::total 0.027745 # mshr miss rate for overall accesses 1057system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16496.552951 # average ReadReq mshr miss latency 1058system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16496.552951 # average ReadReq mshr miss latency 1059system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38132.587730 # average WriteReq mshr miss latency 1060system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38132.587730 # average WriteReq mshr miss latency 1061system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19868.054299 # average SoftPFReq mshr miss latency 1062system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19868.054299 # average SoftPFReq mshr miss latency 1063system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 71514.975475 # average WriteLineReq mshr miss latency 1064system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 71514.975475 # average WriteLineReq mshr miss latency 1065system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14011.822890 # average LoadLockedReq mshr miss latency 1066system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14011.822890 # average LoadLockedReq mshr miss latency 1067system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 53500 # average StoreCondReq mshr miss latency 1068system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 53500 # average StoreCondReq mshr miss latency 1069system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22589.876018 # average overall mshr miss latency 1070system.cpu.dcache.demand_avg_mshr_miss_latency::total 22589.876018 # average overall mshr miss latency 1071system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22208.539874 # average overall mshr miss latency 1072system.cpu.dcache.overall_avg_mshr_miss_latency::total 22208.539874 # average overall mshr miss latency 1073system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 183855.068591 # average ReadReq mshr uncacheable latency 1074system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 183855.068591 # average ReadReq mshr uncacheable latency 1075system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184838.214150 # average WriteReq mshr uncacheable latency 1076system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184838.214150 # average WriteReq mshr uncacheable latency 1077system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 184346.772702 # average overall mshr uncacheable latency 1078system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 184346.772702 # average overall mshr uncacheable latency 1079system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1080system.cpu.icache.tags.replacements 15015869 # number of replacements 1081system.cpu.icache.tags.tagsinuse 511.916858 # Cycle average of tags in use 1082system.cpu.icache.tags.total_refs 339700335 # Total number of references to valid blocks. 1083system.cpu.icache.tags.sampled_refs 15016381 # Sample count of references to valid blocks. 1084system.cpu.icache.tags.avg_refs 22.621984 # Average number of references to valid blocks. 1085system.cpu.icache.tags.warmup_cycle 24730722500 # Cycle when the warmup percentage was hit. 1086system.cpu.icache.tags.occ_blocks::cpu.inst 511.916858 # Average occupied blocks per requestor 1087system.cpu.icache.tags.occ_percent::cpu.inst 0.999838 # Average percentage of cache occupancy 1088system.cpu.icache.tags.occ_percent::total 0.999838 # Average percentage of cache occupancy 1089system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1090system.cpu.icache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id 1091system.cpu.icache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id 1092system.cpu.icache.tags.age_task_id_blocks_1024::2 101 # Occupied blocks per task id 1093system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1094system.cpu.icache.tags.tag_accesses 370501257 # Number of tag accesses 1095system.cpu.icache.tags.data_accesses 370501257 # Number of data accesses 1096system.cpu.icache.ReadReq_hits::cpu.inst 339700335 # number of ReadReq hits 1097system.cpu.icache.ReadReq_hits::total 339700335 # number of ReadReq hits 1098system.cpu.icache.demand_hits::cpu.inst 339700335 # number of demand (read+write) hits 1099system.cpu.icache.demand_hits::total 339700335 # number of demand (read+write) hits 1100system.cpu.icache.overall_hits::cpu.inst 339700335 # number of overall hits 1101system.cpu.icache.overall_hits::total 339700335 # number of overall hits 1102system.cpu.icache.ReadReq_misses::cpu.inst 15784316 # number of ReadReq misses 1103system.cpu.icache.ReadReq_misses::total 15784316 # number of ReadReq misses 1104system.cpu.icache.demand_misses::cpu.inst 15784316 # number of demand (read+write) misses 1105system.cpu.icache.demand_misses::total 15784316 # number of demand (read+write) misses 1106system.cpu.icache.overall_misses::cpu.inst 15784316 # number of overall misses 1107system.cpu.icache.overall_misses::total 15784316 # number of overall misses 1108system.cpu.icache.ReadReq_miss_latency::cpu.inst 213513378383 # number of ReadReq miss cycles 1109system.cpu.icache.ReadReq_miss_latency::total 213513378383 # number of ReadReq miss cycles 1110system.cpu.icache.demand_miss_latency::cpu.inst 213513378383 # number of demand (read+write) miss cycles 1111system.cpu.icache.demand_miss_latency::total 213513378383 # number of demand (read+write) miss cycles 1112system.cpu.icache.overall_miss_latency::cpu.inst 213513378383 # number of overall miss cycles 1113system.cpu.icache.overall_miss_latency::total 213513378383 # number of overall miss cycles 1114system.cpu.icache.ReadReq_accesses::cpu.inst 355484651 # number of ReadReq accesses(hits+misses) 1115system.cpu.icache.ReadReq_accesses::total 355484651 # number of ReadReq accesses(hits+misses) 1116system.cpu.icache.demand_accesses::cpu.inst 355484651 # number of demand (read+write) accesses 1117system.cpu.icache.demand_accesses::total 355484651 # number of demand (read+write) accesses 1118system.cpu.icache.overall_accesses::cpu.inst 355484651 # number of overall (read+write) accesses 1119system.cpu.icache.overall_accesses::total 355484651 # number of overall (read+write) accesses 1120system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044402 # miss rate for ReadReq accesses 1121system.cpu.icache.ReadReq_miss_rate::total 0.044402 # miss rate for ReadReq accesses 1122system.cpu.icache.demand_miss_rate::cpu.inst 0.044402 # miss rate for demand accesses 1123system.cpu.icache.demand_miss_rate::total 0.044402 # miss rate for demand accesses 1124system.cpu.icache.overall_miss_rate::cpu.inst 0.044402 # miss rate for overall accesses 1125system.cpu.icache.overall_miss_rate::total 0.044402 # miss rate for overall accesses 1126system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13526.932582 # average ReadReq miss latency 1127system.cpu.icache.ReadReq_avg_miss_latency::total 13526.932582 # average ReadReq miss latency 1128system.cpu.icache.demand_avg_miss_latency::cpu.inst 13526.932582 # average overall miss latency 1129system.cpu.icache.demand_avg_miss_latency::total 13526.932582 # average overall miss latency 1130system.cpu.icache.overall_avg_miss_latency::cpu.inst 13526.932582 # average overall miss latency 1131system.cpu.icache.overall_avg_miss_latency::total 13526.932582 # average overall miss latency 1132system.cpu.icache.blocked_cycles::no_mshrs 23493 # number of cycles access was blocked 1133system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1134system.cpu.icache.blocked::no_mshrs 1429 # number of cycles access was blocked 1135system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 1136system.cpu.icache.avg_blocked_cycles::no_mshrs 16.440168 # average number of cycles each access was blocked 1137system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1138system.cpu.icache.fast_writes 0 # number of fast writes performed 1139system.cpu.icache.cache_copies 0 # number of cache copies performed 1140system.cpu.icache.writebacks::writebacks 15015869 # number of writebacks 1141system.cpu.icache.writebacks::total 15015869 # number of writebacks 1142system.cpu.icache.ReadReq_mshr_hits::cpu.inst 767710 # number of ReadReq MSHR hits 1143system.cpu.icache.ReadReq_mshr_hits::total 767710 # number of ReadReq MSHR hits 1144system.cpu.icache.demand_mshr_hits::cpu.inst 767710 # number of demand (read+write) MSHR hits 1145system.cpu.icache.demand_mshr_hits::total 767710 # number of demand (read+write) MSHR hits 1146system.cpu.icache.overall_mshr_hits::cpu.inst 767710 # number of overall MSHR hits 1147system.cpu.icache.overall_mshr_hits::total 767710 # number of overall MSHR hits 1148system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15016606 # number of ReadReq MSHR misses 1149system.cpu.icache.ReadReq_mshr_misses::total 15016606 # number of ReadReq MSHR misses 1150system.cpu.icache.demand_mshr_misses::cpu.inst 15016606 # number of demand (read+write) MSHR misses 1151system.cpu.icache.demand_mshr_misses::total 15016606 # number of demand (read+write) MSHR misses 1152system.cpu.icache.overall_mshr_misses::cpu.inst 15016606 # number of overall MSHR misses 1153system.cpu.icache.overall_mshr_misses::total 15016606 # number of overall MSHR misses 1154system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable 1155system.cpu.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable 1156system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses 1157system.cpu.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses 1158system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191214569892 # number of ReadReq MSHR miss cycles 1159system.cpu.icache.ReadReq_mshr_miss_latency::total 191214569892 # number of ReadReq MSHR miss cycles 1160system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191214569892 # number of demand (read+write) MSHR miss cycles 1161system.cpu.icache.demand_mshr_miss_latency::total 191214569892 # number of demand (read+write) MSHR miss cycles 1162system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191214569892 # number of overall MSHR miss cycles 1163system.cpu.icache.overall_mshr_miss_latency::total 191214569892 # number of overall MSHR miss cycles 1164system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 2684938000 # number of ReadReq MSHR uncacheable cycles 1165system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 2684938000 # number of ReadReq MSHR uncacheable cycles 1166system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 2684938000 # number of overall MSHR uncacheable cycles 1167system.cpu.icache.overall_mshr_uncacheable_latency::total 2684938000 # number of overall MSHR uncacheable cycles 1168system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.042243 # mshr miss rate for ReadReq accesses 1169system.cpu.icache.ReadReq_mshr_miss_rate::total 0.042243 # mshr miss rate for ReadReq accesses 1170system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.042243 # mshr miss rate for demand accesses 1171system.cpu.icache.demand_mshr_miss_rate::total 0.042243 # mshr miss rate for demand accesses 1172system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.042243 # mshr miss rate for overall accesses 1173system.cpu.icache.overall_mshr_miss_rate::total 0.042243 # mshr miss rate for overall accesses 1174system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12733.541114 # average ReadReq mshr miss latency 1175system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12733.541114 # average ReadReq mshr miss latency 1176system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12733.541114 # average overall mshr miss latency 1177system.cpu.icache.demand_avg_mshr_miss_latency::total 12733.541114 # average overall mshr miss latency 1178system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12733.541114 # average overall mshr miss latency 1179system.cpu.icache.overall_avg_mshr_miss_latency::total 12733.541114 # average overall mshr miss latency 1180system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 126088.945243 # average ReadReq mshr uncacheable latency 1181system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 126088.945243 # average ReadReq mshr uncacheable latency 1182system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 126088.945243 # average overall mshr uncacheable latency 1183system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 126088.945243 # average overall mshr uncacheable latency 1184system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1185system.cpu.l2cache.tags.replacements 1125252 # number of replacements 1186system.cpu.l2cache.tags.tagsinuse 65288.718100 # Cycle average of tags in use 1187system.cpu.l2cache.tags.total_refs 45967246 # Total number of references to valid blocks. 1188system.cpu.l2cache.tags.sampled_refs 1186784 # Sample count of references to valid blocks. 1189system.cpu.l2cache.tags.avg_refs 38.732614 # Average number of references to valid blocks. 1190system.cpu.l2cache.tags.warmup_cycle 22908442500 # Cycle when the warmup percentage was hit. 1191system.cpu.l2cache.tags.occ_blocks::writebacks 37194.464747 # Average occupied blocks per requestor 1192system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 291.486399 # Average occupied blocks per requestor 1193system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 421.983765 # Average occupied blocks per requestor 1194system.cpu.l2cache.tags.occ_blocks::cpu.inst 7890.372010 # Average occupied blocks per requestor 1195system.cpu.l2cache.tags.occ_blocks::cpu.data 19490.411179 # Average occupied blocks per requestor 1196system.cpu.l2cache.tags.occ_percent::writebacks 0.567542 # Average percentage of cache occupancy 1197system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004448 # Average percentage of cache occupancy 1198system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006439 # Average percentage of cache occupancy 1199system.cpu.l2cache.tags.occ_percent::cpu.inst 0.120398 # Average percentage of cache occupancy 1200system.cpu.l2cache.tags.occ_percent::cpu.data 0.297400 # Average percentage of cache occupancy 1201system.cpu.l2cache.tags.occ_percent::total 0.996227 # Average percentage of cache occupancy 1202system.cpu.l2cache.tags.occ_task_id_blocks::1023 288 # Occupied blocks per task id 1203system.cpu.l2cache.tags.occ_task_id_blocks::1024 61244 # Occupied blocks per task id 1204system.cpu.l2cache.tags.age_task_id_blocks_1023::4 288 # Occupied blocks per task id 1205system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 1206system.cpu.l2cache.tags.age_task_id_blocks_1024::1 554 # Occupied blocks per task id 1207system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2686 # Occupied blocks per task id 1208system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5116 # Occupied blocks per task id 1209system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52825 # Occupied blocks per task id 1210system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004395 # Percentage of cache occupancy per task id 1211system.cpu.l2cache.tags.occ_task_id_percent::1024 0.934509 # Percentage of cache occupancy per task id 1212system.cpu.l2cache.tags.tag_accesses 408147650 # Number of tag accesses 1213system.cpu.l2cache.tags.data_accesses 408147650 # Number of data accesses 1214system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 779679 # number of ReadReq hits 1215system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 299256 # number of ReadReq hits 1216system.cpu.l2cache.ReadReq_hits::total 1078935 # number of ReadReq hits 1217system.cpu.l2cache.WritebackDirty_hits::writebacks 7472245 # number of WritebackDirty hits 1218system.cpu.l2cache.WritebackDirty_hits::total 7472245 # number of WritebackDirty hits 1219system.cpu.l2cache.WritebackClean_hits::writebacks 15013335 # number of WritebackClean hits 1220system.cpu.l2cache.WritebackClean_hits::total 15013335 # number of WritebackClean hits 1221system.cpu.l2cache.UpgradeReq_hits::cpu.data 9316 # number of UpgradeReq hits 1222system.cpu.l2cache.UpgradeReq_hits::total 9316 # number of UpgradeReq hits 1223system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits 1224system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits 1225system.cpu.l2cache.ReadExReq_hits::cpu.data 1569994 # number of ReadExReq hits 1226system.cpu.l2cache.ReadExReq_hits::total 1569994 # number of ReadExReq hits 1227system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 14932694 # number of ReadCleanReq hits 1228system.cpu.l2cache.ReadCleanReq_hits::total 14932694 # number of ReadCleanReq hits 1229system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6224430 # number of ReadSharedReq hits 1230system.cpu.l2cache.ReadSharedReq_hits::total 6224430 # number of ReadSharedReq hits 1231system.cpu.l2cache.InvalidateReq_hits::cpu.data 730294 # number of InvalidateReq hits 1232system.cpu.l2cache.InvalidateReq_hits::total 730294 # number of InvalidateReq hits 1233system.cpu.l2cache.demand_hits::cpu.dtb.walker 779679 # number of demand (read+write) hits 1234system.cpu.l2cache.demand_hits::cpu.itb.walker 299256 # number of demand (read+write) hits 1235system.cpu.l2cache.demand_hits::cpu.inst 14932694 # number of demand (read+write) hits 1236system.cpu.l2cache.demand_hits::cpu.data 7794424 # number of demand (read+write) hits 1237system.cpu.l2cache.demand_hits::total 23806053 # number of demand (read+write) hits 1238system.cpu.l2cache.overall_hits::cpu.dtb.walker 779679 # number of overall hits 1239system.cpu.l2cache.overall_hits::cpu.itb.walker 299256 # number of overall hits 1240system.cpu.l2cache.overall_hits::cpu.inst 14932694 # number of overall hits 1241system.cpu.l2cache.overall_hits::cpu.data 7794424 # number of overall hits 1242system.cpu.l2cache.overall_hits::total 23806053 # number of overall hits 1243system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3212 # number of ReadReq misses 1244system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3085 # number of ReadReq misses 1245system.cpu.l2cache.ReadReq_misses::total 6297 # number of ReadReq misses 1246system.cpu.l2cache.UpgradeReq_misses::cpu.data 33834 # number of UpgradeReq misses 1247system.cpu.l2cache.UpgradeReq_misses::total 33834 # number of UpgradeReq misses 1248system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses 1249system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses 1250system.cpu.l2cache.ReadExReq_misses::cpu.data 386835 # number of ReadExReq misses 1251system.cpu.l2cache.ReadExReq_misses::total 386835 # number of ReadExReq misses 1252system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 83701 # number of ReadCleanReq misses 1253system.cpu.l2cache.ReadCleanReq_misses::total 83701 # number of ReadCleanReq misses 1254system.cpu.l2cache.ReadSharedReq_misses::cpu.data 248420 # number of ReadSharedReq misses 1255system.cpu.l2cache.ReadSharedReq_misses::total 248420 # number of ReadSharedReq misses 1256system.cpu.l2cache.InvalidateReq_misses::cpu.data 494133 # number of InvalidateReq misses 1257system.cpu.l2cache.InvalidateReq_misses::total 494133 # number of InvalidateReq misses 1258system.cpu.l2cache.demand_misses::cpu.dtb.walker 3212 # number of demand (read+write) misses 1259system.cpu.l2cache.demand_misses::cpu.itb.walker 3085 # number of demand (read+write) misses 1260system.cpu.l2cache.demand_misses::cpu.inst 83701 # number of demand (read+write) misses 1261system.cpu.l2cache.demand_misses::cpu.data 635255 # number of demand (read+write) misses 1262system.cpu.l2cache.demand_misses::total 725253 # number of demand (read+write) misses 1263system.cpu.l2cache.overall_misses::cpu.dtb.walker 3212 # number of overall misses 1264system.cpu.l2cache.overall_misses::cpu.itb.walker 3085 # number of overall misses 1265system.cpu.l2cache.overall_misses::cpu.inst 83701 # number of overall misses 1266system.cpu.l2cache.overall_misses::cpu.data 635255 # number of overall misses 1267system.cpu.l2cache.overall_misses::total 725253 # number of overall misses 1268system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 442122000 # number of ReadReq miss cycles 1269system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 426004000 # number of ReadReq miss cycles 1270system.cpu.l2cache.ReadReq_miss_latency::total 868126000 # number of ReadReq miss cycles 1271system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1354898000 # number of UpgradeReq miss cycles 1272system.cpu.l2cache.UpgradeReq_miss_latency::total 1354898000 # number of UpgradeReq miss cycles 1273system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 160500 # number of SCUpgradeReq miss cycles 1274system.cpu.l2cache.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles 1275system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 53636618000 # number of ReadExReq miss cycles 1276system.cpu.l2cache.ReadExReq_miss_latency::total 53636618000 # number of ReadExReq miss cycles 1277system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11266586500 # number of ReadCleanReq miss cycles 1278system.cpu.l2cache.ReadCleanReq_miss_latency::total 11266586500 # number of ReadCleanReq miss cycles 1279system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 34501509500 # number of ReadSharedReq miss cycles 1280system.cpu.l2cache.ReadSharedReq_miss_latency::total 34501509500 # number of ReadSharedReq miss cycles 1281system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 76602045500 # number of InvalidateReq miss cycles 1282system.cpu.l2cache.InvalidateReq_miss_latency::total 76602045500 # number of InvalidateReq miss cycles 1283system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 442122000 # number of demand (read+write) miss cycles 1284system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 426004000 # number of demand (read+write) miss cycles 1285system.cpu.l2cache.demand_miss_latency::cpu.inst 11266586500 # number of demand (read+write) miss cycles 1286system.cpu.l2cache.demand_miss_latency::cpu.data 88138127500 # number of demand (read+write) miss cycles 1287system.cpu.l2cache.demand_miss_latency::total 100272840000 # number of demand (read+write) miss cycles 1288system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 442122000 # number of overall miss cycles 1289system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 426004000 # number of overall miss cycles 1290system.cpu.l2cache.overall_miss_latency::cpu.inst 11266586500 # number of overall miss cycles 1291system.cpu.l2cache.overall_miss_latency::cpu.data 88138127500 # number of overall miss cycles 1292system.cpu.l2cache.overall_miss_latency::total 100272840000 # number of overall miss cycles 1293system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 782891 # number of ReadReq accesses(hits+misses) 1294system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 302341 # number of ReadReq accesses(hits+misses) 1295system.cpu.l2cache.ReadReq_accesses::total 1085232 # number of ReadReq accesses(hits+misses) 1296system.cpu.l2cache.WritebackDirty_accesses::writebacks 7472245 # number of WritebackDirty accesses(hits+misses) 1297system.cpu.l2cache.WritebackDirty_accesses::total 7472245 # number of WritebackDirty accesses(hits+misses) 1298system.cpu.l2cache.WritebackClean_accesses::writebacks 15013335 # number of WritebackClean accesses(hits+misses) 1299system.cpu.l2cache.WritebackClean_accesses::total 15013335 # number of WritebackClean accesses(hits+misses) 1300system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43150 # number of UpgradeReq accesses(hits+misses) 1301system.cpu.l2cache.UpgradeReq_accesses::total 43150 # number of UpgradeReq accesses(hits+misses) 1302system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) 1303system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) 1304system.cpu.l2cache.ReadExReq_accesses::cpu.data 1956829 # number of ReadExReq accesses(hits+misses) 1305system.cpu.l2cache.ReadExReq_accesses::total 1956829 # number of ReadExReq accesses(hits+misses) 1306system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15016395 # number of ReadCleanReq accesses(hits+misses) 1307system.cpu.l2cache.ReadCleanReq_accesses::total 15016395 # number of ReadCleanReq accesses(hits+misses) 1308system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 6472850 # number of ReadSharedReq accesses(hits+misses) 1309system.cpu.l2cache.ReadSharedReq_accesses::total 6472850 # number of ReadSharedReq accesses(hits+misses) 1310system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1224427 # number of InvalidateReq accesses(hits+misses) 1311system.cpu.l2cache.InvalidateReq_accesses::total 1224427 # number of InvalidateReq accesses(hits+misses) 1312system.cpu.l2cache.demand_accesses::cpu.dtb.walker 782891 # number of demand (read+write) accesses 1313system.cpu.l2cache.demand_accesses::cpu.itb.walker 302341 # number of demand (read+write) accesses 1314system.cpu.l2cache.demand_accesses::cpu.inst 15016395 # number of demand (read+write) accesses 1315system.cpu.l2cache.demand_accesses::cpu.data 8429679 # number of demand (read+write) accesses 1316system.cpu.l2cache.demand_accesses::total 24531306 # number of demand (read+write) accesses 1317system.cpu.l2cache.overall_accesses::cpu.dtb.walker 782891 # number of overall (read+write) accesses 1318system.cpu.l2cache.overall_accesses::cpu.itb.walker 302341 # number of overall (read+write) accesses 1319system.cpu.l2cache.overall_accesses::cpu.inst 15016395 # number of overall (read+write) accesses 1320system.cpu.l2cache.overall_accesses::cpu.data 8429679 # number of overall (read+write) accesses 1321system.cpu.l2cache.overall_accesses::total 24531306 # number of overall (read+write) accesses 1322system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.004103 # miss rate for ReadReq accesses 1323system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.010204 # miss rate for ReadReq accesses 1324system.cpu.l2cache.ReadReq_miss_rate::total 0.005802 # miss rate for ReadReq accesses 1325system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.784102 # miss rate for UpgradeReq accesses 1326system.cpu.l2cache.UpgradeReq_miss_rate::total 0.784102 # miss rate for UpgradeReq accesses 1327system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.600000 # miss rate for SCUpgradeReq accesses 1328system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.600000 # miss rate for SCUpgradeReq accesses 1329system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.197685 # miss rate for ReadExReq accesses 1330system.cpu.l2cache.ReadExReq_miss_rate::total 0.197685 # miss rate for ReadExReq accesses 1331system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.005574 # miss rate for ReadCleanReq accesses 1332system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.005574 # miss rate for ReadCleanReq accesses 1333system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.038379 # miss rate for ReadSharedReq accesses 1334system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.038379 # miss rate for ReadSharedReq accesses 1335system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.403563 # miss rate for InvalidateReq accesses 1336system.cpu.l2cache.InvalidateReq_miss_rate::total 0.403563 # miss rate for InvalidateReq accesses 1337system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.004103 # miss rate for demand accesses 1338system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.010204 # miss rate for demand accesses 1339system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005574 # miss rate for demand accesses 1340system.cpu.l2cache.demand_miss_rate::cpu.data 0.075359 # miss rate for demand accesses 1341system.cpu.l2cache.demand_miss_rate::total 0.029564 # miss rate for demand accesses 1342system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.004103 # miss rate for overall accesses 1343system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.010204 # miss rate for overall accesses 1344system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005574 # miss rate for overall accesses 1345system.cpu.l2cache.overall_miss_rate::cpu.data 0.075359 # miss rate for overall accesses 1346system.cpu.l2cache.overall_miss_rate::total 0.029564 # miss rate for overall accesses 1347system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 137646.948941 # average ReadReq miss latency 1348system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 138088.816856 # average ReadReq miss latency 1349system.cpu.l2cache.ReadReq_avg_miss_latency::total 137863.427029 # average ReadReq miss latency 1350system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 40045.457232 # average UpgradeReq miss latency 1351system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 40045.457232 # average UpgradeReq miss latency 1352system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 53500 # average SCUpgradeReq miss latency 1353system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 53500 # average SCUpgradeReq miss latency 1354system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 138655.028630 # average ReadExReq miss latency 1355system.cpu.l2cache.ReadExReq_avg_miss_latency::total 138655.028630 # average ReadExReq miss latency 1356system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 134605.160034 # average ReadCleanReq miss latency 1357system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 134605.160034 # average ReadCleanReq miss latency 1358system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 138883.783512 # average ReadSharedReq miss latency 1359system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 138883.783512 # average ReadSharedReq miss latency 1360system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 155023.132436 # average InvalidateReq miss latency 1361system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 155023.132436 # average InvalidateReq miss latency 1362system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 137646.948941 # average overall miss latency 1363system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 138088.816856 # average overall miss latency 1364system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 134605.160034 # average overall miss latency 1365system.cpu.l2cache.demand_avg_miss_latency::cpu.data 138744.484498 # average overall miss latency 1366system.cpu.l2cache.demand_avg_miss_latency::total 138259.117853 # average overall miss latency 1367system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 137646.948941 # average overall miss latency 1368system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 138088.816856 # average overall miss latency 1369system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 134605.160034 # average overall miss latency 1370system.cpu.l2cache.overall_avg_miss_latency::cpu.data 138744.484498 # average overall miss latency 1371system.cpu.l2cache.overall_avg_miss_latency::total 138259.117853 # average overall miss latency 1372system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1373system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1374system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1375system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1376system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1377system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1378system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1379system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1380system.cpu.l2cache.writebacks::writebacks 944630 # number of writebacks 1381system.cpu.l2cache.writebacks::total 944630 # number of writebacks 1382system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 20 # number of ReadSharedReq MSHR hits 1383system.cpu.l2cache.ReadSharedReq_mshr_hits::total 20 # number of ReadSharedReq MSHR hits 1384system.cpu.l2cache.demand_mshr_hits::cpu.data 20 # number of demand (read+write) MSHR hits 1385system.cpu.l2cache.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits 1386system.cpu.l2cache.overall_mshr_hits::cpu.data 20 # number of overall MSHR hits 1387system.cpu.l2cache.overall_mshr_hits::total 20 # number of overall MSHR hits 1388system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3212 # number of ReadReq MSHR misses 1389system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3085 # number of ReadReq MSHR misses 1390system.cpu.l2cache.ReadReq_mshr_misses::total 6297 # number of ReadReq MSHR misses 1391system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses 1392system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses 1393system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33834 # number of UpgradeReq MSHR misses 1394system.cpu.l2cache.UpgradeReq_mshr_misses::total 33834 # number of UpgradeReq MSHR misses 1395system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses 1396system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses 1397system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 386835 # number of ReadExReq MSHR misses 1398system.cpu.l2cache.ReadExReq_mshr_misses::total 386835 # number of ReadExReq MSHR misses 1399system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 83701 # number of ReadCleanReq MSHR misses 1400system.cpu.l2cache.ReadCleanReq_mshr_misses::total 83701 # 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number of overall MSHR misses 1411system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3085 # number of overall MSHR misses 1412system.cpu.l2cache.overall_mshr_misses::cpu.inst 83701 # number of overall MSHR misses 1413system.cpu.l2cache.overall_mshr_misses::cpu.data 635235 # number of overall MSHR misses 1414system.cpu.l2cache.overall_mshr_misses::total 725233 # number of overall MSHR misses 1415system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 21294 # number of ReadReq MSHR uncacheable 1416system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33678 # number of ReadReq MSHR uncacheable 1417system.cpu.l2cache.ReadReq_mshr_uncacheable::total 54972 # number of ReadReq MSHR uncacheable 1418system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33696 # number of WriteReq MSHR uncacheable 1419system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33696 # number of WriteReq MSHR uncacheable 1420system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21294 # number of overall MSHR uncacheable misses 1421system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67374 # 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number of ReadExReq MSHR miss cycles 1431system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49768267002 # number of ReadExReq MSHR miss cycles 1432system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 10429576500 # number of ReadCleanReq MSHR miss cycles 1433system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 10429576500 # number of ReadCleanReq MSHR miss cycles 1434system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 32015340500 # number of ReadSharedReq MSHR miss cycles 1435system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 32015340500 # number of ReadSharedReq MSHR miss cycles 1436system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 71660712011 # number of InvalidateReq MSHR miss cycles 1437system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 71660712011 # number of InvalidateReq MSHR miss cycles 1438system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 410001501 # number of demand (read+write) MSHR miss cycles 1439system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 395154000 # number of demand (read+write) MSHR miss cycles 1440system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10429576500 # number of demand (read+write) MSHR miss cycles 1441system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 81783607502 # number of demand (read+write) MSHR miss cycles 1442system.cpu.l2cache.demand_mshr_miss_latency::total 93018339503 # number of demand (read+write) MSHR miss cycles 1443system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 410001501 # number of overall MSHR miss cycles 1444system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 395154000 # number of overall MSHR miss cycles 1445system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10429576500 # number of overall MSHR miss cycles 1446system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 81783607502 # number of overall MSHR miss cycles 1447system.cpu.l2cache.overall_mshr_miss_latency::total 93018339503 # number of overall MSHR miss cycles 1448system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2418763000 # number of ReadReq MSHR uncacheable cycles 1449system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5770735500 # number of ReadReq MSHR uncacheable cycles 1450system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8189498500 # number of ReadReq MSHR uncacheable cycles 1451system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5836278000 # number of WriteReq MSHR uncacheable cycles 1452system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5836278000 # number of WriteReq MSHR uncacheable cycles 1453system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2418763000 # number of overall MSHR uncacheable cycles 1454system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 11607013500 # number of overall MSHR uncacheable cycles 1455system.cpu.l2cache.overall_mshr_uncacheable_latency::total 14025776500 # number of overall MSHR uncacheable cycles 1456system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004103 # mshr miss rate for ReadReq accesses 1457system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010204 # mshr miss rate for ReadReq accesses 1458system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.005802 # mshr miss rate for ReadReq accesses 1459system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1460system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1461system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.784102 # mshr miss rate for UpgradeReq accesses 1462system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.784102 # mshr miss rate for UpgradeReq accesses 1463system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.600000 # mshr miss rate for SCUpgradeReq accesses 1464system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.600000 # mshr miss rate for SCUpgradeReq accesses 1465system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.197685 # mshr miss rate for ReadExReq accesses 1466system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.197685 # mshr miss rate for ReadExReq accesses 1467system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.005574 # mshr miss rate for ReadCleanReq accesses 1468system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.005574 # mshr miss rate for ReadCleanReq accesses 1469system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.038376 # mshr miss rate for ReadSharedReq accesses 1470system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.038376 # mshr miss rate for ReadSharedReq accesses 1471system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.403563 # mshr miss rate for InvalidateReq accesses 1472system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.403563 # mshr miss rate for InvalidateReq accesses 1473system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004103 # mshr miss rate for demand accesses 1474system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010204 # mshr miss rate for demand accesses 1475system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005574 # mshr miss rate for demand accesses 1476system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.075357 # mshr miss rate for demand accesses 1477system.cpu.l2cache.demand_mshr_miss_rate::total 0.029564 # mshr miss rate for demand accesses 1478system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004103 # mshr miss rate for overall accesses 1479system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010204 # mshr miss rate for overall accesses 1480system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005574 # mshr miss rate for overall accesses 1481system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.075357 # mshr miss rate for overall accesses 1482system.cpu.l2cache.overall_mshr_miss_rate::total 0.029564 # mshr miss rate for overall accesses 1483system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 127646.793587 # average ReadReq mshr miss latency 1484system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 128088.816856 # average ReadReq mshr miss latency 1485system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 127863.347785 # average ReadReq mshr miss latency 1486system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68011.600757 # average UpgradeReq mshr miss latency 1487system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68011.600757 # average UpgradeReq mshr miss latency 1488system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69666.666667 # average SCUpgradeReq mshr miss latency 1489system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69666.666667 # average SCUpgradeReq mshr miss latency 1490system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 128655.026050 # average ReadExReq mshr miss latency 1491system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 128655.026050 # average ReadExReq mshr miss latency 1492system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 124605.160034 # average ReadCleanReq mshr miss latency 1493system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 124605.160034 # average ReadCleanReq mshr miss latency 1494system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 128886.233897 # average ReadSharedReq mshr miss latency 1495system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 128886.233897 # average ReadSharedReq mshr miss latency 1496system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 145023.125375 # average InvalidateReq mshr miss latency 1497system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 145023.125375 # average InvalidateReq mshr miss latency 1498system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 127646.793587 # average overall mshr miss latency 1499system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 128088.816856 # average overall mshr miss latency 1500system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 124605.160034 # average overall mshr miss latency 1501system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 128745.436731 # average overall mshr miss latency 1502system.cpu.l2cache.demand_avg_mshr_miss_latency::total 128259.937845 # average overall mshr miss latency 1503system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 127646.793587 # average overall mshr miss latency 1504system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 128088.816856 # average overall mshr miss latency 1505system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 124605.160034 # average overall mshr miss latency 1506system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 128745.436731 # average overall mshr miss latency 1507system.cpu.l2cache.overall_avg_mshr_miss_latency::total 128259.937845 # average overall mshr miss latency 1508system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113588.945243 # average ReadReq mshr uncacheable latency 1509system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 171350.302868 # average ReadReq mshr uncacheable latency 1510system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 148975.814960 # average ReadReq mshr uncacheable latency 1511system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 173203.881766 # average WriteReq mshr uncacheable latency 1512system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173203.881766 # average WriteReq mshr uncacheable latency 1513system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113588.945243 # average overall mshr uncacheable latency 1514system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 172277.339923 # average overall mshr uncacheable latency 1515system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 158183.070555 # average overall mshr uncacheable latency 1516system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1517system.cpu.toL2Bus.snoop_filter.tot_requests 50072876 # Total number of requests made to the snoop filter. 1518system.cpu.toL2Bus.snoop_filter.hit_single_requests 25402191 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1519system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3486 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1520system.cpu.toL2Bus.snoop_filter.tot_snoops 2165 # Total number of snoops made to the snoop filter. 1521system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2165 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1522system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1523system.cpu.toL2Bus.trans_dist::ReadReq 1616472 # Transaction distribution 1524system.cpu.toL2Bus.trans_dist::ReadResp 23106705 # Transaction distribution 1525system.cpu.toL2Bus.trans_dist::WriteReq 33696 # Transaction distribution 1526system.cpu.toL2Bus.trans_dist::WriteResp 33696 # Transaction distribution 1527system.cpu.toL2Bus.trans_dist::WritebackDirty 8523542 # Transaction distribution 1528system.cpu.toL2Bus.trans_dist::WritebackClean 15015869 # Transaction distribution 1529system.cpu.toL2Bus.trans_dist::CleanEvict 2370764 # Transaction distribution 1530system.cpu.toL2Bus.trans_dist::UpgradeReq 43153 # Transaction distribution 1531system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution 1532system.cpu.toL2Bus.trans_dist::UpgradeResp 43158 # Transaction distribution 1533system.cpu.toL2Bus.trans_dist::ReadExReq 1956829 # Transaction distribution 1534system.cpu.toL2Bus.trans_dist::ReadExResp 1956829 # Transaction distribution 1535system.cpu.toL2Bus.trans_dist::ReadCleanReq 15016606 # Transaction distribution 1536system.cpu.toL2Bus.trans_dist::ReadSharedReq 6481683 # Transaction distribution 1537system.cpu.toL2Bus.trans_dist::InvalidateReq 1331091 # Transaction distribution 1538system.cpu.toL2Bus.trans_dist::InvalidateResp 1224427 # Transaction distribution 1539system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45091458 # Packet count per connected master and slave (bytes) 1540system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29183621 # Packet count per connected master and slave (bytes) 1541system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 729593 # Packet count per connected master and slave (bytes) 1542system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1917139 # Packet count per connected master and slave (bytes) 1543system.cpu.toL2Bus.pkt_count::total 76921811 # Packet count per connected master and slave (bytes) 1544system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1922405600 # Cumulative packet size per connected master and slave (bytes) 1545system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1017963166 # Cumulative packet size per connected master and slave (bytes) 1546system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2418728 # Cumulative packet size per connected master and slave (bytes) 1547system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6263128 # Cumulative packet size per connected master and slave (bytes) 1548system.cpu.toL2Bus.pkt_size::total 2949050622 # Cumulative packet size per connected master and slave (bytes) 1549system.cpu.toL2Bus.snoops 1833494 # Total snoops (count) 1550system.cpu.toL2Bus.snoop_fanout::samples 27720270 # Request fanout histogram 1551system.cpu.toL2Bus.snoop_fanout::mean 0.025088 # Request fanout histogram 1552system.cpu.toL2Bus.snoop_fanout::stdev 0.156393 # Request fanout histogram 1553system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1554system.cpu.toL2Bus.snoop_fanout::0 27024822 97.49% 97.49% # Request fanout histogram 1555system.cpu.toL2Bus.snoop_fanout::1 695448 2.51% 100.00% # Request fanout histogram 1556system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1557system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1558system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1559system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1560system.cpu.toL2Bus.snoop_fanout::total 27720270 # Request fanout histogram 1561system.cpu.toL2Bus.reqLayer0.occupancy 48021701496 # Layer occupancy (ticks) 1562system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1563system.cpu.toL2Bus.snoopLayer0.occupancy 1471889 # Layer occupancy (ticks) 1564system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1565system.cpu.toL2Bus.respLayer0.occupancy 22555136481 # Layer occupancy (ticks) 1566system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1567system.cpu.toL2Bus.respLayer1.occupancy 13331758520 # Layer occupancy (ticks) 1568system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1569system.cpu.toL2Bus.respLayer2.occupancy 427610263 # Layer occupancy (ticks) 1570system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1571system.cpu.toL2Bus.respLayer3.occupancy 1134604242 # Layer occupancy (ticks) 1572system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1573system.iobus.trans_dist::ReadReq 40281 # Transaction distribution 1574system.iobus.trans_dist::ReadResp 40281 # Transaction distribution 1575system.iobus.trans_dist::WriteReq 136571 # Transaction distribution 1576system.iobus.trans_dist::WriteResp 136571 # Transaction distribution 1577system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 1578system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1579system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1580system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1581system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1582system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1583system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1584system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1585system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1586system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1587system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1588system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 1589system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1590system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) 1591system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230920 # Packet count per connected master and slave (bytes) 1592system.iobus.pkt_count_system.realview.ide.dma::total 230920 # Packet count per connected master and slave (bytes) 1593system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1594system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 1595system.iobus.pkt_count::total 353704 # Packet count per connected master and slave (bytes) 1596system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 1597system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1598system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 1599system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1600system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1601system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1602system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1603system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1604system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1605system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1606system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1607system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 1608system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1609system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) 1610system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334112 # Cumulative packet size per connected master and slave (bytes) 1611system.iobus.pkt_size_system.realview.ide.dma::total 7334112 # Cumulative packet size per connected master and slave (bytes) 1612system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1613system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 1614system.iobus.pkt_size::total 7492032 # Cumulative packet size per connected master and slave (bytes) 1615system.iobus.reqLayer0.occupancy 41869500 # Layer occupancy (ticks) 1616system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1617system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) 1618system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1619system.iobus.reqLayer2.occupancy 342000 # Layer occupancy (ticks) 1620system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1621system.iobus.reqLayer3.occupancy 9500 # Layer occupancy (ticks) 1622system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1623system.iobus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) 1624system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1625system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) 1626system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1627system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) 1628system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1629system.iobus.reqLayer14.occupancy 9500 # Layer occupancy (ticks) 1630system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1631system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) 1632system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1633system.iobus.reqLayer16.occupancy 14500 # Layer occupancy (ticks) 1634system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1635system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 1636system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1637system.iobus.reqLayer23.occupancy 25153000 # Layer occupancy (ticks) 1638system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1639system.iobus.reqLayer24.occupancy 36496500 # Layer occupancy (ticks) 1640system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1641system.iobus.reqLayer25.occupancy 567170357 # Layer occupancy (ticks) 1642system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1643system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 1644system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1645system.iobus.respLayer3.occupancy 147680000 # Layer occupancy (ticks) 1646system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1647system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 1648system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 1649system.iocache.tags.replacements 115446 # number of replacements 1650system.iocache.tags.tagsinuse 10.422236 # Cycle average of tags in use 1651system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 1652system.iocache.tags.sampled_refs 115462 # Sample count of references to valid blocks. 1653system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1654system.iocache.tags.warmup_cycle 13103145496000 # Cycle when the warmup percentage was hit. 1655system.iocache.tags.occ_blocks::realview.ethernet 5.903254 # Average occupied blocks per requestor 1656system.iocache.tags.occ_blocks::realview.ide 4.518982 # Average occupied blocks per requestor 1657system.iocache.tags.occ_percent::realview.ethernet 0.368953 # Average percentage of cache occupancy 1658system.iocache.tags.occ_percent::realview.ide 0.282436 # Average percentage of cache occupancy 1659system.iocache.tags.occ_percent::total 0.651390 # Average percentage of cache occupancy 1660system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1661system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1662system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1663system.iocache.tags.tag_accesses 1039497 # Number of tag accesses 1664system.iocache.tags.data_accesses 1039497 # Number of data accesses 1665system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1666system.iocache.ReadReq_misses::realview.ide 8796 # number of ReadReq misses 1667system.iocache.ReadReq_misses::total 8833 # number of ReadReq misses 1668system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1669system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1670system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1671system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1672system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 1673system.iocache.demand_misses::realview.ide 8796 # number of demand (read+write) misses 1674system.iocache.demand_misses::total 8836 # number of demand (read+write) misses 1675system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 1676system.iocache.overall_misses::realview.ide 8796 # number of overall misses 1677system.iocache.overall_misses::total 8836 # number of overall misses 1678system.iocache.ReadReq_miss_latency::realview.ethernet 5069500 # number of ReadReq miss cycles 1679system.iocache.ReadReq_miss_latency::realview.ide 1678447047 # number of ReadReq miss cycles 1680system.iocache.ReadReq_miss_latency::total 1683516547 # number of ReadReq miss cycles 1681system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 1682system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 1683system.iocache.WriteLineReq_miss_latency::realview.ide 13410212810 # number of WriteLineReq miss cycles 1684system.iocache.WriteLineReq_miss_latency::total 13410212810 # number of WriteLineReq miss cycles 1685system.iocache.demand_miss_latency::realview.ethernet 5420500 # number of demand (read+write) miss cycles 1686system.iocache.demand_miss_latency::realview.ide 1678447047 # number of demand (read+write) miss cycles 1687system.iocache.demand_miss_latency::total 1683867547 # number of demand (read+write) miss cycles 1688system.iocache.overall_miss_latency::realview.ethernet 5420500 # number of overall miss cycles 1689system.iocache.overall_miss_latency::realview.ide 1678447047 # number of overall miss cycles 1690system.iocache.overall_miss_latency::total 1683867547 # number of overall miss cycles 1691system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1692system.iocache.ReadReq_accesses::realview.ide 8796 # number of ReadReq accesses(hits+misses) 1693system.iocache.ReadReq_accesses::total 8833 # number of ReadReq accesses(hits+misses) 1694system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1695system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1696system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 1697system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 1698system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 1699system.iocache.demand_accesses::realview.ide 8796 # number of demand (read+write) accesses 1700system.iocache.demand_accesses::total 8836 # number of demand (read+write) accesses 1701system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 1702system.iocache.overall_accesses::realview.ide 8796 # number of overall (read+write) accesses 1703system.iocache.overall_accesses::total 8836 # number of overall (read+write) accesses 1704system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1705system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1706system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1707system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1708system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1709system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1710system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1711system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1712system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1713system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1714system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1715system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1716system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1717system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137013.513514 # average ReadReq miss latency 1718system.iocache.ReadReq_avg_miss_latency::realview.ide 190819.355048 # average ReadReq miss latency 1719system.iocache.ReadReq_avg_miss_latency::total 190593.971131 # average ReadReq miss latency 1720system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 1721system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 1722system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125723.888191 # average WriteLineReq miss latency 1723system.iocache.WriteLineReq_avg_miss_latency::total 125723.888191 # average WriteLineReq miss latency 1724system.iocache.demand_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency 1725system.iocache.demand_avg_miss_latency::realview.ide 190819.355048 # average overall miss latency 1726system.iocache.demand_avg_miss_latency::total 190568.984495 # average overall miss latency 1727system.iocache.overall_avg_miss_latency::realview.ethernet 135512.500000 # average overall miss latency 1728system.iocache.overall_avg_miss_latency::realview.ide 190819.355048 # average overall miss latency 1729system.iocache.overall_avg_miss_latency::total 190568.984495 # average overall miss latency 1730system.iocache.blocked_cycles::no_mshrs 34452 # number of cycles access was blocked 1731system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1732system.iocache.blocked::no_mshrs 3448 # number of cycles access was blocked 1733system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1734system.iocache.avg_blocked_cycles::no_mshrs 9.991879 # average number of cycles each access was blocked 1735system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1736system.iocache.fast_writes 0 # number of fast writes performed 1737system.iocache.cache_copies 0 # number of cache copies performed 1738system.iocache.writebacks::writebacks 106630 # number of writebacks 1739system.iocache.writebacks::total 106630 # number of writebacks 1740system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 1741system.iocache.ReadReq_mshr_misses::realview.ide 8796 # number of ReadReq MSHR misses 1742system.iocache.ReadReq_mshr_misses::total 8833 # number of ReadReq MSHR misses 1743system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1744system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1745system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 1746system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 1747system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 1748system.iocache.demand_mshr_misses::realview.ide 8796 # number of demand (read+write) MSHR misses 1749system.iocache.demand_mshr_misses::total 8836 # number of demand (read+write) MSHR misses 1750system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 1751system.iocache.overall_mshr_misses::realview.ide 8796 # number of overall MSHR misses 1752system.iocache.overall_mshr_misses::total 8836 # number of overall MSHR misses 1753system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219500 # number of ReadReq MSHR miss cycles 1754system.iocache.ReadReq_mshr_miss_latency::realview.ide 1238647047 # number of ReadReq MSHR miss cycles 1755system.iocache.ReadReq_mshr_miss_latency::total 1241866547 # number of ReadReq MSHR miss cycles 1756system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 1757system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 1758system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8071956842 # number of WriteLineReq MSHR miss cycles 1759system.iocache.WriteLineReq_mshr_miss_latency::total 8071956842 # number of WriteLineReq MSHR miss cycles 1760system.iocache.demand_mshr_miss_latency::realview.ethernet 3420500 # number of demand (read+write) MSHR miss cycles 1761system.iocache.demand_mshr_miss_latency::realview.ide 1238647047 # number of demand (read+write) MSHR miss cycles 1762system.iocache.demand_mshr_miss_latency::total 1242067547 # number of demand (read+write) MSHR miss cycles 1763system.iocache.overall_mshr_miss_latency::realview.ethernet 3420500 # number of overall MSHR miss cycles 1764system.iocache.overall_mshr_miss_latency::realview.ide 1238647047 # number of overall MSHR miss cycles 1765system.iocache.overall_mshr_miss_latency::total 1242067547 # number of overall MSHR miss cycles 1766system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1767system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1768system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1769system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1770system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1771system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1772system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1773system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 1774system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1775system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1776system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 1777system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1778system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1779system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87013.513514 # average ReadReq mshr miss latency 1780system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 140819.355048 # average ReadReq mshr miss latency 1781system.iocache.ReadReq_avg_mshr_miss_latency::total 140593.971131 # average ReadReq mshr miss latency 1782system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 1783system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 1784system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75676.487306 # average WriteLineReq mshr miss latency 1785system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75676.487306 # average WriteLineReq mshr miss latency 1786system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency 1787system.iocache.demand_avg_mshr_miss_latency::realview.ide 140819.355048 # average overall mshr miss latency 1788system.iocache.demand_avg_mshr_miss_latency::total 140568.984495 # average overall mshr miss latency 1789system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85512.500000 # average overall mshr miss latency 1790system.iocache.overall_avg_mshr_miss_latency::realview.ide 140819.355048 # average overall mshr miss latency 1791system.iocache.overall_avg_mshr_miss_latency::total 140568.984495 # average overall mshr miss latency 1792system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1793system.membus.trans_dist::ReadReq 54972 # Transaction distribution 1794system.membus.trans_dist::ReadResp 402203 # Transaction distribution 1795system.membus.trans_dist::WriteReq 33696 # Transaction distribution 1796system.membus.trans_dist::WriteResp 33696 # Transaction distribution 1797system.membus.trans_dist::WritebackDirty 1051260 # Transaction distribution 1798system.membus.trans_dist::CleanEvict 188377 # Transaction distribution 1799system.membus.trans_dist::UpgradeReq 34626 # Transaction distribution 1800system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution 1801system.membus.trans_dist::UpgradeResp 8 # Transaction distribution 1802system.membus.trans_dist::ReadExReq 880179 # Transaction distribution 1803system.membus.trans_dist::ReadExResp 880179 # Transaction distribution 1804system.membus.trans_dist::ReadSharedReq 347231 # Transaction distribution 1805system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution 1806system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 1807system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) 1808system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) 1809system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3643028 # Packet count per connected master and slave (bytes) 1810system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3772648 # Packet count per connected master and slave (bytes) 1811system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237638 # Packet count per connected master and slave (bytes) 1812system.membus.pkt_count_system.iocache.mem_side::total 237638 # Packet count per connected master and slave (bytes) 1813system.membus.pkt_count::total 4010286 # Packet count per connected master and slave (bytes) 1814system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 1815system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 420 # Cumulative packet size per connected master and slave (bytes) 1816system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) 1817system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 138764108 # Cumulative packet size per connected master and slave (bytes) 1818system.membus.pkt_size_system.cpu.l2cache.mem_side::total 138934078 # Cumulative packet size per connected master and slave (bytes) 1819system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7252608 # Cumulative packet size per connected master and slave (bytes) 1820system.membus.pkt_size_system.iocache.mem_side::total 7252608 # Cumulative packet size per connected master and slave (bytes) 1821system.membus.pkt_size::total 146186686 # Cumulative packet size per connected master and slave (bytes) 1822system.membus.snoops 2808 # Total snoops (count) 1823system.membus.snoop_fanout::samples 2697046 # Request fanout histogram 1824system.membus.snoop_fanout::mean 1 # Request fanout histogram 1825system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1826system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1827system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1828system.membus.snoop_fanout::1 2697046 100.00% 100.00% # Request fanout histogram 1829system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1830system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1831system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1832system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1833system.membus.snoop_fanout::total 2697046 # Request fanout histogram 1834system.membus.reqLayer0.occupancy 103954500 # Layer occupancy (ticks) 1835system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1836system.membus.reqLayer1.occupancy 32000 # Layer occupancy (ticks) 1837system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1838system.membus.reqLayer2.occupancy 5466500 # Layer occupancy (ticks) 1839system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1840system.membus.reqLayer5.occupancy 7139670905 # Layer occupancy (ticks) 1841system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1842system.membus.respLayer2.occupancy 6571001988 # Layer occupancy (ticks) 1843system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1844system.membus.respLayer3.occupancy 44720417 # Layer occupancy (ticks) 1845system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1846system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1847system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1848system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1849system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1850system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1851system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1852system.realview.ethernet.txBytes 966 # Bytes Transmitted 1853system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1854system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1855system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1856system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1857system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1858system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1859system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1860system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1861system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) 1862system.realview.ethernet.totPackets 3 # Total Packets 1863system.realview.ethernet.totBytes 966 # Total Bytes 1864system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 1865system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) 1866system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 1867system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1868system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 1869system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1870system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1871system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 1872system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1873system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1874system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 1875system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1876system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1877system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 1878system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1879system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1880system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 1881system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1882system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1883system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 1884system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1885system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1886system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1887system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1888system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1889system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1890system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1891system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1892system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1893system.realview.ethernet.droppedPackets 0 # number of packets dropped 1894system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1895system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1896system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1897system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1898system.cpu.kern.inst.arm 0 # number of arm instructions executed 1899system.cpu.kern.inst.quiesce 16102 # number of quiesce instructions executed 1900 1901---------- End Simulation Statistics ---------- 1902