stats.txt revision 11376:a6968f06a5e0
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.389788 # Number of seconds simulated 4sim_ticks 47389787812000 # Number of ticks simulated 5final_tick 47389787812000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 198747 # Simulator instruction rate (inst/s) 8host_op_rate 233711 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 10002045644 # Simulator tick rate (ticks/s) 10host_mem_usage 770464 # Number of bytes of host memory used 11host_seconds 4738.01 # Real time elapsed on the host 12sim_insts 941666991 # Number of instructions simulated 13sim_ops 1107326086 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 242048 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 235072 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 4481952 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 17644744 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 24714560 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 130176 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 100480 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 2927520 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 10373200 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 13817664 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 418560 # Number of bytes read from this memory 27system.physmem.bytes_read::total 75085976 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 4481952 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 2927520 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 7409472 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 91336640 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 34system.physmem.bytes_written::total 91357224 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 3782 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 3673 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 85983 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 275712 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 386165 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 2034 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 1570 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 45786 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 162094 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 215901 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 6540 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 1189240 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 1427135 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 50system.physmem.num_writes::total 1429709 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 5108 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 4960 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 94576 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 372332 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 521517 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 2747 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 2120 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 61775 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 218891 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 291575 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 8832 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 1584434 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 94576 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 61775 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 156352 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1927349 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::total 1927783 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1927349 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 5108 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 4960 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 94576 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 372766 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 521517 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 2747 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 2120 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 61775 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 218891 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 291575 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 8832 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 3512217 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 1189240 # Number of read requests accepted 84system.physmem.writeReqs 1429709 # Number of write requests accepted 85system.physmem.readBursts 1189240 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 1429709 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 76085248 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 26112 # Total number of bytes read from write queue 89system.physmem.bytesWritten 91355968 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 75085976 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 91357224 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 408 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 75559 # Per bank write bursts 96system.physmem.perBankRdBursts::1 80347 # Per bank write bursts 97system.physmem.perBankRdBursts::2 72779 # Per bank write bursts 98system.physmem.perBankRdBursts::3 76774 # Per bank write bursts 99system.physmem.perBankRdBursts::4 67339 # Per bank write bursts 100system.physmem.perBankRdBursts::5 74455 # Per bank write bursts 101system.physmem.perBankRdBursts::6 73080 # Per bank write bursts 102system.physmem.perBankRdBursts::7 76470 # Per bank write bursts 103system.physmem.perBankRdBursts::8 66258 # Per bank write bursts 104system.physmem.perBankRdBursts::9 90024 # Per bank write bursts 105system.physmem.perBankRdBursts::10 66637 # Per bank write bursts 106system.physmem.perBankRdBursts::11 75253 # Per bank write bursts 107system.physmem.perBankRdBursts::12 70442 # Per bank write bursts 108system.physmem.perBankRdBursts::13 75330 # Per bank write bursts 109system.physmem.perBankRdBursts::14 75010 # Per bank write bursts 110system.physmem.perBankRdBursts::15 73075 # Per bank write bursts 111system.physmem.perBankWrBursts::0 90501 # Per bank write bursts 112system.physmem.perBankWrBursts::1 95401 # Per bank write bursts 113system.physmem.perBankWrBursts::2 90023 # Per bank write bursts 114system.physmem.perBankWrBursts::3 92589 # Per bank write bursts 115system.physmem.perBankWrBursts::4 84855 # Per bank write bursts 116system.physmem.perBankWrBursts::5 90903 # Per bank write bursts 117system.physmem.perBankWrBursts::6 89246 # Per bank write bursts 118system.physmem.perBankWrBursts::7 91287 # Per bank write bursts 119system.physmem.perBankWrBursts::8 85201 # Per bank write bursts 120system.physmem.perBankWrBursts::9 88427 # Per bank write bursts 121system.physmem.perBankWrBursts::10 83204 # Per bank write bursts 122system.physmem.perBankWrBursts::11 90055 # Per bank write bursts 123system.physmem.perBankWrBursts::12 88087 # Per bank write bursts 124system.physmem.perBankWrBursts::13 89545 # Per bank write bursts 125system.physmem.perBankWrBursts::14 89641 # Per bank write bursts 126system.physmem.perBankWrBursts::15 88472 # Per bank write bursts 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 128system.physmem.numWrRetry 54 # Number of times write queue was full causing retry 129system.physmem.totGap 47389786204500 # Total gap between requests 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 0 # Read request sizes (log2) 133system.physmem.readPktSize::3 25 # Read request sizes (log2) 134system.physmem.readPktSize::4 21333 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) 136system.physmem.readPktSize::6 1167882 # Read request sizes (log2) 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) 140system.physmem.writePktSize::3 2572 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) 143system.physmem.writePktSize::6 1427135 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 517223 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 309889 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 86868 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 62308 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 44912 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 40171 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 37097 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 35200 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 31021 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 8620 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 4820 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 3062 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 2092 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 1731 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 1164 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 973 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 801 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 612 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 168 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 91 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 7 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 2 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::15 27129 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 32204 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 45048 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 50289 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 57286 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 61809 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 67754 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 74659 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 80821 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 85044 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 90854 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 96241 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 95504 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 100014 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 112663 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 99616 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 90045 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 84036 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 13635 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 10081 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 8296 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 6959 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 5731 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 4894 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 4062 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 3275 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 2801 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 2368 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 2057 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 1806 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 1553 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 1352 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 1254 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 1017 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 979 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 831 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 620 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 596 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 417 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 389 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 296 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 250 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 175 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 141 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 152 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 108 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 118 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 65 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 154 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 1166319 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 143.563495 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 97.562003 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 190.410734 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 788306 67.59% 67.59% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 223066 19.13% 86.71% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 56490 4.84% 91.56% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 24874 2.13% 93.69% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 21482 1.84% 95.53% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 12177 1.04% 96.58% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 8088 0.69% 97.27% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 4845 0.42% 97.69% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 26991 2.31% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 1166319 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 68435 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 17.371564 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 68.388871 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-511 68432 100.00% 100.00% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::512-1023 1 0.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::total 68435 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 68435 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 20.858289 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 17.984573 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 74.928718 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::0-127 68190 99.64% 99.64% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::128-255 151 0.22% 99.86% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::256-383 21 0.03% 99.89% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::384-511 14 0.02% 99.91% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::512-639 8 0.01% 99.93% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::640-767 2 0.00% 99.93% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::768-895 5 0.01% 99.94% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::896-1023 6 0.01% 99.94% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::1024-1151 3 0.00% 99.95% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::1152-1279 2 0.00% 99.95% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::1280-1407 2 0.00% 99.95% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::1536-1663 2 0.00% 99.96% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::1664-1791 4 0.01% 99.96% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::1792-1919 2 0.00% 99.97% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::2304-2431 4 0.01% 99.97% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::2432-2559 5 0.01% 99.98% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::2560-2687 1 0.00% 99.98% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::2688-2815 1 0.00% 99.98% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::2816-2943 1 0.00% 99.98% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::2944-3071 2 0.00% 99.99% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::3072-3199 1 0.00% 99.99% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::3584-3711 1 0.00% 99.99% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::3712-3839 1 0.00% 99.99% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::4096-4223 1 0.00% 99.99% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::4224-4351 1 0.00% 99.99% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::4864-4991 1 0.00% 100.00% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::5504-5631 1 0.00% 100.00% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::6656-6783 1 0.00% 100.00% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::7680-7807 1 0.00% 100.00% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::total 68435 # Writes before turning the bus around for reads 296system.physmem.totQLat 53856464568 # Total ticks spent queuing 297system.physmem.totMemAccLat 76147064568 # Total ticks spent from burst creation until serviced by the DRAM 298system.physmem.totBusLat 5944160000 # Total ticks spent in databus transfers 299system.physmem.avgQLat 45302.00 # Average queueing delay per DRAM burst 300system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 301system.physmem.avgMemAccLat 64052.00 # Average memory access latency per DRAM burst 302system.physmem.avgRdBW 1.61 # Average DRAM read bandwidth in MiByte/s 303system.physmem.avgWrBW 1.93 # Average achieved write bandwidth in MiByte/s 304system.physmem.avgRdBWSys 1.58 # Average system read bandwidth in MiByte/s 305system.physmem.avgWrBWSys 1.93 # Average system write bandwidth in MiByte/s 306system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 307system.physmem.busUtil 0.03 # Data bus utilization in percentage 308system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 309system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 310system.physmem.avgRdQLen 1.31 # Average read queue length when enqueuing 311system.physmem.avgWrQLen 23.02 # Average write queue length when enqueuing 312system.physmem.readRowHits 898304 # Number of row buffer hits during reads 313system.physmem.writeRowHits 551645 # Number of row buffer hits during writes 314system.physmem.readRowHitRate 75.56 # Row buffer hit rate for reads 315system.physmem.writeRowHitRate 38.65 # Row buffer hit rate for writes 316system.physmem.avgGap 18094963.36 # Average gap between requests 317system.physmem.pageHitRate 55.42 # Row buffer hit rate, read and write combined 318system.physmem_0.actEnergy 4527963720 # Energy for activate commands per rank (pJ) 319system.physmem_0.preEnergy 2470615125 # Energy for precharge commands per rank (pJ) 320system.physmem_0.readEnergy 4655063400 # Energy for read commands per rank (pJ) 321system.physmem_0.writeEnergy 4696736400 # Energy for write commands per rank (pJ) 322system.physmem_0.refreshEnergy 3095270087520 # Energy for refresh commands per rank (pJ) 323system.physmem_0.actBackEnergy 1182204826065 # Energy for active background per rank (pJ) 324system.physmem_0.preBackEnergy 27396846617250 # Energy for precharge background per rank (pJ) 325system.physmem_0.totalEnergy 31690671909480 # Total energy per rank (pJ) 326system.physmem_0.averagePower 668.723752 # Core power per rank (mW) 327system.physmem_0.memoryStateTime::IDLE 45576929865903 # Time in different power states 328system.physmem_0.memoryStateTime::REF 1582448920000 # Time in different power states 329system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 330system.physmem_0.memoryStateTime::ACT 230401885347 # Time in different power states 331system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 332system.physmem_1.actEnergy 4289407920 # Energy for activate commands per rank (pJ) 333system.physmem_1.preEnergy 2340450750 # Energy for precharge commands per rank (pJ) 334system.physmem_1.readEnergy 4617779400 # Energy for read commands per rank (pJ) 335system.physmem_1.writeEnergy 4553055360 # Energy for write commands per rank (pJ) 336system.physmem_1.refreshEnergy 3095270087520 # Energy for refresh commands per rank (pJ) 337system.physmem_1.actBackEnergy 1179475938810 # Energy for active background per rank (pJ) 338system.physmem_1.preBackEnergy 27399240378000 # Energy for precharge background per rank (pJ) 339system.physmem_1.totalEnergy 31689787097760 # Total energy per rank (pJ) 340system.physmem_1.averagePower 668.705081 # Core power per rank (mW) 341system.physmem_1.memoryStateTime::IDLE 45580905738073 # Time in different power states 342system.physmem_1.memoryStateTime::REF 1582448920000 # Time in different power states 343system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 344system.physmem_1.memoryStateTime::ACT 226432462927 # Time in different power states 345system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 346system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory 347system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 348system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory 349system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 350system.realview.nvmem.bytes_read::total 556 # Number of bytes read from this memory 351system.realview.nvmem.bytes_inst_read::cpu0.inst 368 # Number of instructions bytes read from this memory 352system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory 353system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory 354system.realview.nvmem.num_reads::cpu0.inst 23 # Number of read requests responded to by this memory 355system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 356system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory 357system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 358system.realview.nvmem.num_reads::total 38 # Number of read requests responded to by this memory 359system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) 360system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 361system.realview.nvmem.bw_read::cpu1.inst 3 # Total read bandwidth from this memory (bytes/s) 362system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 363system.realview.nvmem.bw_read::total 12 # Total read bandwidth from this memory (bytes/s) 364system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) 365system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s) 366system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s) 367system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) 368system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 369system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) 370system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 371system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) 372system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 373system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 374system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 375system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 376system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 377system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 378system.cpu0.branchPred.lookups 148316317 # Number of BP lookups 379system.cpu0.branchPred.condPredicted 98700135 # Number of conditional branches predicted 380system.cpu0.branchPred.condIncorrect 7173487 # Number of conditional branches incorrect 381system.cpu0.branchPred.BTBLookups 104790534 # Number of BTB lookups 382system.cpu0.branchPred.BTBHits 69246034 # Number of BTB hits 383system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 384system.cpu0.branchPred.BTBHitPct 66.080429 # BTB Hit Percentage 385system.cpu0.branchPred.usedRAS 20257126 # Number of times the RAS was used to get a target. 386system.cpu0.branchPred.RASInCorrect 200970 # Number of incorrect RAS predictions. 387system.cpu_clk_domain.clock 500 # Clock period in ticks 388system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 389system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 390system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 391system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 392system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 393system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 394system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 396system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 397system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 398system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 399system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 400system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 401system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 402system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 403system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 404system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 405system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 406system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 407system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 408system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 409system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 410system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 411system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 412system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 413system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 414system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 415system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 416system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 417system.cpu0.dtb.walker.walks 656451 # Table walker walks requested 418system.cpu0.dtb.walker.walksLong 656451 # Table walker walks initiated with long descriptors 419system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 15175 # Level at which table walker walks with long descriptors terminate 420system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 105539 # Level at which table walker walks with long descriptors terminate 421system.cpu0.dtb.walker.walksSquashedBefore 311743 # Table walks squashed before starting 422system.cpu0.dtb.walker.walkWaitTime::samples 344708 # Table walker wait (enqueue to first request) latency 423system.cpu0.dtb.walker.walkWaitTime::mean 2528.499484 # Table walker wait (enqueue to first request) latency 424system.cpu0.dtb.walker.walkWaitTime::stdev 15542.861274 # Table walker wait (enqueue to first request) latency 425system.cpu0.dtb.walker.walkWaitTime::0-65535 341657 99.11% 99.11% # Table walker wait (enqueue to first request) latency 426system.cpu0.dtb.walker.walkWaitTime::65536-131071 1528 0.44% 99.56% # Table walker wait (enqueue to first request) latency 427system.cpu0.dtb.walker.walkWaitTime::131072-196607 1197 0.35% 99.91% # Table walker wait (enqueue to first request) latency 428system.cpu0.dtb.walker.walkWaitTime::196608-262143 153 0.04% 99.95% # Table walker wait (enqueue to first request) latency 429system.cpu0.dtb.walker.walkWaitTime::262144-327679 49 0.01% 99.96% # Table walker wait (enqueue to first request) latency 430system.cpu0.dtb.walker.walkWaitTime::327680-393215 98 0.03% 99.99% # Table walker wait (enqueue to first request) latency 431system.cpu0.dtb.walker.walkWaitTime::393216-458751 19 0.01% 100.00% # Table walker wait (enqueue to first request) latency 432system.cpu0.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 433system.cpu0.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 434system.cpu0.dtb.walker.walkWaitTime::655360-720895 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 435system.cpu0.dtb.walker.walkWaitTime::total 344708 # Table walker wait (enqueue to first request) latency 436system.cpu0.dtb.walker.walkCompletionTime::samples 348998 # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::mean 21459.124408 # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walkCompletionTime::gmean 17964.910208 # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walkCompletionTime::stdev 23694.067201 # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walkCompletionTime::0-65535 343876 98.53% 98.53% # Table walker service (enqueue to completion) latency 441system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1141 0.33% 98.86% # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walkCompletionTime::131072-196607 2753 0.79% 99.65% # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::196608-262143 227 0.07% 99.71% # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::262144-327679 627 0.18% 99.89% # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walkCompletionTime::327680-393215 192 0.06% 99.95% # Table walker service (enqueue to completion) latency 446system.cpu0.dtb.walker.walkCompletionTime::393216-458751 104 0.03% 99.98% # Table walker service (enqueue to completion) latency 447system.cpu0.dtb.walker.walkCompletionTime::458752-524287 60 0.02% 99.99% # Table walker service (enqueue to completion) latency 448system.cpu0.dtb.walker.walkCompletionTime::524288-589823 15 0.00% 100.00% # Table walker service (enqueue to completion) latency 449system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 450system.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 451system.cpu0.dtb.walker.walkCompletionTime::total 348998 # Table walker service (enqueue to completion) latency 452system.cpu0.dtb.walker.walksPending::samples 578933652396 # Table walker pending requests distribution 453system.cpu0.dtb.walker.walksPending::mean 0.598699 # Table walker pending requests distribution 454system.cpu0.dtb.walker.walksPending::stdev 0.548790 # Table walker pending requests distribution 455system.cpu0.dtb.walker.walksPending::0-1 577357711896 99.73% 99.73% # Table walker pending requests distribution 456system.cpu0.dtb.walker.walksPending::2-3 896498000 0.15% 99.88% # Table walker pending requests distribution 457system.cpu0.dtb.walker.walksPending::4-5 316445000 0.05% 99.94% # Table walker pending requests distribution 458system.cpu0.dtb.walker.walksPending::6-7 146967500 0.03% 99.96% # Table walker pending requests distribution 459system.cpu0.dtb.walker.walksPending::8-9 111299500 0.02% 99.98% # Table walker pending requests distribution 460system.cpu0.dtb.walker.walksPending::10-11 56334000 0.01% 99.99% # Table walker pending requests distribution 461system.cpu0.dtb.walker.walksPending::12-13 19702000 0.00% 100.00% # Table walker pending requests distribution 462system.cpu0.dtb.walker.walksPending::14-15 27806500 0.00% 100.00% # Table walker pending requests distribution 463system.cpu0.dtb.walker.walksPending::16-17 847500 0.00% 100.00% # Table walker pending requests distribution 464system.cpu0.dtb.walker.walksPending::18-19 17500 0.00% 100.00% # Table walker pending requests distribution 465system.cpu0.dtb.walker.walksPending::20-21 1000 0.00% 100.00% # Table walker pending requests distribution 466system.cpu0.dtb.walker.walksPending::22-23 1500 0.00% 100.00% # Table walker pending requests distribution 467system.cpu0.dtb.walker.walksPending::24-25 1500 0.00% 100.00% # Table walker pending requests distribution 468system.cpu0.dtb.walker.walksPending::26-27 2500 0.00% 100.00% # Table walker pending requests distribution 469system.cpu0.dtb.walker.walksPending::28-29 1500 0.00% 100.00% # Table walker pending requests distribution 470system.cpu0.dtb.walker.walksPending::30-31 15000 0.00% 100.00% # Table walker pending requests distribution 471system.cpu0.dtb.walker.walksPending::total 578933652396 # Table walker pending requests distribution 472system.cpu0.dtb.walker.walkPageSizes::4K 105540 87.43% 87.43% # Table walker page sizes translated 473system.cpu0.dtb.walker.walkPageSizes::2M 15175 12.57% 100.00% # Table walker page sizes translated 474system.cpu0.dtb.walker.walkPageSizes::total 120715 # Table walker page sizes translated 475system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 656451 # Table walker requests started/completed, data/inst 476system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 477system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 656451 # Table walker requests started/completed, data/inst 478system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 120715 # Table walker requests started/completed, data/inst 479system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 480system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 120715 # Table walker requests started/completed, data/inst 481system.cpu0.dtb.walker.walkRequestOrigin::total 777166 # Table walker requests started/completed, data/inst 482system.cpu0.dtb.inst_hits 0 # ITB inst hits 483system.cpu0.dtb.inst_misses 0 # ITB inst misses 484system.cpu0.dtb.read_hits 108931388 # DTB read hits 485system.cpu0.dtb.read_misses 471682 # DTB read misses 486system.cpu0.dtb.write_hits 89197418 # DTB write hits 487system.cpu0.dtb.write_misses 184769 # DTB write misses 488system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed 489system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 490system.cpu0.dtb.flush_tlb_mva_asid 46180 # Number of times TLB was flushed by MVA & ASID 491system.cpu0.dtb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID 492system.cpu0.dtb.flush_entries 44365 # Number of entries that have been flushed from TLB 493system.cpu0.dtb.align_faults 621 # Number of TLB faults due to alignment restrictions 494system.cpu0.dtb.prefetch_faults 7762 # Number of TLB faults due to prefetch 495system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 496system.cpu0.dtb.perms_faults 42293 # Number of TLB faults due to permissions restrictions 497system.cpu0.dtb.read_accesses 109403070 # DTB read accesses 498system.cpu0.dtb.write_accesses 89382187 # DTB write accesses 499system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 500system.cpu0.dtb.hits 198128806 # DTB hits 501system.cpu0.dtb.misses 656451 # DTB misses 502system.cpu0.dtb.accesses 198785257 # DTB accesses 503system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 504system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 505system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 506system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 507system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 508system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 509system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 510system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 511system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 512system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 513system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 514system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 515system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 516system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 517system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 518system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 519system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 520system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 521system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 522system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 523system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 524system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 525system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 526system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 527system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 528system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 529system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 530system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 531system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 532system.cpu0.itb.walker.walks 90363 # Table walker walks requested 533system.cpu0.itb.walker.walksLong 90363 # Table walker walks initiated with long descriptors 534system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1091 # Level at which table walker walks with long descriptors terminate 535system.cpu0.itb.walker.walksLongTerminationLevel::Level3 64708 # Level at which table walker walks with long descriptors terminate 536system.cpu0.itb.walker.walksSquashedBefore 10655 # Table walks squashed before starting 537system.cpu0.itb.walker.walkWaitTime::samples 79708 # Table walker wait (enqueue to first request) latency 538system.cpu0.itb.walker.walkWaitTime::mean 1706.014453 # Table walker wait (enqueue to first request) latency 539system.cpu0.itb.walker.walkWaitTime::stdev 13195.811582 # Table walker wait (enqueue to first request) latency 540system.cpu0.itb.walker.walkWaitTime::0-32767 78781 98.84% 98.84% # Table walker wait (enqueue to first request) latency 541system.cpu0.itb.walker.walkWaitTime::32768-65535 448 0.56% 99.40% # Table walker wait (enqueue to first request) latency 542system.cpu0.itb.walker.walkWaitTime::65536-98303 48 0.06% 99.46% # Table walker wait (enqueue to first request) latency 543system.cpu0.itb.walker.walkWaitTime::98304-131071 68 0.09% 99.54% # Table walker wait (enqueue to first request) latency 544system.cpu0.itb.walker.walkWaitTime::131072-163839 262 0.33% 99.87% # Table walker wait (enqueue to first request) latency 545system.cpu0.itb.walker.walkWaitTime::163840-196607 71 0.09% 99.96% # Table walker wait (enqueue to first request) latency 546system.cpu0.itb.walker.walkWaitTime::196608-229375 3 0.00% 99.97% # Table walker wait (enqueue to first request) latency 547system.cpu0.itb.walker.walkWaitTime::229376-262143 4 0.01% 99.97% # Table walker wait (enqueue to first request) latency 548system.cpu0.itb.walker.walkWaitTime::262144-294911 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency 549system.cpu0.itb.walker.walkWaitTime::294912-327679 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency 550system.cpu0.itb.walker.walkWaitTime::327680-360447 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency 551system.cpu0.itb.walker.walkWaitTime::360448-393215 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency 552system.cpu0.itb.walker.walkWaitTime::393216-425983 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 553system.cpu0.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 554system.cpu0.itb.walker.walkWaitTime::491520-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 555system.cpu0.itb.walker.walkWaitTime::total 79708 # Table walker wait (enqueue to first request) latency 556system.cpu0.itb.walker.walkCompletionTime::samples 76454 # Table walker service (enqueue to completion) latency 557system.cpu0.itb.walker.walkCompletionTime::mean 28396.329819 # Table walker service (enqueue to completion) latency 558system.cpu0.itb.walker.walkCompletionTime::gmean 23477.172430 # Table walker service (enqueue to completion) latency 559system.cpu0.itb.walker.walkCompletionTime::stdev 32204.710724 # Table walker service (enqueue to completion) latency 560system.cpu0.itb.walker.walkCompletionTime::0-65535 73773 96.49% 96.49% # Table walker service (enqueue to completion) latency 561system.cpu0.itb.walker.walkCompletionTime::65536-131071 162 0.21% 96.71% # Table walker service (enqueue to completion) latency 562system.cpu0.itb.walker.walkCompletionTime::131072-196607 2119 2.77% 99.48% # Table walker service (enqueue to completion) latency 563system.cpu0.itb.walker.walkCompletionTime::196608-262143 153 0.20% 99.68% # Table walker service (enqueue to completion) latency 564system.cpu0.itb.walker.walkCompletionTime::262144-327679 135 0.18% 99.85% # Table walker service (enqueue to completion) latency 565system.cpu0.itb.walker.walkCompletionTime::327680-393215 40 0.05% 99.91% # Table walker service (enqueue to completion) latency 566system.cpu0.itb.walker.walkCompletionTime::393216-458751 46 0.06% 99.97% # Table walker service (enqueue to completion) latency 567system.cpu0.itb.walker.walkCompletionTime::458752-524287 11 0.01% 99.98% # Table walker service (enqueue to completion) latency 568system.cpu0.itb.walker.walkCompletionTime::524288-589823 8 0.01% 99.99% # Table walker service (enqueue to completion) latency 569system.cpu0.itb.walker.walkCompletionTime::589824-655359 5 0.01% 100.00% # Table walker service (enqueue to completion) latency 570system.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 571system.cpu0.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 572system.cpu0.itb.walker.walkCompletionTime::total 76454 # Table walker service (enqueue to completion) latency 573system.cpu0.itb.walker.walksPending::samples 441465071924 # Table walker pending requests distribution 574system.cpu0.itb.walker.walksPending::mean 0.843066 # Table walker pending requests distribution 575system.cpu0.itb.walker.walksPending::stdev 0.363947 # Table walker pending requests distribution 576system.cpu0.itb.walker.walksPending::0 69311314608 15.70% 15.70% # Table walker pending requests distribution 577system.cpu0.itb.walker.walksPending::1 372126528316 84.29% 99.99% # Table walker pending requests distribution 578system.cpu0.itb.walker.walksPending::2 24340500 0.01% 100.00% # Table walker pending requests distribution 579system.cpu0.itb.walker.walksPending::3 2776500 0.00% 100.00% # Table walker pending requests distribution 580system.cpu0.itb.walker.walksPending::4 112000 0.00% 100.00% # Table walker pending requests distribution 581system.cpu0.itb.walker.walksPending::total 441465071924 # Table walker pending requests distribution 582system.cpu0.itb.walker.walkPageSizes::4K 64708 98.34% 98.34% # Table walker page sizes translated 583system.cpu0.itb.walker.walkPageSizes::2M 1091 1.66% 100.00% # Table walker page sizes translated 584system.cpu0.itb.walker.walkPageSizes::total 65799 # Table walker page sizes translated 585system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 586system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 90363 # Table walker requests started/completed, data/inst 587system.cpu0.itb.walker.walkRequestOrigin_Requested::total 90363 # Table walker requests started/completed, data/inst 588system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 589system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 65799 # Table walker requests started/completed, data/inst 590system.cpu0.itb.walker.walkRequestOrigin_Completed::total 65799 # Table walker requests started/completed, data/inst 591system.cpu0.itb.walker.walkRequestOrigin::total 156162 # Table walker requests started/completed, data/inst 592system.cpu0.itb.inst_hits 234328898 # ITB inst hits 593system.cpu0.itb.inst_misses 90363 # ITB inst misses 594system.cpu0.itb.read_hits 0 # DTB read hits 595system.cpu0.itb.read_misses 0 # DTB read misses 596system.cpu0.itb.write_hits 0 # DTB write hits 597system.cpu0.itb.write_misses 0 # DTB write misses 598system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed 599system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 600system.cpu0.itb.flush_tlb_mva_asid 46180 # Number of times TLB was flushed by MVA & ASID 601system.cpu0.itb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID 602system.cpu0.itb.flush_entries 32417 # Number of entries that have been flushed from TLB 603system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 604system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 605system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 606system.cpu0.itb.perms_faults 232055 # Number of TLB faults due to permissions restrictions 607system.cpu0.itb.read_accesses 0 # DTB read accesses 608system.cpu0.itb.write_accesses 0 # DTB write accesses 609system.cpu0.itb.inst_accesses 234419261 # ITB inst accesses 610system.cpu0.itb.hits 234328898 # DTB hits 611system.cpu0.itb.misses 90363 # DTB misses 612system.cpu0.itb.accesses 234419261 # DTB accesses 613system.cpu0.numCycles 866695747 # number of cpu cycles simulated 614system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 615system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 616system.cpu0.fetch.icacheStallCycles 96427999 # Number of cycles fetch is stalled on an Icache miss 617system.cpu0.fetch.Insts 657049317 # Number of instructions fetch has processed 618system.cpu0.fetch.Branches 148316317 # Number of branches that fetch encountered 619system.cpu0.fetch.predictedBranches 89503160 # Number of branches that fetch has predicted taken 620system.cpu0.fetch.Cycles 718043211 # Number of cycles fetch has run and was not squashing or blocked 621system.cpu0.fetch.SquashCycles 15454228 # Number of cycles fetch has spent squashing 622system.cpu0.fetch.TlbCycles 2249933 # Number of cycles fetch has spent waiting for tlb 623system.cpu0.fetch.MiscStallCycles 346517 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 624system.cpu0.fetch.PendingTrapStallCycles 6840136 # Number of stall cycles due to pending traps 625system.cpu0.fetch.PendingQuiesceStallCycles 871998 # Number of stall cycles due to pending quiesce instructions 626system.cpu0.fetch.IcacheWaitRetryStallCycles 916038 # Number of stall cycles due to full MSHR 627system.cpu0.fetch.CacheLines 234095625 # Number of cache lines fetched 628system.cpu0.fetch.IcacheSquashes 1822748 # Number of outstanding Icache misses that were squashed 629system.cpu0.fetch.ItlbSquashes 30173 # Number of outstanding ITLB misses that were squashed 630system.cpu0.fetch.rateDist::samples 833422946 # Number of instructions fetched each cycle (Total) 631system.cpu0.fetch.rateDist::mean 0.924189 # Number of instructions fetched each cycle (Total) 632system.cpu0.fetch.rateDist::stdev 1.205964 # Number of instructions fetched each cycle (Total) 633system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 634system.cpu0.fetch.rateDist::0 464359111 55.72% 55.72% # Number of instructions fetched each cycle (Total) 635system.cpu0.fetch.rateDist::1 143558418 17.23% 72.94% # Number of instructions fetched each cycle (Total) 636system.cpu0.fetch.rateDist::2 49834021 5.98% 78.92% # Number of instructions fetched each cycle (Total) 637system.cpu0.fetch.rateDist::3 175671396 21.08% 100.00% # Number of instructions fetched each cycle (Total) 638system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 639system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 640system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 641system.cpu0.fetch.rateDist::total 833422946 # Number of instructions fetched each cycle (Total) 642system.cpu0.fetch.branchRate 0.171128 # Number of branch fetches per cycle 643system.cpu0.fetch.rate 0.758108 # Number of inst fetches per cycle 644system.cpu0.decode.IdleCycles 115740257 # Number of cycles decode is idle 645system.cpu0.decode.BlockedCycles 426691474 # Number of cycles decode is blocked 646system.cpu0.decode.RunCycles 243999178 # Number of cycles decode is running 647system.cpu0.decode.UnblockCycles 41506758 # Number of cycles decode is unblocking 648system.cpu0.decode.SquashCycles 5485279 # Number of cycles decode is squashing 649system.cpu0.decode.BranchResolved 21281954 # Number of times decode resolved a branch 650system.cpu0.decode.BranchMispred 2285386 # Number of times decode detected a branch misprediction 651system.cpu0.decode.DecodedInsts 681861872 # Number of instructions handled by decode 652system.cpu0.decode.SquashedInsts 24692274 # Number of squashed instructions handled by decode 653system.cpu0.rename.SquashCycles 5485279 # Number of cycles rename is squashing 654system.cpu0.rename.IdleCycles 154051427 # Number of cycles rename is idle 655system.cpu0.rename.BlockCycles 67882232 # Number of cycles rename is blocking 656system.cpu0.rename.serializeStallCycles 271801592 # count of cycles rename stalled for serializing inst 657system.cpu0.rename.RunCycles 246639237 # Number of cycles rename is running 658system.cpu0.rename.UnblockCycles 87563179 # Number of cycles rename is unblocking 659system.cpu0.rename.RenamedInsts 663764828 # Number of instructions processed by rename 660system.cpu0.rename.SquashedInsts 6318012 # Number of squashed instructions processed by rename 661system.cpu0.rename.ROBFullEvents 12552479 # Number of times rename has blocked due to ROB full 662system.cpu0.rename.IQFullEvents 452890 # Number of times rename has blocked due to IQ full 663system.cpu0.rename.LQFullEvents 885924 # Number of times rename has blocked due to LQ full 664system.cpu0.rename.SQFullEvents 48607179 # Number of times rename has blocked due to SQ full 665system.cpu0.rename.FullRegisterEvents 12032 # Number of times there has been no free registers 666system.cpu0.rename.RenamedOperands 634283684 # Number of destination operands rename has renamed 667system.cpu0.rename.RenameLookups 1028589268 # Number of register rename lookups that rename has made 668system.cpu0.rename.int_rename_lookups 784350114 # Number of integer rename lookups 669system.cpu0.rename.fp_rename_lookups 810310 # Number of floating rename lookups 670system.cpu0.rename.CommittedMaps 573100551 # Number of HB maps that are committed 671system.cpu0.rename.UndoneMaps 61183133 # Number of HB maps that are undone due to squashing 672system.cpu0.rename.serializingInsts 17365169 # count of serializing insts renamed 673system.cpu0.rename.tempSerializingInsts 15184195 # count of temporary serializing insts renamed 674system.cpu0.rename.skidInsts 83196676 # count of insts added to the skid buffer 675system.cpu0.memDep0.insertedLoads 108756528 # Number of loads inserted to the mem dependence unit. 676system.cpu0.memDep0.insertedStores 92814116 # Number of stores inserted to the mem dependence unit. 677system.cpu0.memDep0.conflictingLoads 10086189 # Number of conflicting loads. 678system.cpu0.memDep0.conflictingStores 8556855 # Number of conflicting stores. 679system.cpu0.iq.iqInstsAdded 639440304 # Number of instructions added to the IQ (excludes non-spec) 680system.cpu0.iq.iqNonSpecInstsAdded 17486234 # Number of non-speculative instructions added to the IQ 681system.cpu0.iq.iqInstsIssued 645371130 # Number of instructions issued 682system.cpu0.iq.iqSquashedInstsIssued 2878587 # Number of squashed instructions issued 683system.cpu0.iq.iqSquashedInstsExamined 57563182 # Number of squashed instructions iterated over during squash; mainly for profiling 684system.cpu0.iq.iqSquashedOperandsExamined 37565263 # Number of squashed operands that are examined and possibly removed from graph 685system.cpu0.iq.iqSquashedNonSpecRemoved 301808 # Number of squashed non-spec instructions that were removed 686system.cpu0.iq.issued_per_cycle::samples 833422946 # Number of insts issued each cycle 687system.cpu0.iq.issued_per_cycle::mean 0.774362 # Number of insts issued each cycle 688system.cpu0.iq.issued_per_cycle::stdev 1.052683 # Number of insts issued each cycle 689system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 690system.cpu0.iq.issued_per_cycle::0 480257343 57.62% 57.62% # Number of insts issued each cycle 691system.cpu0.iq.issued_per_cycle::1 149217372 17.90% 75.53% # Number of insts issued each cycle 692system.cpu0.iq.issued_per_cycle::2 124187121 14.90% 90.43% # Number of insts issued each cycle 693system.cpu0.iq.issued_per_cycle::3 71270973 8.55% 98.98% # Number of insts issued each cycle 694system.cpu0.iq.issued_per_cycle::4 8484088 1.02% 100.00% # Number of insts issued each cycle 695system.cpu0.iq.issued_per_cycle::5 6049 0.00% 100.00% # Number of insts issued each cycle 696system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 697system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 698system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 699system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 700system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 701system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 702system.cpu0.iq.issued_per_cycle::total 833422946 # Number of insts issued each cycle 703system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 704system.cpu0.iq.fu_full::IntAlu 66055625 45.01% 45.01% # attempts to use FU when none available 705system.cpu0.iq.fu_full::IntMult 69293 0.05% 45.06% # attempts to use FU when none available 706system.cpu0.iq.fu_full::IntDiv 22404 0.02% 45.08% # attempts to use FU when none available 707system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.08% # attempts to use FU when none available 708system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.08% # attempts to use FU when none available 709system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.08% # attempts to use FU when none available 710system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.08% # attempts to use FU when none available 711system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.08% # attempts to use FU when none available 712system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.08% # attempts to use FU when none available 713system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.08% # attempts to use FU when none available 714system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.08% # attempts to use FU when none available 715system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.08% # attempts to use FU when none available 716system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.08% # attempts to use FU when none available 717system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.08% # attempts to use FU when none available 718system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.08% # attempts to use FU when none available 719system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.08% # attempts to use FU when none available 720system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.08% # attempts to use FU when none available 721system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.08% # attempts to use FU when none available 722system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.08% # attempts to use FU when none available 723system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.08% # attempts to use FU when none available 724system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.08% # attempts to use FU when none available 725system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.08% # attempts to use FU when none available 726system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.08% # attempts to use FU when none available 727system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.08% # attempts to use FU when none available 728system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.08% # attempts to use FU when none available 729system.cpu0.iq.fu_full::SimdFloatMisc 17 0.00% 45.08% # attempts to use FU when none available 730system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.08% # attempts to use FU when none available 731system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.08% # attempts to use FU when none available 732system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.08% # attempts to use FU when none available 733system.cpu0.iq.fu_full::MemRead 38927283 26.53% 71.60% # attempts to use FU when none available 734system.cpu0.iq.fu_full::MemWrite 41671380 28.40% 100.00% # attempts to use FU when none available 735system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 736system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 737system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 738system.cpu0.iq.FU_type_0::IntAlu 440798988 68.30% 68.30% # Type of FU issued 739system.cpu0.iq.FU_type_0::IntMult 1592862 0.25% 68.55% # Type of FU issued 740system.cpu0.iq.FU_type_0::IntDiv 83426 0.01% 68.56% # Type of FU issued 741system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.56% # Type of FU issued 742system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.56% # Type of FU issued 743system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.56% # Type of FU issued 744system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.56% # Type of FU issued 745system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.56% # Type of FU issued 746system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.56% # Type of FU issued 747system.cpu0.iq.FU_type_0::SimdAdd 2 0.00% 68.56% # Type of FU issued 748system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.56% # Type of FU issued 749system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.56% # Type of FU issued 750system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.56% # Type of FU issued 751system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.56% # Type of FU issued 752system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.56% # Type of FU issued 753system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.56% # Type of FU issued 754system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.56% # Type of FU issued 755system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.56% # Type of FU issued 756system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.56% # Type of FU issued 757system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.56% # Type of FU issued 758system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.56% # Type of FU issued 759system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.56% # Type of FU issued 760system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.56% # Type of FU issued 761system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.56% # Type of FU issued 762system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.56% # Type of FU issued 763system.cpu0.iq.FU_type_0::SimdFloatMisc 82619 0.01% 68.57% # Type of FU issued 764system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.57% # Type of FU issued 765system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.57% # Type of FU issued 766system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.57% # Type of FU issued 767system.cpu0.iq.FU_type_0::MemRead 112232372 17.39% 85.96% # Type of FU issued 768system.cpu0.iq.FU_type_0::MemWrite 90580861 14.04% 100.00% # Type of FU issued 769system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 770system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 771system.cpu0.iq.FU_type_0::total 645371130 # Type of FU issued 772system.cpu0.iq.rate 0.744634 # Inst issue rate 773system.cpu0.iq.fu_busy_cnt 146746002 # FU busy when requested 774system.cpu0.iq.fu_busy_rate 0.227382 # FU busy rate (busy events/executed inst) 775system.cpu0.iq.int_inst_queue_reads 2272436054 # Number of integer instruction queue reads 776system.cpu0.iq.int_inst_queue_writes 714094331 # Number of integer instruction queue writes 777system.cpu0.iq.int_inst_queue_wakeup_accesses 626839047 # Number of integer instruction queue wakeup accesses 778system.cpu0.iq.fp_inst_queue_reads 1353741 # Number of floating instruction queue reads 779system.cpu0.iq.fp_inst_queue_writes 552796 # Number of floating instruction queue writes 780system.cpu0.iq.fp_inst_queue_wakeup_accesses 503202 # Number of floating instruction queue wakeup accesses 781system.cpu0.iq.int_alu_accesses 791281833 # Number of integer alu accesses 782system.cpu0.iq.fp_alu_accesses 835299 # Number of floating point alu accesses 783system.cpu0.iew.lsq.thread0.forwLoads 3004923 # Number of loads that had data forwarded from stores 784system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 785system.cpu0.iew.lsq.thread0.squashedLoads 13275769 # Number of loads squashed 786system.cpu0.iew.lsq.thread0.ignoredResponses 18782 # Number of memory responses ignored because the instruction is squashed 787system.cpu0.iew.lsq.thread0.memOrderViolation 159110 # Number of memory ordering violations 788system.cpu0.iew.lsq.thread0.squashedStores 6200623 # Number of stores squashed 789system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 790system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 791system.cpu0.iew.lsq.thread0.rescheduledLoads 2963562 # Number of loads that were rescheduled 792system.cpu0.iew.lsq.thread0.cacheBlocked 5149852 # Number of times an access to memory failed due to the cache being blocked 793system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 794system.cpu0.iew.iewSquashCycles 5485279 # Number of cycles IEW is squashing 795system.cpu0.iew.iewBlockCycles 8917054 # Number of cycles IEW is blocking 796system.cpu0.iew.iewUnblockCycles 3122413 # Number of cycles IEW is unblocking 797system.cpu0.iew.iewDispatchedInsts 657057128 # Number of instructions dispatched to IQ 798system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 799system.cpu0.iew.iewDispLoadInsts 108756528 # Number of dispatched load instructions 800system.cpu0.iew.iewDispStoreInsts 92814116 # Number of dispatched store instructions 801system.cpu0.iew.iewDispNonSpecInsts 14923426 # Number of dispatched non-speculative instructions 802system.cpu0.iew.iewIQFullEvents 69667 # Number of times the IQ has become full, causing a stall 803system.cpu0.iew.iewLSQFullEvents 2968943 # Number of times the LSQ has become full, causing a stall 804system.cpu0.iew.memOrderViolationEvents 159110 # Number of memory order violations 805system.cpu0.iew.predictedTakenIncorrect 2170447 # Number of branches that were predicted taken incorrectly 806system.cpu0.iew.predictedNotTakenIncorrect 3075539 # Number of branches that were predicted not taken incorrectly 807system.cpu0.iew.branchMispredicts 5245986 # Number of branch mispredicts detected at execute 808system.cpu0.iew.iewExecutedInsts 637077586 # Number of executed instructions 809system.cpu0.iew.iewExecLoadInsts 108926469 # Number of load instructions executed 810system.cpu0.iew.iewExecSquashedInsts 7646279 # Number of squashed instructions skipped in execute 811system.cpu0.iew.exec_swp 0 # number of swp insts executed 812system.cpu0.iew.exec_nop 130590 # number of nop insts executed 813system.cpu0.iew.exec_refs 198124159 # number of memory reference insts executed 814system.cpu0.iew.exec_branches 119913450 # Number of branches executed 815system.cpu0.iew.exec_stores 89197690 # Number of stores executed 816system.cpu0.iew.exec_rate 0.735065 # Inst execution rate 817system.cpu0.iew.wb_sent 628157908 # cumulative count of insts sent to commit 818system.cpu0.iew.wb_count 627342249 # cumulative count of insts written-back 819system.cpu0.iew.wb_producers 305063287 # num instructions producing a value 820system.cpu0.iew.wb_consumers 500478465 # num instructions consuming a value 821system.cpu0.iew.wb_rate 0.723832 # insts written-back per cycle 822system.cpu0.iew.wb_fanout 0.609543 # average fanout of values written-back 823system.cpu0.commit.commitSquashedInsts 50300993 # The number of squashed insts skipped by commit 824system.cpu0.commit.commitNonSpecStalls 17184426 # The number of times commit has been forced to stall to communicate backwards 825system.cpu0.commit.branchMispredicts 4931652 # The number of times a branch was mispredicted 826system.cpu0.commit.committed_per_cycle::samples 823863885 # Number of insts commited each cycle 827system.cpu0.commit.committed_per_cycle::mean 0.727503 # Number of insts commited each cycle 828system.cpu0.commit.committed_per_cycle::stdev 1.534838 # Number of insts commited each cycle 829system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 830system.cpu0.commit.committed_per_cycle::0 560826617 68.07% 68.07% # Number of insts commited each cycle 831system.cpu0.commit.committed_per_cycle::1 136759290 16.60% 84.67% # Number of insts commited each cycle 832system.cpu0.commit.committed_per_cycle::2 58156007 7.06% 91.73% # Number of insts commited each cycle 833system.cpu0.commit.committed_per_cycle::3 19570368 2.38% 94.11% # Number of insts commited each cycle 834system.cpu0.commit.committed_per_cycle::4 13861730 1.68% 95.79% # Number of insts commited each cycle 835system.cpu0.commit.committed_per_cycle::5 9557005 1.16% 96.95% # Number of insts commited each cycle 836system.cpu0.commit.committed_per_cycle::6 6407217 0.78% 97.73% # Number of insts commited each cycle 837system.cpu0.commit.committed_per_cycle::7 3899508 0.47% 98.20% # Number of insts commited each cycle 838system.cpu0.commit.committed_per_cycle::8 14826143 1.80% 100.00% # Number of insts commited each cycle 839system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 840system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 841system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 842system.cpu0.commit.committed_per_cycle::total 823863885 # Number of insts commited each cycle 843system.cpu0.commit.committedInsts 510319417 # Number of instructions committed 844system.cpu0.commit.committedOps 599363355 # Number of ops (including micro ops) committed 845system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 846system.cpu0.commit.refs 182094252 # Number of memory references committed 847system.cpu0.commit.loads 95480759 # Number of loads committed 848system.cpu0.commit.membars 4094698 # Number of memory barriers committed 849system.cpu0.commit.branches 113994539 # Number of branches committed 850system.cpu0.commit.fp_insts 490256 # Number of committed floating point instructions. 851system.cpu0.commit.int_insts 549724602 # Number of committed integer instructions. 852system.cpu0.commit.function_calls 15118537 # Number of function calls committed. 853system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 854system.cpu0.commit.op_class_0::IntAlu 415786848 69.37% 69.37% # Class of committed instruction 855system.cpu0.commit.op_class_0::IntMult 1342849 0.22% 69.60% # Class of committed instruction 856system.cpu0.commit.op_class_0::IntDiv 66347 0.01% 69.61% # Class of committed instruction 857system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.61% # Class of committed instruction 858system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.61% # Class of committed instruction 859system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.61% # Class of committed instruction 860system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.61% # Class of committed instruction 861system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.61% # Class of committed instruction 862system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction 863system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction 864system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction 865system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction 866system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction 867system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction 868system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction 869system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction 870system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction 871system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction 872system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction 873system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction 874system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction 875system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction 876system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction 877system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction 878system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction 879system.cpu0.commit.op_class_0::SimdFloatMisc 73059 0.01% 69.62% # Class of committed instruction 880system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.62% # Class of committed instruction 881system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.62% # Class of committed instruction 882system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.62% # Class of committed instruction 883system.cpu0.commit.op_class_0::MemRead 95480759 15.93% 85.55% # Class of committed instruction 884system.cpu0.commit.op_class_0::MemWrite 86613493 14.45% 100.00% # Class of committed instruction 885system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 886system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 887system.cpu0.commit.op_class_0::total 599363355 # Class of committed instruction 888system.cpu0.commit.bw_lim_events 14826143 # number cycles where commit BW limit reached 889system.cpu0.rob.rob_reads 1454251951 # The number of ROB reads 890system.cpu0.rob.rob_writes 1308847090 # The number of ROB writes 891system.cpu0.timesIdled 1090671 # Number of times that the entire CPU went into an idle state and unscheduled itself 892system.cpu0.idleCycles 33272801 # Total number of cycles that the CPU has spent unscheduled due to idling 893system.cpu0.quiesceCycles 93912870328 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 894system.cpu0.committedInsts 510319417 # Number of Instructions Simulated 895system.cpu0.committedOps 599363355 # Number of Ops (including micro ops) Simulated 896system.cpu0.cpi 1.698340 # CPI: Cycles Per Instruction 897system.cpu0.cpi_total 1.698340 # CPI: Total CPI of All Threads 898system.cpu0.ipc 0.588810 # IPC: Instructions Per Cycle 899system.cpu0.ipc_total 0.588810 # IPC: Total IPC of All Threads 900system.cpu0.int_regfile_reads 752522588 # number of integer regfile reads 901system.cpu0.int_regfile_writes 446228364 # number of integer regfile writes 902system.cpu0.fp_regfile_reads 791452 # number of floating regfile reads 903system.cpu0.fp_regfile_writes 475504 # number of floating regfile writes 904system.cpu0.cc_regfile_reads 139593627 # number of cc regfile reads 905system.cpu0.cc_regfile_writes 140336082 # number of cc regfile writes 906system.cpu0.misc_regfile_reads 1450242581 # number of misc regfile reads 907system.cpu0.misc_regfile_writes 17300190 # number of misc regfile writes 908system.cpu0.dcache.tags.replacements 6628748 # number of replacements 909system.cpu0.dcache.tags.tagsinuse 507.898673 # Cycle average of tags in use 910system.cpu0.dcache.tags.total_refs 168544062 # Total number of references to valid blocks. 911system.cpu0.dcache.tags.sampled_refs 6629257 # Sample count of references to valid blocks. 912system.cpu0.dcache.tags.avg_refs 25.424276 # Average number of references to valid blocks. 913system.cpu0.dcache.tags.warmup_cycle 2962390000 # Cycle when the warmup percentage was hit. 914system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.898673 # Average occupied blocks per requestor 915system.cpu0.dcache.tags.occ_percent::cpu0.data 0.991990 # Average percentage of cache occupancy 916system.cpu0.dcache.tags.occ_percent::total 0.991990 # Average percentage of cache occupancy 917system.cpu0.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id 918system.cpu0.dcache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 919system.cpu0.dcache.tags.age_task_id_blocks_1024::1 381 # Occupied blocks per task id 920system.cpu0.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id 921system.cpu0.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id 922system.cpu0.dcache.tags.tag_accesses 377708512 # Number of tag accesses 923system.cpu0.dcache.tags.data_accesses 377708512 # Number of data accesses 924system.cpu0.dcache.ReadReq_hits::cpu0.data 88226592 # number of ReadReq hits 925system.cpu0.dcache.ReadReq_hits::total 88226592 # number of ReadReq hits 926system.cpu0.dcache.WriteReq_hits::cpu0.data 75029005 # number of WriteReq hits 927system.cpu0.dcache.WriteReq_hits::total 75029005 # number of WriteReq hits 928system.cpu0.dcache.SoftPFReq_hits::cpu0.data 221757 # number of SoftPFReq hits 929system.cpu0.dcache.SoftPFReq_hits::total 221757 # number of SoftPFReq hits 930system.cpu0.dcache.WriteLineReq_hits::cpu0.data 177850 # number of WriteLineReq hits 931system.cpu0.dcache.WriteLineReq_hits::total 177850 # number of WriteLineReq hits 932system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1970217 # number of LoadLockedReq hits 933system.cpu0.dcache.LoadLockedReq_hits::total 1970217 # number of LoadLockedReq hits 934system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2022489 # number of StoreCondReq hits 935system.cpu0.dcache.StoreCondReq_hits::total 2022489 # number of StoreCondReq hits 936system.cpu0.dcache.demand_hits::cpu0.data 163255597 # number of demand (read+write) hits 937system.cpu0.dcache.demand_hits::total 163255597 # number of demand (read+write) hits 938system.cpu0.dcache.overall_hits::cpu0.data 163477354 # number of overall hits 939system.cpu0.dcache.overall_hits::total 163477354 # number of overall hits 940system.cpu0.dcache.ReadReq_misses::cpu0.data 7367994 # number of ReadReq misses 941system.cpu0.dcache.ReadReq_misses::total 7367994 # number of ReadReq misses 942system.cpu0.dcache.WriteReq_misses::cpu0.data 8340746 # number of WriteReq misses 943system.cpu0.dcache.WriteReq_misses::total 8340746 # number of WriteReq misses 944system.cpu0.dcache.SoftPFReq_misses::cpu0.data 804684 # number of SoftPFReq misses 945system.cpu0.dcache.SoftPFReq_misses::total 804684 # number of SoftPFReq misses 946system.cpu0.dcache.WriteLineReq_misses::cpu0.data 826218 # number of WriteLineReq misses 947system.cpu0.dcache.WriteLineReq_misses::total 826218 # number of WriteLineReq misses 948system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 297937 # number of LoadLockedReq misses 949system.cpu0.dcache.LoadLockedReq_misses::total 297937 # number of LoadLockedReq misses 950system.cpu0.dcache.StoreCondReq_misses::cpu0.data 206643 # number of StoreCondReq misses 951system.cpu0.dcache.StoreCondReq_misses::total 206643 # number of StoreCondReq misses 952system.cpu0.dcache.demand_misses::cpu0.data 15708740 # number of demand (read+write) misses 953system.cpu0.dcache.demand_misses::total 15708740 # number of demand (read+write) misses 954system.cpu0.dcache.overall_misses::cpu0.data 16513424 # number of overall misses 955system.cpu0.dcache.overall_misses::total 16513424 # number of overall misses 956system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 129957875000 # number of ReadReq miss cycles 957system.cpu0.dcache.ReadReq_miss_latency::total 129957875000 # number of ReadReq miss cycles 958system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 197611984656 # number of WriteReq miss cycles 959system.cpu0.dcache.WriteReq_miss_latency::total 197611984656 # number of WriteReq miss cycles 960system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 55152577242 # number of WriteLineReq miss cycles 961system.cpu0.dcache.WriteLineReq_miss_latency::total 55152577242 # number of WriteLineReq miss cycles 962system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4832056500 # number of LoadLockedReq miss cycles 963system.cpu0.dcache.LoadLockedReq_miss_latency::total 4832056500 # number of LoadLockedReq miss cycles 964system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5849414000 # number of StoreCondReq miss cycles 965system.cpu0.dcache.StoreCondReq_miss_latency::total 5849414000 # number of StoreCondReq miss cycles 966system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5216000 # number of StoreCondFailReq miss cycles 967system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5216000 # number of StoreCondFailReq miss cycles 968system.cpu0.dcache.demand_miss_latency::cpu0.data 327569859656 # number of demand (read+write) miss cycles 969system.cpu0.dcache.demand_miss_latency::total 327569859656 # number of demand (read+write) miss cycles 970system.cpu0.dcache.overall_miss_latency::cpu0.data 327569859656 # number of overall miss cycles 971system.cpu0.dcache.overall_miss_latency::total 327569859656 # number of overall miss cycles 972system.cpu0.dcache.ReadReq_accesses::cpu0.data 95594586 # number of ReadReq accesses(hits+misses) 973system.cpu0.dcache.ReadReq_accesses::total 95594586 # number of ReadReq accesses(hits+misses) 974system.cpu0.dcache.WriteReq_accesses::cpu0.data 83369751 # number of WriteReq accesses(hits+misses) 975system.cpu0.dcache.WriteReq_accesses::total 83369751 # number of WriteReq accesses(hits+misses) 976system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1026441 # number of SoftPFReq accesses(hits+misses) 977system.cpu0.dcache.SoftPFReq_accesses::total 1026441 # number of SoftPFReq accesses(hits+misses) 978system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1004068 # number of WriteLineReq accesses(hits+misses) 979system.cpu0.dcache.WriteLineReq_accesses::total 1004068 # number of WriteLineReq accesses(hits+misses) 980system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2268154 # number of LoadLockedReq accesses(hits+misses) 981system.cpu0.dcache.LoadLockedReq_accesses::total 2268154 # number of LoadLockedReq accesses(hits+misses) 982system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2229132 # number of StoreCondReq accesses(hits+misses) 983system.cpu0.dcache.StoreCondReq_accesses::total 2229132 # number of StoreCondReq accesses(hits+misses) 984system.cpu0.dcache.demand_accesses::cpu0.data 178964337 # number of demand (read+write) accesses 985system.cpu0.dcache.demand_accesses::total 178964337 # number of demand (read+write) accesses 986system.cpu0.dcache.overall_accesses::cpu0.data 179990778 # number of overall (read+write) accesses 987system.cpu0.dcache.overall_accesses::total 179990778 # number of overall (read+write) accesses 988system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.077075 # miss rate for ReadReq accesses 989system.cpu0.dcache.ReadReq_miss_rate::total 0.077075 # miss rate for ReadReq accesses 990system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.100045 # miss rate for WriteReq accesses 991system.cpu0.dcache.WriteReq_miss_rate::total 0.100045 # miss rate for WriteReq accesses 992system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.783955 # miss rate for SoftPFReq accesses 993system.cpu0.dcache.SoftPFReq_miss_rate::total 0.783955 # miss rate for SoftPFReq accesses 994system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.822871 # miss rate for WriteLineReq accesses 995system.cpu0.dcache.WriteLineReq_miss_rate::total 0.822871 # miss rate for WriteLineReq accesses 996system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.131357 # miss rate for LoadLockedReq accesses 997system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.131357 # miss rate for LoadLockedReq accesses 998system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.092701 # miss rate for StoreCondReq accesses 999system.cpu0.dcache.StoreCondReq_miss_rate::total 0.092701 # miss rate for StoreCondReq accesses 1000system.cpu0.dcache.demand_miss_rate::cpu0.data 0.087776 # miss rate for demand accesses 1001system.cpu0.dcache.demand_miss_rate::total 0.087776 # miss rate for demand accesses 1002system.cpu0.dcache.overall_miss_rate::cpu0.data 0.091746 # miss rate for overall accesses 1003system.cpu0.dcache.overall_miss_rate::total 0.091746 # miss rate for overall accesses 1004system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17638.162436 # average ReadReq miss latency 1005system.cpu0.dcache.ReadReq_avg_miss_latency::total 17638.162436 # average ReadReq miss latency 1006system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23692.363328 # average WriteReq miss latency 1007system.cpu0.dcache.WriteReq_avg_miss_latency::total 23692.363328 # average WriteReq miss latency 1008system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 66753.056992 # average WriteLineReq miss latency 1009system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 66753.056992 # average WriteLineReq miss latency 1010system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16218.383417 # average LoadLockedReq miss latency 1011system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16218.383417 # average LoadLockedReq miss latency 1012system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28306.857721 # average StoreCondReq miss latency 1013system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28306.857721 # average StoreCondReq miss latency 1014system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 1015system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1016system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20852.713818 # average overall miss latency 1017system.cpu0.dcache.demand_avg_miss_latency::total 20852.713818 # average overall miss latency 1018system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19836.580206 # average overall miss latency 1019system.cpu0.dcache.overall_avg_miss_latency::total 19836.580206 # average overall miss latency 1020system.cpu0.dcache.blocked_cycles::no_mshrs 17065024 # number of cycles access was blocked 1021system.cpu0.dcache.blocked_cycles::no_targets 30777617 # number of cycles access was blocked 1022system.cpu0.dcache.blocked::no_mshrs 770223 # number of cycles access was blocked 1023system.cpu0.dcache.blocked::no_targets 827793 # number of cycles access was blocked 1024system.cpu0.dcache.avg_blocked_cycles::no_mshrs 22.155952 # average number of cycles each access was blocked 1025system.cpu0.dcache.avg_blocked_cycles::no_targets 37.180330 # average number of cycles each access was blocked 1026system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1027system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1028system.cpu0.dcache.writebacks::writebacks 6628874 # number of writebacks 1029system.cpu0.dcache.writebacks::total 6628874 # number of writebacks 1030system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3770079 # number of ReadReq MSHR hits 1031system.cpu0.dcache.ReadReq_mshr_hits::total 3770079 # number of ReadReq MSHR hits 1032system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6700876 # number of WriteReq MSHR hits 1033system.cpu0.dcache.WriteReq_mshr_hits::total 6700876 # number of WriteReq MSHR hits 1034system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4178 # number of WriteLineReq MSHR hits 1035system.cpu0.dcache.WriteLineReq_mshr_hits::total 4178 # number of WriteLineReq MSHR hits 1036system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 152938 # number of LoadLockedReq MSHR hits 1037system.cpu0.dcache.LoadLockedReq_mshr_hits::total 152938 # number of LoadLockedReq MSHR hits 1038system.cpu0.dcache.demand_mshr_hits::cpu0.data 10470955 # number of demand (read+write) MSHR hits 1039system.cpu0.dcache.demand_mshr_hits::total 10470955 # number of demand (read+write) MSHR hits 1040system.cpu0.dcache.overall_mshr_hits::cpu0.data 10470955 # number of overall MSHR hits 1041system.cpu0.dcache.overall_mshr_hits::total 10470955 # number of overall MSHR hits 1042system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3597915 # number of ReadReq MSHR misses 1043system.cpu0.dcache.ReadReq_mshr_misses::total 3597915 # number of ReadReq MSHR misses 1044system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1639870 # number of WriteReq MSHR misses 1045system.cpu0.dcache.WriteReq_mshr_misses::total 1639870 # number of WriteReq MSHR misses 1046system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 797671 # number of SoftPFReq MSHR misses 1047system.cpu0.dcache.SoftPFReq_mshr_misses::total 797671 # number of SoftPFReq MSHR misses 1048system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 822040 # number of WriteLineReq MSHR misses 1049system.cpu0.dcache.WriteLineReq_mshr_misses::total 822040 # number of WriteLineReq MSHR misses 1050system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 144999 # number of LoadLockedReq MSHR misses 1051system.cpu0.dcache.LoadLockedReq_mshr_misses::total 144999 # number of LoadLockedReq MSHR misses 1052system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 206643 # number of StoreCondReq MSHR misses 1053system.cpu0.dcache.StoreCondReq_mshr_misses::total 206643 # number of StoreCondReq MSHR misses 1054system.cpu0.dcache.demand_mshr_misses::cpu0.data 5237785 # number of demand (read+write) MSHR misses 1055system.cpu0.dcache.demand_mshr_misses::total 5237785 # number of demand (read+write) MSHR misses 1056system.cpu0.dcache.overall_mshr_misses::cpu0.data 6035456 # number of overall MSHR misses 1057system.cpu0.dcache.overall_mshr_misses::total 6035456 # number of overall MSHR misses 1058system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 19715 # number of ReadReq MSHR uncacheable 1059system.cpu0.dcache.ReadReq_mshr_uncacheable::total 19715 # number of ReadReq MSHR uncacheable 1060system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 21606 # number of WriteReq MSHR uncacheable 1061system.cpu0.dcache.WriteReq_mshr_uncacheable::total 21606 # number of WriteReq MSHR uncacheable 1062system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 41321 # number of overall MSHR uncacheable misses 1063system.cpu0.dcache.overall_mshr_uncacheable_misses::total 41321 # number of overall MSHR uncacheable misses 1064system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 58751059000 # number of ReadReq MSHR miss cycles 1065system.cpu0.dcache.ReadReq_mshr_miss_latency::total 58751059000 # number of ReadReq MSHR miss cycles 1066system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 44752175448 # number of WriteReq MSHR miss cycles 1067system.cpu0.dcache.WriteReq_mshr_miss_latency::total 44752175448 # number of WriteReq MSHR miss cycles 1068system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 21047920500 # number of SoftPFReq MSHR miss cycles 1069system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 21047920500 # number of SoftPFReq MSHR miss cycles 1070system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 54096896242 # number of WriteLineReq MSHR miss cycles 1071system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 54096896242 # number of WriteLineReq MSHR miss cycles 1072system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 2128355000 # number of LoadLockedReq MSHR miss cycles 1073system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2128355000 # number of LoadLockedReq MSHR miss cycles 1074system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5642835000 # number of StoreCondReq MSHR miss cycles 1075system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5642835000 # number of StoreCondReq MSHR miss cycles 1076system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5152000 # number of StoreCondFailReq MSHR miss cycles 1077system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5152000 # number of StoreCondFailReq MSHR miss cycles 1078system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 103503234448 # number of demand (read+write) MSHR miss cycles 1079system.cpu0.dcache.demand_mshr_miss_latency::total 103503234448 # number of demand (read+write) MSHR miss cycles 1080system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 124551154948 # number of overall MSHR miss cycles 1081system.cpu0.dcache.overall_mshr_miss_latency::total 124551154948 # number of overall MSHR miss cycles 1082system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3829698500 # number of ReadReq MSHR uncacheable cycles 1083system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3829698500 # number of ReadReq MSHR uncacheable cycles 1084system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4085083000 # number of WriteReq MSHR uncacheable cycles 1085system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4085083000 # number of WriteReq MSHR uncacheable cycles 1086system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7914781500 # number of overall MSHR uncacheable cycles 1087system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7914781500 # number of overall MSHR uncacheable cycles 1088system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037637 # mshr miss rate for ReadReq accesses 1089system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037637 # mshr miss rate for ReadReq accesses 1090system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019670 # mshr miss rate for WriteReq accesses 1091system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019670 # mshr miss rate for WriteReq accesses 1092system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.777123 # mshr miss rate for SoftPFReq accesses 1093system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.777123 # mshr miss rate for SoftPFReq accesses 1094system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.818709 # mshr miss rate for WriteLineReq accesses 1095system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.818709 # mshr miss rate for WriteLineReq accesses 1096system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063928 # mshr miss rate for LoadLockedReq accesses 1097system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063928 # mshr miss rate for LoadLockedReq accesses 1098system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.092701 # mshr miss rate for StoreCondReq accesses 1099system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.092701 # mshr miss rate for StoreCondReq accesses 1100system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029267 # mshr miss rate for demand accesses 1101system.cpu0.dcache.demand_mshr_miss_rate::total 0.029267 # mshr miss rate for demand accesses 1102system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.033532 # mshr miss rate for overall accesses 1103system.cpu0.dcache.overall_mshr_miss_rate::total 0.033532 # mshr miss rate for overall accesses 1104system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16329.195937 # average ReadReq mshr miss latency 1105system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16329.195937 # average ReadReq mshr miss latency 1106system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27290.075096 # average WriteReq mshr miss latency 1107system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27290.075096 # average WriteReq mshr miss latency 1108system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 26386.718961 # average SoftPFReq mshr miss latency 1109system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 26386.718961 # average SoftPFReq mshr miss latency 1110system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 65808.106956 # average WriteLineReq mshr miss latency 1111system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 65808.106956 # average WriteLineReq mshr miss latency 1112system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14678.411575 # average LoadLockedReq mshr miss latency 1113system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14678.411575 # average LoadLockedReq mshr miss latency 1114system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27307.167434 # average StoreCondReq mshr miss latency 1115system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27307.167434 # average StoreCondReq mshr miss latency 1116system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1117system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1118system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19760.878778 # average overall mshr miss latency 1119system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19760.878778 # average overall mshr miss latency 1120system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20636.577410 # average overall mshr miss latency 1121system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20636.577410 # average overall mshr miss latency 1122system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194253.030687 # average ReadReq mshr uncacheable latency 1123system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 194253.030687 # average ReadReq mshr uncacheable latency 1124system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189071.693048 # average WriteReq mshr uncacheable latency 1125system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189071.693048 # average WriteReq mshr uncacheable latency 1126system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 191543.803393 # average overall mshr uncacheable latency 1127system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 191543.803393 # average overall mshr uncacheable latency 1128system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1129system.cpu0.icache.tags.replacements 6540239 # number of replacements 1130system.cpu0.icache.tags.tagsinuse 511.944561 # Cycle average of tags in use 1131system.cpu0.icache.tags.total_refs 227144563 # Total number of references to valid blocks. 1132system.cpu0.icache.tags.sampled_refs 6540751 # Sample count of references to valid blocks. 1133system.cpu0.icache.tags.avg_refs 34.727597 # Average number of references to valid blocks. 1134system.cpu0.icache.tags.warmup_cycle 18012149000 # Cycle when the warmup percentage was hit. 1135system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.944561 # Average occupied blocks per requestor 1136system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999892 # Average percentage of cache occupancy 1137system.cpu0.icache.tags.occ_percent::total 0.999892 # Average percentage of cache occupancy 1138system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1139system.cpu0.icache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id 1140system.cpu0.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id 1141system.cpu0.icache.tags.age_task_id_blocks_1024::2 96 # Occupied blocks per task id 1142system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1143system.cpu0.icache.tags.tag_accesses 474674738 # Number of tag accesses 1144system.cpu0.icache.tags.data_accesses 474674738 # Number of data accesses 1145system.cpu0.icache.ReadReq_hits::cpu0.inst 227144563 # number of ReadReq hits 1146system.cpu0.icache.ReadReq_hits::total 227144563 # number of ReadReq hits 1147system.cpu0.icache.demand_hits::cpu0.inst 227144563 # number of demand (read+write) hits 1148system.cpu0.icache.demand_hits::total 227144563 # number of demand (read+write) hits 1149system.cpu0.icache.overall_hits::cpu0.inst 227144563 # number of overall hits 1150system.cpu0.icache.overall_hits::total 227144563 # number of overall hits 1151system.cpu0.icache.ReadReq_misses::cpu0.inst 6922414 # number of ReadReq misses 1152system.cpu0.icache.ReadReq_misses::total 6922414 # number of ReadReq misses 1153system.cpu0.icache.demand_misses::cpu0.inst 6922414 # number of demand (read+write) misses 1154system.cpu0.icache.demand_misses::total 6922414 # number of demand (read+write) misses 1155system.cpu0.icache.overall_misses::cpu0.inst 6922414 # number of overall misses 1156system.cpu0.icache.overall_misses::total 6922414 # number of overall misses 1157system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 78815703700 # number of ReadReq miss cycles 1158system.cpu0.icache.ReadReq_miss_latency::total 78815703700 # number of ReadReq miss cycles 1159system.cpu0.icache.demand_miss_latency::cpu0.inst 78815703700 # number of demand (read+write) miss cycles 1160system.cpu0.icache.demand_miss_latency::total 78815703700 # number of demand (read+write) miss cycles 1161system.cpu0.icache.overall_miss_latency::cpu0.inst 78815703700 # number of overall miss cycles 1162system.cpu0.icache.overall_miss_latency::total 78815703700 # number of overall miss cycles 1163system.cpu0.icache.ReadReq_accesses::cpu0.inst 234066977 # number of ReadReq accesses(hits+misses) 1164system.cpu0.icache.ReadReq_accesses::total 234066977 # number of ReadReq accesses(hits+misses) 1165system.cpu0.icache.demand_accesses::cpu0.inst 234066977 # number of demand (read+write) accesses 1166system.cpu0.icache.demand_accesses::total 234066977 # number of demand (read+write) accesses 1167system.cpu0.icache.overall_accesses::cpu0.inst 234066977 # number of overall (read+write) accesses 1168system.cpu0.icache.overall_accesses::total 234066977 # number of overall (read+write) accesses 1169system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029575 # miss rate for ReadReq accesses 1170system.cpu0.icache.ReadReq_miss_rate::total 0.029575 # miss rate for ReadReq accesses 1171system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029575 # miss rate for demand accesses 1172system.cpu0.icache.demand_miss_rate::total 0.029575 # miss rate for demand accesses 1173system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029575 # miss rate for overall accesses 1174system.cpu0.icache.overall_miss_rate::total 0.029575 # miss rate for overall accesses 1175system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11385.580767 # average ReadReq miss latency 1176system.cpu0.icache.ReadReq_avg_miss_latency::total 11385.580767 # average ReadReq miss latency 1177system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11385.580767 # average overall miss latency 1178system.cpu0.icache.demand_avg_miss_latency::total 11385.580767 # average overall miss latency 1179system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11385.580767 # average overall miss latency 1180system.cpu0.icache.overall_avg_miss_latency::total 11385.580767 # average overall miss latency 1181system.cpu0.icache.blocked_cycles::no_mshrs 12205805 # number of cycles access was blocked 1182system.cpu0.icache.blocked_cycles::no_targets 1929 # number of cycles access was blocked 1183system.cpu0.icache.blocked::no_mshrs 815036 # number of cycles access was blocked 1184system.cpu0.icache.blocked::no_targets 13 # number of cycles access was blocked 1185system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.975786 # average number of cycles each access was blocked 1186system.cpu0.icache.avg_blocked_cycles::no_targets 148.384615 # average number of cycles each access was blocked 1187system.cpu0.icache.fast_writes 0 # number of fast writes performed 1188system.cpu0.icache.cache_copies 0 # number of cache copies performed 1189system.cpu0.icache.writebacks::writebacks 6540239 # number of writebacks 1190system.cpu0.icache.writebacks::total 6540239 # number of writebacks 1191system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 381630 # number of ReadReq MSHR hits 1192system.cpu0.icache.ReadReq_mshr_hits::total 381630 # number of ReadReq MSHR hits 1193system.cpu0.icache.demand_mshr_hits::cpu0.inst 381630 # number of demand (read+write) MSHR hits 1194system.cpu0.icache.demand_mshr_hits::total 381630 # number of demand (read+write) MSHR hits 1195system.cpu0.icache.overall_mshr_hits::cpu0.inst 381630 # number of overall MSHR hits 1196system.cpu0.icache.overall_mshr_hits::total 381630 # number of overall MSHR hits 1197system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6540784 # number of ReadReq MSHR misses 1198system.cpu0.icache.ReadReq_mshr_misses::total 6540784 # number of ReadReq MSHR misses 1199system.cpu0.icache.demand_mshr_misses::cpu0.inst 6540784 # number of demand (read+write) MSHR misses 1200system.cpu0.icache.demand_mshr_misses::total 6540784 # number of demand (read+write) MSHR misses 1201system.cpu0.icache.overall_mshr_misses::cpu0.inst 6540784 # number of overall MSHR misses 1202system.cpu0.icache.overall_mshr_misses::total 6540784 # number of overall MSHR misses 1203system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable 1204system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable 1205system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses 1206system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses 1207system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 70913768580 # number of ReadReq MSHR miss cycles 1208system.cpu0.icache.ReadReq_mshr_miss_latency::total 70913768580 # number of ReadReq MSHR miss cycles 1209system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 70913768580 # number of demand (read+write) MSHR miss cycles 1210system.cpu0.icache.demand_mshr_miss_latency::total 70913768580 # number of demand (read+write) MSHR miss cycles 1211system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 70913768580 # number of overall MSHR miss cycles 1212system.cpu0.icache.overall_mshr_miss_latency::total 70913768580 # number of overall MSHR miss cycles 1213system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2939780998 # number of ReadReq MSHR uncacheable cycles 1214system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2939780998 # number of ReadReq MSHR uncacheable cycles 1215system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2939780998 # number of overall MSHR uncacheable cycles 1216system.cpu0.icache.overall_mshr_uncacheable_latency::total 2939780998 # number of overall MSHR uncacheable cycles 1217system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027944 # mshr miss rate for ReadReq accesses 1218system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027944 # mshr miss rate for ReadReq accesses 1219system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027944 # mshr miss rate for demand accesses 1220system.cpu0.icache.demand_mshr_miss_rate::total 0.027944 # mshr miss rate for demand accesses 1221system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027944 # mshr miss rate for overall accesses 1222system.cpu0.icache.overall_mshr_miss_rate::total 0.027944 # mshr miss rate for overall accesses 1223system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10841.784193 # average ReadReq mshr miss latency 1224system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10841.784193 # average ReadReq mshr miss latency 1225system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10841.784193 # average overall mshr miss latency 1226system.cpu0.icache.demand_avg_mshr_miss_latency::total 10841.784193 # average overall mshr miss latency 1227system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10841.784193 # average overall mshr miss latency 1228system.cpu0.icache.overall_avg_mshr_miss_latency::total 10841.784193 # average overall mshr miss latency 1229system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138063.260132 # average ReadReq mshr uncacheable latency 1230system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138063.260132 # average ReadReq mshr uncacheable latency 1231system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138063.260132 # average overall mshr uncacheable latency 1232system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138063.260132 # average overall mshr uncacheable latency 1233system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1234system.cpu0.l2cache.prefetcher.num_hwpf_issued 9036202 # number of hwpf issued 1235system.cpu0.l2cache.prefetcher.pfIdentified 9047325 # number of prefetch candidates identified 1236system.cpu0.l2cache.prefetcher.pfBufferHit 9983 # number of redundant prefetches already in prefetch queue 1237system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1238system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1239system.cpu0.l2cache.prefetcher.pfSpanPage 1166339 # number of prefetches not generated due to page crossing 1240system.cpu0.l2cache.tags.replacements 3033682 # number of replacements 1241system.cpu0.l2cache.tags.tagsinuse 16193.393040 # Cycle average of tags in use 1242system.cpu0.l2cache.tags.total_refs 19026764 # Total number of references to valid blocks. 1243system.cpu0.l2cache.tags.sampled_refs 3049439 # Sample count of references to valid blocks. 1244system.cpu0.l2cache.tags.avg_refs 6.239431 # Average number of references to valid blocks. 1245system.cpu0.l2cache.tags.warmup_cycle 3423113000 # Cycle when the warmup percentage was hit. 1246system.cpu0.l2cache.tags.occ_blocks::writebacks 15201.196894 # Average occupied blocks per requestor 1247system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 62.932138 # Average occupied blocks per requestor 1248system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 78.683801 # Average occupied blocks per requestor 1249system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000068 # Average occupied blocks per requestor 1250system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 850.580138 # Average occupied blocks per requestor 1251system.cpu0.l2cache.tags.occ_percent::writebacks 0.927807 # Average percentage of cache occupancy 1252system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003841 # Average percentage of cache occupancy 1253system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004802 # Average percentage of cache occupancy 1254system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.000000 # Average percentage of cache occupancy 1255system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.051915 # Average percentage of cache occupancy 1256system.cpu0.l2cache.tags.occ_percent::total 0.988366 # Average percentage of cache occupancy 1257system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1326 # Occupied blocks per task id 1258system.cpu0.l2cache.tags.occ_task_id_blocks::1023 91 # Occupied blocks per task id 1259system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14340 # Occupied blocks per task id 1260system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 70 # Occupied blocks per task id 1261system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 174 # Occupied blocks per task id 1262system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 642 # Occupied blocks per task id 1263system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 440 # Occupied blocks per task id 1264system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id 1265system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 70 # Occupied blocks per task id 1266system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id 1267system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id 1268system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id 1269system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 900 # Occupied blocks per task id 1270system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4799 # Occupied blocks per task id 1271system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4876 # Occupied blocks per task id 1272system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3646 # Occupied blocks per task id 1273system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.080933 # Percentage of cache occupancy per task id 1274system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005554 # Percentage of cache occupancy per task id 1275system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.875244 # Percentage of cache occupancy per task id 1276system.cpu0.l2cache.tags.tag_accesses 451755433 # Number of tag accesses 1277system.cpu0.l2cache.tags.data_accesses 451755433 # Number of data accesses 1278system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 669148 # number of ReadReq hits 1279system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 205466 # number of ReadReq hits 1280system.cpu0.l2cache.ReadReq_hits::total 874614 # number of ReadReq hits 1281system.cpu0.l2cache.WritebackDirty_hits::writebacks 4337694 # number of WritebackDirty hits 1282system.cpu0.l2cache.WritebackDirty_hits::total 4337694 # number of WritebackDirty hits 1283system.cpu0.l2cache.WritebackClean_hits::writebacks 8829361 # number of WritebackClean hits 1284system.cpu0.l2cache.WritebackClean_hits::total 8829361 # number of WritebackClean hits 1285system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1023 # number of UpgradeReq hits 1286system.cpu0.l2cache.UpgradeReq_hits::total 1023 # number of UpgradeReq hits 1287system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1 # number of SCUpgradeReq hits 1288system.cpu0.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits 1289system.cpu0.l2cache.ReadExReq_hits::cpu0.data 1003467 # number of ReadExReq hits 1290system.cpu0.l2cache.ReadExReq_hits::total 1003467 # number of ReadExReq hits 1291system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5907946 # number of ReadCleanReq hits 1292system.cpu0.l2cache.ReadCleanReq_hits::total 5907946 # number of ReadCleanReq hits 1293system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3394515 # number of ReadSharedReq hits 1294system.cpu0.l2cache.ReadSharedReq_hits::total 3394515 # number of ReadSharedReq hits 1295system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 175024 # number of InvalidateReq hits 1296system.cpu0.l2cache.InvalidateReq_hits::total 175024 # number of InvalidateReq hits 1297system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 669148 # number of demand (read+write) hits 1298system.cpu0.l2cache.demand_hits::cpu0.itb.walker 205466 # number of demand (read+write) hits 1299system.cpu0.l2cache.demand_hits::cpu0.inst 5907946 # number of demand (read+write) hits 1300system.cpu0.l2cache.demand_hits::cpu0.data 4397982 # number of demand (read+write) hits 1301system.cpu0.l2cache.demand_hits::total 11180542 # number of demand (read+write) hits 1302system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 669148 # number of overall hits 1303system.cpu0.l2cache.overall_hits::cpu0.itb.walker 205466 # number of overall hits 1304system.cpu0.l2cache.overall_hits::cpu0.inst 5907946 # number of overall hits 1305system.cpu0.l2cache.overall_hits::cpu0.data 4397982 # number of overall hits 1306system.cpu0.l2cache.overall_hits::total 11180542 # number of overall hits 1307system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 14498 # number of ReadReq misses 1308system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10801 # number of ReadReq misses 1309system.cpu0.l2cache.ReadReq_misses::total 25299 # number of ReadReq misses 1310system.cpu0.l2cache.WritebackDirty_misses::writebacks 6 # number of WritebackDirty misses 1311system.cpu0.l2cache.WritebackDirty_misses::total 6 # number of WritebackDirty misses 1312system.cpu0.l2cache.WritebackClean_misses::writebacks 2 # number of WritebackClean misses 1313system.cpu0.l2cache.WritebackClean_misses::total 2 # number of WritebackClean misses 1314system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 283162 # number of UpgradeReq misses 1315system.cpu0.l2cache.UpgradeReq_misses::total 283162 # number of UpgradeReq misses 1316system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 206636 # number of SCUpgradeReq misses 1317system.cpu0.l2cache.SCUpgradeReq_misses::total 206636 # number of SCUpgradeReq misses 1318system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 6 # number of SCUpgradeFailReq misses 1319system.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses 1320system.cpu0.l2cache.ReadExReq_misses::cpu0.data 363386 # number of ReadExReq misses 1321system.cpu0.l2cache.ReadExReq_misses::total 363386 # number of ReadExReq misses 1322system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 632821 # number of ReadCleanReq misses 1323system.cpu0.l2cache.ReadCleanReq_misses::total 632821 # number of ReadCleanReq misses 1324system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1142961 # number of ReadSharedReq misses 1325system.cpu0.l2cache.ReadSharedReq_misses::total 1142961 # number of ReadSharedReq misses 1326system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 644935 # number of InvalidateReq misses 1327system.cpu0.l2cache.InvalidateReq_misses::total 644935 # number of InvalidateReq misses 1328system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 14498 # number of demand (read+write) misses 1329system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10801 # number of demand (read+write) misses 1330system.cpu0.l2cache.demand_misses::cpu0.inst 632821 # number of demand (read+write) misses 1331system.cpu0.l2cache.demand_misses::cpu0.data 1506347 # number of demand (read+write) misses 1332system.cpu0.l2cache.demand_misses::total 2164467 # number of demand (read+write) misses 1333system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 14498 # number of overall misses 1334system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10801 # number of overall misses 1335system.cpu0.l2cache.overall_misses::cpu0.inst 632821 # number of overall misses 1336system.cpu0.l2cache.overall_misses::cpu0.data 1506347 # number of overall misses 1337system.cpu0.l2cache.overall_misses::total 2164467 # number of overall misses 1338system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 831200000 # number of ReadReq miss cycles 1339system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 735223500 # number of ReadReq miss cycles 1340system.cpu0.l2cache.ReadReq_miss_latency::total 1566423500 # number of ReadReq miss cycles 1341system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3616020000 # number of UpgradeReq miss cycles 1342system.cpu0.l2cache.UpgradeReq_miss_latency::total 3616020000 # number of UpgradeReq miss cycles 1343system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2092116500 # number of SCUpgradeReq miss cycles 1344system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2092116500 # number of SCUpgradeReq miss cycles 1345system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 5056000 # number of SCUpgradeFailReq miss cycles 1346system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 5056000 # number of SCUpgradeFailReq miss cycles 1347system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 25090830000 # number of ReadExReq miss cycles 1348system.cpu0.l2cache.ReadExReq_miss_latency::total 25090830000 # number of ReadExReq miss cycles 1349system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 25302734498 # number of ReadCleanReq miss cycles 1350system.cpu0.l2cache.ReadCleanReq_miss_latency::total 25302734498 # number of ReadCleanReq miss cycles 1351system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 52461352979 # number of ReadSharedReq miss cycles 1352system.cpu0.l2cache.ReadSharedReq_miss_latency::total 52461352979 # number of ReadSharedReq miss cycles 1353system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 386032000 # number of InvalidateReq miss cycles 1354system.cpu0.l2cache.InvalidateReq_miss_latency::total 386032000 # number of InvalidateReq miss cycles 1355system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 831200000 # number of demand (read+write) miss cycles 1356system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 735223500 # number of demand (read+write) miss cycles 1357system.cpu0.l2cache.demand_miss_latency::cpu0.inst 25302734498 # number of demand (read+write) miss cycles 1358system.cpu0.l2cache.demand_miss_latency::cpu0.data 77552182979 # number of demand (read+write) miss cycles 1359system.cpu0.l2cache.demand_miss_latency::total 104421340977 # number of demand (read+write) miss cycles 1360system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 831200000 # number of overall miss cycles 1361system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 735223500 # number of overall miss cycles 1362system.cpu0.l2cache.overall_miss_latency::cpu0.inst 25302734498 # number of overall miss cycles 1363system.cpu0.l2cache.overall_miss_latency::cpu0.data 77552182979 # number of overall miss cycles 1364system.cpu0.l2cache.overall_miss_latency::total 104421340977 # number of overall miss cycles 1365system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 683646 # number of ReadReq accesses(hits+misses) 1366system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 216267 # number of ReadReq accesses(hits+misses) 1367system.cpu0.l2cache.ReadReq_accesses::total 899913 # number of ReadReq accesses(hits+misses) 1368system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4337700 # number of WritebackDirty accesses(hits+misses) 1369system.cpu0.l2cache.WritebackDirty_accesses::total 4337700 # number of WritebackDirty accesses(hits+misses) 1370system.cpu0.l2cache.WritebackClean_accesses::writebacks 8829363 # number of WritebackClean accesses(hits+misses) 1371system.cpu0.l2cache.WritebackClean_accesses::total 8829363 # number of WritebackClean accesses(hits+misses) 1372system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 284185 # number of UpgradeReq accesses(hits+misses) 1373system.cpu0.l2cache.UpgradeReq_accesses::total 284185 # number of UpgradeReq accesses(hits+misses) 1374system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 206637 # number of SCUpgradeReq accesses(hits+misses) 1375system.cpu0.l2cache.SCUpgradeReq_accesses::total 206637 # number of SCUpgradeReq accesses(hits+misses) 1376system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 6 # number of SCUpgradeFailReq accesses(hits+misses) 1377system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) 1378system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1366853 # number of ReadExReq accesses(hits+misses) 1379system.cpu0.l2cache.ReadExReq_accesses::total 1366853 # number of ReadExReq accesses(hits+misses) 1380system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6540767 # number of ReadCleanReq accesses(hits+misses) 1381system.cpu0.l2cache.ReadCleanReq_accesses::total 6540767 # number of ReadCleanReq accesses(hits+misses) 1382system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4537476 # number of ReadSharedReq accesses(hits+misses) 1383system.cpu0.l2cache.ReadSharedReq_accesses::total 4537476 # number of ReadSharedReq accesses(hits+misses) 1384system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 819959 # number of InvalidateReq accesses(hits+misses) 1385system.cpu0.l2cache.InvalidateReq_accesses::total 819959 # number of InvalidateReq accesses(hits+misses) 1386system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 683646 # number of demand (read+write) accesses 1387system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 216267 # number of demand (read+write) accesses 1388system.cpu0.l2cache.demand_accesses::cpu0.inst 6540767 # number of demand (read+write) accesses 1389system.cpu0.l2cache.demand_accesses::cpu0.data 5904329 # number of demand (read+write) accesses 1390system.cpu0.l2cache.demand_accesses::total 13345009 # number of demand (read+write) accesses 1391system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 683646 # number of overall (read+write) accesses 1392system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 216267 # number of overall (read+write) accesses 1393system.cpu0.l2cache.overall_accesses::cpu0.inst 6540767 # number of overall (read+write) accesses 1394system.cpu0.l2cache.overall_accesses::cpu0.data 5904329 # number of overall (read+write) accesses 1395system.cpu0.l2cache.overall_accesses::total 13345009 # number of overall (read+write) accesses 1396system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021207 # miss rate for ReadReq accesses 1397system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.049943 # miss rate for ReadReq accesses 1398system.cpu0.l2cache.ReadReq_miss_rate::total 0.028113 # miss rate for ReadReq accesses 1399system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses 1400system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses 1401system.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses 1402system.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses 1403system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.996400 # miss rate for UpgradeReq accesses 1404system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.996400 # miss rate for UpgradeReq accesses 1405system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999995 # miss rate for SCUpgradeReq accesses 1406system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999995 # miss rate for SCUpgradeReq accesses 1407system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1408system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1409system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.265856 # miss rate for ReadExReq accesses 1410system.cpu0.l2cache.ReadExReq_miss_rate::total 0.265856 # miss rate for ReadExReq accesses 1411system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.096750 # miss rate for ReadCleanReq accesses 1412system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.096750 # miss rate for ReadCleanReq accesses 1413system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.251894 # miss rate for ReadSharedReq accesses 1414system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.251894 # miss rate for ReadSharedReq accesses 1415system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.786545 # miss rate for InvalidateReq accesses 1416system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.786545 # miss rate for InvalidateReq accesses 1417system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021207 # miss rate for demand accesses 1418system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.049943 # miss rate for demand accesses 1419system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.096750 # miss rate for demand accesses 1420system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.255126 # miss rate for demand accesses 1421system.cpu0.l2cache.demand_miss_rate::total 0.162193 # miss rate for demand accesses 1422system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021207 # miss rate for overall accesses 1423system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.049943 # miss rate for overall accesses 1424system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.096750 # miss rate for overall accesses 1425system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.255126 # miss rate for overall accesses 1426system.cpu0.l2cache.overall_miss_rate::total 0.162193 # miss rate for overall accesses 1427system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 57332.045799 # average ReadReq miss latency 1428system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 68069.947227 # average ReadReq miss latency 1429system.cpu0.l2cache.ReadReq_avg_miss_latency::total 61916.419621 # average ReadReq miss latency 1430system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 12770.145712 # average UpgradeReq miss latency 1431system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 12770.145712 # average UpgradeReq miss latency 1432system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10124.646722 # average SCUpgradeReq miss latency 1433system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10124.646722 # average SCUpgradeReq miss latency 1434system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 842666.666667 # average SCUpgradeFailReq miss latency 1435system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 842666.666667 # average SCUpgradeFailReq miss latency 1436system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 69047.321581 # average ReadExReq miss latency 1437system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 69047.321581 # average ReadExReq miss latency 1438system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 39984.031026 # average ReadCleanReq miss latency 1439system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 39984.031026 # average ReadCleanReq miss latency 1440system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 45899.512738 # average ReadSharedReq miss latency 1441system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 45899.512738 # average ReadSharedReq miss latency 1442system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 598.559545 # average InvalidateReq miss latency 1443system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 598.559545 # average InvalidateReq miss latency 1444system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 57332.045799 # average overall miss latency 1445system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 68069.947227 # average overall miss latency 1446system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39984.031026 # average overall miss latency 1447system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 51483.611000 # average overall miss latency 1448system.cpu0.l2cache.demand_avg_miss_latency::total 48243.443294 # average overall miss latency 1449system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 57332.045799 # average overall miss latency 1450system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 68069.947227 # average overall miss latency 1451system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39984.031026 # average overall miss latency 1452system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 51483.611000 # average overall miss latency 1453system.cpu0.l2cache.overall_avg_miss_latency::total 48243.443294 # average overall miss latency 1454system.cpu0.l2cache.blocked_cycles::no_mshrs 2497 # number of cycles access was blocked 1455system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1456system.cpu0.l2cache.blocked::no_mshrs 23 # number of cycles access was blocked 1457system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1458system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 108.565217 # average number of cycles each access was blocked 1459system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1460system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1461system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1462system.cpu0.l2cache.writebacks::writebacks 1894575 # number of writebacks 1463system.cpu0.l2cache.writebacks::total 1894575 # number of writebacks 1464system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 5 # number of ReadReq MSHR hits 1465system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 193 # number of ReadReq MSHR hits 1466system.cpu0.l2cache.ReadReq_mshr_hits::total 198 # number of ReadReq MSHR hits 1467system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 69860 # number of ReadExReq MSHR hits 1468system.cpu0.l2cache.ReadExReq_mshr_hits::total 69860 # number of ReadExReq MSHR hits 1469system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 6 # number of ReadCleanReq MSHR hits 1470system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 6 # number of ReadCleanReq MSHR hits 1471system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 7488 # number of ReadSharedReq MSHR hits 1472system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 7488 # number of ReadSharedReq MSHR hits 1473system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 6 # number of InvalidateReq MSHR hits 1474system.cpu0.l2cache.InvalidateReq_mshr_hits::total 6 # number of InvalidateReq MSHR hits 1475system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 5 # number of demand (read+write) MSHR hits 1476system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 193 # number of demand (read+write) MSHR hits 1477system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 6 # number of demand (read+write) MSHR hits 1478system.cpu0.l2cache.demand_mshr_hits::cpu0.data 77348 # number of demand (read+write) MSHR hits 1479system.cpu0.l2cache.demand_mshr_hits::total 77552 # number of demand (read+write) MSHR hits 1480system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 5 # number of overall MSHR hits 1481system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 193 # number of overall MSHR hits 1482system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 6 # number of overall MSHR hits 1483system.cpu0.l2cache.overall_mshr_hits::cpu0.data 77348 # number of overall MSHR hits 1484system.cpu0.l2cache.overall_mshr_hits::total 77552 # number of overall MSHR hits 1485system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 14493 # number of ReadReq MSHR misses 1486system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 10608 # number of ReadReq MSHR misses 1487system.cpu0.l2cache.ReadReq_mshr_misses::total 25101 # number of ReadReq MSHR misses 1488system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 6 # number of WritebackDirty MSHR misses 1489system.cpu0.l2cache.WritebackDirty_mshr_misses::total 6 # number of WritebackDirty MSHR misses 1490system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 2 # number of WritebackClean MSHR misses 1491system.cpu0.l2cache.WritebackClean_mshr_misses::total 2 # number of WritebackClean MSHR misses 1492system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 934637 # number of HardPFReq MSHR misses 1493system.cpu0.l2cache.HardPFReq_mshr_misses::total 934637 # number of HardPFReq MSHR misses 1494system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 283162 # number of UpgradeReq MSHR misses 1495system.cpu0.l2cache.UpgradeReq_mshr_misses::total 283162 # number of UpgradeReq MSHR misses 1496system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 206636 # number of SCUpgradeReq MSHR misses 1497system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 206636 # number of SCUpgradeReq MSHR misses 1498system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 6 # number of SCUpgradeFailReq MSHR misses 1499system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses 1500system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 293526 # number of ReadExReq MSHR misses 1501system.cpu0.l2cache.ReadExReq_mshr_misses::total 293526 # number of ReadExReq MSHR misses 1502system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 632815 # number of ReadCleanReq MSHR misses 1503system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 632815 # number of ReadCleanReq MSHR misses 1504system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1135473 # number of ReadSharedReq MSHR misses 1505system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1135473 # number of ReadSharedReq MSHR misses 1506system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 644929 # number of InvalidateReq MSHR misses 1507system.cpu0.l2cache.InvalidateReq_mshr_misses::total 644929 # number of InvalidateReq MSHR misses 1508system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 14493 # number of demand (read+write) MSHR misses 1509system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10608 # number of demand (read+write) MSHR misses 1510system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 632815 # number of demand (read+write) MSHR misses 1511system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1428999 # number of demand (read+write) MSHR misses 1512system.cpu0.l2cache.demand_mshr_misses::total 2086915 # number of demand (read+write) MSHR misses 1513system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 14493 # number of overall MSHR misses 1514system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10608 # number of overall MSHR misses 1515system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 632815 # number of overall MSHR misses 1516system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1428999 # number of overall MSHR misses 1517system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 934637 # number of overall MSHR misses 1518system.cpu0.l2cache.overall_mshr_misses::total 3021552 # number of overall MSHR misses 1519system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable 1520system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 19715 # number of ReadReq MSHR uncacheable 1521system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 41008 # number of ReadReq MSHR uncacheable 1522system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 21606 # number of WriteReq MSHR uncacheable 1523system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 21606 # number of WriteReq MSHR uncacheable 1524system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses 1525system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 41321 # number of overall MSHR uncacheable misses 1526system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 62614 # number of overall MSHR uncacheable misses 1527system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 744149500 # number of ReadReq MSHR miss cycles 1528system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 659971500 # number of ReadReq MSHR miss cycles 1529system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1404121000 # number of ReadReq MSHR miss cycles 1530system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 78126139116 # number of HardPFReq MSHR miss cycles 1531system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 78126139116 # number of HardPFReq MSHR miss cycles 1532system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 8227819495 # number of UpgradeReq MSHR miss cycles 1533system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 8227819495 # number of UpgradeReq MSHR miss cycles 1534system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 4089973495 # number of SCUpgradeReq MSHR miss cycles 1535system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 4089973495 # number of SCUpgradeReq MSHR miss cycles 1536system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4672000 # number of SCUpgradeFailReq MSHR miss cycles 1537system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4672000 # number of SCUpgradeFailReq MSHR miss cycles 1538system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 18739186500 # number of ReadExReq MSHR miss cycles 1539system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 18739186500 # number of ReadExReq MSHR miss cycles 1540system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 21505748998 # number of ReadCleanReq MSHR miss cycles 1541system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 21505748998 # number of ReadCleanReq MSHR miss cycles 1542system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 45049566980 # number of ReadSharedReq MSHR miss cycles 1543system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 45049566980 # number of ReadSharedReq MSHR miss cycles 1544system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 46970391994 # number of InvalidateReq MSHR miss cycles 1545system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 46970391994 # number of InvalidateReq MSHR miss cycles 1546system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 744149500 # number of demand (read+write) MSHR miss cycles 1547system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 659971500 # number of demand (read+write) MSHR miss cycles 1548system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 21505748998 # number of demand (read+write) MSHR miss cycles 1549system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 63788753480 # number of demand (read+write) MSHR miss cycles 1550system.cpu0.l2cache.demand_mshr_miss_latency::total 86698623478 # number of demand (read+write) MSHR miss cycles 1551system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 744149500 # number of overall MSHR miss cycles 1552system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 659971500 # number of overall MSHR miss cycles 1553system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 21505748998 # number of overall MSHR miss cycles 1554system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 63788753480 # number of overall MSHR miss cycles 1555system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 78126139116 # number of overall MSHR miss cycles 1556system.cpu0.l2cache.overall_mshr_miss_latency::total 164824762594 # number of overall MSHR miss cycles 1557system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2780082500 # number of ReadReq MSHR uncacheable cycles 1558system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3671826500 # number of ReadReq MSHR uncacheable cycles 1559system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6451909000 # number of ReadReq MSHR uncacheable cycles 1560system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3917316467 # number of WriteReq MSHR uncacheable cycles 1561system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3917316467 # number of WriteReq MSHR uncacheable cycles 1562system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 2780082500 # number of overall MSHR uncacheable cycles 1563system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7589142967 # number of overall MSHR uncacheable cycles 1564system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10369225467 # number of overall MSHR uncacheable cycles 1565system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021200 # mshr miss rate for ReadReq accesses 1566system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.049050 # mshr miss rate for ReadReq accesses 1567system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.027893 # mshr miss rate for ReadReq accesses 1568system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses 1569system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses 1570system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses 1571system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses 1572system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1573system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1574system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.996400 # mshr miss rate for UpgradeReq accesses 1575system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.996400 # mshr miss rate for UpgradeReq accesses 1576system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999995 # mshr miss rate for SCUpgradeReq accesses 1577system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for SCUpgradeReq accesses 1578system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1579system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1580system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.214746 # mshr miss rate for ReadExReq accesses 1581system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.214746 # mshr miss rate for ReadExReq accesses 1582system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.096749 # mshr miss rate for ReadCleanReq accesses 1583system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096749 # mshr miss rate for ReadCleanReq accesses 1584system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.250243 # mshr miss rate for ReadSharedReq accesses 1585system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.250243 # mshr miss rate for ReadSharedReq accesses 1586system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.786538 # mshr miss rate for InvalidateReq accesses 1587system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.786538 # mshr miss rate for InvalidateReq accesses 1588system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021200 # mshr miss rate for demand accesses 1589system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.049050 # mshr miss rate for demand accesses 1590system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.096749 # mshr miss rate for demand accesses 1591system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.242026 # mshr miss rate for demand accesses 1592system.cpu0.l2cache.demand_mshr_miss_rate::total 0.156382 # mshr miss rate for demand accesses 1593system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021200 # mshr miss rate for overall accesses 1594system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.049050 # mshr miss rate for overall accesses 1595system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.096749 # mshr miss rate for overall accesses 1596system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.242026 # mshr miss rate for overall accesses 1597system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1598system.cpu0.l2cache.overall_mshr_miss_rate::total 0.226418 # mshr miss rate for overall accesses 1599system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 51345.442627 # average ReadReq mshr miss latency 1600system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62214.507919 # average ReadReq mshr miss latency 1601system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 55938.847058 # average ReadReq mshr miss latency 1602system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83589.820557 # average HardPFReq mshr miss latency 1603system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 83589.820557 # average HardPFReq mshr miss latency 1604system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 29056.933822 # average UpgradeReq mshr miss latency 1605system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 29056.933822 # average UpgradeReq mshr miss latency 1606system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19793.131376 # average SCUpgradeReq mshr miss latency 1607system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19793.131376 # average SCUpgradeReq mshr miss latency 1608system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 778666.666667 # average SCUpgradeFailReq mshr miss latency 1609system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 778666.666667 # average SCUpgradeFailReq mshr miss latency 1610system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 63841.657979 # average ReadExReq mshr miss latency 1611system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 63841.657979 # average ReadExReq mshr miss latency 1612system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 33984.259220 # average ReadCleanReq mshr miss latency 1613system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 33984.259220 # average ReadCleanReq mshr miss latency 1614system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 39674.714397 # average ReadSharedReq mshr miss latency 1615system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 39674.714397 # average ReadSharedReq mshr miss latency 1616system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 72830.330151 # average InvalidateReq mshr miss latency 1617system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 72830.330151 # average InvalidateReq mshr miss latency 1618system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 51345.442627 # average overall mshr miss latency 1619system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 62214.507919 # average overall mshr miss latency 1620system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 33984.259220 # average overall mshr miss latency 1621system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 44638.767053 # average overall mshr miss latency 1622system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 41543.916967 # average overall mshr miss latency 1623system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 51345.442627 # average overall mshr miss latency 1624system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 62214.507919 # average overall mshr miss latency 1625system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 33984.259220 # average overall mshr miss latency 1626system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 44638.767053 # average overall mshr miss latency 1627system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 83589.820557 # average overall mshr miss latency 1628system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 54549.702469 # average overall mshr miss latency 1629system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263 # average ReadReq mshr uncacheable latency 1630system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 186245.320822 # average ReadReq mshr uncacheable latency 1631system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 157332.935037 # average ReadReq mshr uncacheable latency 1632system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181306.880820 # average WriteReq mshr uncacheable latency 1633system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181306.880820 # average WriteReq mshr uncacheable latency 1634system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263 # average overall mshr uncacheable latency 1635system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 183663.100288 # average overall mshr uncacheable latency 1636system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 165605.542962 # average overall mshr uncacheable latency 1637system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1638system.cpu0.toL2Bus.snoop_filter.tot_requests 27325930 # Total number of requests made to the snoop filter. 1639system.cpu0.toL2Bus.snoop_filter.hit_single_requests 14061042 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1640system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2043 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1641system.cpu0.toL2Bus.snoop_filter.tot_snoops 2238708 # Total number of snoops made to the snoop filter. 1642system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2238208 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1643system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 500 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1644system.cpu0.toL2Bus.trans_dist::ReadReq 1035490 # Transaction distribution 1645system.cpu0.toL2Bus.trans_dist::ReadResp 12208665 # Transaction distribution 1646system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 1647system.cpu0.toL2Bus.trans_dist::WriteReq 21607 # Transaction distribution 1648system.cpu0.toL2Bus.trans_dist::WriteResp 21606 # Transaction distribution 1649system.cpu0.toL2Bus.trans_dist::WritebackDirty 6237038 # Transaction distribution 1650system.cpu0.toL2Bus.trans_dist::WritebackClean 8831409 # Transaction distribution 1651system.cpu0.toL2Bus.trans_dist::CleanEvict 2977562 # Transaction distribution 1652system.cpu0.toL2Bus.trans_dist::HardPFReq 1194062 # Transaction distribution 1653system.cpu0.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution 1654system.cpu0.toL2Bus.trans_dist::UpgradeReq 497340 # Transaction distribution 1655system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 368088 # Transaction distribution 1656system.cpu0.toL2Bus.trans_dist::UpgradeResp 556890 # Transaction distribution 1657system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 60 # Transaction distribution 1658system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 118 # Transaction distribution 1659system.cpu0.toL2Bus.trans_dist::ReadExReq 1397051 # Transaction distribution 1660system.cpu0.toL2Bus.trans_dist::ReadExResp 1373685 # Transaction distribution 1661system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6540784 # Transaction distribution 1662system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5522441 # Transaction distribution 1663system.cpu0.toL2Bus.trans_dist::InvalidateReq 877204 # Transaction distribution 1664system.cpu0.toL2Bus.trans_dist::InvalidateResp 819959 # Transaction distribution 1665system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 19664376 # Packet count per connected master and slave (bytes) 1666system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 21309678 # Packet count per connected master and slave (bytes) 1667system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 452328 # Packet count per connected master and slave (bytes) 1668system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1442065 # Packet count per connected master and slave (bytes) 1669system.cpu0.toL2Bus.pkt_count::total 42868447 # Packet count per connected master and slave (bytes) 1670system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 837525072 # Cumulative packet size per connected master and slave (bytes) 1671system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 808748037 # Cumulative packet size per connected master and slave (bytes) 1672system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1730136 # Cumulative packet size per connected master and slave (bytes) 1673system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5469168 # Cumulative packet size per connected master and slave (bytes) 1674system.cpu0.toL2Bus.pkt_size::total 1653472413 # Cumulative packet size per connected master and slave (bytes) 1675system.cpu0.toL2Bus.snoops 7780551 # Total snoops (count) 1676system.cpu0.toL2Bus.snoop_fanout::samples 22331077 # Request fanout histogram 1677system.cpu0.toL2Bus.snoop_fanout::mean 0.118319 # Request fanout histogram 1678system.cpu0.toL2Bus.snoop_fanout::stdev 0.323054 # Request fanout histogram 1679system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1680system.cpu0.toL2Bus.snoop_fanout::0 19689394 88.17% 88.17% # Request fanout histogram 1681system.cpu0.toL2Bus.snoop_fanout::1 2641183 11.83% 100.00% # Request fanout histogram 1682system.cpu0.toL2Bus.snoop_fanout::2 500 0.00% 100.00% # Request fanout histogram 1683system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1684system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1685system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1686system.cpu0.toL2Bus.snoop_fanout::total 22331077 # Request fanout histogram 1687system.cpu0.toL2Bus.reqLayer0.occupancy 27171038408 # Layer occupancy (ticks) 1688system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1689system.cpu0.toL2Bus.snoopLayer0.occupancy 185981894 # Layer occupancy (ticks) 1690system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1691system.cpu0.toL2Bus.respLayer0.occupancy 9839167037 # Layer occupancy (ticks) 1692system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1693system.cpu0.toL2Bus.respLayer1.occupancy 9551310776 # Layer occupancy (ticks) 1694system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1695system.cpu0.toL2Bus.respLayer2.occupancy 236496624 # Layer occupancy (ticks) 1696system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1697system.cpu0.toL2Bus.respLayer3.occupancy 759104112 # Layer occupancy (ticks) 1698system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1699system.cpu1.branchPred.lookups 126248667 # Number of BP lookups 1700system.cpu1.branchPred.condPredicted 84543955 # Number of conditional branches predicted 1701system.cpu1.branchPred.condIncorrect 6151855 # Number of conditional branches incorrect 1702system.cpu1.branchPred.BTBLookups 88859655 # Number of BTB lookups 1703system.cpu1.branchPred.BTBHits 57842551 # Number of BTB hits 1704system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1705system.cpu1.branchPred.BTBHitPct 65.094278 # BTB Hit Percentage 1706system.cpu1.branchPred.usedRAS 16827370 # Number of times the RAS was used to get a target. 1707system.cpu1.branchPred.RASInCorrect 172583 # Number of incorrect RAS predictions. 1708system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1709system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1710system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1711system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1712system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1713system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1714system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1715system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1716system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1717system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1718system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1719system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1720system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1721system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1722system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1723system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1724system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1725system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1726system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1727system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1728system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1729system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1730system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1731system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1732system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1733system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1734system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1735system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1736system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1737system.cpu1.dtb.walker.walks 548057 # Table walker walks requested 1738system.cpu1.dtb.walker.walksLong 548057 # Table walker walks initiated with long descriptors 1739system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11885 # Level at which table walker walks with long descriptors terminate 1740system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 88263 # Level at which table walker walks with long descriptors terminate 1741system.cpu1.dtb.walker.walksSquashedBefore 254796 # Table walks squashed before starting 1742system.cpu1.dtb.walker.walkWaitTime::samples 293261 # Table walker wait (enqueue to first request) latency 1743system.cpu1.dtb.walker.walkWaitTime::mean 2461.776370 # Table walker wait (enqueue to first request) latency 1744system.cpu1.dtb.walker.walkWaitTime::stdev 15099.601662 # Table walker wait (enqueue to first request) latency 1745system.cpu1.dtb.walker.walkWaitTime::0-131071 292248 99.65% 99.65% # Table walker wait (enqueue to first request) latency 1746system.cpu1.dtb.walker.walkWaitTime::131072-262143 874 0.30% 99.95% # Table walker wait (enqueue to first request) latency 1747system.cpu1.dtb.walker.walkWaitTime::262144-393215 111 0.04% 99.99% # Table walker wait (enqueue to first request) latency 1748system.cpu1.dtb.walker.walkWaitTime::393216-524287 22 0.01% 100.00% # Table walker wait (enqueue to first request) latency 1749system.cpu1.dtb.walker.walkWaitTime::524288-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1750system.cpu1.dtb.walker.walkWaitTime::655360-786431 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1751system.cpu1.dtb.walker.walkWaitTime::917504-1.04858e+06 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1752system.cpu1.dtb.walker.walkWaitTime::1.04858e+06-1.17965e+06 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1753system.cpu1.dtb.walker.walkWaitTime::total 293261 # Table walker wait (enqueue to first request) latency 1754system.cpu1.dtb.walker.walkCompletionTime::samples 284367 # Table walker service (enqueue to completion) latency 1755system.cpu1.dtb.walker.walkCompletionTime::mean 20156.804411 # Table walker service (enqueue to completion) latency 1756system.cpu1.dtb.walker.walkCompletionTime::gmean 17511.621467 # Table walker service (enqueue to completion) latency 1757system.cpu1.dtb.walker.walkCompletionTime::stdev 17128.200610 # Table walker service (enqueue to completion) latency 1758system.cpu1.dtb.walker.walkCompletionTime::0-65535 282098 99.20% 99.20% # Table walker service (enqueue to completion) latency 1759system.cpu1.dtb.walker.walkCompletionTime::65536-131071 636 0.22% 99.43% # Table walker service (enqueue to completion) latency 1760system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1232 0.43% 99.86% # Table walker service (enqueue to completion) latency 1761system.cpu1.dtb.walker.walkCompletionTime::196608-262143 88 0.03% 99.89% # Table walker service (enqueue to completion) latency 1762system.cpu1.dtb.walker.walkCompletionTime::262144-327679 184 0.06% 99.95% # Table walker service (enqueue to completion) latency 1763system.cpu1.dtb.walker.walkCompletionTime::327680-393215 74 0.03% 99.98% # Table walker service (enqueue to completion) latency 1764system.cpu1.dtb.walker.walkCompletionTime::393216-458751 33 0.01% 99.99% # Table walker service (enqueue to completion) latency 1765system.cpu1.dtb.walker.walkCompletionTime::458752-524287 13 0.00% 100.00% # Table walker service (enqueue to completion) latency 1766system.cpu1.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 100.00% # Table walker service (enqueue to completion) latency 1767system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1768system.cpu1.dtb.walker.walkCompletionTime::total 284367 # Table walker service (enqueue to completion) latency 1769system.cpu1.dtb.walker.walksPending::samples 458679401608 # Table walker pending requests distribution 1770system.cpu1.dtb.walker.walksPending::mean 0.570209 # Table walker pending requests distribution 1771system.cpu1.dtb.walker.walksPending::stdev 0.555852 # Table walker pending requests distribution 1772system.cpu1.dtb.walker.walksPending::0-1 457501852108 99.74% 99.74% # Table walker pending requests distribution 1773system.cpu1.dtb.walker.walksPending::2-3 610883500 0.13% 99.88% # Table walker pending requests distribution 1774system.cpu1.dtb.walker.walksPending::4-5 255647500 0.06% 99.93% # Table walker pending requests distribution 1775system.cpu1.dtb.walker.walksPending::6-7 124159500 0.03% 99.96% # Table walker pending requests distribution 1776system.cpu1.dtb.walker.walksPending::8-9 89499500 0.02% 99.98% # Table walker pending requests distribution 1777system.cpu1.dtb.walker.walksPending::10-11 56037000 0.01% 99.99% # Table walker pending requests distribution 1778system.cpu1.dtb.walker.walksPending::12-13 17511000 0.00% 99.99% # Table walker pending requests distribution 1779system.cpu1.dtb.walker.walksPending::14-15 23464500 0.01% 100.00% # Table walker pending requests distribution 1780system.cpu1.dtb.walker.walksPending::16-17 345500 0.00% 100.00% # Table walker pending requests distribution 1781system.cpu1.dtb.walker.walksPending::18-19 1500 0.00% 100.00% # Table walker pending requests distribution 1782system.cpu1.dtb.walker.walksPending::total 458679401608 # Table walker pending requests distribution 1783system.cpu1.dtb.walker.walkPageSizes::4K 88263 88.13% 88.13% # Table walker page sizes translated 1784system.cpu1.dtb.walker.walkPageSizes::2M 11885 11.87% 100.00% # Table walker page sizes translated 1785system.cpu1.dtb.walker.walkPageSizes::total 100148 # Table walker page sizes translated 1786system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 548057 # Table walker requests started/completed, data/inst 1787system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1788system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 548057 # Table walker requests started/completed, data/inst 1789system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 100148 # Table walker requests started/completed, data/inst 1790system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1791system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 100148 # Table walker requests started/completed, data/inst 1792system.cpu1.dtb.walker.walkRequestOrigin::total 648205 # Table walker requests started/completed, data/inst 1793system.cpu1.dtb.inst_hits 0 # ITB inst hits 1794system.cpu1.dtb.inst_misses 0 # ITB inst misses 1795system.cpu1.dtb.read_hits 92943696 # DTB read hits 1796system.cpu1.dtb.read_misses 375200 # DTB read misses 1797system.cpu1.dtb.write_hits 76575759 # DTB write hits 1798system.cpu1.dtb.write_misses 172857 # DTB write misses 1799system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed 1800system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1801system.cpu1.dtb.flush_tlb_mva_asid 46180 # Number of times TLB was flushed by MVA & ASID 1802system.cpu1.dtb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID 1803system.cpu1.dtb.flush_entries 35565 # Number of entries that have been flushed from TLB 1804system.cpu1.dtb.align_faults 273 # Number of TLB faults due to alignment restrictions 1805system.cpu1.dtb.prefetch_faults 6009 # Number of TLB faults due to prefetch 1806system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1807system.cpu1.dtb.perms_faults 39938 # Number of TLB faults due to permissions restrictions 1808system.cpu1.dtb.read_accesses 93318896 # DTB read accesses 1809system.cpu1.dtb.write_accesses 76748616 # DTB write accesses 1810system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1811system.cpu1.dtb.hits 169519455 # DTB hits 1812system.cpu1.dtb.misses 548057 # DTB misses 1813system.cpu1.dtb.accesses 170067512 # DTB accesses 1814system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1815system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1816system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1817system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1818system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1819system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1820system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1821system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1822system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1823system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1824system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1825system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1826system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1827system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1828system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1829system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1830system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1831system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1832system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1833system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1834system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1835system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1836system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1837system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1838system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1839system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1840system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1841system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1842system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1843system.cpu1.itb.walker.walks 81693 # Table walker walks requested 1844system.cpu1.itb.walker.walksLong 81693 # Table walker walks initiated with long descriptors 1845system.cpu1.itb.walker.walksLongTerminationLevel::Level2 804 # Level at which table walker walks with long descriptors terminate 1846system.cpu1.itb.walker.walksLongTerminationLevel::Level3 58754 # Level at which table walker walks with long descriptors terminate 1847system.cpu1.itb.walker.walksSquashedBefore 9814 # Table walks squashed before starting 1848system.cpu1.itb.walker.walkWaitTime::samples 71879 # Table walker wait (enqueue to first request) latency 1849system.cpu1.itb.walker.walkWaitTime::mean 1351.430877 # Table walker wait (enqueue to first request) latency 1850system.cpu1.itb.walker.walkWaitTime::stdev 10594.939676 # Table walker wait (enqueue to first request) latency 1851system.cpu1.itb.walker.walkWaitTime::0-32767 71238 99.11% 99.11% # Table walker wait (enqueue to first request) latency 1852system.cpu1.itb.walker.walkWaitTime::32768-65535 384 0.53% 99.64% # Table walker wait (enqueue to first request) latency 1853system.cpu1.itb.walker.walkWaitTime::65536-98303 26 0.04% 99.68% # Table walker wait (enqueue to first request) latency 1854system.cpu1.itb.walker.walkWaitTime::98304-131071 48 0.07% 99.75% # Table walker wait (enqueue to first request) latency 1855system.cpu1.itb.walker.walkWaitTime::131072-163839 113 0.16% 99.90% # Table walker wait (enqueue to first request) latency 1856system.cpu1.itb.walker.walkWaitTime::163840-196607 53 0.07% 99.98% # Table walker wait (enqueue to first request) latency 1857system.cpu1.itb.walker.walkWaitTime::196608-229375 3 0.00% 99.98% # Table walker wait (enqueue to first request) latency 1858system.cpu1.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency 1859system.cpu1.itb.walker.walkWaitTime::262144-294911 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency 1860system.cpu1.itb.walker.walkWaitTime::294912-327679 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency 1861system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency 1862system.cpu1.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1863system.cpu1.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1864system.cpu1.itb.walker.walkWaitTime::458752-491519 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1865system.cpu1.itb.walker.walkWaitTime::total 71879 # Table walker wait (enqueue to first request) latency 1866system.cpu1.itb.walker.walkCompletionTime::samples 69372 # Table walker service (enqueue to completion) latency 1867system.cpu1.itb.walker.walkCompletionTime::mean 25253.272214 # Table walker service (enqueue to completion) latency 1868system.cpu1.itb.walker.walkCompletionTime::gmean 22467.195437 # Table walker service (enqueue to completion) latency 1869system.cpu1.itb.walker.walkCompletionTime::stdev 22091.390725 # Table walker service (enqueue to completion) latency 1870system.cpu1.itb.walker.walkCompletionTime::0-65535 68357 98.54% 98.54% # Table walker service (enqueue to completion) latency 1871system.cpu1.itb.walker.walkCompletionTime::65536-131071 80 0.12% 98.65% # Table walker service (enqueue to completion) latency 1872system.cpu1.itb.walker.walkCompletionTime::131072-196607 757 1.09% 99.74% # Table walker service (enqueue to completion) latency 1873system.cpu1.itb.walker.walkCompletionTime::196608-262143 76 0.11% 99.85% # Table walker service (enqueue to completion) latency 1874system.cpu1.itb.walker.walkCompletionTime::262144-327679 55 0.08% 99.93% # Table walker service (enqueue to completion) latency 1875system.cpu1.itb.walker.walkCompletionTime::327680-393215 17 0.02% 99.96% # Table walker service (enqueue to completion) latency 1876system.cpu1.itb.walker.walkCompletionTime::393216-458751 15 0.02% 99.98% # Table walker service (enqueue to completion) latency 1877system.cpu1.itb.walker.walkCompletionTime::458752-524287 11 0.02% 99.99% # Table walker service (enqueue to completion) latency 1878system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1879system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1880system.cpu1.itb.walker.walkCompletionTime::total 69372 # Table walker service (enqueue to completion) latency 1881system.cpu1.itb.walker.walksPending::samples 407136400556 # Table walker pending requests distribution 1882system.cpu1.itb.walker.walksPending::mean 0.838375 # Table walker pending requests distribution 1883system.cpu1.itb.walker.walksPending::stdev 0.368280 # Table walker pending requests distribution 1884system.cpu1.itb.walker.walksPending::0 65826877124 16.17% 16.17% # Table walker pending requests distribution 1885system.cpu1.itb.walker.walksPending::1 341288268432 83.83% 99.99% # Table walker pending requests distribution 1886system.cpu1.itb.walker.walksPending::2 19212000 0.00% 100.00% # Table walker pending requests distribution 1887system.cpu1.itb.walker.walksPending::3 1863000 0.00% 100.00% # Table walker pending requests distribution 1888system.cpu1.itb.walker.walksPending::4 150500 0.00% 100.00% # Table walker pending requests distribution 1889system.cpu1.itb.walker.walksPending::5 29500 0.00% 100.00% # Table walker pending requests distribution 1890system.cpu1.itb.walker.walksPending::total 407136400556 # Table walker pending requests distribution 1891system.cpu1.itb.walker.walkPageSizes::4K 58754 98.65% 98.65% # Table walker page sizes translated 1892system.cpu1.itb.walker.walkPageSizes::2M 804 1.35% 100.00% # Table walker page sizes translated 1893system.cpu1.itb.walker.walkPageSizes::total 59558 # Table walker page sizes translated 1894system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1895system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 81693 # Table walker requests started/completed, data/inst 1896system.cpu1.itb.walker.walkRequestOrigin_Requested::total 81693 # Table walker requests started/completed, data/inst 1897system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1898system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 59558 # Table walker requests started/completed, data/inst 1899system.cpu1.itb.walker.walkRequestOrigin_Completed::total 59558 # Table walker requests started/completed, data/inst 1900system.cpu1.itb.walker.walkRequestOrigin::total 141251 # Table walker requests started/completed, data/inst 1901system.cpu1.itb.inst_hits 198485673 # ITB inst hits 1902system.cpu1.itb.inst_misses 81693 # ITB inst misses 1903system.cpu1.itb.read_hits 0 # DTB read hits 1904system.cpu1.itb.read_misses 0 # DTB read misses 1905system.cpu1.itb.write_hits 0 # DTB write hits 1906system.cpu1.itb.write_misses 0 # DTB write misses 1907system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed 1908system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1909system.cpu1.itb.flush_tlb_mva_asid 46180 # Number of times TLB was flushed by MVA & ASID 1910system.cpu1.itb.flush_tlb_asid 1083 # Number of times TLB was flushed by ASID 1911system.cpu1.itb.flush_entries 25168 # Number of entries that have been flushed from TLB 1912system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1913system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1914system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1915system.cpu1.itb.perms_faults 206844 # Number of TLB faults due to permissions restrictions 1916system.cpu1.itb.read_accesses 0 # DTB read accesses 1917system.cpu1.itb.write_accesses 0 # DTB write accesses 1918system.cpu1.itb.inst_accesses 198567366 # ITB inst accesses 1919system.cpu1.itb.hits 198485673 # DTB hits 1920system.cpu1.itb.misses 81693 # DTB misses 1921system.cpu1.itb.accesses 198567366 # DTB accesses 1922system.cpu1.numCycles 706357244 # number of cpu cycles simulated 1923system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1924system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1925system.cpu1.fetch.icacheStallCycles 79757859 # Number of cycles fetch is stalled on an Icache miss 1926system.cpu1.fetch.Insts 558826368 # Number of instructions fetch has processed 1927system.cpu1.fetch.Branches 126248667 # Number of branches that fetch encountered 1928system.cpu1.fetch.predictedBranches 74669921 # Number of branches that fetch has predicted taken 1929system.cpu1.fetch.Cycles 588203471 # Number of cycles fetch has run and was not squashing or blocked 1930system.cpu1.fetch.SquashCycles 13287396 # Number of cycles fetch has spent squashing 1931system.cpu1.fetch.TlbCycles 1859618 # Number of cycles fetch has spent waiting for tlb 1932system.cpu1.fetch.MiscStallCycles 301703 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1933system.cpu1.fetch.PendingTrapStallCycles 6107940 # Number of stall cycles due to pending traps 1934system.cpu1.fetch.PendingQuiesceStallCycles 765855 # Number of stall cycles due to pending quiesce instructions 1935system.cpu1.fetch.IcacheWaitRetryStallCycles 800562 # Number of stall cycles due to full MSHR 1936system.cpu1.fetch.CacheLines 198257766 # Number of cache lines fetched 1937system.cpu1.fetch.IcacheSquashes 1531728 # Number of outstanding Icache misses that were squashed 1938system.cpu1.fetch.ItlbSquashes 28220 # Number of outstanding ITLB misses that were squashed 1939system.cpu1.fetch.rateDist::samples 684440706 # Number of instructions fetched each cycle (Total) 1940system.cpu1.fetch.rateDist::mean 0.958907 # Number of instructions fetched each cycle (Total) 1941system.cpu1.fetch.rateDist::stdev 1.215902 # Number of instructions fetched each cycle (Total) 1942system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1943system.cpu1.fetch.rateDist::0 370240796 54.09% 54.09% # Number of instructions fetched each cycle (Total) 1944system.cpu1.fetch.rateDist::1 122429423 17.89% 71.98% # Number of instructions fetched each cycle (Total) 1945system.cpu1.fetch.rateDist::2 41426108 6.05% 78.03% # Number of instructions fetched each cycle (Total) 1946system.cpu1.fetch.rateDist::3 150344379 21.97% 100.00% # Number of instructions fetched each cycle (Total) 1947system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1948system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1949system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 1950system.cpu1.fetch.rateDist::total 684440706 # Number of instructions fetched each cycle (Total) 1951system.cpu1.fetch.branchRate 0.178732 # Number of branch fetches per cycle 1952system.cpu1.fetch.rate 0.791138 # Number of inst fetches per cycle 1953system.cpu1.decode.IdleCycles 96144629 # Number of cycles decode is idle 1954system.cpu1.decode.BlockedCycles 340788757 # Number of cycles decode is blocked 1955system.cpu1.decode.RunCycles 207685438 # Number of cycles decode is running 1956system.cpu1.decode.UnblockCycles 35085697 # Number of cycles decode is unblocking 1957system.cpu1.decode.SquashCycles 4736185 # Number of cycles decode is squashing 1958system.cpu1.decode.BranchResolved 17812454 # Number of times decode resolved a branch 1959system.cpu1.decode.BranchMispred 1944962 # Number of times decode detected a branch misprediction 1960system.cpu1.decode.DecodedInsts 579921351 # Number of instructions handled by decode 1961system.cpu1.decode.SquashedInsts 21338656 # Number of squashed instructions handled by decode 1962system.cpu1.rename.SquashCycles 4736185 # Number of cycles rename is squashing 1963system.cpu1.rename.IdleCycles 128930138 # Number of cycles rename is idle 1964system.cpu1.rename.BlockCycles 49237812 # Number of cycles rename is blocking 1965system.cpu1.rename.serializeStallCycles 228920665 # count of cycles rename stalled for serializing inst 1966system.cpu1.rename.RunCycles 209565208 # Number of cycles rename is running 1967system.cpu1.rename.UnblockCycles 63050698 # Number of cycles rename is unblocking 1968system.cpu1.rename.RenamedInsts 564205236 # Number of instructions processed by rename 1969system.cpu1.rename.SquashedInsts 5454916 # Number of squashed instructions processed by rename 1970system.cpu1.rename.ROBFullEvents 10256691 # Number of times rename has blocked due to ROB full 1971system.cpu1.rename.IQFullEvents 240677 # Number of times rename has blocked due to IQ full 1972system.cpu1.rename.LQFullEvents 354262 # Number of times rename has blocked due to LQ full 1973system.cpu1.rename.SQFullEvents 30213880 # Number of times rename has blocked due to SQ full 1974system.cpu1.rename.FullRegisterEvents 11171 # Number of times there has been no free registers 1975system.cpu1.rename.RenamedOperands 537096625 # Number of destination operands rename has renamed 1976system.cpu1.rename.RenameLookups 872562806 # Number of register rename lookups that rename has made 1977system.cpu1.rename.int_rename_lookups 667157366 # Number of integer rename lookups 1978system.cpu1.rename.fp_rename_lookups 686134 # Number of floating rename lookups 1979system.cpu1.rename.CommittedMaps 483982102 # Number of HB maps that are committed 1980system.cpu1.rename.UndoneMaps 53114517 # Number of HB maps that are undone due to squashing 1981system.cpu1.rename.serializingInsts 15098547 # count of serializing insts renamed 1982system.cpu1.rename.tempSerializingInsts 13303136 # count of temporary serializing insts renamed 1983system.cpu1.rename.skidInsts 70645723 # count of insts added to the skid buffer 1984system.cpu1.memDep0.insertedLoads 92937642 # Number of loads inserted to the mem dependence unit. 1985system.cpu1.memDep0.insertedStores 79702799 # Number of stores inserted to the mem dependence unit. 1986system.cpu1.memDep0.conflictingLoads 8581032 # Number of conflicting loads. 1987system.cpu1.memDep0.conflictingStores 7318731 # Number of conflicting stores. 1988system.cpu1.iq.iqInstsAdded 542982721 # Number of instructions added to the IQ (excludes non-spec) 1989system.cpu1.iq.iqNonSpecInstsAdded 15290733 # Number of non-speculative instructions added to the IQ 1990system.cpu1.iq.iqInstsIssued 547999845 # Number of instructions issued 1991system.cpu1.iq.iqSquashedInstsIssued 2492376 # Number of squashed instructions issued 1992system.cpu1.iq.iqSquashedInstsExamined 50310716 # Number of squashed instructions iterated over during squash; mainly for profiling 1993system.cpu1.iq.iqSquashedOperandsExamined 32527030 # Number of squashed operands that are examined and possibly removed from graph 1994system.cpu1.iq.iqSquashedNonSpecRemoved 258040 # Number of squashed non-spec instructions that were removed 1995system.cpu1.iq.issued_per_cycle::samples 684440706 # Number of insts issued each cycle 1996system.cpu1.iq.issued_per_cycle::mean 0.800653 # Number of insts issued each cycle 1997system.cpu1.iq.issued_per_cycle::stdev 1.060998 # Number of insts issued each cycle 1998system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1999system.cpu1.iq.issued_per_cycle::0 384384408 56.16% 56.16% # Number of insts issued each cycle 2000system.cpu1.iq.issued_per_cycle::1 127393239 18.61% 74.77% # Number of insts issued each cycle 2001system.cpu1.iq.issued_per_cycle::2 104776738 15.31% 90.08% # Number of insts issued each cycle 2002system.cpu1.iq.issued_per_cycle::3 60496264 8.84% 98.92% # Number of insts issued each cycle 2003system.cpu1.iq.issued_per_cycle::4 7385947 1.08% 100.00% # Number of insts issued each cycle 2004system.cpu1.iq.issued_per_cycle::5 4110 0.00% 100.00% # Number of insts issued each cycle 2005system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 2006system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 2007system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 2008system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 2009system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 2010system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 2011system.cpu1.iq.issued_per_cycle::total 684440706 # Number of insts issued each cycle 2012system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 2013system.cpu1.iq.fu_full::IntAlu 55139379 44.00% 44.00% # attempts to use FU when none available 2014system.cpu1.iq.fu_full::IntMult 46977 0.04% 44.04% # attempts to use FU when none available 2015system.cpu1.iq.fu_full::IntDiv 11488 0.01% 44.05% # attempts to use FU when none available 2016system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.05% # attempts to use FU when none available 2017system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.05% # attempts to use FU when none available 2018system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.05% # attempts to use FU when none available 2019system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.05% # attempts to use FU when none available 2020system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.05% # attempts to use FU when none available 2021system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.05% # attempts to use FU when none available 2022system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.05% # attempts to use FU when none available 2023system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.05% # attempts to use FU when none available 2024system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.05% # attempts to use FU when none available 2025system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.05% # attempts to use FU when none available 2026system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.05% # attempts to use FU when none available 2027system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.05% # attempts to use FU when none available 2028system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.05% # attempts to use FU when none available 2029system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.05% # attempts to use FU when none available 2030system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.05% # attempts to use FU when none available 2031system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.05% # attempts to use FU when none available 2032system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.05% # attempts to use FU when none available 2033system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.05% # attempts to use FU when none available 2034system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.05% # attempts to use FU when none available 2035system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.05% # attempts to use FU when none available 2036system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.05% # attempts to use FU when none available 2037system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.05% # attempts to use FU when none available 2038system.cpu1.iq.fu_full::SimdFloatMisc 7 0.00% 44.05% # attempts to use FU when none available 2039system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.05% # attempts to use FU when none available 2040system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.05% # attempts to use FU when none available 2041system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.05% # attempts to use FU when none available 2042system.cpu1.iq.fu_full::MemRead 33502933 26.74% 70.78% # attempts to use FU when none available 2043system.cpu1.iq.fu_full::MemWrite 36611567 29.22% 100.00% # attempts to use FU when none available 2044system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2045system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 2046system.cpu1.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued 2047system.cpu1.iq.FU_type_0::IntAlu 373183107 68.10% 68.10% # Type of FU issued 2048system.cpu1.iq.FU_type_0::IntMult 1202540 0.22% 68.32% # Type of FU issued 2049system.cpu1.iq.FU_type_0::IntDiv 67362 0.01% 68.33% # Type of FU issued 2050system.cpu1.iq.FU_type_0::FloatAdd 2 0.00% 68.33% # Type of FU issued 2051system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.33% # Type of FU issued 2052system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.33% # Type of FU issued 2053system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.33% # Type of FU issued 2054system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.33% # Type of FU issued 2055system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.33% # Type of FU issued 2056system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.33% # Type of FU issued 2057system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.33% # Type of FU issued 2058system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 68.33% # Type of FU issued 2059system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.33% # Type of FU issued 2060system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.33% # Type of FU issued 2061system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.33% # Type of FU issued 2062system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.33% # Type of FU issued 2063system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.33% # Type of FU issued 2064system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.33% # Type of FU issued 2065system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.33% # Type of FU issued 2066system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.33% # Type of FU issued 2067system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.33% # Type of FU issued 2068system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.33% # Type of FU issued 2069system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.33% # Type of FU issued 2070system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.33% # Type of FU issued 2071system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.33% # Type of FU issued 2072system.cpu1.iq.FU_type_0::SimdFloatMisc 42387 0.01% 68.34% # Type of FU issued 2073system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.34% # Type of FU issued 2074system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.34% # Type of FU issued 2075system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.34% # Type of FU issued 2076system.cpu1.iq.FU_type_0::MemRead 95737452 17.47% 85.81% # Type of FU issued 2077system.cpu1.iq.FU_type_0::MemWrite 77766935 14.19% 100.00% # Type of FU issued 2078system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2079system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2080system.cpu1.iq.FU_type_0::total 547999845 # Type of FU issued 2081system.cpu1.iq.rate 0.775811 # Inst issue rate 2082system.cpu1.iq.fu_busy_cnt 125312351 # FU busy when requested 2083system.cpu1.iq.fu_busy_rate 0.228672 # FU busy rate (busy events/executed inst) 2084system.cpu1.iq.int_inst_queue_reads 1907132649 # Number of integer instruction queue reads 2085system.cpu1.iq.int_inst_queue_writes 608283649 # Number of integer instruction queue writes 2086system.cpu1.iq.int_inst_queue_wakeup_accesses 532258075 # Number of integer instruction queue wakeup accesses 2087system.cpu1.iq.fp_inst_queue_reads 1112472 # Number of floating instruction queue reads 2088system.cpu1.iq.fp_inst_queue_writes 437179 # Number of floating instruction queue writes 2089system.cpu1.iq.fp_inst_queue_wakeup_accesses 408398 # Number of floating instruction queue wakeup accesses 2090system.cpu1.iq.int_alu_accesses 672616839 # Number of integer alu accesses 2091system.cpu1.iq.fp_alu_accesses 695346 # Number of floating point alu accesses 2092system.cpu1.iew.lsq.thread0.forwLoads 2459057 # Number of loads that had data forwarded from stores 2093system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2094system.cpu1.iew.lsq.thread0.squashedLoads 11465284 # Number of loads squashed 2095system.cpu1.iew.lsq.thread0.ignoredResponses 14564 # Number of memory responses ignored because the instruction is squashed 2096system.cpu1.iew.lsq.thread0.memOrderViolation 137615 # Number of memory ordering violations 2097system.cpu1.iew.lsq.thread0.squashedStores 5482962 # Number of stores squashed 2098system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2099system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2100system.cpu1.iew.lsq.thread0.rescheduledLoads 2463728 # Number of loads that were rescheduled 2101system.cpu1.iew.lsq.thread0.cacheBlocked 4019009 # Number of times an access to memory failed due to the cache being blocked 2102system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2103system.cpu1.iew.iewSquashCycles 4736185 # Number of cycles IEW is squashing 2104system.cpu1.iew.iewBlockCycles 6263173 # Number of cycles IEW is blocking 2105system.cpu1.iew.iewUnblockCycles 2375395 # Number of cycles IEW is unblocking 2106system.cpu1.iew.iewDispatchedInsts 558389408 # Number of instructions dispatched to IQ 2107system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 2108system.cpu1.iew.iewDispLoadInsts 92937642 # Number of dispatched load instructions 2109system.cpu1.iew.iewDispStoreInsts 79702799 # Number of dispatched store instructions 2110system.cpu1.iew.iewDispNonSpecInsts 13061254 # Number of dispatched non-speculative instructions 2111system.cpu1.iew.iewIQFullEvents 63231 # Number of times the IQ has become full, causing a stall 2112system.cpu1.iew.iewLSQFullEvents 2253383 # Number of times the LSQ has become full, causing a stall 2113system.cpu1.iew.memOrderViolationEvents 137615 # Number of memory order violations 2114system.cpu1.iew.predictedTakenIncorrect 1902304 # Number of branches that were predicted taken incorrectly 2115system.cpu1.iew.predictedNotTakenIncorrect 2611236 # Number of branches that were predicted not taken incorrectly 2116system.cpu1.iew.branchMispredicts 4513540 # Number of branch mispredicts detected at execute 2117system.cpu1.iew.iewExecutedInsts 540870869 # Number of executed instructions 2118system.cpu1.iew.iewExecLoadInsts 92937926 # Number of load instructions executed 2119system.cpu1.iew.iewExecSquashedInsts 6592838 # Number of squashed instructions skipped in execute 2120system.cpu1.iew.exec_swp 0 # number of swp insts executed 2121system.cpu1.iew.exec_nop 115954 # number of nop insts executed 2122system.cpu1.iew.exec_refs 169513519 # number of memory reference insts executed 2123system.cpu1.iew.exec_branches 101590895 # Number of branches executed 2124system.cpu1.iew.exec_stores 76575593 # Number of stores executed 2125system.cpu1.iew.exec_rate 0.765719 # Inst execution rate 2126system.cpu1.iew.wb_sent 533377466 # cumulative count of insts sent to commit 2127system.cpu1.iew.wb_count 532666473 # cumulative count of insts written-back 2128system.cpu1.iew.wb_producers 257434056 # num instructions producing a value 2129system.cpu1.iew.wb_consumers 422362739 # num instructions consuming a value 2130system.cpu1.iew.wb_rate 0.754104 # insts written-back per cycle 2131system.cpu1.iew.wb_fanout 0.609509 # average fanout of values written-back 2132system.cpu1.commit.commitSquashedInsts 44033715 # The number of squashed insts skipped by commit 2133system.cpu1.commit.commitNonSpecStalls 15032693 # The number of times commit has been forced to stall to communicate backwards 2134system.cpu1.commit.branchMispredicts 4244342 # The number of times a branch was mispredicted 2135system.cpu1.commit.committed_per_cycle::samples 676109975 # Number of insts commited each cycle 2136system.cpu1.commit.committed_per_cycle::mean 0.751302 # Number of insts commited each cycle 2137system.cpu1.commit.committed_per_cycle::stdev 1.553770 # Number of insts commited each cycle 2138system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2139system.cpu1.commit.committed_per_cycle::0 452513238 66.93% 66.93% # Number of insts commited each cycle 2140system.cpu1.commit.committed_per_cycle::1 117033560 17.31% 84.24% # Number of insts commited each cycle 2141system.cpu1.commit.committed_per_cycle::2 49159205 7.27% 91.51% # Number of insts commited each cycle 2142system.cpu1.commit.committed_per_cycle::3 16297256 2.41% 93.92% # Number of insts commited each cycle 2143system.cpu1.commit.committed_per_cycle::4 11766410 1.74% 95.66% # Number of insts commited each cycle 2144system.cpu1.commit.committed_per_cycle::5 7925929 1.17% 96.83% # Number of insts commited each cycle 2145system.cpu1.commit.committed_per_cycle::6 5496145 0.81% 97.65% # Number of insts commited each cycle 2146system.cpu1.commit.committed_per_cycle::7 3299018 0.49% 98.13% # Number of insts commited each cycle 2147system.cpu1.commit.committed_per_cycle::8 12619214 1.87% 100.00% # Number of insts commited each cycle 2148system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2149system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2150system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2151system.cpu1.commit.committed_per_cycle::total 676109975 # Number of insts commited each cycle 2152system.cpu1.commit.committedInsts 431347574 # Number of instructions committed 2153system.cpu1.commit.committedOps 507962731 # Number of ops (including micro ops) committed 2154system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 2155system.cpu1.commit.refs 155692194 # Number of memory references committed 2156system.cpu1.commit.loads 81472357 # Number of loads committed 2157system.cpu1.commit.membars 3613840 # Number of memory barriers committed 2158system.cpu1.commit.branches 96395557 # Number of branches committed 2159system.cpu1.commit.fp_insts 400161 # Number of committed floating point instructions. 2160system.cpu1.commit.int_insts 466077725 # Number of committed integer instructions. 2161system.cpu1.commit.function_calls 12507771 # Number of function calls committed. 2162system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 2163system.cpu1.commit.op_class_0::IntAlu 351213617 69.14% 69.14% # Class of committed instruction 2164system.cpu1.commit.op_class_0::IntMult 966298 0.19% 69.33% # Class of committed instruction 2165system.cpu1.commit.op_class_0::IntDiv 53161 0.01% 69.34% # Class of committed instruction 2166system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.34% # Class of committed instruction 2167system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.34% # Class of committed instruction 2168system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.34% # Class of committed instruction 2169system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.34% # Class of committed instruction 2170system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.34% # Class of committed instruction 2171system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.34% # Class of committed instruction 2172system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.34% # Class of committed instruction 2173system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.34% # Class of committed instruction 2174system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.34% # Class of committed instruction 2175system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.34% # Class of committed instruction 2176system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.34% # Class of committed instruction 2177system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.34% # Class of committed instruction 2178system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.34% # Class of committed instruction 2179system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.34% # Class of committed instruction 2180system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.34% # Class of committed instruction 2181system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.34% # Class of committed instruction 2182system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.34% # Class of committed instruction 2183system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.34% # Class of committed instruction 2184system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.34% # Class of committed instruction 2185system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.34% # Class of committed instruction 2186system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.34% # Class of committed instruction 2187system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.34% # Class of committed instruction 2188system.cpu1.commit.op_class_0::SimdFloatMisc 37419 0.01% 69.35% # Class of committed instruction 2189system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.35% # Class of committed instruction 2190system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.35% # Class of committed instruction 2191system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.35% # Class of committed instruction 2192system.cpu1.commit.op_class_0::MemRead 81472357 16.04% 85.39% # Class of committed instruction 2193system.cpu1.commit.op_class_0::MemWrite 74219837 14.61% 100.00% # Class of committed instruction 2194system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2195system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 2196system.cpu1.commit.op_class_0::total 507962731 # Class of committed instruction 2197system.cpu1.commit.bw_lim_events 12619214 # number cycles where commit BW limit reached 2198system.cpu1.rob.rob_reads 1211577193 # The number of ROB reads 2199system.cpu1.rob.rob_writes 1112287280 # The number of ROB writes 2200system.cpu1.timesIdled 906823 # Number of times that the entire CPU went into an idle state and unscheduled itself 2201system.cpu1.idleCycles 21916538 # Total number of cycles that the CPU has spent unscheduled due to idling 2202system.cpu1.quiesceCycles 94073218429 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2203system.cpu1.committedInsts 431347574 # Number of Instructions Simulated 2204system.cpu1.committedOps 507962731 # Number of Ops (including micro ops) Simulated 2205system.cpu1.cpi 1.637559 # CPI: Cycles Per Instruction 2206system.cpu1.cpi_total 1.637559 # CPI: Total CPI of All Threads 2207system.cpu1.ipc 0.610665 # IPC: Instructions Per Cycle 2208system.cpu1.ipc_total 0.610665 # IPC: Total IPC of All Threads 2209system.cpu1.int_regfile_reads 639350275 # number of integer regfile reads 2210system.cpu1.int_regfile_writes 378298878 # number of integer regfile writes 2211system.cpu1.fp_regfile_reads 675031 # number of floating regfile reads 2212system.cpu1.fp_regfile_writes 302028 # number of floating regfile writes 2213system.cpu1.cc_regfile_reads 116956107 # number of cc regfile reads 2214system.cpu1.cc_regfile_writes 117682636 # number of cc regfile writes 2215system.cpu1.misc_regfile_reads 1203449961 # number of misc regfile reads 2216system.cpu1.misc_regfile_writes 15173732 # number of misc regfile writes 2217system.cpu1.dcache.tags.replacements 5181385 # number of replacements 2218system.cpu1.dcache.tags.tagsinuse 448.144658 # Cycle average of tags in use 2219system.cpu1.dcache.tags.total_refs 145015910 # Total number of references to valid blocks. 2220system.cpu1.dcache.tags.sampled_refs 5181896 # Sample count of references to valid blocks. 2221system.cpu1.dcache.tags.avg_refs 27.985106 # Average number of references to valid blocks. 2222system.cpu1.dcache.tags.warmup_cycle 8482612216500 # Cycle when the warmup percentage was hit. 2223system.cpu1.dcache.tags.occ_blocks::cpu1.data 448.144658 # Average occupied blocks per requestor 2224system.cpu1.dcache.tags.occ_percent::cpu1.data 0.875283 # Average percentage of cache occupancy 2225system.cpu1.dcache.tags.occ_percent::total 0.875283 # Average percentage of cache occupancy 2226system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 2227system.cpu1.dcache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id 2228system.cpu1.dcache.tags.age_task_id_blocks_1024::1 377 # Occupied blocks per task id 2229system.cpu1.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id 2230system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 2231system.cpu1.dcache.tags.tag_accesses 322931039 # Number of tag accesses 2232system.cpu1.dcache.tags.data_accesses 322931039 # Number of data accesses 2233system.cpu1.dcache.ReadReq_hits::cpu1.data 75698887 # number of ReadReq hits 2234system.cpu1.dcache.ReadReq_hits::total 75698887 # number of ReadReq hits 2235system.cpu1.dcache.WriteReq_hits::cpu1.data 64698314 # number of WriteReq hits 2236system.cpu1.dcache.WriteReq_hits::total 64698314 # number of WriteReq hits 2237system.cpu1.dcache.SoftPFReq_hits::cpu1.data 177630 # number of SoftPFReq hits 2238system.cpu1.dcache.SoftPFReq_hits::total 177630 # number of SoftPFReq hits 2239system.cpu1.dcache.WriteLineReq_hits::cpu1.data 137318 # number of WriteLineReq hits 2240system.cpu1.dcache.WriteLineReq_hits::total 137318 # number of WriteLineReq hits 2241system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1768516 # number of LoadLockedReq hits 2242system.cpu1.dcache.LoadLockedReq_hits::total 1768516 # number of LoadLockedReq hits 2243system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1769874 # number of StoreCondReq hits 2244system.cpu1.dcache.StoreCondReq_hits::total 1769874 # number of StoreCondReq hits 2245system.cpu1.dcache.demand_hits::cpu1.data 140397201 # number of demand (read+write) hits 2246system.cpu1.dcache.demand_hits::total 140397201 # number of demand (read+write) hits 2247system.cpu1.dcache.overall_hits::cpu1.data 140574831 # number of overall hits 2248system.cpu1.dcache.overall_hits::total 140574831 # number of overall hits 2249system.cpu1.dcache.ReadReq_misses::cpu1.data 6071314 # number of ReadReq misses 2250system.cpu1.dcache.ReadReq_misses::total 6071314 # number of ReadReq misses 2251system.cpu1.dcache.WriteReq_misses::cpu1.data 6974888 # number of WriteReq misses 2252system.cpu1.dcache.WriteReq_misses::total 6974888 # number of WriteReq misses 2253system.cpu1.dcache.SoftPFReq_misses::cpu1.data 655927 # number of SoftPFReq misses 2254system.cpu1.dcache.SoftPFReq_misses::total 655927 # number of SoftPFReq misses 2255system.cpu1.dcache.WriteLineReq_misses::cpu1.data 434582 # number of WriteLineReq misses 2256system.cpu1.dcache.WriteLineReq_misses::total 434582 # number of WriteLineReq misses 2257system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 243161 # number of LoadLockedReq misses 2258system.cpu1.dcache.LoadLockedReq_misses::total 243161 # number of LoadLockedReq misses 2259system.cpu1.dcache.StoreCondReq_misses::cpu1.data 198274 # number of StoreCondReq misses 2260system.cpu1.dcache.StoreCondReq_misses::total 198274 # number of StoreCondReq misses 2261system.cpu1.dcache.demand_misses::cpu1.data 13046202 # number of demand (read+write) misses 2262system.cpu1.dcache.demand_misses::total 13046202 # number of demand (read+write) misses 2263system.cpu1.dcache.overall_misses::cpu1.data 13702129 # number of overall misses 2264system.cpu1.dcache.overall_misses::total 13702129 # number of overall misses 2265system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 101097830500 # number of ReadReq miss cycles 2266system.cpu1.dcache.ReadReq_miss_latency::total 101097830500 # number of ReadReq miss cycles 2267system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 149656092437 # number of WriteReq miss cycles 2268system.cpu1.dcache.WriteReq_miss_latency::total 149656092437 # number of WriteReq miss cycles 2269system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 16022463739 # number of WriteLineReq miss cycles 2270system.cpu1.dcache.WriteLineReq_miss_latency::total 16022463739 # number of WriteLineReq miss cycles 2271system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3928870000 # number of LoadLockedReq miss cycles 2272system.cpu1.dcache.LoadLockedReq_miss_latency::total 3928870000 # number of LoadLockedReq miss cycles 2273system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5496174000 # number of StoreCondReq miss cycles 2274system.cpu1.dcache.StoreCondReq_miss_latency::total 5496174000 # number of StoreCondReq miss cycles 2275system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4605500 # number of StoreCondFailReq miss cycles 2276system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4605500 # number of StoreCondFailReq miss cycles 2277system.cpu1.dcache.demand_miss_latency::cpu1.data 250753922937 # number of demand (read+write) miss cycles 2278system.cpu1.dcache.demand_miss_latency::total 250753922937 # number of demand (read+write) miss cycles 2279system.cpu1.dcache.overall_miss_latency::cpu1.data 250753922937 # number of overall miss cycles 2280system.cpu1.dcache.overall_miss_latency::total 250753922937 # number of overall miss cycles 2281system.cpu1.dcache.ReadReq_accesses::cpu1.data 81770201 # number of ReadReq accesses(hits+misses) 2282system.cpu1.dcache.ReadReq_accesses::total 81770201 # number of ReadReq accesses(hits+misses) 2283system.cpu1.dcache.WriteReq_accesses::cpu1.data 71673202 # number of WriteReq accesses(hits+misses) 2284system.cpu1.dcache.WriteReq_accesses::total 71673202 # number of WriteReq accesses(hits+misses) 2285system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 833557 # number of SoftPFReq accesses(hits+misses) 2286system.cpu1.dcache.SoftPFReq_accesses::total 833557 # number of SoftPFReq accesses(hits+misses) 2287system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 571900 # number of WriteLineReq accesses(hits+misses) 2288system.cpu1.dcache.WriteLineReq_accesses::total 571900 # number of WriteLineReq accesses(hits+misses) 2289system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2011677 # number of LoadLockedReq accesses(hits+misses) 2290system.cpu1.dcache.LoadLockedReq_accesses::total 2011677 # number of LoadLockedReq accesses(hits+misses) 2291system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1968148 # number of StoreCondReq accesses(hits+misses) 2292system.cpu1.dcache.StoreCondReq_accesses::total 1968148 # number of StoreCondReq accesses(hits+misses) 2293system.cpu1.dcache.demand_accesses::cpu1.data 153443403 # number of demand (read+write) accesses 2294system.cpu1.dcache.demand_accesses::total 153443403 # number of demand (read+write) accesses 2295system.cpu1.dcache.overall_accesses::cpu1.data 154276960 # number of overall (read+write) accesses 2296system.cpu1.dcache.overall_accesses::total 154276960 # number of overall (read+write) accesses 2297system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074248 # miss rate for ReadReq accesses 2298system.cpu1.dcache.ReadReq_miss_rate::total 0.074248 # miss rate for ReadReq accesses 2299system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.097315 # miss rate for WriteReq accesses 2300system.cpu1.dcache.WriteReq_miss_rate::total 0.097315 # miss rate for WriteReq accesses 2301system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.786901 # miss rate for SoftPFReq accesses 2302system.cpu1.dcache.SoftPFReq_miss_rate::total 0.786901 # miss rate for SoftPFReq accesses 2303system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.759892 # miss rate for WriteLineReq accesses 2304system.cpu1.dcache.WriteLineReq_miss_rate::total 0.759892 # miss rate for WriteLineReq accesses 2305system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120875 # miss rate for LoadLockedReq accesses 2306system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120875 # miss rate for LoadLockedReq accesses 2307system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100741 # miss rate for StoreCondReq accesses 2308system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100741 # miss rate for StoreCondReq accesses 2309system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085023 # miss rate for demand accesses 2310system.cpu1.dcache.demand_miss_rate::total 0.085023 # miss rate for demand accesses 2311system.cpu1.dcache.overall_miss_rate::cpu1.data 0.088815 # miss rate for overall accesses 2312system.cpu1.dcache.overall_miss_rate::total 0.088815 # miss rate for overall accesses 2313system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16651.721604 # average ReadReq miss latency 2314system.cpu1.dcache.ReadReq_avg_miss_latency::total 16651.721604 # average ReadReq miss latency 2315system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21456.415133 # average WriteReq miss latency 2316system.cpu1.dcache.WriteReq_avg_miss_latency::total 21456.415133 # average WriteReq miss latency 2317system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 36868.677808 # average WriteLineReq miss latency 2318system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 36868.677808 # average WriteLineReq miss latency 2319system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 16157.484136 # average LoadLockedReq miss latency 2320system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 16157.484136 # average LoadLockedReq miss latency 2321system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27720.094415 # average StoreCondReq miss latency 2322system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27720.094415 # average StoreCondReq miss latency 2323system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2324system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 2325system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19220.453810 # average overall miss latency 2326system.cpu1.dcache.demand_avg_miss_latency::total 19220.453810 # average overall miss latency 2327system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18300.362151 # average overall miss latency 2328system.cpu1.dcache.overall_avg_miss_latency::total 18300.362151 # average overall miss latency 2329system.cpu1.dcache.blocked_cycles::no_mshrs 4223664 # number of cycles access was blocked 2330system.cpu1.dcache.blocked_cycles::no_targets 23883166 # number of cycles access was blocked 2331system.cpu1.dcache.blocked::no_mshrs 349910 # number of cycles access was blocked 2332system.cpu1.dcache.blocked::no_targets 702949 # number of cycles access was blocked 2333system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12.070715 # average number of cycles each access was blocked 2334system.cpu1.dcache.avg_blocked_cycles::no_targets 33.975674 # average number of cycles each access was blocked 2335system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2336system.cpu1.dcache.cache_copies 0 # number of cache copies performed 2337system.cpu1.dcache.writebacks::writebacks 5181409 # number of writebacks 2338system.cpu1.dcache.writebacks::total 5181409 # number of writebacks 2339system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3107506 # number of ReadReq MSHR hits 2340system.cpu1.dcache.ReadReq_mshr_hits::total 3107506 # number of ReadReq MSHR hits 2341system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5642769 # number of WriteReq MSHR hits 2342system.cpu1.dcache.WriteReq_mshr_hits::total 5642769 # number of WriteReq MSHR hits 2343system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3498 # number of WriteLineReq MSHR hits 2344system.cpu1.dcache.WriteLineReq_mshr_hits::total 3498 # number of WriteLineReq MSHR hits 2345system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 127094 # number of LoadLockedReq MSHR hits 2346system.cpu1.dcache.LoadLockedReq_mshr_hits::total 127094 # number of LoadLockedReq MSHR hits 2347system.cpu1.dcache.demand_mshr_hits::cpu1.data 8750275 # number of demand (read+write) MSHR hits 2348system.cpu1.dcache.demand_mshr_hits::total 8750275 # number of demand (read+write) MSHR hits 2349system.cpu1.dcache.overall_mshr_hits::cpu1.data 8750275 # number of overall MSHR hits 2350system.cpu1.dcache.overall_mshr_hits::total 8750275 # number of overall MSHR hits 2351system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2963808 # number of ReadReq MSHR misses 2352system.cpu1.dcache.ReadReq_mshr_misses::total 2963808 # number of ReadReq MSHR misses 2353system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1332119 # number of WriteReq MSHR misses 2354system.cpu1.dcache.WriteReq_mshr_misses::total 1332119 # number of WriteReq MSHR misses 2355system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 655846 # number of SoftPFReq MSHR misses 2356system.cpu1.dcache.SoftPFReq_mshr_misses::total 655846 # number of SoftPFReq MSHR misses 2357system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 431084 # number of WriteLineReq MSHR misses 2358system.cpu1.dcache.WriteLineReq_mshr_misses::total 431084 # number of WriteLineReq MSHR misses 2359system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116067 # number of LoadLockedReq MSHR misses 2360system.cpu1.dcache.LoadLockedReq_mshr_misses::total 116067 # number of LoadLockedReq MSHR misses 2361system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 198274 # number of StoreCondReq MSHR misses 2362system.cpu1.dcache.StoreCondReq_mshr_misses::total 198274 # number of StoreCondReq MSHR misses 2363system.cpu1.dcache.demand_mshr_misses::cpu1.data 4295927 # number of demand (read+write) MSHR misses 2364system.cpu1.dcache.demand_mshr_misses::total 4295927 # number of demand (read+write) MSHR misses 2365system.cpu1.dcache.overall_mshr_misses::cpu1.data 4951773 # number of overall MSHR misses 2366system.cpu1.dcache.overall_mshr_misses::total 4951773 # number of overall MSHR misses 2367system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 18536 # number of ReadReq MSHR uncacheable 2368system.cpu1.dcache.ReadReq_mshr_uncacheable::total 18536 # number of ReadReq MSHR uncacheable 2369system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 16538 # number of WriteReq MSHR uncacheable 2370system.cpu1.dcache.WriteReq_mshr_uncacheable::total 16538 # number of WriteReq MSHR uncacheable 2371system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 35074 # number of overall MSHR uncacheable misses 2372system.cpu1.dcache.overall_mshr_uncacheable_misses::total 35074 # number of overall MSHR uncacheable misses 2373system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 45006607000 # number of ReadReq MSHR miss cycles 2374system.cpu1.dcache.ReadReq_mshr_miss_latency::total 45006607000 # number of ReadReq MSHR miss cycles 2375system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 31827699093 # number of WriteReq MSHR miss cycles 2376system.cpu1.dcache.WriteReq_mshr_miss_latency::total 31827699093 # number of WriteReq MSHR miss cycles 2377system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 16353139500 # number of SoftPFReq MSHR miss cycles 2378system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 16353139500 # number of SoftPFReq MSHR miss cycles 2379system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 15385116239 # number of WriteLineReq MSHR miss cycles 2380system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 15385116239 # number of WriteLineReq MSHR miss cycles 2381system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1766523500 # number of LoadLockedReq MSHR miss cycles 2382system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1766523500 # number of LoadLockedReq MSHR miss cycles 2383system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5297954000 # number of StoreCondReq MSHR miss cycles 2384system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5297954000 # number of StoreCondReq MSHR miss cycles 2385system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4551500 # number of StoreCondFailReq MSHR miss cycles 2386system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4551500 # number of StoreCondFailReq MSHR miss cycles 2387system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 76834306093 # number of demand (read+write) MSHR miss cycles 2388system.cpu1.dcache.demand_mshr_miss_latency::total 76834306093 # number of demand (read+write) MSHR miss cycles 2389system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 93187445593 # number of overall MSHR miss cycles 2390system.cpu1.dcache.overall_mshr_miss_latency::total 93187445593 # number of overall MSHR miss cycles 2391system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3073252500 # number of ReadReq MSHR uncacheable cycles 2392system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3073252500 # number of ReadReq MSHR uncacheable cycles 2393system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2816431000 # number of WriteReq MSHR uncacheable cycles 2394system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2816431000 # number of WriteReq MSHR uncacheable cycles 2395system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 5889683500 # number of overall MSHR uncacheable cycles 2396system.cpu1.dcache.overall_mshr_uncacheable_latency::total 5889683500 # number of overall MSHR uncacheable cycles 2397system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036246 # mshr miss rate for ReadReq accesses 2398system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036246 # mshr miss rate for ReadReq accesses 2399system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018586 # mshr miss rate for WriteReq accesses 2400system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018586 # mshr miss rate for WriteReq accesses 2401system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.786804 # mshr miss rate for SoftPFReq accesses 2402system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.786804 # mshr miss rate for SoftPFReq accesses 2403system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.753775 # mshr miss rate for WriteLineReq accesses 2404system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.753775 # mshr miss rate for WriteLineReq accesses 2405system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.057697 # mshr miss rate for LoadLockedReq accesses 2406system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.057697 # mshr miss rate for LoadLockedReq accesses 2407system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100741 # mshr miss rate for StoreCondReq accesses 2408system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100741 # mshr miss rate for StoreCondReq accesses 2409system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027997 # mshr miss rate for demand accesses 2410system.cpu1.dcache.demand_mshr_miss_rate::total 0.027997 # mshr miss rate for demand accesses 2411system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032097 # mshr miss rate for overall accesses 2412system.cpu1.dcache.overall_mshr_miss_rate::total 0.032097 # mshr miss rate for overall accesses 2413system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15185.398987 # average ReadReq mshr miss latency 2414system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15185.398987 # average ReadReq mshr miss latency 2415system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23892.534445 # average WriteReq mshr miss latency 2416system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23892.534445 # average WriteReq mshr miss latency 2417system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24934.419818 # average SoftPFReq mshr miss latency 2418system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24934.419818 # average SoftPFReq mshr miss latency 2419system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 35689.369680 # average WriteLineReq mshr miss latency 2420system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 35689.369680 # average WriteLineReq mshr miss latency 2421system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15219.860081 # average LoadLockedReq mshr miss latency 2422system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15219.860081 # average LoadLockedReq mshr miss latency 2423system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26720.366765 # average StoreCondReq mshr miss latency 2424system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26720.366765 # average StoreCondReq mshr miss latency 2425system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2426system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 2427system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17885.384480 # average overall mshr miss latency 2428system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17885.384480 # average overall mshr miss latency 2429system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18819.005959 # average overall mshr miss latency 2430system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18819.005959 # average overall mshr miss latency 2431system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165799.120630 # average ReadReq mshr uncacheable latency 2432system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 165799.120630 # average ReadReq mshr uncacheable latency 2433system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 170300.580481 # average WriteReq mshr uncacheable latency 2434system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 170300.580481 # average WriteReq mshr uncacheable latency 2435system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 167921.637110 # average overall mshr uncacheable latency 2436system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 167921.637110 # average overall mshr uncacheable latency 2437system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2438system.cpu1.icache.tags.replacements 5433139 # number of replacements 2439system.cpu1.icache.tags.tagsinuse 501.652394 # Cycle average of tags in use 2440system.cpu1.icache.tags.total_refs 192499091 # Total number of references to valid blocks. 2441system.cpu1.icache.tags.sampled_refs 5433651 # Sample count of references to valid blocks. 2442system.cpu1.icache.tags.avg_refs 35.427209 # Average number of references to valid blocks. 2443system.cpu1.icache.tags.warmup_cycle 8522355919000 # Cycle when the warmup percentage was hit. 2444system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.652394 # Average occupied blocks per requestor 2445system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979790 # Average percentage of cache occupancy 2446system.cpu1.icache.tags.occ_percent::total 0.979790 # Average percentage of cache occupancy 2447system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2448system.cpu1.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id 2449system.cpu1.icache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id 2450system.cpu1.icache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id 2451system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2452system.cpu1.icache.tags.tag_accesses 401935440 # Number of tag accesses 2453system.cpu1.icache.tags.data_accesses 401935440 # Number of data accesses 2454system.cpu1.icache.ReadReq_hits::cpu1.inst 192499091 # number of ReadReq hits 2455system.cpu1.icache.ReadReq_hits::total 192499091 # number of ReadReq hits 2456system.cpu1.icache.demand_hits::cpu1.inst 192499091 # number of demand (read+write) hits 2457system.cpu1.icache.demand_hits::total 192499091 # number of demand (read+write) hits 2458system.cpu1.icache.overall_hits::cpu1.inst 192499091 # number of overall hits 2459system.cpu1.icache.overall_hits::total 192499091 # number of overall hits 2460system.cpu1.icache.ReadReq_misses::cpu1.inst 5751797 # number of ReadReq misses 2461system.cpu1.icache.ReadReq_misses::total 5751797 # number of ReadReq misses 2462system.cpu1.icache.demand_misses::cpu1.inst 5751797 # number of demand (read+write) misses 2463system.cpu1.icache.demand_misses::total 5751797 # number of demand (read+write) misses 2464system.cpu1.icache.overall_misses::cpu1.inst 5751797 # number of overall misses 2465system.cpu1.icache.overall_misses::total 5751797 # number of overall misses 2466system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 64772051533 # number of ReadReq miss cycles 2467system.cpu1.icache.ReadReq_miss_latency::total 64772051533 # number of ReadReq miss cycles 2468system.cpu1.icache.demand_miss_latency::cpu1.inst 64772051533 # number of demand (read+write) miss cycles 2469system.cpu1.icache.demand_miss_latency::total 64772051533 # number of demand (read+write) miss cycles 2470system.cpu1.icache.overall_miss_latency::cpu1.inst 64772051533 # number of overall miss cycles 2471system.cpu1.icache.overall_miss_latency::total 64772051533 # number of overall miss cycles 2472system.cpu1.icache.ReadReq_accesses::cpu1.inst 198250888 # number of ReadReq accesses(hits+misses) 2473system.cpu1.icache.ReadReq_accesses::total 198250888 # number of ReadReq accesses(hits+misses) 2474system.cpu1.icache.demand_accesses::cpu1.inst 198250888 # number of demand (read+write) accesses 2475system.cpu1.icache.demand_accesses::total 198250888 # number of demand (read+write) accesses 2476system.cpu1.icache.overall_accesses::cpu1.inst 198250888 # number of overall (read+write) accesses 2477system.cpu1.icache.overall_accesses::total 198250888 # number of overall (read+write) accesses 2478system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029013 # miss rate for ReadReq accesses 2479system.cpu1.icache.ReadReq_miss_rate::total 0.029013 # miss rate for ReadReq accesses 2480system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029013 # miss rate for demand accesses 2481system.cpu1.icache.demand_miss_rate::total 0.029013 # miss rate for demand accesses 2482system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029013 # miss rate for overall accesses 2483system.cpu1.icache.overall_miss_rate::total 0.029013 # miss rate for overall accesses 2484system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11261.185249 # average ReadReq miss latency 2485system.cpu1.icache.ReadReq_avg_miss_latency::total 11261.185249 # average ReadReq miss latency 2486system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11261.185249 # average overall miss latency 2487system.cpu1.icache.demand_avg_miss_latency::total 11261.185249 # average overall miss latency 2488system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11261.185249 # average overall miss latency 2489system.cpu1.icache.overall_avg_miss_latency::total 11261.185249 # average overall miss latency 2490system.cpu1.icache.blocked_cycles::no_mshrs 9932539 # number of cycles access was blocked 2491system.cpu1.icache.blocked_cycles::no_targets 584 # number of cycles access was blocked 2492system.cpu1.icache.blocked::no_mshrs 679779 # number of cycles access was blocked 2493system.cpu1.icache.blocked::no_targets 7 # number of cycles access was blocked 2494system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.611424 # average number of cycles each access was blocked 2495system.cpu1.icache.avg_blocked_cycles::no_targets 83.428571 # average number of cycles each access was blocked 2496system.cpu1.icache.fast_writes 0 # number of fast writes performed 2497system.cpu1.icache.cache_copies 0 # number of cache copies performed 2498system.cpu1.icache.writebacks::writebacks 5433139 # number of writebacks 2499system.cpu1.icache.writebacks::total 5433139 # number of writebacks 2500system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 318133 # number of ReadReq MSHR hits 2501system.cpu1.icache.ReadReq_mshr_hits::total 318133 # number of ReadReq MSHR hits 2502system.cpu1.icache.demand_mshr_hits::cpu1.inst 318133 # number of demand (read+write) MSHR hits 2503system.cpu1.icache.demand_mshr_hits::total 318133 # number of demand (read+write) MSHR hits 2504system.cpu1.icache.overall_mshr_hits::cpu1.inst 318133 # number of overall MSHR hits 2505system.cpu1.icache.overall_mshr_hits::total 318133 # number of overall MSHR hits 2506system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5433664 # number of ReadReq MSHR misses 2507system.cpu1.icache.ReadReq_mshr_misses::total 5433664 # number of ReadReq MSHR misses 2508system.cpu1.icache.demand_mshr_misses::cpu1.inst 5433664 # number of demand (read+write) MSHR misses 2509system.cpu1.icache.demand_mshr_misses::total 5433664 # number of demand (read+write) MSHR misses 2510system.cpu1.icache.overall_mshr_misses::cpu1.inst 5433664 # number of overall MSHR misses 2511system.cpu1.icache.overall_mshr_misses::total 5433664 # number of overall MSHR misses 2512system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 2513system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable 2514system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 2515system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses 2516system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 58335043744 # number of ReadReq MSHR miss cycles 2517system.cpu1.icache.ReadReq_mshr_miss_latency::total 58335043744 # number of ReadReq MSHR miss cycles 2518system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 58335043744 # number of demand (read+write) MSHR miss cycles 2519system.cpu1.icache.demand_mshr_miss_latency::total 58335043744 # number of demand (read+write) MSHR miss cycles 2520system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 58335043744 # number of overall MSHR miss cycles 2521system.cpu1.icache.overall_mshr_miss_latency::total 58335043744 # number of overall MSHR miss cycles 2522system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9645998 # number of ReadReq MSHR uncacheable cycles 2523system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9645998 # number of ReadReq MSHR uncacheable cycles 2524system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9645998 # number of overall MSHR uncacheable cycles 2525system.cpu1.icache.overall_mshr_uncacheable_latency::total 9645998 # number of overall MSHR uncacheable cycles 2526system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027408 # mshr miss rate for ReadReq accesses 2527system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027408 # mshr miss rate for ReadReq accesses 2528system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027408 # mshr miss rate for demand accesses 2529system.cpu1.icache.demand_mshr_miss_rate::total 0.027408 # mshr miss rate for demand accesses 2530system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027408 # mshr miss rate for overall accesses 2531system.cpu1.icache.overall_mshr_miss_rate::total 0.027408 # mshr miss rate for overall accesses 2532system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10735.857746 # average ReadReq mshr miss latency 2533system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10735.857746 # average ReadReq mshr miss latency 2534system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10735.857746 # average overall mshr miss latency 2535system.cpu1.icache.demand_avg_mshr_miss_latency::total 10735.857746 # average overall mshr miss latency 2536system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10735.857746 # average overall mshr miss latency 2537system.cpu1.icache.overall_avg_mshr_miss_latency::total 10735.857746 # average overall mshr miss latency 2538system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 143970.119403 # average ReadReq mshr uncacheable latency 2539system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 143970.119403 # average ReadReq mshr uncacheable latency 2540system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 143970.119403 # average overall mshr uncacheable latency 2541system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 143970.119403 # average overall mshr uncacheable latency 2542system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2543system.cpu1.l2cache.prefetcher.num_hwpf_issued 7104582 # number of hwpf issued 2544system.cpu1.l2cache.prefetcher.pfIdentified 7110323 # number of prefetch candidates identified 2545system.cpu1.l2cache.prefetcher.pfBufferHit 5229 # number of redundant prefetches already in prefetch queue 2546system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2547system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 2548system.cpu1.l2cache.prefetcher.pfSpanPage 868037 # number of prefetches not generated due to page crossing 2549system.cpu1.l2cache.tags.replacements 2129197 # number of replacements 2550system.cpu1.l2cache.tags.tagsinuse 13328.245122 # Cycle average of tags in use 2551system.cpu1.l2cache.tags.total_refs 15739911 # Total number of references to valid blocks. 2552system.cpu1.l2cache.tags.sampled_refs 2145331 # Sample count of references to valid blocks. 2553system.cpu1.l2cache.tags.avg_refs 7.336822 # Average number of references to valid blocks. 2554system.cpu1.l2cache.tags.warmup_cycle 9958132586000 # Cycle when the warmup percentage was hit. 2555system.cpu1.l2cache.tags.occ_blocks::writebacks 12434.905270 # Average occupied blocks per requestor 2556system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 47.585138 # Average occupied blocks per requestor 2557system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 48.632741 # Average occupied blocks per requestor 2558system.cpu1.l2cache.tags.occ_blocks::cpu1.data 0.000002 # Average occupied blocks per requestor 2559system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 797.121970 # Average occupied blocks per requestor 2560system.cpu1.l2cache.tags.occ_percent::writebacks 0.758966 # Average percentage of cache occupancy 2561system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002904 # Average percentage of cache occupancy 2562system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.002968 # Average percentage of cache occupancy 2563system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.000000 # Average percentage of cache occupancy 2564system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.048652 # Average percentage of cache occupancy 2565system.cpu1.l2cache.tags.occ_percent::total 0.813492 # Average percentage of cache occupancy 2566system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1216 # Occupied blocks per task id 2567system.cpu1.l2cache.tags.occ_task_id_blocks::1023 75 # Occupied blocks per task id 2568system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14843 # Occupied blocks per task id 2569system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id 2570system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 26 # Occupied blocks per task id 2571system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 201 # Occupied blocks per task id 2572system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 613 # Occupied blocks per task id 2573system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 375 # Occupied blocks per task id 2574system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id 2575system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 43 # Occupied blocks per task id 2576system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id 2577system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id 2578system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id 2579system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1347 # Occupied blocks per task id 2580system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 6023 # Occupied blocks per task id 2581system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4378 # Occupied blocks per task id 2582system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2999 # Occupied blocks per task id 2583system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.074219 # Percentage of cache occupancy per task id 2584system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004578 # Percentage of cache occupancy per task id 2585system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.905945 # Percentage of cache occupancy per task id 2586system.cpu1.l2cache.tags.tag_accesses 365454297 # Number of tag accesses 2587system.cpu1.l2cache.tags.data_accesses 365454297 # Number of data accesses 2588system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 563276 # number of ReadReq hits 2589system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 186249 # number of ReadReq hits 2590system.cpu1.l2cache.ReadReq_hits::total 749525 # number of ReadReq hits 2591system.cpu1.l2cache.WritebackDirty_hits::writebacks 3287486 # number of WritebackDirty hits 2592system.cpu1.l2cache.WritebackDirty_hits::total 3287486 # number of WritebackDirty hits 2593system.cpu1.l2cache.WritebackClean_hits::writebacks 7325630 # number of WritebackClean hits 2594system.cpu1.l2cache.WritebackClean_hits::total 7325630 # number of WritebackClean hits 2595system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 588 # number of UpgradeReq hits 2596system.cpu1.l2cache.UpgradeReq_hits::total 588 # number of UpgradeReq hits 2597system.cpu1.l2cache.ReadExReq_hits::cpu1.data 828832 # number of ReadExReq hits 2598system.cpu1.l2cache.ReadExReq_hits::total 828832 # number of ReadExReq hits 2599system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4887396 # number of ReadCleanReq hits 2600system.cpu1.l2cache.ReadCleanReq_hits::total 4887396 # number of ReadCleanReq hits 2601system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2758073 # number of ReadSharedReq hits 2602system.cpu1.l2cache.ReadSharedReq_hits::total 2758073 # number of ReadSharedReq hits 2603system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 186873 # number of InvalidateReq hits 2604system.cpu1.l2cache.InvalidateReq_hits::total 186873 # number of InvalidateReq hits 2605system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 563276 # number of demand (read+write) hits 2606system.cpu1.l2cache.demand_hits::cpu1.itb.walker 186249 # number of demand (read+write) hits 2607system.cpu1.l2cache.demand_hits::cpu1.inst 4887396 # number of demand (read+write) hits 2608system.cpu1.l2cache.demand_hits::cpu1.data 3586905 # number of demand (read+write) hits 2609system.cpu1.l2cache.demand_hits::total 9223826 # number of demand (read+write) hits 2610system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 563276 # number of overall hits 2611system.cpu1.l2cache.overall_hits::cpu1.itb.walker 186249 # number of overall hits 2612system.cpu1.l2cache.overall_hits::cpu1.inst 4887396 # number of overall hits 2613system.cpu1.l2cache.overall_hits::cpu1.data 3586905 # number of overall hits 2614system.cpu1.l2cache.overall_hits::total 9223826 # number of overall hits 2615system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11569 # number of ReadReq misses 2616system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8316 # number of ReadReq misses 2617system.cpu1.l2cache.ReadReq_misses::total 19885 # number of ReadReq misses 2618system.cpu1.l2cache.WritebackDirty_misses::writebacks 5 # number of WritebackDirty misses 2619system.cpu1.l2cache.WritebackDirty_misses::total 5 # number of WritebackDirty misses 2620system.cpu1.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses 2621system.cpu1.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses 2622system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 227542 # number of UpgradeReq misses 2623system.cpu1.l2cache.UpgradeReq_misses::total 227542 # number of UpgradeReq misses 2624system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 198269 # number of SCUpgradeReq misses 2625system.cpu1.l2cache.SCUpgradeReq_misses::total 198269 # number of SCUpgradeReq misses 2626system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses 2627system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses 2628system.cpu1.l2cache.ReadExReq_misses::cpu1.data 283901 # number of ReadExReq misses 2629system.cpu1.l2cache.ReadExReq_misses::total 283901 # number of ReadExReq misses 2630system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 546263 # number of ReadCleanReq misses 2631system.cpu1.l2cache.ReadCleanReq_misses::total 546263 # number of ReadCleanReq misses 2632system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 973715 # number of ReadSharedReq misses 2633system.cpu1.l2cache.ReadSharedReq_misses::total 973715 # number of ReadSharedReq misses 2634system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 242230 # number of InvalidateReq misses 2635system.cpu1.l2cache.InvalidateReq_misses::total 242230 # number of InvalidateReq misses 2636system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11569 # number of demand (read+write) misses 2637system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8316 # number of demand (read+write) misses 2638system.cpu1.l2cache.demand_misses::cpu1.inst 546263 # number of demand (read+write) misses 2639system.cpu1.l2cache.demand_misses::cpu1.data 1257616 # number of demand (read+write) misses 2640system.cpu1.l2cache.demand_misses::total 1823764 # number of demand (read+write) misses 2641system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11569 # number of overall misses 2642system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8316 # number of overall misses 2643system.cpu1.l2cache.overall_misses::cpu1.inst 546263 # number of overall misses 2644system.cpu1.l2cache.overall_misses::cpu1.data 1257616 # number of overall misses 2645system.cpu1.l2cache.overall_misses::total 1823764 # number of overall misses 2646system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 548560000 # number of ReadReq miss cycles 2647system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 408520000 # number of ReadReq miss cycles 2648system.cpu1.l2cache.ReadReq_miss_latency::total 957080000 # number of ReadReq miss cycles 2649system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3391225500 # number of UpgradeReq miss cycles 2650system.cpu1.l2cache.UpgradeReq_miss_latency::total 3391225500 # number of UpgradeReq miss cycles 2651system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1846888500 # number of SCUpgradeReq miss cycles 2652system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1846888500 # number of SCUpgradeReq miss cycles 2653system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 4469999 # number of SCUpgradeFailReq miss cycles 2654system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 4469999 # number of SCUpgradeFailReq miss cycles 2655system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 15324598999 # number of ReadExReq miss cycles 2656system.cpu1.l2cache.ReadExReq_miss_latency::total 15324598999 # number of ReadExReq miss cycles 2657system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 20599116500 # number of ReadCleanReq miss cycles 2658system.cpu1.l2cache.ReadCleanReq_miss_latency::total 20599116500 # number of ReadCleanReq miss cycles 2659system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 39102280478 # number of ReadSharedReq miss cycles 2660system.cpu1.l2cache.ReadSharedReq_miss_latency::total 39102280478 # number of ReadSharedReq miss cycles 2661system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 513890000 # number of InvalidateReq miss cycles 2662system.cpu1.l2cache.InvalidateReq_miss_latency::total 513890000 # number of InvalidateReq miss cycles 2663system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 548560000 # number of demand (read+write) miss cycles 2664system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 408520000 # number of demand (read+write) miss cycles 2665system.cpu1.l2cache.demand_miss_latency::cpu1.inst 20599116500 # number of demand (read+write) miss cycles 2666system.cpu1.l2cache.demand_miss_latency::cpu1.data 54426879477 # number of demand (read+write) miss cycles 2667system.cpu1.l2cache.demand_miss_latency::total 75983075977 # number of demand (read+write) miss cycles 2668system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 548560000 # number of overall miss cycles 2669system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 408520000 # number of overall miss cycles 2670system.cpu1.l2cache.overall_miss_latency::cpu1.inst 20599116500 # number of overall miss cycles 2671system.cpu1.l2cache.overall_miss_latency::cpu1.data 54426879477 # number of overall miss cycles 2672system.cpu1.l2cache.overall_miss_latency::total 75983075977 # number of overall miss cycles 2673system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 574845 # number of ReadReq accesses(hits+misses) 2674system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 194565 # number of ReadReq accesses(hits+misses) 2675system.cpu1.l2cache.ReadReq_accesses::total 769410 # number of ReadReq accesses(hits+misses) 2676system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3287491 # number of WritebackDirty accesses(hits+misses) 2677system.cpu1.l2cache.WritebackDirty_accesses::total 3287491 # number of WritebackDirty accesses(hits+misses) 2678system.cpu1.l2cache.WritebackClean_accesses::writebacks 7325631 # number of WritebackClean accesses(hits+misses) 2679system.cpu1.l2cache.WritebackClean_accesses::total 7325631 # number of WritebackClean accesses(hits+misses) 2680system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 228130 # number of UpgradeReq accesses(hits+misses) 2681system.cpu1.l2cache.UpgradeReq_accesses::total 228130 # number of UpgradeReq accesses(hits+misses) 2682system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 198269 # number of SCUpgradeReq accesses(hits+misses) 2683system.cpu1.l2cache.SCUpgradeReq_accesses::total 198269 # number of SCUpgradeReq accesses(hits+misses) 2684system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses) 2685system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) 2686system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1112733 # number of ReadExReq accesses(hits+misses) 2687system.cpu1.l2cache.ReadExReq_accesses::total 1112733 # number of ReadExReq accesses(hits+misses) 2688system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5433659 # number of ReadCleanReq accesses(hits+misses) 2689system.cpu1.l2cache.ReadCleanReq_accesses::total 5433659 # number of ReadCleanReq accesses(hits+misses) 2690system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3731788 # number of ReadSharedReq accesses(hits+misses) 2691system.cpu1.l2cache.ReadSharedReq_accesses::total 3731788 # number of ReadSharedReq accesses(hits+misses) 2692system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 429103 # number of InvalidateReq accesses(hits+misses) 2693system.cpu1.l2cache.InvalidateReq_accesses::total 429103 # number of InvalidateReq accesses(hits+misses) 2694system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 574845 # number of demand (read+write) accesses 2695system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 194565 # number of demand (read+write) accesses 2696system.cpu1.l2cache.demand_accesses::cpu1.inst 5433659 # number of demand (read+write) accesses 2697system.cpu1.l2cache.demand_accesses::cpu1.data 4844521 # number of demand (read+write) accesses 2698system.cpu1.l2cache.demand_accesses::total 11047590 # number of demand (read+write) accesses 2699system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 574845 # number of overall (read+write) accesses 2700system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 194565 # number of overall (read+write) accesses 2701system.cpu1.l2cache.overall_accesses::cpu1.inst 5433659 # number of overall (read+write) accesses 2702system.cpu1.l2cache.overall_accesses::cpu1.data 4844521 # number of overall (read+write) accesses 2703system.cpu1.l2cache.overall_accesses::total 11047590 # number of overall (read+write) accesses 2704system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020125 # miss rate for ReadReq accesses 2705system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.042742 # miss rate for ReadReq accesses 2706system.cpu1.l2cache.ReadReq_miss_rate::total 0.025844 # miss rate for ReadReq accesses 2707system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000002 # miss rate for WritebackDirty accesses 2708system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000002 # miss rate for WritebackDirty accesses 2709system.cpu1.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses 2710system.cpu1.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses 2711system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.997423 # miss rate for UpgradeReq accesses 2712system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.997423 # miss rate for UpgradeReq accesses 2713system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2714system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2715system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2716system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2717system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.255138 # miss rate for ReadExReq accesses 2718system.cpu1.l2cache.ReadExReq_miss_rate::total 0.255138 # miss rate for ReadExReq accesses 2719system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.100533 # miss rate for ReadCleanReq accesses 2720system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.100533 # miss rate for ReadCleanReq accesses 2721system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.260925 # miss rate for ReadSharedReq accesses 2722system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.260925 # miss rate for ReadSharedReq accesses 2723system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.564503 # miss rate for InvalidateReq accesses 2724system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.564503 # miss rate for InvalidateReq accesses 2725system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020125 # miss rate for demand accesses 2726system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.042742 # miss rate for demand accesses 2727system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.100533 # miss rate for demand accesses 2728system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.259596 # miss rate for demand accesses 2729system.cpu1.l2cache.demand_miss_rate::total 0.165083 # miss rate for demand accesses 2730system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020125 # miss rate for overall accesses 2731system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.042742 # miss rate for overall accesses 2732system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.100533 # miss rate for overall accesses 2733system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.259596 # miss rate for overall accesses 2734system.cpu1.l2cache.overall_miss_rate::total 0.165083 # miss rate for overall accesses 2735system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 47416.371337 # average ReadReq miss latency 2736system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 49124.579125 # average ReadReq miss latency 2737system.cpu1.l2cache.ReadReq_avg_miss_latency::total 48130.751823 # average ReadReq miss latency 2738system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 14903.734256 # average UpgradeReq miss latency 2739system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 14903.734256 # average UpgradeReq miss latency 2740system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9315.064382 # average SCUpgradeReq miss latency 2741system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9315.064382 # average SCUpgradeReq miss latency 2742system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 893999.800000 # average SCUpgradeFailReq miss latency 2743system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 893999.800000 # average SCUpgradeFailReq miss latency 2744system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53978.672139 # average ReadExReq miss latency 2745system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53978.672139 # average ReadExReq miss latency 2746system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37709.155663 # average ReadCleanReq miss latency 2747system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37709.155663 # average ReadCleanReq miss latency 2748system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 40157.829014 # average ReadSharedReq miss latency 2749system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 40157.829014 # average ReadSharedReq miss latency 2750system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 2121.496099 # average InvalidateReq miss latency 2751system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 2121.496099 # average InvalidateReq miss latency 2752system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 47416.371337 # average overall miss latency 2753system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 49124.579125 # average overall miss latency 2754system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37709.155663 # average overall miss latency 2755system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 43277.820477 # average overall miss latency 2756system.cpu1.l2cache.demand_avg_miss_latency::total 41662.778724 # average overall miss latency 2757system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 47416.371337 # average overall miss latency 2758system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 49124.579125 # average overall miss latency 2759system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37709.155663 # average overall miss latency 2760system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 43277.820477 # average overall miss latency 2761system.cpu1.l2cache.overall_avg_miss_latency::total 41662.778724 # average overall miss latency 2762system.cpu1.l2cache.blocked_cycles::no_mshrs 699 # number of cycles access was blocked 2763system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2764system.cpu1.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked 2765system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2766system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 87.375000 # average number of cycles each access was blocked 2767system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2768system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2769system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2770system.cpu1.l2cache.writebacks::writebacks 1118169 # number of writebacks 2771system.cpu1.l2cache.writebacks::total 1118169 # number of writebacks 2772system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 4 # number of ReadReq MSHR hits 2773system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 196 # number of ReadReq MSHR hits 2774system.cpu1.l2cache.ReadReq_mshr_hits::total 200 # number of ReadReq MSHR hits 2775system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 38879 # number of ReadExReq MSHR hits 2776system.cpu1.l2cache.ReadExReq_mshr_hits::total 38879 # number of ReadExReq MSHR hits 2777system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 1 # number of ReadCleanReq MSHR hits 2778system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 2779system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 4580 # number of ReadSharedReq MSHR hits 2780system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 4580 # number of ReadSharedReq MSHR hits 2781system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 9 # number of InvalidateReq MSHR hits 2782system.cpu1.l2cache.InvalidateReq_mshr_hits::total 9 # number of InvalidateReq MSHR hits 2783system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 4 # number of demand (read+write) MSHR hits 2784system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 196 # number of demand (read+write) MSHR hits 2785system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits 2786system.cpu1.l2cache.demand_mshr_hits::cpu1.data 43459 # number of demand (read+write) MSHR hits 2787system.cpu1.l2cache.demand_mshr_hits::total 43660 # number of demand (read+write) MSHR hits 2788system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 4 # number of overall MSHR hits 2789system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 196 # number of overall MSHR hits 2790system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits 2791system.cpu1.l2cache.overall_mshr_hits::cpu1.data 43459 # number of overall MSHR hits 2792system.cpu1.l2cache.overall_mshr_hits::total 43660 # number of overall MSHR hits 2793system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11565 # number of ReadReq MSHR misses 2794system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8120 # number of ReadReq MSHR misses 2795system.cpu1.l2cache.ReadReq_mshr_misses::total 19685 # number of ReadReq MSHR misses 2796system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 5 # number of WritebackDirty MSHR misses 2797system.cpu1.l2cache.WritebackDirty_mshr_misses::total 5 # number of WritebackDirty MSHR misses 2798system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses 2799system.cpu1.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses 2800system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 735217 # number of HardPFReq MSHR misses 2801system.cpu1.l2cache.HardPFReq_mshr_misses::total 735217 # number of HardPFReq MSHR misses 2802system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 227542 # number of UpgradeReq MSHR misses 2803system.cpu1.l2cache.UpgradeReq_mshr_misses::total 227542 # number of UpgradeReq MSHR misses 2804system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 198269 # number of SCUpgradeReq MSHR misses 2805system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 198269 # number of SCUpgradeReq MSHR misses 2806system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 5 # number of SCUpgradeFailReq MSHR misses 2807system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses 2808system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 245022 # number of ReadExReq MSHR misses 2809system.cpu1.l2cache.ReadExReq_mshr_misses::total 245022 # number of ReadExReq MSHR misses 2810system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 546262 # number of ReadCleanReq MSHR misses 2811system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 546262 # number of ReadCleanReq MSHR misses 2812system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 969135 # number of ReadSharedReq MSHR misses 2813system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 969135 # number of ReadSharedReq MSHR misses 2814system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 242221 # number of InvalidateReq MSHR misses 2815system.cpu1.l2cache.InvalidateReq_mshr_misses::total 242221 # number of InvalidateReq MSHR misses 2816system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11565 # number of demand (read+write) MSHR misses 2817system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8120 # number of demand (read+write) MSHR misses 2818system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 546262 # number of demand (read+write) MSHR misses 2819system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1214157 # number of demand (read+write) MSHR misses 2820system.cpu1.l2cache.demand_mshr_misses::total 1780104 # number of demand (read+write) MSHR misses 2821system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11565 # number of overall MSHR misses 2822system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8120 # number of overall MSHR misses 2823system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 546262 # number of overall MSHR misses 2824system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1214157 # number of overall MSHR misses 2825system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 735217 # number of overall MSHR misses 2826system.cpu1.l2cache.overall_mshr_misses::total 2515321 # number of overall MSHR misses 2827system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 2828system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 18536 # number of ReadReq MSHR uncacheable 2829system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 18603 # number of ReadReq MSHR uncacheable 2830system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 16538 # number of WriteReq MSHR uncacheable 2831system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 16538 # number of WriteReq MSHR uncacheable 2832system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 2833system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 35074 # number of overall MSHR uncacheable misses 2834system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 35141 # number of overall MSHR uncacheable misses 2835system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 479105500 # number of ReadReq MSHR miss cycles 2836system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 347671000 # number of ReadReq MSHR miss cycles 2837system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 826776500 # number of ReadReq MSHR miss cycles 2838system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 45381598688 # number of HardPFReq MSHR miss cycles 2839system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 45381598688 # number of HardPFReq MSHR miss cycles 2840system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 7175483993 # number of UpgradeReq MSHR miss cycles 2841system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 7175483993 # number of UpgradeReq MSHR miss cycles 2842system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3808164996 # number of SCUpgradeReq MSHR miss cycles 2843system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3808164996 # number of SCUpgradeReq MSHR miss cycles 2844system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 4145999 # number of SCUpgradeFailReq MSHR miss cycles 2845system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4145999 # number of SCUpgradeFailReq MSHR miss cycles 2846system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 11475367999 # number of ReadExReq MSHR miss cycles 2847system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 11475367999 # number of ReadExReq MSHR miss cycles 2848system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 17321524000 # number of ReadCleanReq MSHR miss cycles 2849system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 17321524000 # number of ReadCleanReq MSHR miss cycles 2850system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 33026830978 # number of ReadSharedReq MSHR miss cycles 2851system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 33026830978 # number of ReadSharedReq MSHR miss cycles 2852system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 11580370998 # number of InvalidateReq MSHR miss cycles 2853system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 11580370998 # number of InvalidateReq MSHR miss cycles 2854system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 479105500 # number of demand (read+write) MSHR miss cycles 2855system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 347671000 # number of demand (read+write) MSHR miss cycles 2856system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 17321524000 # number of demand (read+write) MSHR miss cycles 2857system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 44502198977 # number of demand (read+write) MSHR miss cycles 2858system.cpu1.l2cache.demand_mshr_miss_latency::total 62650499477 # number of demand (read+write) MSHR miss cycles 2859system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 479105500 # number of overall MSHR miss cycles 2860system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 347671000 # number of overall MSHR miss cycles 2861system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 17321524000 # number of overall MSHR miss cycles 2862system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 44502198977 # number of overall MSHR miss cycles 2863system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 45381598688 # number of overall MSHR miss cycles 2864system.cpu1.l2cache.overall_mshr_miss_latency::total 108032098165 # number of overall MSHR miss cycles 2865system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9142500 # number of ReadReq MSHR uncacheable cycles 2866system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2924847500 # number of ReadReq MSHR uncacheable cycles 2867system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2933990000 # number of ReadReq MSHR uncacheable cycles 2868system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2692324500 # number of WriteReq MSHR uncacheable cycles 2869system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2692324500 # number of WriteReq MSHR uncacheable cycles 2870system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9142500 # number of overall MSHR uncacheable cycles 2871system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 5617172000 # number of overall MSHR uncacheable cycles 2872system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 5626314500 # number of overall MSHR uncacheable cycles 2873system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020118 # mshr miss rate for ReadReq accesses 2874system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.041734 # mshr miss rate for ReadReq accesses 2875system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.025585 # mshr miss rate for ReadReq accesses 2876system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for WritebackDirty accesses 2877system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000002 # mshr miss rate for WritebackDirty accesses 2878system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses 2879system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses 2880system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2881system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2882system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.997423 # mshr miss rate for UpgradeReq accesses 2883system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.997423 # mshr miss rate for UpgradeReq accesses 2884system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2885system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2886system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2887system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2888system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.220198 # mshr miss rate for ReadExReq accesses 2889system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.220198 # mshr miss rate for ReadExReq accesses 2890system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.100533 # mshr miss rate for ReadCleanReq accesses 2891system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.100533 # mshr miss rate for ReadCleanReq accesses 2892system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.259697 # mshr miss rate for ReadSharedReq accesses 2893system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.259697 # mshr miss rate for ReadSharedReq accesses 2894system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.564482 # mshr miss rate for InvalidateReq accesses 2895system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.564482 # mshr miss rate for InvalidateReq accesses 2896system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020118 # mshr miss rate for demand accesses 2897system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.041734 # mshr miss rate for demand accesses 2898system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.100533 # mshr miss rate for demand accesses 2899system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.250625 # mshr miss rate for demand accesses 2900system.cpu1.l2cache.demand_mshr_miss_rate::total 0.161131 # mshr miss rate for demand accesses 2901system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020118 # mshr miss rate for overall accesses 2902system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.041734 # mshr miss rate for overall accesses 2903system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.100533 # mshr miss rate for overall accesses 2904system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.250625 # mshr miss rate for overall accesses 2905system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2906system.cpu1.l2cache.overall_mshr_miss_rate::total 0.227681 # mshr miss rate for overall accesses 2907system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 41427.194120 # average ReadReq mshr miss latency 2908system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 42816.625616 # average ReadReq mshr miss latency 2909system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 42000.330201 # average ReadReq mshr miss latency 2910system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 61725.447981 # average HardPFReq mshr miss latency 2911system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 61725.447981 # average HardPFReq mshr miss latency 2912system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31534.767177 # average UpgradeReq mshr miss latency 2913system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31534.767177 # average UpgradeReq mshr miss latency 2914system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19207.062102 # average SCUpgradeReq mshr miss latency 2915system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19207.062102 # average SCUpgradeReq mshr miss latency 2916system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 829199.800000 # average SCUpgradeFailReq mshr miss latency 2917system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 829199.800000 # average SCUpgradeFailReq mshr miss latency 2918system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46834.031226 # average ReadExReq mshr miss latency 2919system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46834.031226 # average ReadExReq mshr miss latency 2920system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31709.187167 # average ReadCleanReq mshr miss latency 2921system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31709.187167 # average ReadCleanReq mshr miss latency 2922system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 34078.669100 # average ReadSharedReq mshr miss latency 2923system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 34078.669100 # average ReadSharedReq mshr miss latency 2924system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 47809.112331 # average InvalidateReq mshr miss latency 2925system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 47809.112331 # average InvalidateReq mshr miss latency 2926system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 41427.194120 # average overall mshr miss latency 2927system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 42816.625616 # average overall mshr miss latency 2928system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31709.187167 # average overall mshr miss latency 2929system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 36652.754938 # average overall mshr miss latency 2930system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35194.853490 # average overall mshr miss latency 2931system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 41427.194120 # average overall mshr miss latency 2932system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 42816.625616 # average overall mshr miss latency 2933system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31709.187167 # average overall mshr miss latency 2934system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 36652.754938 # average overall mshr miss latency 2935system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 61725.447981 # average overall mshr miss latency 2936system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42949.626773 # average overall mshr miss latency 2937system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 136455.223881 # average ReadReq mshr uncacheable latency 2938system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 157792.808589 # average ReadReq mshr uncacheable latency 2939system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 157715.959791 # average ReadReq mshr uncacheable latency 2940system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 162796.257105 # average WriteReq mshr uncacheable latency 2941system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162796.257105 # average WriteReq mshr uncacheable latency 2942system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 136455.223881 # average overall mshr uncacheable latency 2943system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 160152.021440 # average overall mshr uncacheable latency 2944system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 160106.841012 # average overall mshr uncacheable latency 2945system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2946system.cpu1.toL2Bus.snoop_filter.tot_requests 22091106 # Total number of requests made to the snoop filter. 2947system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11384004 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2948system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1413 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2949system.cpu1.toL2Bus.snoop_filter.tot_snoops 1936993 # Total number of snoops made to the snoop filter. 2950system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 1936645 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2951system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 348 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2952system.cpu1.toL2Bus.trans_dist::ReadReq 874786 # Transaction distribution 2953system.cpu1.toL2Bus.trans_dist::ReadResp 10136227 # Transaction distribution 2954system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution 2955system.cpu1.toL2Bus.trans_dist::WriteReq 16538 # Transaction distribution 2956system.cpu1.toL2Bus.trans_dist::WriteResp 16538 # Transaction distribution 2957system.cpu1.toL2Bus.trans_dist::WritebackDirty 4413805 # Transaction distribution 2958system.cpu1.toL2Bus.trans_dist::WritebackClean 7327056 # Transaction distribution 2959system.cpu1.toL2Bus.trans_dist::CleanEvict 2612396 # Transaction distribution 2960system.cpu1.toL2Bus.trans_dist::HardPFReq 936031 # Transaction distribution 2961system.cpu1.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution 2962system.cpu1.toL2Bus.trans_dist::UpgradeReq 441152 # Transaction distribution 2963system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 362021 # Transaction distribution 2964system.cpu1.toL2Bus.trans_dist::UpgradeResp 491027 # Transaction distribution 2965system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 69 # Transaction distribution 2966system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 118 # Transaction distribution 2967system.cpu1.toL2Bus.trans_dist::ReadExReq 1142611 # Transaction distribution 2968system.cpu1.toL2Bus.trans_dist::ReadExResp 1118724 # Transaction distribution 2969system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5433664 # Transaction distribution 2970system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4777910 # Transaction distribution 2971system.cpu1.toL2Bus.trans_dist::InvalidateReq 490221 # Transaction distribution 2972system.cpu1.toL2Bus.trans_dist::InvalidateResp 429103 # Transaction distribution 2973system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 16300596 # Packet count per connected master and slave (bytes) 2974system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16818339 # Packet count per connected master and slave (bytes) 2975system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 407716 # Packet count per connected master and slave (bytes) 2976system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1217877 # Packet count per connected master and slave (bytes) 2977system.cpu1.toL2Bus.pkt_count::total 34744528 # Packet count per connected master and slave (bytes) 2978system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 695476144 # Cumulative packet size per connected master and slave (bytes) 2979system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 648316997 # Cumulative packet size per connected master and slave (bytes) 2980system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1556520 # Cumulative packet size per connected master and slave (bytes) 2981system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4598760 # Cumulative packet size per connected master and slave (bytes) 2982system.cpu1.toL2Bus.pkt_size::total 1349948421 # Cumulative packet size per connected master and slave (bytes) 2983system.cpu1.toL2Bus.snoops 6442202 # Total snoops (count) 2984system.cpu1.toL2Bus.snoop_fanout::samples 18213717 # Request fanout histogram 2985system.cpu1.toL2Bus.snoop_fanout::mean 0.125270 # Request fanout histogram 2986system.cpu1.toL2Bus.snoop_fanout::stdev 0.331083 # Request fanout histogram 2987system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2988system.cpu1.toL2Bus.snoop_fanout::0 15932433 87.47% 87.47% # Request fanout histogram 2989system.cpu1.toL2Bus.snoop_fanout::1 2280936 12.52% 100.00% # Request fanout histogram 2990system.cpu1.toL2Bus.snoop_fanout::2 348 0.00% 100.00% # Request fanout histogram 2991system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2992system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2993system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2994system.cpu1.toL2Bus.snoop_fanout::total 18213717 # Request fanout histogram 2995system.cpu1.toL2Bus.reqLayer0.occupancy 21942621967 # Layer occupancy (ticks) 2996system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2997system.cpu1.toL2Bus.snoopLayer0.occupancy 185589939 # Layer occupancy (ticks) 2998system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2999system.cpu1.toL2Bus.respLayer0.occupancy 8156255052 # Layer occupancy (ticks) 3000system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3001system.cpu1.toL2Bus.respLayer1.occupancy 7729530656 # Layer occupancy (ticks) 3002system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3003system.cpu1.toL2Bus.respLayer2.occupancy 213583628 # Layer occupancy (ticks) 3004system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 3005system.cpu1.toL2Bus.respLayer3.occupancy 643750548 # Layer occupancy (ticks) 3006system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 3007system.iobus.trans_dist::ReadReq 40360 # Transaction distribution 3008system.iobus.trans_dist::ReadResp 40360 # Transaction distribution 3009system.iobus.trans_dist::WriteReq 136653 # Transaction distribution 3010system.iobus.trans_dist::WriteResp 136653 # Transaction distribution 3011system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47814 # Packet count per connected master and slave (bytes) 3012system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 3013system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 3014system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 3015system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 3016system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 3017system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 3018system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 3019system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 3020system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 3021system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 3022system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 3023system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 3024system.iobus.pkt_count_system.bridge.master::total 122696 # Packet count per connected master and slave (bytes) 3025system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231250 # Packet count per connected master and slave (bytes) 3026system.iobus.pkt_count_system.realview.ide.dma::total 231250 # Packet count per connected master and slave (bytes) 3027system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 3028system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 3029system.iobus.pkt_count::total 354026 # Packet count per connected master and slave (bytes) 3030system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47834 # Cumulative packet size per connected master and slave (bytes) 3031system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 3032system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 3033system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 3034system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 3035system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 3036system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3037system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3038system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3039system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 3040system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3041system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 3042system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 3043system.iobus.pkt_size_system.bridge.master::total 155826 # Cumulative packet size per connected master and slave (bytes) 3044system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339016 # Cumulative packet size per connected master and slave (bytes) 3045system.iobus.pkt_size_system.realview.ide.dma::total 7339016 # Cumulative packet size per connected master and slave (bytes) 3046system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 3047system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 3048system.iobus.pkt_size::total 7496928 # Cumulative packet size per connected master and slave (bytes) 3049system.iobus.reqLayer0.occupancy 37078503 # Layer occupancy (ticks) 3050system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 3051system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) 3052system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 3053system.iobus.reqLayer2.occupancy 334500 # Layer occupancy (ticks) 3054system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 3055system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks) 3056system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 3057system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) 3058system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 3059system.iobus.reqLayer10.occupancy 10500 # Layer occupancy (ticks) 3060system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 3061system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) 3062system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 3063system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) 3064system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 3065system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) 3066system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 3067system.iobus.reqLayer16.occupancy 13500 # Layer occupancy (ticks) 3068system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 3069system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) 3070system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 3071system.iobus.reqLayer23.occupancy 24630000 # Layer occupancy (ticks) 3072system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 3073system.iobus.reqLayer24.occupancy 36390000 # Layer occupancy (ticks) 3074system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 3075system.iobus.reqLayer25.occupancy 567310169 # Layer occupancy (ticks) 3076system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 3077system.iobus.respLayer0.occupancy 92774000 # Layer occupancy (ticks) 3078system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 3079system.iobus.respLayer3.occupancy 147946000 # Layer occupancy (ticks) 3080system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 3081system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 3082system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 3083system.iocache.tags.replacements 115606 # number of replacements 3084system.iocache.tags.tagsinuse 11.303294 # Cycle average of tags in use 3085system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 3086system.iocache.tags.sampled_refs 115622 # Sample count of references to valid blocks. 3087system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 3088system.iocache.tags.warmup_cycle 9121340835000 # Cycle when the warmup percentage was hit. 3089system.iocache.tags.occ_blocks::realview.ethernet 3.838171 # Average occupied blocks per requestor 3090system.iocache.tags.occ_blocks::realview.ide 7.465123 # Average occupied blocks per requestor 3091system.iocache.tags.occ_percent::realview.ethernet 0.239886 # Average percentage of cache occupancy 3092system.iocache.tags.occ_percent::realview.ide 0.466570 # Average percentage of cache occupancy 3093system.iocache.tags.occ_percent::total 0.706456 # Average percentage of cache occupancy 3094system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 3095system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 3096system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 3097system.iocache.tags.tag_accesses 1040982 # Number of tag accesses 3098system.iocache.tags.data_accesses 1040982 # Number of data accesses 3099system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 3100system.iocache.ReadReq_misses::realview.ide 8897 # number of ReadReq misses 3101system.iocache.ReadReq_misses::total 8934 # number of ReadReq misses 3102system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 3103system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 3104system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 3105system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 3106system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 3107system.iocache.demand_misses::realview.ide 8897 # number of demand (read+write) misses 3108system.iocache.demand_misses::total 8937 # number of demand (read+write) misses 3109system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 3110system.iocache.overall_misses::realview.ide 8897 # number of overall misses 3111system.iocache.overall_misses::total 8937 # number of overall misses 3112system.iocache.ReadReq_miss_latency::realview.ethernet 5248000 # number of ReadReq miss cycles 3113system.iocache.ReadReq_miss_latency::realview.ide 1663076066 # number of ReadReq miss cycles 3114system.iocache.ReadReq_miss_latency::total 1668324066 # number of ReadReq miss cycles 3115system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 3116system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 3117system.iocache.WriteLineReq_miss_latency::realview.ide 13545989103 # number of WriteLineReq miss cycles 3118system.iocache.WriteLineReq_miss_latency::total 13545989103 # number of WriteLineReq miss cycles 3119system.iocache.demand_miss_latency::realview.ethernet 5617000 # number of demand (read+write) miss cycles 3120system.iocache.demand_miss_latency::realview.ide 1663076066 # number of demand (read+write) miss cycles 3121system.iocache.demand_miss_latency::total 1668693066 # number of demand (read+write) miss cycles 3122system.iocache.overall_miss_latency::realview.ethernet 5617000 # number of overall miss cycles 3123system.iocache.overall_miss_latency::realview.ide 1663076066 # number of overall miss cycles 3124system.iocache.overall_miss_latency::total 1668693066 # number of overall miss cycles 3125system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 3126system.iocache.ReadReq_accesses::realview.ide 8897 # number of ReadReq accesses(hits+misses) 3127system.iocache.ReadReq_accesses::total 8934 # number of ReadReq accesses(hits+misses) 3128system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 3129system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 3130system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 3131system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 3132system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 3133system.iocache.demand_accesses::realview.ide 8897 # number of demand (read+write) accesses 3134system.iocache.demand_accesses::total 8937 # number of demand (read+write) accesses 3135system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 3136system.iocache.overall_accesses::realview.ide 8897 # number of overall (read+write) accesses 3137system.iocache.overall_accesses::total 8937 # number of overall (read+write) accesses 3138system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 3139system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 3140system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 3141system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 3142system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 3143system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 3144system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 3145system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 3146system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 3147system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 3148system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 3149system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 3150system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 3151system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141837.837838 # average ReadReq miss latency 3152system.iocache.ReadReq_avg_miss_latency::realview.ide 186925.487917 # average ReadReq miss latency 3153system.iocache.ReadReq_avg_miss_latency::total 186738.758227 # average ReadReq miss latency 3154system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 3155system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 3156system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126920.668456 # average WriteLineReq miss latency 3157system.iocache.WriteLineReq_avg_miss_latency::total 126920.668456 # average WriteLineReq miss latency 3158system.iocache.demand_avg_miss_latency::realview.ethernet 140425 # average overall miss latency 3159system.iocache.demand_avg_miss_latency::realview.ide 186925.487917 # average overall miss latency 3160system.iocache.demand_avg_miss_latency::total 186717.362202 # average overall miss latency 3161system.iocache.overall_avg_miss_latency::realview.ethernet 140425 # average overall miss latency 3162system.iocache.overall_avg_miss_latency::realview.ide 186925.487917 # average overall miss latency 3163system.iocache.overall_avg_miss_latency::total 186717.362202 # average overall miss latency 3164system.iocache.blocked_cycles::no_mshrs 33278 # number of cycles access was blocked 3165system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3166system.iocache.blocked::no_mshrs 3432 # number of cycles access was blocked 3167system.iocache.blocked::no_targets 0 # number of cycles access was blocked 3168system.iocache.avg_blocked_cycles::no_mshrs 9.696387 # average number of cycles each access was blocked 3169system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3170system.iocache.fast_writes 0 # number of fast writes performed 3171system.iocache.cache_copies 0 # number of cache copies performed 3172system.iocache.writebacks::writebacks 106694 # number of writebacks 3173system.iocache.writebacks::total 106694 # number of writebacks 3174system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 3175system.iocache.ReadReq_mshr_misses::realview.ide 8897 # number of ReadReq MSHR misses 3176system.iocache.ReadReq_mshr_misses::total 8934 # number of ReadReq MSHR misses 3177system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 3178system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 3179system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 3180system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 3181system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 3182system.iocache.demand_mshr_misses::realview.ide 8897 # number of demand (read+write) MSHR misses 3183system.iocache.demand_mshr_misses::total 8937 # number of demand (read+write) MSHR misses 3184system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 3185system.iocache.overall_mshr_misses::realview.ide 8897 # number of overall MSHR misses 3186system.iocache.overall_mshr_misses::total 8937 # number of overall MSHR misses 3187system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3398000 # number of ReadReq MSHR miss cycles 3188system.iocache.ReadReq_mshr_miss_latency::realview.ide 1218226066 # number of ReadReq MSHR miss cycles 3189system.iocache.ReadReq_mshr_miss_latency::total 1221624066 # number of ReadReq MSHR miss cycles 3190system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 3191system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 3192system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8203200483 # number of WriteLineReq MSHR miss cycles 3193system.iocache.WriteLineReq_mshr_miss_latency::total 8203200483 # number of WriteLineReq MSHR miss cycles 3194system.iocache.demand_mshr_miss_latency::realview.ethernet 3617000 # number of demand (read+write) MSHR miss cycles 3195system.iocache.demand_mshr_miss_latency::realview.ide 1218226066 # number of demand (read+write) MSHR miss cycles 3196system.iocache.demand_mshr_miss_latency::total 1221843066 # number of demand (read+write) MSHR miss cycles 3197system.iocache.overall_mshr_miss_latency::realview.ethernet 3617000 # number of overall MSHR miss cycles 3198system.iocache.overall_mshr_miss_latency::realview.ide 1218226066 # number of overall MSHR miss cycles 3199system.iocache.overall_mshr_miss_latency::total 1221843066 # number of overall MSHR miss cycles 3200system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 3201system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 3202system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 3203system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 3204system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 3205system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 3206system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 3207system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 3208system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 3209system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 3210system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 3211system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 3212system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 3213system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 91837.837838 # average ReadReq mshr miss latency 3214system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136925.487917 # average ReadReq mshr miss latency 3215system.iocache.ReadReq_avg_mshr_miss_latency::total 136738.758227 # average ReadReq mshr miss latency 3216system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 3217system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 3218system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76860.809563 # average WriteLineReq mshr miss latency 3219system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76860.809563 # average WriteLineReq mshr miss latency 3220system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 90425 # average overall mshr miss latency 3221system.iocache.demand_avg_mshr_miss_latency::realview.ide 136925.487917 # average overall mshr miss latency 3222system.iocache.demand_avg_mshr_miss_latency::total 136717.362202 # average overall mshr miss latency 3223system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 90425 # average overall mshr miss latency 3224system.iocache.overall_avg_mshr_miss_latency::realview.ide 136925.487917 # average overall mshr miss latency 3225system.iocache.overall_avg_mshr_miss_latency::total 136717.362202 # average overall mshr miss latency 3226system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 3227system.l2c.tags.replacements 1667118 # number of replacements 3228system.l2c.tags.tagsinuse 63361.638008 # Cycle average of tags in use 3229system.l2c.tags.total_refs 6455366 # Total number of references to valid blocks. 3230system.l2c.tags.sampled_refs 1727204 # Sample count of references to valid blocks. 3231system.l2c.tags.avg_refs 3.737466 # Average number of references to valid blocks. 3232system.l2c.tags.warmup_cycle 4891044000 # Cycle when the warmup percentage was hit. 3233system.l2c.tags.occ_blocks::writebacks 22165.641734 # Average occupied blocks per requestor 3234system.l2c.tags.occ_blocks::cpu0.dtb.walker 239.050229 # Average occupied blocks per requestor 3235system.l2c.tags.occ_blocks::cpu0.itb.walker 385.051566 # Average occupied blocks per requestor 3236system.l2c.tags.occ_blocks::cpu0.inst 4239.404809 # Average occupied blocks per requestor 3237system.l2c.tags.occ_blocks::cpu0.data 8813.325361 # Average occupied blocks per requestor 3238system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14013.639467 # Average occupied blocks per requestor 3239system.l2c.tags.occ_blocks::cpu1.dtb.walker 94.428510 # Average occupied blocks per requestor 3240system.l2c.tags.occ_blocks::cpu1.itb.walker 121.397759 # Average occupied blocks per requestor 3241system.l2c.tags.occ_blocks::cpu1.inst 2981.044706 # Average occupied blocks per requestor 3242system.l2c.tags.occ_blocks::cpu1.data 5621.582558 # Average occupied blocks per requestor 3243system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4687.071308 # Average occupied blocks per requestor 3244system.l2c.tags.occ_percent::writebacks 0.338221 # Average percentage of cache occupancy 3245system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003648 # Average percentage of cache occupancy 3246system.l2c.tags.occ_percent::cpu0.itb.walker 0.005875 # Average percentage of cache occupancy 3247system.l2c.tags.occ_percent::cpu0.inst 0.064688 # Average percentage of cache occupancy 3248system.l2c.tags.occ_percent::cpu0.data 0.134481 # Average percentage of cache occupancy 3249system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.213831 # Average percentage of cache occupancy 3250system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001441 # Average percentage of cache occupancy 3251system.l2c.tags.occ_percent::cpu1.itb.walker 0.001852 # Average percentage of cache occupancy 3252system.l2c.tags.occ_percent::cpu1.inst 0.045487 # Average percentage of cache occupancy 3253system.l2c.tags.occ_percent::cpu1.data 0.085779 # Average percentage of cache occupancy 3254system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.071519 # Average percentage of cache occupancy 3255system.l2c.tags.occ_percent::total 0.966822 # Average percentage of cache occupancy 3256system.l2c.tags.occ_task_id_blocks::1022 9996 # Occupied blocks per task id 3257system.l2c.tags.occ_task_id_blocks::1023 251 # Occupied blocks per task id 3258system.l2c.tags.occ_task_id_blocks::1024 49839 # Occupied blocks per task id 3259system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id 3260system.l2c.tags.age_task_id_blocks_1022::2 1469 # Occupied blocks per task id 3261system.l2c.tags.age_task_id_blocks_1022::3 415 # Occupied blocks per task id 3262system.l2c.tags.age_task_id_blocks_1022::4 8111 # Occupied blocks per task id 3263system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id 3264system.l2c.tags.age_task_id_blocks_1023::4 247 # Occupied blocks per task id 3265system.l2c.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 3266system.l2c.tags.age_task_id_blocks_1024::1 395 # Occupied blocks per task id 3267system.l2c.tags.age_task_id_blocks_1024::2 2991 # Occupied blocks per task id 3268system.l2c.tags.age_task_id_blocks_1024::3 5625 # Occupied blocks per task id 3269system.l2c.tags.age_task_id_blocks_1024::4 40782 # Occupied blocks per task id 3270system.l2c.tags.occ_task_id_percent::1022 0.152527 # Percentage of cache occupancy per task id 3271system.l2c.tags.occ_task_id_percent::1023 0.003830 # Percentage of cache occupancy per task id 3272system.l2c.tags.occ_task_id_percent::1024 0.760483 # Percentage of cache occupancy per task id 3273system.l2c.tags.tag_accesses 82621731 # Number of tag accesses 3274system.l2c.tags.data_accesses 82621731 # Number of data accesses 3275system.l2c.WritebackDirty_hits::writebacks 3012753 # number of WritebackDirty hits 3276system.l2c.WritebackDirty_hits::total 3012753 # number of WritebackDirty hits 3277system.l2c.WritebackClean_hits::writebacks 2 # number of WritebackClean hits 3278system.l2c.WritebackClean_hits::total 2 # number of WritebackClean hits 3279system.l2c.UpgradeReq_hits::cpu0.data 188217 # number of UpgradeReq hits 3280system.l2c.UpgradeReq_hits::cpu1.data 137513 # number of UpgradeReq hits 3281system.l2c.UpgradeReq_hits::total 325730 # number of UpgradeReq hits 3282system.l2c.SCUpgradeReq_hits::cpu0.data 45011 # number of SCUpgradeReq hits 3283system.l2c.SCUpgradeReq_hits::cpu1.data 38650 # number of SCUpgradeReq hits 3284system.l2c.SCUpgradeReq_hits::total 83661 # number of SCUpgradeReq hits 3285system.l2c.ReadExReq_hits::cpu0.data 56653 # number of ReadExReq hits 3286system.l2c.ReadExReq_hits::cpu1.data 53670 # number of ReadExReq hits 3287system.l2c.ReadExReq_hits::total 110323 # number of ReadExReq hits 3288system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6963 # number of ReadSharedReq hits 3289system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4319 # number of ReadSharedReq hits 3290system.l2c.ReadSharedReq_hits::cpu0.inst 567930 # number of ReadSharedReq hits 3291system.l2c.ReadSharedReq_hits::cpu0.data 682126 # number of ReadSharedReq hits 3292system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 295320 # number of ReadSharedReq hits 3293system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6606 # number of ReadSharedReq hits 3294system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4484 # number of ReadSharedReq hits 3295system.l2c.ReadSharedReq_hits::cpu1.inst 500301 # number of ReadSharedReq hits 3296system.l2c.ReadSharedReq_hits::cpu1.data 595581 # number of ReadSharedReq hits 3297system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 300895 # number of ReadSharedReq hits 3298system.l2c.ReadSharedReq_hits::total 2964525 # number of ReadSharedReq hits 3299system.l2c.InvalidateReq_hits::cpu0.data 123921 # number of InvalidateReq hits 3300system.l2c.InvalidateReq_hits::cpu1.data 128483 # number of InvalidateReq hits 3301system.l2c.InvalidateReq_hits::total 252404 # number of InvalidateReq hits 3302system.l2c.demand_hits::cpu0.dtb.walker 6963 # number of demand (read+write) hits 3303system.l2c.demand_hits::cpu0.itb.walker 4319 # number of demand (read+write) hits 3304system.l2c.demand_hits::cpu0.inst 567930 # number of demand (read+write) hits 3305system.l2c.demand_hits::cpu0.data 738779 # number of demand (read+write) hits 3306system.l2c.demand_hits::cpu0.l2cache.prefetcher 295320 # number of demand (read+write) hits 3307system.l2c.demand_hits::cpu1.dtb.walker 6606 # number of demand (read+write) hits 3308system.l2c.demand_hits::cpu1.itb.walker 4484 # number of demand (read+write) hits 3309system.l2c.demand_hits::cpu1.inst 500301 # number of demand (read+write) hits 3310system.l2c.demand_hits::cpu1.data 649251 # number of demand (read+write) hits 3311system.l2c.demand_hits::cpu1.l2cache.prefetcher 300895 # number of demand (read+write) hits 3312system.l2c.demand_hits::total 3074848 # number of demand (read+write) hits 3313system.l2c.overall_hits::cpu0.dtb.walker 6963 # number of overall hits 3314system.l2c.overall_hits::cpu0.itb.walker 4319 # number of overall hits 3315system.l2c.overall_hits::cpu0.inst 567930 # number of overall hits 3316system.l2c.overall_hits::cpu0.data 738779 # number of overall hits 3317system.l2c.overall_hits::cpu0.l2cache.prefetcher 295320 # number of overall hits 3318system.l2c.overall_hits::cpu1.dtb.walker 6606 # number of overall hits 3319system.l2c.overall_hits::cpu1.itb.walker 4484 # number of overall hits 3320system.l2c.overall_hits::cpu1.inst 500301 # number of overall hits 3321system.l2c.overall_hits::cpu1.data 649251 # number of overall hits 3322system.l2c.overall_hits::cpu1.l2cache.prefetcher 300895 # number of overall hits 3323system.l2c.overall_hits::total 3074848 # number of overall hits 3324system.l2c.UpgradeReq_misses::cpu0.data 63777 # number of UpgradeReq misses 3325system.l2c.UpgradeReq_misses::cpu1.data 64352 # number of UpgradeReq misses 3326system.l2c.UpgradeReq_misses::total 128129 # number of UpgradeReq misses 3327system.l2c.SCUpgradeReq_misses::cpu0.data 13748 # number of SCUpgradeReq misses 3328system.l2c.SCUpgradeReq_misses::cpu1.data 11919 # number of SCUpgradeReq misses 3329system.l2c.SCUpgradeReq_misses::total 25667 # number of SCUpgradeReq misses 3330system.l2c.ReadExReq_misses::cpu0.data 97262 # number of ReadExReq misses 3331system.l2c.ReadExReq_misses::cpu1.data 50904 # number of ReadExReq misses 3332system.l2c.ReadExReq_misses::total 148166 # number of ReadExReq misses 3333system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3782 # number of ReadSharedReq misses 3334system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3673 # number of ReadSharedReq misses 3335system.l2c.ReadSharedReq_misses::cpu0.inst 64884 # number of ReadSharedReq misses 3336system.l2c.ReadSharedReq_misses::cpu0.data 181110 # number of ReadSharedReq misses 3337system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 386357 # number of ReadSharedReq misses 3338system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2034 # number of ReadSharedReq misses 3339system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1570 # number of ReadSharedReq misses 3340system.l2c.ReadSharedReq_misses::cpu1.inst 45959 # number of ReadSharedReq misses 3341system.l2c.ReadSharedReq_misses::cpu1.data 114229 # number of ReadSharedReq misses 3342system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 215943 # number of ReadSharedReq misses 3343system.l2c.ReadSharedReq_misses::total 1019541 # number of ReadSharedReq misses 3344system.l2c.InvalidateReq_misses::cpu0.data 509164 # number of InvalidateReq misses 3345system.l2c.InvalidateReq_misses::cpu1.data 100519 # number of InvalidateReq misses 3346system.l2c.InvalidateReq_misses::total 609683 # number of InvalidateReq misses 3347system.l2c.demand_misses::cpu0.dtb.walker 3782 # number of demand (read+write) misses 3348system.l2c.demand_misses::cpu0.itb.walker 3673 # number of demand (read+write) misses 3349system.l2c.demand_misses::cpu0.inst 64884 # number of demand (read+write) misses 3350system.l2c.demand_misses::cpu0.data 278372 # number of demand (read+write) misses 3351system.l2c.demand_misses::cpu0.l2cache.prefetcher 386357 # number of demand (read+write) misses 3352system.l2c.demand_misses::cpu1.dtb.walker 2034 # number of demand (read+write) misses 3353system.l2c.demand_misses::cpu1.itb.walker 1570 # number of demand (read+write) misses 3354system.l2c.demand_misses::cpu1.inst 45959 # number of demand (read+write) misses 3355system.l2c.demand_misses::cpu1.data 165133 # number of demand (read+write) misses 3356system.l2c.demand_misses::cpu1.l2cache.prefetcher 215943 # number of demand (read+write) misses 3357system.l2c.demand_misses::total 1167707 # number of demand (read+write) misses 3358system.l2c.overall_misses::cpu0.dtb.walker 3782 # number of overall misses 3359system.l2c.overall_misses::cpu0.itb.walker 3673 # number of overall misses 3360system.l2c.overall_misses::cpu0.inst 64884 # number of overall misses 3361system.l2c.overall_misses::cpu0.data 278372 # number of overall misses 3362system.l2c.overall_misses::cpu0.l2cache.prefetcher 386357 # number of overall misses 3363system.l2c.overall_misses::cpu1.dtb.walker 2034 # number of overall misses 3364system.l2c.overall_misses::cpu1.itb.walker 1570 # number of overall misses 3365system.l2c.overall_misses::cpu1.inst 45959 # number of overall misses 3366system.l2c.overall_misses::cpu1.data 165133 # number of overall misses 3367system.l2c.overall_misses::cpu1.l2cache.prefetcher 215943 # number of overall misses 3368system.l2c.overall_misses::total 1167707 # number of overall misses 3369system.l2c.UpgradeReq_miss_latency::cpu0.data 1085442500 # number of UpgradeReq miss cycles 3370system.l2c.UpgradeReq_miss_latency::cpu1.data 1077777500 # number of UpgradeReq miss cycles 3371system.l2c.UpgradeReq_miss_latency::total 2163220000 # number of UpgradeReq miss cycles 3372system.l2c.SCUpgradeReq_miss_latency::cpu0.data 211973500 # number of SCUpgradeReq miss cycles 3373system.l2c.SCUpgradeReq_miss_latency::cpu1.data 184474000 # number of SCUpgradeReq miss cycles 3374system.l2c.SCUpgradeReq_miss_latency::total 396447500 # number of SCUpgradeReq miss cycles 3375system.l2c.ReadExReq_miss_latency::cpu0.data 13946644494 # number of ReadExReq miss cycles 3376system.l2c.ReadExReq_miss_latency::cpu1.data 6989170497 # number of ReadExReq miss cycles 3377system.l2c.ReadExReq_miss_latency::total 20935814991 # number of ReadExReq miss cycles 3378system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 531173000 # number of ReadSharedReq miss cycles 3379system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 521770500 # number of ReadSharedReq miss cycles 3380system.l2c.ReadSharedReq_miss_latency::cpu0.inst 8947284001 # number of ReadSharedReq miss cycles 3381system.l2c.ReadSharedReq_miss_latency::cpu0.data 26625748999 # number of ReadSharedReq miss cycles 3382system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 72546834291 # number of ReadSharedReq miss cycles 3383system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 297030000 # number of ReadSharedReq miss cycles 3384system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 228999000 # number of ReadSharedReq miss cycles 3385system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6329750999 # number of ReadSharedReq miss cycles 3386system.l2c.ReadSharedReq_miss_latency::cpu1.data 16747831000 # number of ReadSharedReq miss cycles 3387system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 39888708640 # number of ReadSharedReq miss cycles 3388system.l2c.ReadSharedReq_miss_latency::total 172665130430 # number of ReadSharedReq miss cycles 3389system.l2c.InvalidateReq_miss_latency::cpu0.data 156554500 # number of InvalidateReq miss cycles 3390system.l2c.InvalidateReq_miss_latency::cpu1.data 157821500 # number of InvalidateReq miss cycles 3391system.l2c.InvalidateReq_miss_latency::total 314376000 # number of InvalidateReq miss cycles 3392system.l2c.demand_miss_latency::cpu0.dtb.walker 531173000 # number of demand (read+write) miss cycles 3393system.l2c.demand_miss_latency::cpu0.itb.walker 521770500 # number of demand (read+write) miss cycles 3394system.l2c.demand_miss_latency::cpu0.inst 8947284001 # number of demand (read+write) miss cycles 3395system.l2c.demand_miss_latency::cpu0.data 40572393493 # number of demand (read+write) miss cycles 3396system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 72546834291 # number of demand (read+write) miss cycles 3397system.l2c.demand_miss_latency::cpu1.dtb.walker 297030000 # number of demand (read+write) miss cycles 3398system.l2c.demand_miss_latency::cpu1.itb.walker 228999000 # number of demand (read+write) miss cycles 3399system.l2c.demand_miss_latency::cpu1.inst 6329750999 # number of demand (read+write) miss cycles 3400system.l2c.demand_miss_latency::cpu1.data 23737001497 # number of demand (read+write) miss cycles 3401system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 39888708640 # number of demand (read+write) miss cycles 3402system.l2c.demand_miss_latency::total 193600945421 # number of demand (read+write) miss cycles 3403system.l2c.overall_miss_latency::cpu0.dtb.walker 531173000 # number of overall miss cycles 3404system.l2c.overall_miss_latency::cpu0.itb.walker 521770500 # number of overall miss cycles 3405system.l2c.overall_miss_latency::cpu0.inst 8947284001 # number of overall miss cycles 3406system.l2c.overall_miss_latency::cpu0.data 40572393493 # number of overall miss cycles 3407system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 72546834291 # number of overall miss cycles 3408system.l2c.overall_miss_latency::cpu1.dtb.walker 297030000 # number of overall miss cycles 3409system.l2c.overall_miss_latency::cpu1.itb.walker 228999000 # number of overall miss cycles 3410system.l2c.overall_miss_latency::cpu1.inst 6329750999 # number of overall miss cycles 3411system.l2c.overall_miss_latency::cpu1.data 23737001497 # number of overall miss cycles 3412system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 39888708640 # number of overall miss cycles 3413system.l2c.overall_miss_latency::total 193600945421 # number of overall miss cycles 3414system.l2c.WritebackDirty_accesses::writebacks 3012753 # number of WritebackDirty accesses(hits+misses) 3415system.l2c.WritebackDirty_accesses::total 3012753 # number of WritebackDirty accesses(hits+misses) 3416system.l2c.WritebackClean_accesses::writebacks 2 # number of WritebackClean accesses(hits+misses) 3417system.l2c.WritebackClean_accesses::total 2 # number of WritebackClean accesses(hits+misses) 3418system.l2c.UpgradeReq_accesses::cpu0.data 251994 # number of UpgradeReq accesses(hits+misses) 3419system.l2c.UpgradeReq_accesses::cpu1.data 201865 # number of UpgradeReq accesses(hits+misses) 3420system.l2c.UpgradeReq_accesses::total 453859 # number of UpgradeReq accesses(hits+misses) 3421system.l2c.SCUpgradeReq_accesses::cpu0.data 58759 # number of SCUpgradeReq accesses(hits+misses) 3422system.l2c.SCUpgradeReq_accesses::cpu1.data 50569 # number of SCUpgradeReq accesses(hits+misses) 3423system.l2c.SCUpgradeReq_accesses::total 109328 # number of SCUpgradeReq accesses(hits+misses) 3424system.l2c.ReadExReq_accesses::cpu0.data 153915 # number of ReadExReq accesses(hits+misses) 3425system.l2c.ReadExReq_accesses::cpu1.data 104574 # number of ReadExReq accesses(hits+misses) 3426system.l2c.ReadExReq_accesses::total 258489 # number of ReadExReq accesses(hits+misses) 3427system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 10745 # number of ReadSharedReq accesses(hits+misses) 3428system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7992 # number of ReadSharedReq accesses(hits+misses) 3429system.l2c.ReadSharedReq_accesses::cpu0.inst 632814 # number of ReadSharedReq accesses(hits+misses) 3430system.l2c.ReadSharedReq_accesses::cpu0.data 863236 # number of ReadSharedReq accesses(hits+misses) 3431system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 681677 # number of ReadSharedReq accesses(hits+misses) 3432system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8640 # number of ReadSharedReq accesses(hits+misses) 3433system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6054 # number of ReadSharedReq accesses(hits+misses) 3434system.l2c.ReadSharedReq_accesses::cpu1.inst 546260 # number of ReadSharedReq accesses(hits+misses) 3435system.l2c.ReadSharedReq_accesses::cpu1.data 709810 # number of ReadSharedReq accesses(hits+misses) 3436system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 516838 # number of ReadSharedReq accesses(hits+misses) 3437system.l2c.ReadSharedReq_accesses::total 3984066 # number of ReadSharedReq accesses(hits+misses) 3438system.l2c.InvalidateReq_accesses::cpu0.data 633085 # number of InvalidateReq accesses(hits+misses) 3439system.l2c.InvalidateReq_accesses::cpu1.data 229002 # number of InvalidateReq accesses(hits+misses) 3440system.l2c.InvalidateReq_accesses::total 862087 # number of InvalidateReq accesses(hits+misses) 3441system.l2c.demand_accesses::cpu0.dtb.walker 10745 # number of demand (read+write) accesses 3442system.l2c.demand_accesses::cpu0.itb.walker 7992 # number of demand (read+write) accesses 3443system.l2c.demand_accesses::cpu0.inst 632814 # number of demand (read+write) accesses 3444system.l2c.demand_accesses::cpu0.data 1017151 # number of demand (read+write) accesses 3445system.l2c.demand_accesses::cpu0.l2cache.prefetcher 681677 # number of demand (read+write) accesses 3446system.l2c.demand_accesses::cpu1.dtb.walker 8640 # number of demand (read+write) accesses 3447system.l2c.demand_accesses::cpu1.itb.walker 6054 # number of demand (read+write) accesses 3448system.l2c.demand_accesses::cpu1.inst 546260 # number of demand (read+write) accesses 3449system.l2c.demand_accesses::cpu1.data 814384 # number of demand (read+write) accesses 3450system.l2c.demand_accesses::cpu1.l2cache.prefetcher 516838 # number of demand (read+write) accesses 3451system.l2c.demand_accesses::total 4242555 # number of demand (read+write) accesses 3452system.l2c.overall_accesses::cpu0.dtb.walker 10745 # number of overall (read+write) accesses 3453system.l2c.overall_accesses::cpu0.itb.walker 7992 # number of overall (read+write) accesses 3454system.l2c.overall_accesses::cpu0.inst 632814 # number of overall (read+write) accesses 3455system.l2c.overall_accesses::cpu0.data 1017151 # number of overall (read+write) accesses 3456system.l2c.overall_accesses::cpu0.l2cache.prefetcher 681677 # number of overall (read+write) accesses 3457system.l2c.overall_accesses::cpu1.dtb.walker 8640 # number of overall (read+write) accesses 3458system.l2c.overall_accesses::cpu1.itb.walker 6054 # number of overall (read+write) accesses 3459system.l2c.overall_accesses::cpu1.inst 546260 # number of overall (read+write) accesses 3460system.l2c.overall_accesses::cpu1.data 814384 # number of overall (read+write) accesses 3461system.l2c.overall_accesses::cpu1.l2cache.prefetcher 516838 # number of overall (read+write) accesses 3462system.l2c.overall_accesses::total 4242555 # number of overall (read+write) accesses 3463system.l2c.UpgradeReq_miss_rate::cpu0.data 0.253089 # miss rate for UpgradeReq accesses 3464system.l2c.UpgradeReq_miss_rate::cpu1.data 0.318787 # miss rate for UpgradeReq accesses 3465system.l2c.UpgradeReq_miss_rate::total 0.282310 # miss rate for UpgradeReq accesses 3466system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.233973 # miss rate for SCUpgradeReq accesses 3467system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.235698 # miss rate for SCUpgradeReq accesses 3468system.l2c.SCUpgradeReq_miss_rate::total 0.234771 # miss rate for SCUpgradeReq accesses 3469system.l2c.ReadExReq_miss_rate::cpu0.data 0.631920 # miss rate for ReadExReq accesses 3470system.l2c.ReadExReq_miss_rate::cpu1.data 0.486775 # miss rate for ReadExReq accesses 3471system.l2c.ReadExReq_miss_rate::total 0.573200 # miss rate for ReadExReq accesses 3472system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.351978 # miss rate for ReadSharedReq accesses 3473system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.459585 # miss rate for ReadSharedReq accesses 3474system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.102532 # miss rate for ReadSharedReq accesses 3475system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.209804 # miss rate for ReadSharedReq accesses 3476system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.566774 # miss rate for ReadSharedReq accesses 3477system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.235417 # miss rate for ReadSharedReq accesses 3478system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.259333 # miss rate for ReadSharedReq accesses 3479system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.084134 # miss rate for ReadSharedReq accesses 3480system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.160929 # miss rate for ReadSharedReq accesses 3481system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.417816 # miss rate for ReadSharedReq accesses 3482system.l2c.ReadSharedReq_miss_rate::total 0.255905 # miss rate for ReadSharedReq accesses 3483system.l2c.InvalidateReq_miss_rate::cpu0.data 0.804259 # miss rate for InvalidateReq accesses 3484system.l2c.InvalidateReq_miss_rate::cpu1.data 0.438944 # miss rate for InvalidateReq accesses 3485system.l2c.InvalidateReq_miss_rate::total 0.707217 # miss rate for InvalidateReq accesses 3486system.l2c.demand_miss_rate::cpu0.dtb.walker 0.351978 # miss rate for demand accesses 3487system.l2c.demand_miss_rate::cpu0.itb.walker 0.459585 # miss rate for demand accesses 3488system.l2c.demand_miss_rate::cpu0.inst 0.102532 # miss rate for demand accesses 3489system.l2c.demand_miss_rate::cpu0.data 0.273678 # miss rate for demand accesses 3490system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.566774 # miss rate for demand accesses 3491system.l2c.demand_miss_rate::cpu1.dtb.walker 0.235417 # miss rate for demand accesses 3492system.l2c.demand_miss_rate::cpu1.itb.walker 0.259333 # miss rate for demand accesses 3493system.l2c.demand_miss_rate::cpu1.inst 0.084134 # miss rate for demand accesses 3494system.l2c.demand_miss_rate::cpu1.data 0.202770 # miss rate for demand accesses 3495system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.417816 # miss rate for demand accesses 3496system.l2c.demand_miss_rate::total 0.275237 # miss rate for demand accesses 3497system.l2c.overall_miss_rate::cpu0.dtb.walker 0.351978 # miss rate for overall accesses 3498system.l2c.overall_miss_rate::cpu0.itb.walker 0.459585 # miss rate for overall accesses 3499system.l2c.overall_miss_rate::cpu0.inst 0.102532 # miss rate for overall accesses 3500system.l2c.overall_miss_rate::cpu0.data 0.273678 # miss rate for overall accesses 3501system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.566774 # miss rate for overall accesses 3502system.l2c.overall_miss_rate::cpu1.dtb.walker 0.235417 # miss rate for overall accesses 3503system.l2c.overall_miss_rate::cpu1.itb.walker 0.259333 # miss rate for overall accesses 3504system.l2c.overall_miss_rate::cpu1.inst 0.084134 # miss rate for overall accesses 3505system.l2c.overall_miss_rate::cpu1.data 0.202770 # miss rate for overall accesses 3506system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.417816 # miss rate for overall accesses 3507system.l2c.overall_miss_rate::total 0.275237 # miss rate for overall accesses 3508system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 17019.340828 # average UpgradeReq miss latency 3509system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 16748.158565 # average UpgradeReq miss latency 3510system.l2c.UpgradeReq_avg_miss_latency::total 16883.141209 # average UpgradeReq miss latency 3511system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15418.497236 # average SCUpgradeReq miss latency 3512system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 15477.305143 # average SCUpgradeReq miss latency 3513system.l2c.SCUpgradeReq_avg_miss_latency::total 15445.805899 # average SCUpgradeReq miss latency 3514system.l2c.ReadExReq_avg_miss_latency::cpu0.data 143392.532479 # average ReadExReq miss latency 3515system.l2c.ReadExReq_avg_miss_latency::cpu1.data 137301.007720 # average ReadExReq miss latency 3516system.l2c.ReadExReq_avg_miss_latency::total 141299.724572 # average ReadExReq miss latency 3517system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 140447.646748 # average ReadSharedReq miss latency 3518system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 142055.676559 # average ReadSharedReq miss latency 3519system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 137896.615514 # average ReadSharedReq miss latency 3520system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 147014.239959 # average ReadSharedReq miss latency 3521system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 187771.502240 # average ReadSharedReq miss latency 3522system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 146032.448378 # average ReadSharedReq miss latency 3523system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 145859.235669 # average ReadSharedReq miss latency 3524system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 137726.038404 # average ReadSharedReq miss latency 3525system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 146616.279579 # average ReadSharedReq miss latency 3526system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 184718.692618 # average ReadSharedReq miss latency 3527system.l2c.ReadSharedReq_avg_miss_latency::total 169355.749725 # average ReadSharedReq miss latency 3528system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 307.473623 # average InvalidateReq miss latency 3529system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 1570.066356 # average InvalidateReq miss latency 3530system.l2c.InvalidateReq_avg_miss_latency::total 515.638455 # average InvalidateReq miss latency 3531system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 140447.646748 # average overall miss latency 3532system.l2c.demand_avg_miss_latency::cpu0.itb.walker 142055.676559 # average overall miss latency 3533system.l2c.demand_avg_miss_latency::cpu0.inst 137896.615514 # average overall miss latency 3534system.l2c.demand_avg_miss_latency::cpu0.data 145748.830676 # average overall miss latency 3535system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 187771.502240 # average overall miss latency 3536system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 146032.448378 # average overall miss latency 3537system.l2c.demand_avg_miss_latency::cpu1.itb.walker 145859.235669 # average overall miss latency 3538system.l2c.demand_avg_miss_latency::cpu1.inst 137726.038404 # average overall miss latency 3539system.l2c.demand_avg_miss_latency::cpu1.data 143744.748155 # average overall miss latency 3540system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 184718.692618 # average overall miss latency 3541system.l2c.demand_avg_miss_latency::total 165795.824998 # average overall miss latency 3542system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 140447.646748 # average overall miss latency 3543system.l2c.overall_avg_miss_latency::cpu0.itb.walker 142055.676559 # average overall miss latency 3544system.l2c.overall_avg_miss_latency::cpu0.inst 137896.615514 # average overall miss latency 3545system.l2c.overall_avg_miss_latency::cpu0.data 145748.830676 # average overall miss latency 3546system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 187771.502240 # average overall miss latency 3547system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 146032.448378 # average overall miss latency 3548system.l2c.overall_avg_miss_latency::cpu1.itb.walker 145859.235669 # average overall miss latency 3549system.l2c.overall_avg_miss_latency::cpu1.inst 137726.038404 # average overall miss latency 3550system.l2c.overall_avg_miss_latency::cpu1.data 143744.748155 # average overall miss latency 3551system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 184718.692618 # average overall miss latency 3552system.l2c.overall_avg_miss_latency::total 165795.824998 # average overall miss latency 3553system.l2c.blocked_cycles::no_mshrs 16571 # number of cycles access was blocked 3554system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 3555system.l2c.blocked::no_mshrs 157 # number of cycles access was blocked 3556system.l2c.blocked::no_targets 0 # number of cycles access was blocked 3557system.l2c.avg_blocked_cycles::no_mshrs 105.547771 # average number of cycles each access was blocked 3558system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3559system.l2c.fast_writes 0 # number of fast writes performed 3560system.l2c.cache_copies 0 # number of cache copies performed 3561system.l2c.writebacks::writebacks 1320441 # number of writebacks 3562system.l2c.writebacks::total 1320441 # number of writebacks 3563system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 157 # number of ReadSharedReq MSHR hits 3564system.l2c.ReadSharedReq_mshr_hits::cpu0.data 33 # number of ReadSharedReq MSHR hits 3565system.l2c.ReadSharedReq_mshr_hits::cpu0.l2cache.prefetcher 2 # number of ReadSharedReq MSHR hits 3566system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 231 # number of ReadSharedReq MSHR hits 3567system.l2c.ReadSharedReq_mshr_hits::cpu1.data 20 # number of ReadSharedReq MSHR hits 3568system.l2c.ReadSharedReq_mshr_hits::total 443 # number of ReadSharedReq MSHR hits 3569system.l2c.demand_mshr_hits::cpu0.inst 157 # number of demand (read+write) MSHR hits 3570system.l2c.demand_mshr_hits::cpu0.data 33 # number of demand (read+write) MSHR hits 3571system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 2 # number of demand (read+write) MSHR hits 3572system.l2c.demand_mshr_hits::cpu1.inst 231 # number of demand (read+write) MSHR hits 3573system.l2c.demand_mshr_hits::cpu1.data 20 # number of demand (read+write) MSHR hits 3574system.l2c.demand_mshr_hits::total 443 # number of demand (read+write) MSHR hits 3575system.l2c.overall_mshr_hits::cpu0.inst 157 # number of overall MSHR hits 3576system.l2c.overall_mshr_hits::cpu0.data 33 # number of overall MSHR hits 3577system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 2 # number of overall MSHR hits 3578system.l2c.overall_mshr_hits::cpu1.inst 231 # number of overall MSHR hits 3579system.l2c.overall_mshr_hits::cpu1.data 20 # number of overall MSHR hits 3580system.l2c.overall_mshr_hits::total 443 # number of overall MSHR hits 3581system.l2c.CleanEvict_mshr_misses::writebacks 61724 # number of CleanEvict MSHR misses 3582system.l2c.CleanEvict_mshr_misses::total 61724 # number of CleanEvict MSHR misses 3583system.l2c.UpgradeReq_mshr_misses::cpu0.data 63777 # number of UpgradeReq MSHR misses 3584system.l2c.UpgradeReq_mshr_misses::cpu1.data 64352 # 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number of ReadSharedReq MSHR miss cycles 3660system.l2c.ReadSharedReq_mshr_miss_latency::total 162413903600 # number of ReadSharedReq MSHR miss cycles 3661system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 35699174001 # number of InvalidateReq MSHR miss cycles 3662system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 7062172000 # number of InvalidateReq MSHR miss cycles 3663system.l2c.InvalidateReq_mshr_miss_latency::total 42761346001 # number of InvalidateReq MSHR miss cycles 3664system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 493342025 # number of demand (read+write) MSHR miss cycles 3665system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 485033021 # number of demand (read+write) MSHR miss cycles 3666system.l2c.demand_mshr_miss_latency::cpu0.inst 8280831088 # number of demand (read+write) MSHR miss cycles 3667system.l2c.demand_mshr_miss_latency::cpu0.data 37783615985 # number of demand (read+write) MSHR miss cycles 3668system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 68681605136 # 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number of ReadReq MSHR uncacheable cycles 3688system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7936000 # number of ReadReq MSHR uncacheable cycles 3689system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2591094528 # number of ReadReq MSHR uncacheable cycles 3690system.l2c.ReadReq_mshr_uncacheable_latency::total 8312604064 # number of ReadReq MSHR uncacheable cycles 3691system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3549490576 # number of WriteReq MSHR uncacheable cycles 3692system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2410843031 # number of WriteReq MSHR uncacheable cycles 3693system.l2c.WriteReq_mshr_uncacheable_latency::total 5960333607 # number of WriteReq MSHR uncacheable cycles 3694system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2396808000 # number of overall MSHR uncacheable cycles 3695system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6866256112 # number of overall MSHR uncacheable cycles 3696system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7936000 # number of overall MSHR uncacheable cycles 3697system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5001937559 # number of overall MSHR uncacheable cycles 3698system.l2c.overall_mshr_uncacheable_latency::total 14272937671 # number of overall MSHR uncacheable cycles 3699system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3700system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3701system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.253089 # mshr miss rate for UpgradeReq accesses 3702system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.318787 # mshr miss rate for UpgradeReq accesses 3703system.l2c.UpgradeReq_mshr_miss_rate::total 0.282310 # mshr miss rate for UpgradeReq accesses 3704system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.233973 # mshr miss rate for SCUpgradeReq accesses 3705system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.235698 # mshr miss rate for SCUpgradeReq accesses 3706system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.234771 # mshr miss rate for SCUpgradeReq accesses 3707system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.631920 # mshr miss rate for ReadExReq accesses 3708system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.486775 # mshr miss rate for ReadExReq accesses 3709system.l2c.ReadExReq_mshr_miss_rate::total 0.573200 # mshr miss rate for ReadExReq accesses 3710system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.351978 # mshr miss rate for ReadSharedReq accesses 3711system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.459585 # mshr miss rate for ReadSharedReq accesses 3712system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.102284 # mshr miss rate for ReadSharedReq accesses 3713system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.209765 # mshr miss rate for ReadSharedReq accesses 3714system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.566771 # mshr miss rate for ReadSharedReq accesses 3715system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.235417 # mshr miss rate for ReadSharedReq accesses 3716system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.259333 # mshr miss rate for ReadSharedReq accesses 3717system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.083711 # mshr miss rate for ReadSharedReq accesses 3718system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.160901 # mshr miss rate for ReadSharedReq accesses 3719system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.417816 # mshr miss rate for ReadSharedReq accesses 3720system.l2c.ReadSharedReq_mshr_miss_rate::total 0.255793 # mshr miss rate for ReadSharedReq accesses 3721system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.804259 # mshr miss rate for InvalidateReq accesses 3722system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.438944 # mshr miss rate for InvalidateReq accesses 3723system.l2c.InvalidateReq_mshr_miss_rate::total 0.707217 # mshr miss rate for InvalidateReq accesses 3724system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.351978 # mshr miss rate for demand accesses 3725system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.459585 # mshr miss rate for demand accesses 3726system.l2c.demand_mshr_miss_rate::cpu0.inst 0.102284 # mshr miss rate for demand accesses 3727system.l2c.demand_mshr_miss_rate::cpu0.data 0.273646 # mshr miss rate for demand accesses 3728system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.566771 # mshr miss rate for demand accesses 3729system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.235417 # mshr miss rate for demand accesses 3730system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.259333 # mshr miss rate for demand accesses 3731system.l2c.demand_mshr_miss_rate::cpu1.inst 0.083711 # mshr miss rate for demand accesses 3732system.l2c.demand_mshr_miss_rate::cpu1.data 0.202746 # mshr miss rate for demand accesses 3733system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.417816 # mshr miss rate for demand accesses 3734system.l2c.demand_mshr_miss_rate::total 0.275132 # mshr miss rate for demand accesses 3735system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.351978 # mshr miss rate for overall accesses 3736system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.459585 # mshr miss rate for overall accesses 3737system.l2c.overall_mshr_miss_rate::cpu0.inst 0.102284 # mshr miss rate for overall accesses 3738system.l2c.overall_mshr_miss_rate::cpu0.data 0.273646 # mshr miss rate for overall accesses 3739system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.566771 # mshr miss rate for overall accesses 3740system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.235417 # mshr miss rate for overall accesses 3741system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.259333 # mshr miss rate for overall accesses 3742system.l2c.overall_mshr_miss_rate::cpu1.inst 0.083711 # mshr miss rate for overall accesses 3743system.l2c.overall_mshr_miss_rate::cpu1.data 0.202746 # mshr miss rate for overall accesses 3744system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.417816 # mshr miss rate for overall accesses 3745system.l2c.overall_mshr_miss_rate::total 0.275132 # mshr miss rate for overall accesses 3746system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 70448.531555 # average UpgradeReq mshr miss latency 3747system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 70759.533394 # average UpgradeReq mshr miss latency 3748system.l2c.UpgradeReq_avg_mshr_miss_latency::total 70604.730311 # average UpgradeReq mshr miss latency 3749system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 73634.273785 # average SCUpgradeReq mshr miss latency 3750system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73691.039349 # average SCUpgradeReq mshr miss latency 3751system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 73660.634044 # average SCUpgradeReq mshr miss latency 3752system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 133387.815570 # average ReadExReq mshr miss latency 3753system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 127291.827027 # average ReadExReq mshr miss latency 3754system.l2c.ReadExReq_avg_mshr_miss_latency::total 131293.474083 # average ReadExReq mshr miss latency 3755system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 130444.744844 # average ReadSharedReq mshr miss latency 3756system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 132053.640348 # average ReadSharedReq mshr miss latency 3757system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 127934.727208 # average ReadSharedReq mshr miss latency 3758system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 137013.813278 # average ReadSharedReq mshr miss latency 3759system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177768.128110 # average ReadSharedReq mshr miss latency 3760system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 136025.584071 # average ReadSharedReq mshr miss latency 3761system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 135853.198726 # average ReadSharedReq mshr miss latency 3762system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127776.483314 # average ReadSharedReq mshr miss latency 3763system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 136612.753688 # average ReadSharedReq mshr miss latency 3764system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174711.416846 # average ReadSharedReq mshr miss latency 3765system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 159370.250555 # average ReadSharedReq mshr miss latency 3766system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 70113.311234 # average InvalidateReq mshr miss latency 3767system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 70257.085725 # average InvalidateReq mshr miss latency 3768system.l2c.InvalidateReq_avg_mshr_miss_latency::total 70137.015467 # average InvalidateReq mshr miss latency 3769system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 130444.744844 # average overall mshr miss latency 3770system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 132053.640348 # average overall mshr miss latency 3771system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 127934.727208 # average overall mshr miss latency 3772system.l2c.demand_avg_mshr_miss_latency::cpu0.data 135746.754803 # average overall mshr miss latency 3773system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177768.128110 # average overall mshr miss latency 3774system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 136025.584071 # average overall mshr miss latency 3775system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 135853.198726 # average overall mshr miss latency 3776system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127776.483314 # average overall mshr miss latency 3777system.l2c.demand_avg_mshr_miss_latency::cpu1.data 133739.131074 # average overall mshr miss latency 3778system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174711.416846 # average overall mshr miss latency 3779system.l2c.demand_avg_mshr_miss_latency::total 155806.340709 # average overall mshr miss latency 3780system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 130444.744844 # average overall mshr miss latency 3781system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 132053.640348 # average overall mshr miss latency 3782system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 127934.727208 # average overall mshr miss latency 3783system.l2c.overall_avg_mshr_miss_latency::cpu0.data 135746.754803 # average overall mshr miss latency 3784system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 177768.128110 # average overall mshr miss latency 3785system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 136025.584071 # average overall mshr miss latency 3786system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 135853.198726 # average overall mshr miss latency 3787system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127776.483314 # average overall mshr miss latency 3788system.l2c.overall_avg_mshr_miss_latency::cpu1.data 133739.131074 # average overall mshr miss latency 3789system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 174711.416846 # average overall mshr miss latency 3790system.l2c.overall_avg_mshr_miss_latency::total 155806.340709 # average overall mshr miss latency 3791system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781 # average ReadReq mshr uncacheable latency 3792system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168235.634593 # average ReadReq mshr uncacheable latency 3793system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 118447.761194 # average ReadReq mshr uncacheable latency 3794system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 139802.229848 # average ReadReq mshr uncacheable latency 3795system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 139452.164338 # average ReadReq mshr uncacheable latency 3796system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164282.633343 # average WriteReq mshr uncacheable latency 3797system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 145775.972367 # average WriteReq mshr uncacheable latency 3798system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 156258.745989 # average WriteReq mshr uncacheable latency 3799system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781 # average overall mshr uncacheable latency 3800system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 166168.682074 # average overall mshr uncacheable latency 3801system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 118447.761194 # average overall mshr uncacheable latency 3802system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 142619.113794 # average overall mshr uncacheable latency 3803system.l2c.overall_avg_mshr_uncacheable_latency::total 146010.226499 # average overall mshr uncacheable latency 3804system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3805system.membus.trans_dist::ReadReq 59609 # Transaction distribution 3806system.membus.trans_dist::ReadResp 1087641 # Transaction distribution 3807system.membus.trans_dist::WriteReq 38144 # Transaction distribution 3808system.membus.trans_dist::WriteResp 38144 # Transaction distribution 3809system.membus.trans_dist::WritebackDirty 1427135 # Transaction distribution 3810system.membus.trans_dist::CleanEvict 277667 # Transaction distribution 3811system.membus.trans_dist::UpgradeReq 445891 # Transaction distribution 3812system.membus.trans_dist::SCUpgradeReq 321137 # Transaction distribution 3813system.membus.trans_dist::UpgradeResp 23 # Transaction distribution 3814system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 3815system.membus.trans_dist::ReadExReq 156981 # Transaction distribution 3816system.membus.trans_dist::ReadExResp 142959 # Transaction distribution 3817system.membus.trans_dist::ReadSharedReq 1028032 # Transaction distribution 3818system.membus.trans_dist::InvalidateReq 712467 # Transaction distribution 3819system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122696 # Packet count per connected master and slave (bytes) 3820system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) 3821system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24870 # Packet count per connected master and slave (bytes) 3822system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5347246 # Packet count per connected master and slave (bytes) 3823system.membus.pkt_count_system.l2c.mem_side::total 5494888 # Packet count per connected master and slave (bytes) 3824system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237811 # Packet count per connected master and slave (bytes) 3825system.membus.pkt_count_system.iocache.mem_side::total 237811 # Packet count per connected master and slave (bytes) 3826system.membus.pkt_count::total 5732699 # Packet count per connected master and slave (bytes) 3827system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155826 # Cumulative packet size per connected master and slave (bytes) 3828system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes) 3829system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49740 # Cumulative packet size per connected master and slave (bytes) 3830system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 159196224 # Cumulative packet size per connected master and slave (bytes) 3831system.membus.pkt_size_system.l2c.mem_side::total 159402346 # Cumulative packet size per connected master and slave (bytes) 3832system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7246976 # Cumulative packet size per connected master and slave (bytes) 3833system.membus.pkt_size_system.iocache.mem_side::total 7246976 # Cumulative packet size per connected master and slave (bytes) 3834system.membus.pkt_size::total 166649322 # Cumulative packet size per connected master and slave (bytes) 3835system.membus.snoops 621233 # Total snoops (count) 3836system.membus.snoop_fanout::samples 4467120 # Request fanout histogram 3837system.membus.snoop_fanout::mean 1 # Request fanout histogram 3838system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3839system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3840system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3841system.membus.snoop_fanout::1 4467120 100.00% 100.00% # Request fanout histogram 3842system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3843system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3844system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3845system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3846system.membus.snoop_fanout::total 4467120 # Request fanout histogram 3847system.membus.reqLayer0.occupancy 98530997 # Layer occupancy (ticks) 3848system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3849system.membus.reqLayer1.occupancy 53000 # Layer occupancy (ticks) 3850system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3851system.membus.reqLayer2.occupancy 20867984 # Layer occupancy (ticks) 3852system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3853system.membus.reqLayer5.occupancy 9912231208 # Layer occupancy (ticks) 3854system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3855system.membus.respLayer2.occupancy 6259994034 # Layer occupancy (ticks) 3856system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3857system.membus.respLayer3.occupancy 45597361 # Layer occupancy (ticks) 3858system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3859system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3860system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3861system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3862system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3863system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3864system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3865system.realview.ethernet.txBytes 966 # Bytes Transmitted 3866system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3867system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3868system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3869system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3870system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3871system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3872system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3873system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3874system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3875system.realview.ethernet.totPackets 3 # Total Packets 3876system.realview.ethernet.totBytes 966 # Total Bytes 3877system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3878system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3879system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3880system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3881system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3882system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3883system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3884system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3885system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3886system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3887system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3888system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3889system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3890system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3891system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3892system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3893system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3894system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3895system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3896system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3897system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3898system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3899system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3900system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3901system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3902system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3903system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3904system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3905system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3906system.realview.ethernet.droppedPackets 0 # number of packets dropped 3907system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3908system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3909system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3910system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3911system.toL2Bus.snoop_filter.tot_requests 12663754 # Total number of requests made to the snoop filter. 3912system.toL2Bus.snoop_filter.hit_single_requests 6874752 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3913system.toL2Bus.snoop_filter.hit_multi_requests 2026071 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3914system.toL2Bus.snoop_filter.tot_snoops 169438 # Total number of snoops made to the snoop filter. 3915system.toL2Bus.snoop_filter.hit_single_snoops 153466 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3916system.toL2Bus.snoop_filter.hit_multi_snoops 15972 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3917system.toL2Bus.trans_dist::ReadReq 59611 # Transaction distribution 3918system.toL2Bus.trans_dist::ReadResp 4844529 # Transaction distribution 3919system.toL2Bus.trans_dist::WriteReq 38144 # Transaction distribution 3920system.toL2Bus.trans_dist::WriteResp 38144 # Transaction distribution 3921system.toL2Bus.trans_dist::WritebackDirty 4439938 # Transaction distribution 3922system.toL2Bus.trans_dist::WritebackClean 3 # Transaction distribution 3923system.toL2Bus.trans_dist::CleanEvict 2880952 # Transaction distribution 3924system.toL2Bus.trans_dist::UpgradeReq 762470 # Transaction distribution 3925system.toL2Bus.trans_dist::SCUpgradeReq 404798 # Transaction distribution 3926system.toL2Bus.trans_dist::UpgradeResp 1167268 # Transaction distribution 3927system.toL2Bus.trans_dist::SCUpgradeFailReq 118 # Transaction distribution 3928system.toL2Bus.trans_dist::UpgradeFailResp 118 # Transaction distribution 3929system.toL2Bus.trans_dist::ReadExReq 311901 # Transaction distribution 3930system.toL2Bus.trans_dist::ReadExResp 311901 # Transaction distribution 3931system.toL2Bus.trans_dist::ReadSharedReq 4792157 # Transaction distribution 3932system.toL2Bus.trans_dist::InvalidateReq 968815 # Transaction distribution 3933system.toL2Bus.trans_dist::InvalidateResp 862087 # Transaction distribution 3934system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10699681 # Packet count per connected master and slave (bytes) 3935system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7828066 # Packet count per connected master and slave (bytes) 3936system.toL2Bus.pkt_count::total 18527747 # Packet count per connected master and slave (bytes) 3937system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 272166853 # Cumulative packet size per connected master and slave (bytes) 3938system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 192849765 # Cumulative packet size per connected master and slave (bytes) 3939system.toL2Bus.pkt_size::total 465016618 # Cumulative packet size per connected master and slave (bytes) 3940system.toL2Bus.snoops 3356905 # Total snoops (count) 3941system.toL2Bus.snoop_fanout::samples 9121086 # Request fanout histogram 3942system.toL2Bus.snoop_fanout::mean 0.343228 # Request fanout histogram 3943system.toL2Bus.snoop_fanout::stdev 0.478461 # Request fanout histogram 3944system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3945system.toL2Bus.snoop_fanout::0 6006442 65.85% 65.85% # Request fanout histogram 3946system.toL2Bus.snoop_fanout::1 3098672 33.97% 99.82% # Request fanout histogram 3947system.toL2Bus.snoop_fanout::2 15972 0.18% 100.00% # Request fanout histogram 3948system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3949system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3950system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3951system.toL2Bus.snoop_fanout::total 9121086 # Request fanout histogram 3952system.toL2Bus.reqLayer0.occupancy 9875342461 # Layer occupancy (ticks) 3953system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3954system.toL2Bus.snoopLayer0.occupancy 2628126 # Layer occupancy (ticks) 3955system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3956system.toL2Bus.respLayer0.occupancy 4863215068 # Layer occupancy (ticks) 3957system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3958system.toL2Bus.respLayer1.occupancy 3891669395 # Layer occupancy (ticks) 3959system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3960system.cpu0.kern.inst.arm 0 # number of arm instructions executed 3961system.cpu0.kern.inst.quiesce 5261 # number of quiesce instructions executed 3962system.cpu1.kern.inst.arm 0 # number of arm instructions executed 3963system.cpu1.kern.inst.quiesce 13576 # number of quiesce instructions executed 3964 3965---------- End Simulation Statistics ---------- 3966