stats.txt revision 11245:1c5102c0a7a9
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.393981 # Number of seconds simulated 4sim_ticks 47393980707000 # Number of ticks simulated 5final_tick 47393980707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 118826 # Simulator instruction rate (inst/s) 8host_op_rate 139727 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 6107626980 # Simulator tick rate (ticks/s) 10host_mem_usage 769604 # Number of bytes of host memory used 11host_seconds 7759.80 # Real time elapsed on the host 12sim_insts 922064003 # Number of instructions simulated 13sim_ops 1084251192 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 150400 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 142336 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 4326432 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 44486728 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 20365824 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 171008 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 152256 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 3129632 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 15575440 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 14887232 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 428800 # Number of bytes read from this memory 27system.physmem.bytes_read::total 103816088 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 4326432 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 3129632 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 7456064 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 86117376 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 34system.physmem.bytes_written::total 86137960 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 2350 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 2224 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 83553 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 695118 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 318216 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 2672 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 2379 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 48944 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 243379 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 232613 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 6700 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 1638148 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 1345584 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 50system.physmem.num_writes::total 1348158 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 3173 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 3003 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 91287 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 938658 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 429713 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 3608 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 3213 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 66034 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 328638 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 314117 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 9048 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 2190491 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 91287 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 66034 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 157321 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1817053 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::total 1817487 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1817053 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 3173 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 3003 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 91287 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 939092 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 429713 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 3608 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 3213 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 66034 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 328638 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 314117 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 9048 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 4007978 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 1638148 # Number of read requests accepted 84system.physmem.writeReqs 1348158 # Number of write requests accepted 85system.physmem.readBursts 1638148 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 1348158 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 104808896 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 32576 # Total number of bytes read from write queue 89system.physmem.bytesWritten 86137280 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 103816088 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 86137960 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 509 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 529318 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 98506 # Per bank write bursts 96system.physmem.perBankRdBursts::1 102125 # Per bank write bursts 97system.physmem.perBankRdBursts::2 96514 # Per bank write bursts 98system.physmem.perBankRdBursts::3 101212 # Per bank write bursts 99system.physmem.perBankRdBursts::4 98283 # Per bank write bursts 100system.physmem.perBankRdBursts::5 109978 # Per bank write bursts 101system.physmem.perBankRdBursts::6 106703 # Per bank write bursts 102system.physmem.perBankRdBursts::7 105175 # Per bank write bursts 103system.physmem.perBankRdBursts::8 93813 # Per bank write bursts 104system.physmem.perBankRdBursts::9 120186 # Per bank write bursts 105system.physmem.perBankRdBursts::10 99379 # Per bank write bursts 106system.physmem.perBankRdBursts::11 109206 # Per bank write bursts 107system.physmem.perBankRdBursts::12 97639 # Per bank write bursts 108system.physmem.perBankRdBursts::13 103304 # Per bank write bursts 109system.physmem.perBankRdBursts::14 94884 # Per bank write bursts 110system.physmem.perBankRdBursts::15 100732 # Per bank write bursts 111system.physmem.perBankWrBursts::0 82092 # Per bank write bursts 112system.physmem.perBankWrBursts::1 86582 # Per bank write bursts 113system.physmem.perBankWrBursts::2 80748 # Per bank write bursts 114system.physmem.perBankWrBursts::3 83407 # Per bank write bursts 115system.physmem.perBankWrBursts::4 81928 # Per bank write bursts 116system.physmem.perBankWrBursts::5 88947 # Per bank write bursts 117system.physmem.perBankWrBursts::6 86848 # Per bank write bursts 118system.physmem.perBankWrBursts::7 87370 # Per bank write bursts 119system.physmem.perBankWrBursts::8 79257 # Per bank write bursts 120system.physmem.perBankWrBursts::9 83439 # Per bank write bursts 121system.physmem.perBankWrBursts::10 82066 # Per bank write bursts 122system.physmem.perBankWrBursts::11 89206 # Per bank write bursts 123system.physmem.perBankWrBursts::12 82040 # Per bank write bursts 124system.physmem.perBankWrBursts::13 87648 # Per bank write bursts 125system.physmem.perBankWrBursts::14 80198 # Per bank write bursts 126system.physmem.perBankWrBursts::15 84119 # Per bank write bursts 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 128system.physmem.numWrRetry 13 # Number of times write queue was full causing retry 129system.physmem.totGap 47393979099500 # Total gap between requests 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 0 # Read request sizes (log2) 133system.physmem.readPktSize::3 25 # Read request sizes (log2) 134system.physmem.readPktSize::4 21333 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) 136system.physmem.readPktSize::6 1616790 # Read request sizes (log2) 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) 140system.physmem.writePktSize::3 2572 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) 143system.physmem.writePktSize::6 1345584 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 619728 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 417888 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 167778 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 159876 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 99605 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 61553 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 33210 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 30819 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 27167 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 7798 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 4294 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 2578 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 1594 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 1279 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 809 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 549 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 455 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 355 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 156 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 112 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 13 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 11 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 5 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 3 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 2 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::15 22060 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 24765 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 36742 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 44665 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 54132 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 62647 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 72218 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 78252 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 84742 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 88110 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 91290 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 97437 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 95426 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 99220 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 110773 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 98211 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 87853 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 81636 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 3839 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 2422 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 1595 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 1092 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 834 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 665 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 558 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 417 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 324 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 380 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 285 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 296 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 228 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 262 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 315 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 294 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 308 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 204 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 172 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 161 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 211 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 210 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 130 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 85 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 82 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 42 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 57 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 74 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 74 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 67 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 35 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 1054994 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 180.992301 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 111.466356 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 240.522304 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 655278 62.11% 62.11% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 195680 18.55% 80.66% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 62552 5.93% 86.59% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 34743 3.29% 89.88% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 24726 2.34% 92.23% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 13789 1.31% 93.53% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 13873 1.31% 94.85% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 7523 0.71% 95.56% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 46830 4.44% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 1054994 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 76193 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 21.493169 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 249.861284 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-4095 76190 100.00% 100.00% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::8192-12287 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::65536-69631 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::total 76193 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 76193 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 17.664287 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 17.191501 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 6.434084 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::16-19 70631 92.70% 92.70% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::20-23 3142 4.12% 96.82% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::24-27 485 0.64% 97.46% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::28-31 323 0.42% 97.88% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::32-35 79 0.10% 97.99% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::36-39 306 0.40% 98.39% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::40-43 178 0.23% 98.62% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::44-47 116 0.15% 98.78% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::48-51 95 0.12% 98.90% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::52-55 99 0.13% 99.03% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::56-59 41 0.05% 99.08% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::60-63 55 0.07% 99.16% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::64-67 407 0.53% 99.69% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::68-71 35 0.05% 99.74% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::72-75 33 0.04% 99.78% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::76-79 86 0.11% 99.89% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::80-83 20 0.03% 99.92% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::84-87 6 0.01% 99.93% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::88-91 2 0.00% 99.93% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::92-95 2 0.00% 99.93% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::96-99 3 0.00% 99.94% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::100-103 6 0.01% 99.94% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::124-127 1 0.00% 99.95% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::128-131 28 0.04% 99.98% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::140-143 1 0.00% 99.99% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::148-151 2 0.00% 99.99% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::152-155 2 0.00% 99.99% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::156-159 4 0.01% 100.00% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::160-163 1 0.00% 100.00% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::164-167 2 0.00% 100.00% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::total 76193 # Writes before turning the bus around for reads 299system.physmem.totQLat 70239099561 # Total ticks spent queuing 300system.physmem.totMemAccLat 100944830811 # Total ticks spent from burst creation until serviced by the DRAM 301system.physmem.totBusLat 8188195000 # Total ticks spent in databus transfers 302system.physmem.avgQLat 42890.47 # Average queueing delay per DRAM burst 303system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 304system.physmem.avgMemAccLat 61640.47 # Average memory access latency per DRAM burst 305system.physmem.avgRdBW 2.21 # Average DRAM read bandwidth in MiByte/s 306system.physmem.avgWrBW 1.82 # Average achieved write bandwidth in MiByte/s 307system.physmem.avgRdBWSys 2.19 # Average system read bandwidth in MiByte/s 308system.physmem.avgWrBWSys 1.82 # Average system write bandwidth in MiByte/s 309system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 310system.physmem.busUtil 0.03 # Data bus utilization in percentage 311system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 312system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 313system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing 314system.physmem.avgWrQLen 24.73 # Average write queue length when enqueuing 315system.physmem.readRowHits 1316973 # Number of row buffer hits during reads 316system.physmem.writeRowHits 611565 # Number of row buffer hits during writes 317system.physmem.readRowHitRate 80.42 # Row buffer hit rate for reads 318system.physmem.writeRowHitRate 45.44 # Row buffer hit rate for writes 319system.physmem.avgGap 15870436.28 # Average gap between requests 320system.physmem.pageHitRate 64.64 # Row buffer hit rate, read and write combined 321system.physmem_0.actEnergy 4035157560 # Energy for activate commands per rank (pJ) 322system.physmem_0.preEnergy 2201722875 # Energy for precharge commands per rank (pJ) 323system.physmem_0.readEnergy 6384222000 # Energy for read commands per rank (pJ) 324system.physmem_0.writeEnergy 4392934560 # Energy for write commands per rank (pJ) 325system.physmem_0.refreshEnergy 3095544201360 # Energy for refresh commands per rank (pJ) 326system.physmem_0.actBackEnergy 1182732038730 # Energy for active background per rank (pJ) 327system.physmem_0.preBackEnergy 27398902223250 # Energy for precharge background per rank (pJ) 328system.physmem_0.totalEnergy 31694192500335 # Total energy per rank (pJ) 329system.physmem_0.averagePower 668.738819 # Core power per rank (mW) 330system.physmem_0.memoryStateTime::IDLE 45580299815708 # Time in different power states 331system.physmem_0.memoryStateTime::REF 1582589060000 # Time in different power states 332system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 333system.physmem_0.memoryStateTime::ACT 231091139792 # Time in different power states 334system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 335system.physmem_1.actEnergy 3940597080 # Energy for activate commands per rank (pJ) 336system.physmem_1.preEnergy 2150127375 # Energy for precharge commands per rank (pJ) 337system.physmem_1.readEnergy 6389315400 # Energy for read commands per rank (pJ) 338system.physmem_1.writeEnergy 4328465040 # Energy for write commands per rank (pJ) 339system.physmem_1.refreshEnergy 3095544201360 # Energy for refresh commands per rank (pJ) 340system.physmem_1.actBackEnergy 1183329754695 # Energy for active background per rank (pJ) 341system.physmem_1.preBackEnergy 27398377902750 # Energy for precharge background per rank (pJ) 342system.physmem_1.totalEnergy 31694060363700 # Total energy per rank (pJ) 343system.physmem_1.averagePower 668.736031 # Core power per rank (mW) 344system.physmem_1.memoryStateTime::IDLE 45579400276584 # Time in different power states 345system.physmem_1.memoryStateTime::REF 1582589060000 # Time in different power states 346system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 347system.physmem_1.memoryStateTime::ACT 231988109666 # Time in different power states 348system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 349system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory 350system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 351system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory 352system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 353system.realview.nvmem.bytes_read::total 556 # Number of bytes read from this memory 354system.realview.nvmem.bytes_inst_read::cpu0.inst 368 # Number of instructions bytes read from this memory 355system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory 356system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory 357system.realview.nvmem.num_reads::cpu0.inst 23 # Number of read requests responded to by this memory 358system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 359system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory 360system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 361system.realview.nvmem.num_reads::total 38 # Number of read requests responded to by this memory 362system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) 363system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 364system.realview.nvmem.bw_read::cpu1.inst 3 # Total read bandwidth from this memory (bytes/s) 365system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 366system.realview.nvmem.bw_read::total 12 # Total read bandwidth from this memory (bytes/s) 367system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) 368system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s) 369system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s) 370system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) 371system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 372system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) 373system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 374system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) 375system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 376system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 377system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 378system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 379system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 380system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 381system.cpu0.branchPred.lookups 135522453 # Number of BP lookups 382system.cpu0.branchPred.condPredicted 89756354 # Number of conditional branches predicted 383system.cpu0.branchPred.condIncorrect 6696164 # Number of conditional branches incorrect 384system.cpu0.branchPred.BTBLookups 95487916 # Number of BTB lookups 385system.cpu0.branchPred.BTBHits 63232655 # Number of BTB hits 386system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 387system.cpu0.branchPred.BTBHitPct 66.220583 # BTB Hit Percentage 388system.cpu0.branchPred.usedRAS 18624977 # Number of times the RAS was used to get a target. 389system.cpu0.branchPred.RASInCorrect 201233 # Number of incorrect RAS predictions. 390system.cpu_clk_domain.clock 500 # Clock period in ticks 391system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 392system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 393system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 394system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 399system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 400system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 401system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 402system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 403system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 404system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 405system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 406system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 407system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 408system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 409system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 410system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 411system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 412system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 413system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 414system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 415system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 416system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 417system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 418system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 419system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 420system.cpu0.dtb.walker.walks 590400 # Table walker walks requested 421system.cpu0.dtb.walker.walksLong 590400 # Table walker walks initiated with long descriptors 422system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12973 # Level at which table walker walks with long descriptors terminate 423system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 94460 # Level at which table walker walks with long descriptors terminate 424system.cpu0.dtb.walker.walksSquashedBefore 278631 # Table walks squashed before starting 425system.cpu0.dtb.walker.walkWaitTime::samples 311769 # Table walker wait (enqueue to first request) latency 426system.cpu0.dtb.walker.walkWaitTime::mean 2427.181663 # Table walker wait (enqueue to first request) latency 427system.cpu0.dtb.walker.walkWaitTime::stdev 14785.327659 # Table walker wait (enqueue to first request) latency 428system.cpu0.dtb.walker.walkWaitTime::0-65535 309280 99.20% 99.20% # Table walker wait (enqueue to first request) latency 429system.cpu0.dtb.walker.walkWaitTime::65536-131071 1331 0.43% 99.63% # Table walker wait (enqueue to first request) latency 430system.cpu0.dtb.walker.walkWaitTime::131072-196607 885 0.28% 99.91% # Table walker wait (enqueue to first request) latency 431system.cpu0.dtb.walker.walkWaitTime::196608-262143 124 0.04% 99.95% # Table walker wait (enqueue to first request) latency 432system.cpu0.dtb.walker.walkWaitTime::262144-327679 48 0.02% 99.97% # Table walker wait (enqueue to first request) latency 433system.cpu0.dtb.walker.walkWaitTime::327680-393215 73 0.02% 99.99% # Table walker wait (enqueue to first request) latency 434system.cpu0.dtb.walker.walkWaitTime::393216-458751 22 0.01% 100.00% # Table walker wait (enqueue to first request) latency 435system.cpu0.dtb.walker.walkWaitTime::458752-524287 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency 436system.cpu0.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 437system.cpu0.dtb.walker.walkWaitTime::total 311769 # Table walker wait (enqueue to first request) latency 438system.cpu0.dtb.walker.walkCompletionTime::samples 310891 # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walkCompletionTime::mean 20766.069137 # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walkCompletionTime::gmean 17798.694444 # Table walker service (enqueue to completion) latency 441system.cpu0.dtb.walker.walkCompletionTime::stdev 20375.668326 # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walkCompletionTime::0-65535 307651 98.96% 98.96% # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::65536-131071 747 0.24% 99.20% # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::131072-196607 1834 0.59% 99.79% # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walkCompletionTime::196608-262143 107 0.03% 99.82% # Table walker service (enqueue to completion) latency 446system.cpu0.dtb.walker.walkCompletionTime::262144-327679 307 0.10% 99.92% # Table walker service (enqueue to completion) latency 447system.cpu0.dtb.walker.walkCompletionTime::327680-393215 102 0.03% 99.95% # Table walker service (enqueue to completion) latency 448system.cpu0.dtb.walker.walkCompletionTime::393216-458751 75 0.02% 99.98% # Table walker service (enqueue to completion) latency 449system.cpu0.dtb.walker.walkCompletionTime::458752-524287 36 0.01% 99.99% # Table walker service (enqueue to completion) latency 450system.cpu0.dtb.walker.walkCompletionTime::524288-589823 21 0.01% 100.00% # Table walker service (enqueue to completion) latency 451system.cpu0.dtb.walker.walkCompletionTime::589824-655359 7 0.00% 100.00% # Table walker service (enqueue to completion) latency 452system.cpu0.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 453system.cpu0.dtb.walker.walkCompletionTime::total 310891 # Table walker service (enqueue to completion) latency 454system.cpu0.dtb.walker.walksPending::samples 523001837252 # Table walker pending requests distribution 455system.cpu0.dtb.walker.walksPending::mean 0.567345 # Table walker pending requests distribution 456system.cpu0.dtb.walker.walksPending::stdev 0.551290 # Table walker pending requests distribution 457system.cpu0.dtb.walker.walksPending::0-1 521647732752 99.74% 99.74% # Table walker pending requests distribution 458system.cpu0.dtb.walker.walksPending::2-3 761373500 0.15% 99.89% # Table walker pending requests distribution 459system.cpu0.dtb.walker.walksPending::4-5 275460500 0.05% 99.94% # Table walker pending requests distribution 460system.cpu0.dtb.walker.walksPending::6-7 125915000 0.02% 99.96% # Table walker pending requests distribution 461system.cpu0.dtb.walker.walksPending::8-9 99351000 0.02% 99.98% # Table walker pending requests distribution 462system.cpu0.dtb.walker.walksPending::10-11 52861000 0.01% 99.99% # Table walker pending requests distribution 463system.cpu0.dtb.walker.walksPending::12-13 16652500 0.00% 100.00% # Table walker pending requests distribution 464system.cpu0.dtb.walker.walksPending::14-15 21714500 0.00% 100.00% # Table walker pending requests distribution 465system.cpu0.dtb.walker.walksPending::16-17 741500 0.00% 100.00% # Table walker pending requests distribution 466system.cpu0.dtb.walker.walksPending::18-19 35000 0.00% 100.00% # Table walker pending requests distribution 467system.cpu0.dtb.walker.walksPending::total 523001837252 # Table walker pending requests distribution 468system.cpu0.dtb.walker.walkPageSizes::4K 94460 87.92% 87.92% # Table walker page sizes translated 469system.cpu0.dtb.walker.walkPageSizes::2M 12973 12.08% 100.00% # Table walker page sizes translated 470system.cpu0.dtb.walker.walkPageSizes::total 107433 # Table walker page sizes translated 471system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 590400 # Table walker requests started/completed, data/inst 472system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 473system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 590400 # Table walker requests started/completed, data/inst 474system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107433 # Table walker requests started/completed, data/inst 475system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 476system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107433 # Table walker requests started/completed, data/inst 477system.cpu0.dtb.walker.walkRequestOrigin::total 697833 # Table walker requests started/completed, data/inst 478system.cpu0.dtb.inst_hits 0 # ITB inst hits 479system.cpu0.dtb.inst_misses 0 # ITB inst misses 480system.cpu0.dtb.read_hits 98363253 # DTB read hits 481system.cpu0.dtb.read_misses 426453 # DTB read misses 482system.cpu0.dtb.write_hits 80524387 # DTB write hits 483system.cpu0.dtb.write_misses 163947 # DTB write misses 484system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 485system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 486system.cpu0.dtb.flush_tlb_mva_asid 44673 # Number of times TLB was flushed by MVA & ASID 487system.cpu0.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID 488system.cpu0.dtb.flush_entries 40807 # Number of entries that have been flushed from TLB 489system.cpu0.dtb.align_faults 204 # Number of TLB faults due to alignment restrictions 490system.cpu0.dtb.prefetch_faults 7493 # Number of TLB faults due to prefetch 491system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 492system.cpu0.dtb.perms_faults 42725 # Number of TLB faults due to permissions restrictions 493system.cpu0.dtb.read_accesses 98789706 # DTB read accesses 494system.cpu0.dtb.write_accesses 80688334 # DTB write accesses 495system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 496system.cpu0.dtb.hits 178887640 # DTB hits 497system.cpu0.dtb.misses 590400 # DTB misses 498system.cpu0.dtb.accesses 179478040 # DTB accesses 499system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 500system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 501system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 502system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 503system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 504system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 505system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 506system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 507system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 508system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 509system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 510system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 511system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 512system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 513system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 514system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 515system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 516system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 517system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 518system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 519system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 520system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 521system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 522system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 523system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 524system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 525system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 526system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 527system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 528system.cpu0.itb.walker.walks 85262 # Table walker walks requested 529system.cpu0.itb.walker.walksLong 85262 # Table walker walks initiated with long descriptors 530system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1098 # Level at which table walker walks with long descriptors terminate 531system.cpu0.itb.walker.walksLongTerminationLevel::Level3 61891 # Level at which table walker walks with long descriptors terminate 532system.cpu0.itb.walker.walksSquashedBefore 9791 # Table walks squashed before starting 533system.cpu0.itb.walker.walkWaitTime::samples 75471 # Table walker wait (enqueue to first request) latency 534system.cpu0.itb.walker.walkWaitTime::mean 1466.000186 # Table walker wait (enqueue to first request) latency 535system.cpu0.itb.walker.walkWaitTime::stdev 11351.229924 # Table walker wait (enqueue to first request) latency 536system.cpu0.itb.walker.walkWaitTime::0-65535 75137 99.56% 99.56% # Table walker wait (enqueue to first request) latency 537system.cpu0.itb.walker.walkWaitTime::65536-131071 79 0.10% 99.66% # Table walker wait (enqueue to first request) latency 538system.cpu0.itb.walker.walkWaitTime::131072-196607 235 0.31% 99.97% # Table walker wait (enqueue to first request) latency 539system.cpu0.itb.walker.walkWaitTime::196608-262143 9 0.01% 99.99% # Table walker wait (enqueue to first request) latency 540system.cpu0.itb.walker.walkWaitTime::262144-327679 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency 541system.cpu0.itb.walker.walkWaitTime::327680-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 542system.cpu0.itb.walker.walkWaitTime::393216-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 543system.cpu0.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 544system.cpu0.itb.walker.walkWaitTime::total 75471 # Table walker wait (enqueue to first request) latency 545system.cpu0.itb.walker.walkCompletionTime::samples 72780 # Table walker service (enqueue to completion) latency 546system.cpu0.itb.walker.walkCompletionTime::mean 26660.353119 # Table walker service (enqueue to completion) latency 547system.cpu0.itb.walker.walkCompletionTime::gmean 23025.074927 # Table walker service (enqueue to completion) latency 548system.cpu0.itb.walker.walkCompletionTime::stdev 26139.582838 # Table walker service (enqueue to completion) latency 549system.cpu0.itb.walker.walkCompletionTime::0-65535 71045 97.62% 97.62% # Table walker service (enqueue to completion) latency 550system.cpu0.itb.walker.walkCompletionTime::65536-131071 123 0.17% 97.79% # Table walker service (enqueue to completion) latency 551system.cpu0.itb.walker.walkCompletionTime::131072-196607 1365 1.88% 99.66% # Table walker service (enqueue to completion) latency 552system.cpu0.itb.walker.walkCompletionTime::196608-262143 91 0.13% 99.79% # Table walker service (enqueue to completion) latency 553system.cpu0.itb.walker.walkCompletionTime::262144-327679 88 0.12% 99.91% # Table walker service (enqueue to completion) latency 554system.cpu0.itb.walker.walkCompletionTime::327680-393215 30 0.04% 99.95% # Table walker service (enqueue to completion) latency 555system.cpu0.itb.walker.walkCompletionTime::393216-458751 31 0.04% 99.99% # Table walker service (enqueue to completion) latency 556system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 557system.cpu0.itb.walker.walkCompletionTime::524288-589823 4 0.01% 100.00% # Table walker service (enqueue to completion) latency 558system.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 559system.cpu0.itb.walker.walkCompletionTime::total 72780 # Table walker service (enqueue to completion) latency 560system.cpu0.itb.walker.walksPending::samples 389854695076 # Table walker pending requests distribution 561system.cpu0.itb.walker.walksPending::mean 0.839132 # Table walker pending requests distribution 562system.cpu0.itb.walker.walksPending::stdev 0.367626 # Table walker pending requests distribution 563system.cpu0.itb.walker.walksPending::0 62743884640 16.09% 16.09% # Table walker pending requests distribution 564system.cpu0.itb.walker.walksPending::1 327084697936 83.90% 99.99% # Table walker pending requests distribution 565system.cpu0.itb.walker.walksPending::2 23698000 0.01% 100.00% # Table walker pending requests distribution 566system.cpu0.itb.walker.walksPending::3 2390500 0.00% 100.00% # Table walker pending requests distribution 567system.cpu0.itb.walker.walksPending::4 24000 0.00% 100.00% # Table walker pending requests distribution 568system.cpu0.itb.walker.walksPending::total 389854695076 # Table walker pending requests distribution 569system.cpu0.itb.walker.walkPageSizes::4K 61891 98.26% 98.26% # Table walker page sizes translated 570system.cpu0.itb.walker.walkPageSizes::2M 1098 1.74% 100.00% # Table walker page sizes translated 571system.cpu0.itb.walker.walkPageSizes::total 62989 # Table walker page sizes translated 572system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 573system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 85262 # Table walker requests started/completed, data/inst 574system.cpu0.itb.walker.walkRequestOrigin_Requested::total 85262 # Table walker requests started/completed, data/inst 575system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 576system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 62989 # Table walker requests started/completed, data/inst 577system.cpu0.itb.walker.walkRequestOrigin_Completed::total 62989 # Table walker requests started/completed, data/inst 578system.cpu0.itb.walker.walkRequestOrigin::total 148251 # Table walker requests started/completed, data/inst 579system.cpu0.itb.inst_hits 213975614 # ITB inst hits 580system.cpu0.itb.inst_misses 85262 # ITB inst misses 581system.cpu0.itb.read_hits 0 # DTB read hits 582system.cpu0.itb.read_misses 0 # DTB read misses 583system.cpu0.itb.write_hits 0 # DTB write hits 584system.cpu0.itb.write_misses 0 # DTB write misses 585system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 586system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 587system.cpu0.itb.flush_tlb_mva_asid 44673 # Number of times TLB was flushed by MVA & ASID 588system.cpu0.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID 589system.cpu0.itb.flush_entries 29309 # Number of entries that have been flushed from TLB 590system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 591system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 592system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 593system.cpu0.itb.perms_faults 214464 # Number of TLB faults due to permissions restrictions 594system.cpu0.itb.read_accesses 0 # DTB read accesses 595system.cpu0.itb.write_accesses 0 # DTB write accesses 596system.cpu0.itb.inst_accesses 214060876 # ITB inst accesses 597system.cpu0.itb.hits 213975614 # DTB hits 598system.cpu0.itb.misses 85262 # DTB misses 599system.cpu0.itb.accesses 214060876 # DTB accesses 600system.cpu0.numCycles 807659312 # number of cpu cycles simulated 601system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 602system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 603system.cpu0.fetch.icacheStallCycles 88233839 # Number of cycles fetch is stalled on an Icache miss 604system.cpu0.fetch.Insts 599476727 # Number of instructions fetch has processed 605system.cpu0.fetch.Branches 135522453 # Number of branches that fetch encountered 606system.cpu0.fetch.predictedBranches 81857632 # Number of branches that fetch has predicted taken 607system.cpu0.fetch.Cycles 670713114 # Number of cycles fetch has run and was not squashing or blocked 608system.cpu0.fetch.SquashCycles 14447630 # Number of cycles fetch has spent squashing 609system.cpu0.fetch.TlbCycles 2036483 # Number of cycles fetch has spent waiting for tlb 610system.cpu0.fetch.MiscStallCycles 334818 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 611system.cpu0.fetch.PendingTrapStallCycles 6261942 # Number of stall cycles due to pending traps 612system.cpu0.fetch.PendingQuiesceStallCycles 813783 # Number of stall cycles due to pending quiesce instructions 613system.cpu0.fetch.IcacheWaitRetryStallCycles 863786 # Number of stall cycles due to full MSHR 614system.cpu0.fetch.CacheLines 213760838 # Number of cache lines fetched 615system.cpu0.fetch.IcacheSquashes 1698349 # Number of outstanding Icache misses that were squashed 616system.cpu0.fetch.ItlbSquashes 28412 # Number of outstanding ITLB misses that were squashed 617system.cpu0.fetch.rateDist::samples 776481580 # Number of instructions fetched each cycle (Total) 618system.cpu0.fetch.rateDist::mean 0.903685 # Number of instructions fetched each cycle (Total) 619system.cpu0.fetch.rateDist::stdev 1.199979 # Number of instructions fetched each cycle (Total) 620system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 621system.cpu0.fetch.rateDist::0 440207018 56.69% 56.69% # Number of instructions fetched each cycle (Total) 622system.cpu0.fetch.rateDist::1 130689201 16.83% 73.52% # Number of instructions fetched each cycle (Total) 623system.cpu0.fetch.rateDist::2 45750499 5.89% 79.42% # Number of instructions fetched each cycle (Total) 624system.cpu0.fetch.rateDist::3 159834862 20.58% 100.00% # Number of instructions fetched each cycle (Total) 625system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 626system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 627system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 628system.cpu0.fetch.rateDist::total 776481580 # Number of instructions fetched each cycle (Total) 629system.cpu0.fetch.branchRate 0.167797 # Number of branch fetches per cycle 630system.cpu0.fetch.rate 0.742240 # Number of inst fetches per cycle 631system.cpu0.decode.IdleCycles 105533428 # Number of cycles decode is idle 632system.cpu0.decode.BlockedCycles 405339788 # Number of cycles decode is blocked 633system.cpu0.decode.RunCycles 223093644 # Number of cycles decode is running 634system.cpu0.decode.UnblockCycles 37388098 # Number of cycles decode is unblocking 635system.cpu0.decode.SquashCycles 5126622 # Number of cycles decode is squashing 636system.cpu0.decode.BranchResolved 19615970 # Number of times decode resolved a branch 637system.cpu0.decode.BranchMispred 2136984 # Number of times decode detected a branch misprediction 638system.cpu0.decode.DecodedInsts 619581339 # Number of instructions handled by decode 639system.cpu0.decode.SquashedInsts 23102207 # Number of squashed instructions handled by decode 640system.cpu0.rename.SquashCycles 5126622 # Number of cycles rename is squashing 641system.cpu0.rename.IdleCycles 140592491 # Number of cycles rename is idle 642system.cpu0.rename.BlockCycles 65041706 # Number of cycles rename is blocking 643system.cpu0.rename.serializeStallCycles 253704898 # count of cycles rename stalled for serializing inst 644system.cpu0.rename.RunCycles 224831888 # Number of cycles rename is running 645system.cpu0.rename.UnblockCycles 87183975 # Number of cycles rename is unblocking 646system.cpu0.rename.RenamedInsts 602582059 # Number of instructions processed by rename 647system.cpu0.rename.SquashedInsts 5894427 # Number of squashed instructions processed by rename 648system.cpu0.rename.ROBFullEvents 10859505 # Number of times rename has blocked due to ROB full 649system.cpu0.rename.IQFullEvents 384608 # Number of times rename has blocked due to IQ full 650system.cpu0.rename.LQFullEvents 879717 # Number of times rename has blocked due to LQ full 651system.cpu0.rename.SQFullEvents 52095352 # Number of times rename has blocked due to SQ full 652system.cpu0.rename.FullRegisterEvents 10977 # Number of times there has been no free registers 653system.cpu0.rename.RenamedOperands 576174683 # Number of destination operands rename has renamed 654system.cpu0.rename.RenameLookups 933371731 # Number of register rename lookups that rename has made 655system.cpu0.rename.int_rename_lookups 711261087 # Number of integer rename lookups 656system.cpu0.rename.fp_rename_lookups 684793 # Number of floating rename lookups 657system.cpu0.rename.CommittedMaps 519247735 # Number of HB maps that are committed 658system.cpu0.rename.UndoneMaps 56926942 # Number of HB maps that are undone due to squashing 659system.cpu0.rename.serializingInsts 15518812 # count of serializing insts renamed 660system.cpu0.rename.tempSerializingInsts 13493208 # count of temporary serializing insts renamed 661system.cpu0.rename.skidInsts 75428854 # count of insts added to the skid buffer 662system.cpu0.memDep0.insertedLoads 98376014 # Number of loads inserted to the mem dependence unit. 663system.cpu0.memDep0.insertedStores 83834868 # Number of stores inserted to the mem dependence unit. 664system.cpu0.memDep0.conflictingLoads 8883598 # Number of conflicting loads. 665system.cpu0.memDep0.conflictingStores 7640207 # Number of conflicting stores. 666system.cpu0.iq.iqInstsAdded 580665271 # Number of instructions added to the IQ (excludes non-spec) 667system.cpu0.iq.iqNonSpecInstsAdded 15522553 # Number of non-speculative instructions added to the IQ 668system.cpu0.iq.iqInstsIssued 585221400 # Number of instructions issued 669system.cpu0.iq.iqSquashedInstsIssued 2674583 # Number of squashed instructions issued 670system.cpu0.iq.iqSquashedInstsExamined 53398017 # Number of squashed instructions iterated over during squash; mainly for profiling 671system.cpu0.iq.iqSquashedOperandsExamined 34936380 # Number of squashed operands that are examined and possibly removed from graph 672system.cpu0.iq.iqSquashedNonSpecRemoved 261009 # Number of squashed non-spec instructions that were removed 673system.cpu0.iq.issued_per_cycle::samples 776481580 # Number of insts issued each cycle 674system.cpu0.iq.issued_per_cycle::mean 0.753684 # Number of insts issued each cycle 675system.cpu0.iq.issued_per_cycle::stdev 1.045500 # Number of insts issued each cycle 676system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 677system.cpu0.iq.issued_per_cycle::0 456332573 58.77% 58.77% # Number of insts issued each cycle 678system.cpu0.iq.issued_per_cycle::1 134692381 17.35% 76.12% # Number of insts issued each cycle 679system.cpu0.iq.issued_per_cycle::2 113447710 14.61% 90.73% # Number of insts issued each cycle 680system.cpu0.iq.issued_per_cycle::3 64406978 8.29% 99.02% # Number of insts issued each cycle 681system.cpu0.iq.issued_per_cycle::4 7597025 0.98% 100.00% # Number of insts issued each cycle 682system.cpu0.iq.issued_per_cycle::5 4913 0.00% 100.00% # Number of insts issued each cycle 683system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 684system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 685system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 686system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 687system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 688system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 689system.cpu0.iq.issued_per_cycle::total 776481580 # Number of insts issued each cycle 690system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 691system.cpu0.iq.fu_full::IntAlu 60244006 45.44% 45.44% # attempts to use FU when none available 692system.cpu0.iq.fu_full::IntMult 62130 0.05% 45.49% # attempts to use FU when none available 693system.cpu0.iq.fu_full::IntDiv 15273 0.01% 45.50% # attempts to use FU when none available 694system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.50% # attempts to use FU when none available 695system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.50% # attempts to use FU when none available 696system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.50% # attempts to use FU when none available 697system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.50% # attempts to use FU when none available 698system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.50% # attempts to use FU when none available 699system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.50% # attempts to use FU when none available 700system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.50% # attempts to use FU when none available 701system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.50% # attempts to use FU when none available 702system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.50% # attempts to use FU when none available 703system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.50% # attempts to use FU when none available 704system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.50% # attempts to use FU when none available 705system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.50% # attempts to use FU when none available 706system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.50% # attempts to use FU when none available 707system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.50% # attempts to use FU when none available 708system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.50% # attempts to use FU when none available 709system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.50% # attempts to use FU when none available 710system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.50% # attempts to use FU when none available 711system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.50% # attempts to use FU when none available 712system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.50% # attempts to use FU when none available 713system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.50% # attempts to use FU when none available 714system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.50% # attempts to use FU when none available 715system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.50% # attempts to use FU when none available 716system.cpu0.iq.fu_full::SimdFloatMisc 15 0.00% 45.50% # attempts to use FU when none available 717system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.50% # attempts to use FU when none available 718system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.50% # attempts to use FU when none available 719system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.50% # attempts to use FU when none available 720system.cpu0.iq.fu_full::MemRead 34917494 26.34% 71.84% # attempts to use FU when none available 721system.cpu0.iq.fu_full::MemWrite 37330795 28.16% 100.00% # attempts to use FU when none available 722system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 723system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 724system.cpu0.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued 725system.cpu0.iq.FU_type_0::IntAlu 400469737 68.43% 68.43% # Type of FU issued 726system.cpu0.iq.FU_type_0::IntMult 1445270 0.25% 68.68% # Type of FU issued 727system.cpu0.iq.FU_type_0::IntDiv 74848 0.01% 68.69% # Type of FU issued 728system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.69% # Type of FU issued 729system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.69% # Type of FU issued 730system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.69% # Type of FU issued 731system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.69% # Type of FU issued 732system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.69% # Type of FU issued 733system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.69% # Type of FU issued 734system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.69% # Type of FU issued 735system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.69% # Type of FU issued 736system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.69% # Type of FU issued 737system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.69% # Type of FU issued 738system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.69% # Type of FU issued 739system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.69% # Type of FU issued 740system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.69% # Type of FU issued 741system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.69% # Type of FU issued 742system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.69% # Type of FU issued 743system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.69% # Type of FU issued 744system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.69% # Type of FU issued 745system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.69% # Type of FU issued 746system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.69% # Type of FU issued 747system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.69% # Type of FU issued 748system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.69% # Type of FU issued 749system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.69% # Type of FU issued 750system.cpu0.iq.FU_type_0::SimdFloatMisc 41036 0.01% 68.70% # Type of FU issued 751system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.70% # Type of FU issued 752system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.70% # Type of FU issued 753system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.70% # Type of FU issued 754system.cpu0.iq.FU_type_0::MemRead 101401840 17.33% 86.02% # Type of FU issued 755system.cpu0.iq.FU_type_0::MemWrite 81788668 13.98% 100.00% # Type of FU issued 756system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 757system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 758system.cpu0.iq.FU_type_0::total 585221400 # Type of FU issued 759system.cpu0.iq.rate 0.724589 # Inst issue rate 760system.cpu0.iq.fu_busy_cnt 132569713 # FU busy when requested 761system.cpu0.iq.fu_busy_rate 0.226529 # FU busy rate (busy events/executed inst) 762system.cpu0.iq.int_inst_queue_reads 2081071755 # Number of integer instruction queue reads 763system.cpu0.iq.int_inst_queue_writes 649281804 # Number of integer instruction queue writes 764system.cpu0.iq.int_inst_queue_wakeup_accesses 568296572 # Number of integer instruction queue wakeup accesses 765system.cpu0.iq.fp_inst_queue_reads 1096919 # Number of floating instruction queue reads 766system.cpu0.iq.fp_inst_queue_writes 437057 # Number of floating instruction queue writes 767system.cpu0.iq.fp_inst_queue_wakeup_accesses 404655 # Number of floating instruction queue wakeup accesses 768system.cpu0.iq.int_alu_accesses 717109128 # Number of integer alu accesses 769system.cpu0.iq.fp_alu_accesses 681984 # Number of floating point alu accesses 770system.cpu0.iew.lsq.thread0.forwLoads 2687978 # Number of loads that had data forwarded from stores 771system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 772system.cpu0.iew.lsq.thread0.squashedLoads 12198109 # Number of loads squashed 773system.cpu0.iew.lsq.thread0.ignoredResponses 15815 # Number of memory responses ignored because the instruction is squashed 774system.cpu0.iew.lsq.thread0.memOrderViolation 133954 # Number of memory ordering violations 775system.cpu0.iew.lsq.thread0.squashedStores 5685458 # Number of stores squashed 776system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 777system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 778system.cpu0.iew.lsq.thread0.rescheduledLoads 2533664 # Number of loads that were rescheduled 779system.cpu0.iew.lsq.thread0.cacheBlocked 4860713 # Number of times an access to memory failed due to the cache being blocked 780system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 781system.cpu0.iew.iewSquashCycles 5126622 # Number of cycles IEW is squashing 782system.cpu0.iew.iewBlockCycles 8215667 # Number of cycles IEW is blocking 783system.cpu0.iew.iewUnblockCycles 7173428 # Number of cycles IEW is unblocking 784system.cpu0.iew.iewDispatchedInsts 596307716 # Number of instructions dispatched to IQ 785system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 786system.cpu0.iew.iewDispLoadInsts 98376014 # Number of dispatched load instructions 787system.cpu0.iew.iewDispStoreInsts 83834868 # Number of dispatched store instructions 788system.cpu0.iew.iewDispNonSpecInsts 13216543 # Number of dispatched non-speculative instructions 789system.cpu0.iew.iewIQFullEvents 57072 # Number of times the IQ has become full, causing a stall 790system.cpu0.iew.iewLSQFullEvents 7044703 # Number of times the LSQ has become full, causing a stall 791system.cpu0.iew.memOrderViolationEvents 133954 # Number of memory order violations 792system.cpu0.iew.predictedTakenIncorrect 2031236 # Number of branches that were predicted taken incorrectly 793system.cpu0.iew.predictedNotTakenIncorrect 2866413 # Number of branches that were predicted not taken incorrectly 794system.cpu0.iew.branchMispredicts 4897649 # Number of branch mispredicts detected at execute 795system.cpu0.iew.iewExecutedInsts 577519741 # Number of executed instructions 796system.cpu0.iew.iewExecLoadInsts 98358575 # Number of load instructions executed 797system.cpu0.iew.iewExecSquashedInsts 7118543 # Number of squashed instructions skipped in execute 798system.cpu0.iew.exec_swp 0 # number of swp insts executed 799system.cpu0.iew.exec_nop 119892 # number of nop insts executed 800system.cpu0.iew.exec_refs 178881734 # number of memory reference insts executed 801system.cpu0.iew.exec_branches 109041178 # Number of branches executed 802system.cpu0.iew.exec_stores 80523159 # Number of stores executed 803system.cpu0.iew.exec_rate 0.715054 # Inst execution rate 804system.cpu0.iew.wb_sent 569480217 # cumulative count of insts sent to commit 805system.cpu0.iew.wb_count 568701227 # cumulative count of insts written-back 806system.cpu0.iew.wb_producers 276442254 # num instructions producing a value 807system.cpu0.iew.wb_consumers 453748356 # num instructions consuming a value 808system.cpu0.iew.wb_rate 0.704135 # insts written-back per cycle 809system.cpu0.iew.wb_fanout 0.609241 # average fanout of values written-back 810system.cpu0.commit.commitSquashedInsts 46598328 # The number of squashed insts skipped by commit 811system.cpu0.commit.commitNonSpecStalls 15261544 # The number of times commit has been forced to stall to communicate backwards 812system.cpu0.commit.branchMispredicts 4598971 # The number of times a branch was mispredicted 813system.cpu0.commit.committed_per_cycle::samples 767596191 # Number of insts commited each cycle 814system.cpu0.commit.committed_per_cycle::mean 0.707129 # Number of insts commited each cycle 815system.cpu0.commit.committed_per_cycle::stdev 1.516118 # Number of insts commited each cycle 816system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 817system.cpu0.commit.committed_per_cycle::0 529386438 68.97% 68.97% # Number of insts commited each cycle 818system.cpu0.commit.committed_per_cycle::1 123369518 16.07% 85.04% # Number of insts commited each cycle 819system.cpu0.commit.committed_per_cycle::2 53181556 6.93% 91.97% # Number of insts commited each cycle 820system.cpu0.commit.committed_per_cycle::3 17664925 2.30% 94.27% # Number of insts commited each cycle 821system.cpu0.commit.committed_per_cycle::4 12675398 1.65% 95.92% # Number of insts commited each cycle 822system.cpu0.commit.committed_per_cycle::5 8710511 1.13% 97.05% # Number of insts commited each cycle 823system.cpu0.commit.committed_per_cycle::6 5748655 0.75% 97.80% # Number of insts commited each cycle 824system.cpu0.commit.committed_per_cycle::7 3557202 0.46% 98.27% # Number of insts commited each cycle 825system.cpu0.commit.committed_per_cycle::8 13301988 1.73% 100.00% # Number of insts commited each cycle 826system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 827system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 828system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 829system.cpu0.commit.committed_per_cycle::total 767596191 # Number of insts commited each cycle 830system.cpu0.commit.committedInsts 462839739 # Number of instructions committed 831system.cpu0.commit.committedOps 542789800 # Number of ops (including micro ops) committed 832system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 833system.cpu0.commit.refs 164327314 # Number of memory references committed 834system.cpu0.commit.loads 86177904 # Number of loads committed 835system.cpu0.commit.membars 3634236 # Number of memory barriers committed 836system.cpu0.commit.branches 103555612 # Number of branches committed 837system.cpu0.commit.fp_insts 396011 # Number of committed floating point instructions. 838system.cpu0.commit.int_insts 497579695 # Number of committed integer instructions. 839system.cpu0.commit.function_calls 13818381 # Number of function calls committed. 840system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 841system.cpu0.commit.op_class_0::IntAlu 377157891 69.49% 69.49% # Class of committed instruction 842system.cpu0.commit.op_class_0::IntMult 1210852 0.22% 69.71% # Class of committed instruction 843system.cpu0.commit.op_class_0::IntDiv 58620 0.01% 69.72% # Class of committed instruction 844system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.72% # Class of committed instruction 845system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.72% # Class of committed instruction 846system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.72% # Class of committed instruction 847system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.72% # Class of committed instruction 848system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.72% # Class of committed instruction 849system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.72% # Class of committed instruction 850system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.72% # Class of committed instruction 851system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.72% # Class of committed instruction 852system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.72% # Class of committed instruction 853system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.72% # Class of committed instruction 854system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.72% # Class of committed instruction 855system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.72% # Class of committed instruction 856system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.72% # Class of committed instruction 857system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.72% # Class of committed instruction 858system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.72% # Class of committed instruction 859system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.72% # Class of committed instruction 860system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.72% # Class of committed instruction 861system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.72% # Class of committed instruction 862system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.72% # Class of committed instruction 863system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.72% # Class of committed instruction 864system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.72% # Class of committed instruction 865system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.72% # Class of committed instruction 866system.cpu0.commit.op_class_0::SimdFloatMisc 35123 0.01% 69.73% # Class of committed instruction 867system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.73% # Class of committed instruction 868system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.73% # Class of committed instruction 869system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.73% # Class of committed instruction 870system.cpu0.commit.op_class_0::MemRead 86177904 15.88% 85.60% # Class of committed instruction 871system.cpu0.commit.op_class_0::MemWrite 78149410 14.40% 100.00% # Class of committed instruction 872system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 873system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 874system.cpu0.commit.op_class_0::total 542789800 # Class of committed instruction 875system.cpu0.commit.bw_lim_events 13301988 # number cycles where commit BW limit reached 876system.cpu0.rob.rob_reads 1339296609 # The number of ROB reads 877system.cpu0.rob.rob_writes 1187626415 # The number of ROB writes 878system.cpu0.timesIdled 1008617 # Number of times that the entire CPU went into an idle state and unscheduled itself 879system.cpu0.idleCycles 31177732 # Total number of cycles that the CPU has spent unscheduled due to idling 880system.cpu0.quiesceCycles 93980302134 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 881system.cpu0.committedInsts 462839739 # Number of Instructions Simulated 882system.cpu0.committedOps 542789800 # Number of Ops (including micro ops) Simulated 883system.cpu0.cpi 1.745009 # CPI: Cycles Per Instruction 884system.cpu0.cpi_total 1.745009 # CPI: Total CPI of All Threads 885system.cpu0.ipc 0.573063 # IPC: Instructions Per Cycle 886system.cpu0.ipc_total 0.573063 # IPC: Total IPC of All Threads 887system.cpu0.int_regfile_reads 681400785 # number of integer regfile reads 888system.cpu0.int_regfile_writes 404691660 # number of integer regfile writes 889system.cpu0.fp_regfile_reads 669454 # number of floating regfile reads 890system.cpu0.fp_regfile_writes 305508 # number of floating regfile writes 891system.cpu0.cc_regfile_reads 127155216 # number of cc regfile reads 892system.cpu0.cc_regfile_writes 127713312 # number of cc regfile writes 893system.cpu0.misc_regfile_reads 1347757085 # number of misc regfile reads 894system.cpu0.misc_regfile_writes 15341922 # number of misc regfile writes 895system.cpu0.dcache.tags.replacements 6037671 # number of replacements 896system.cpu0.dcache.tags.tagsinuse 477.387062 # Cycle average of tags in use 897system.cpu0.dcache.tags.total_refs 152039806 # Total number of references to valid blocks. 898system.cpu0.dcache.tags.sampled_refs 6038183 # Sample count of references to valid blocks. 899system.cpu0.dcache.tags.avg_refs 25.179728 # Average number of references to valid blocks. 900system.cpu0.dcache.tags.warmup_cycle 2962390000 # Cycle when the warmup percentage was hit. 901system.cpu0.dcache.tags.occ_blocks::cpu0.data 477.387062 # Average occupied blocks per requestor 902system.cpu0.dcache.tags.occ_percent::cpu0.data 0.932397 # Average percentage of cache occupancy 903system.cpu0.dcache.tags.occ_percent::total 0.932397 # Average percentage of cache occupancy 904system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 905system.cpu0.dcache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id 906system.cpu0.dcache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id 907system.cpu0.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id 908system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 909system.cpu0.dcache.tags.tag_accesses 341097294 # Number of tag accesses 910system.cpu0.dcache.tags.data_accesses 341097294 # Number of data accesses 911system.cpu0.dcache.ReadReq_hits::cpu0.data 79771007 # number of ReadReq hits 912system.cpu0.dcache.ReadReq_hits::total 79771007 # number of ReadReq hits 913system.cpu0.dcache.WriteReq_hits::cpu0.data 67422867 # number of WriteReq hits 914system.cpu0.dcache.WriteReq_hits::total 67422867 # number of WriteReq hits 915system.cpu0.dcache.SoftPFReq_hits::cpu0.data 213459 # number of SoftPFReq hits 916system.cpu0.dcache.SoftPFReq_hits::total 213459 # number of SoftPFReq hits 917system.cpu0.dcache.WriteLineReq_hits::cpu0.data 258123 # number of WriteLineReq hits 918system.cpu0.dcache.WriteLineReq_hits::total 258123 # number of WriteLineReq hits 919system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1760749 # number of LoadLockedReq hits 920system.cpu0.dcache.LoadLockedReq_hits::total 1760749 # number of LoadLockedReq hits 921system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1785447 # number of StoreCondReq hits 922system.cpu0.dcache.StoreCondReq_hits::total 1785447 # number of StoreCondReq hits 923system.cpu0.dcache.demand_hits::cpu0.data 147193874 # number of demand (read+write) hits 924system.cpu0.dcache.demand_hits::total 147193874 # number of demand (read+write) hits 925system.cpu0.dcache.overall_hits::cpu0.data 147407333 # number of overall hits 926system.cpu0.dcache.overall_hits::total 147407333 # number of overall hits 927system.cpu0.dcache.ReadReq_misses::cpu0.data 6628879 # number of ReadReq misses 928system.cpu0.dcache.ReadReq_misses::total 6628879 # number of ReadReq misses 929system.cpu0.dcache.WriteReq_misses::cpu0.data 7648651 # number of WriteReq misses 930system.cpu0.dcache.WriteReq_misses::total 7648651 # number of WriteReq misses 931system.cpu0.dcache.SoftPFReq_misses::cpu0.data 727328 # number of SoftPFReq misses 932system.cpu0.dcache.SoftPFReq_misses::total 727328 # number of SoftPFReq misses 933system.cpu0.dcache.WriteLineReq_misses::cpu0.data 823977 # number of WriteLineReq misses 934system.cpu0.dcache.WriteLineReq_misses::total 823977 # number of WriteLineReq misses 935system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 249122 # number of LoadLockedReq misses 936system.cpu0.dcache.LoadLockedReq_misses::total 249122 # number of LoadLockedReq misses 937system.cpu0.dcache.StoreCondReq_misses::cpu0.data 189214 # number of StoreCondReq misses 938system.cpu0.dcache.StoreCondReq_misses::total 189214 # number of StoreCondReq misses 939system.cpu0.dcache.demand_misses::cpu0.data 14277530 # number of demand (read+write) misses 940system.cpu0.dcache.demand_misses::total 14277530 # number of demand (read+write) misses 941system.cpu0.dcache.overall_misses::cpu0.data 15004858 # number of overall misses 942system.cpu0.dcache.overall_misses::total 15004858 # number of overall misses 943system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 114348877500 # number of ReadReq miss cycles 944system.cpu0.dcache.ReadReq_miss_latency::total 114348877500 # number of ReadReq miss cycles 945system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 176760598457 # number of WriteReq miss cycles 946system.cpu0.dcache.WriteReq_miss_latency::total 176760598457 # number of WriteReq miss cycles 947system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 91829921579 # number of WriteLineReq miss cycles 948system.cpu0.dcache.WriteLineReq_miss_latency::total 91829921579 # number of WriteLineReq miss cycles 949system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3934102000 # number of LoadLockedReq miss cycles 950system.cpu0.dcache.LoadLockedReq_miss_latency::total 3934102000 # number of LoadLockedReq miss cycles 951system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5393439500 # number of StoreCondReq miss cycles 952system.cpu0.dcache.StoreCondReq_miss_latency::total 5393439500 # number of StoreCondReq miss cycles 953system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4601000 # number of StoreCondFailReq miss cycles 954system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4601000 # number of StoreCondFailReq miss cycles 955system.cpu0.dcache.demand_miss_latency::cpu0.data 291109475957 # number of demand (read+write) miss cycles 956system.cpu0.dcache.demand_miss_latency::total 291109475957 # number of demand (read+write) miss cycles 957system.cpu0.dcache.overall_miss_latency::cpu0.data 291109475957 # number of overall miss cycles 958system.cpu0.dcache.overall_miss_latency::total 291109475957 # number of overall miss cycles 959system.cpu0.dcache.ReadReq_accesses::cpu0.data 86399886 # number of ReadReq accesses(hits+misses) 960system.cpu0.dcache.ReadReq_accesses::total 86399886 # number of ReadReq accesses(hits+misses) 961system.cpu0.dcache.WriteReq_accesses::cpu0.data 75071518 # number of WriteReq accesses(hits+misses) 962system.cpu0.dcache.WriteReq_accesses::total 75071518 # number of WriteReq accesses(hits+misses) 963system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 940787 # number of SoftPFReq accesses(hits+misses) 964system.cpu0.dcache.SoftPFReq_accesses::total 940787 # number of SoftPFReq accesses(hits+misses) 965system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1082100 # number of WriteLineReq accesses(hits+misses) 966system.cpu0.dcache.WriteLineReq_accesses::total 1082100 # number of WriteLineReq accesses(hits+misses) 967system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2009871 # number of LoadLockedReq accesses(hits+misses) 968system.cpu0.dcache.LoadLockedReq_accesses::total 2009871 # number of LoadLockedReq accesses(hits+misses) 969system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1974661 # number of StoreCondReq accesses(hits+misses) 970system.cpu0.dcache.StoreCondReq_accesses::total 1974661 # number of StoreCondReq accesses(hits+misses) 971system.cpu0.dcache.demand_accesses::cpu0.data 161471404 # number of demand (read+write) accesses 972system.cpu0.dcache.demand_accesses::total 161471404 # number of demand (read+write) accesses 973system.cpu0.dcache.overall_accesses::cpu0.data 162412191 # number of overall (read+write) accesses 974system.cpu0.dcache.overall_accesses::total 162412191 # number of overall (read+write) accesses 975system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.076723 # miss rate for ReadReq accesses 976system.cpu0.dcache.ReadReq_miss_rate::total 0.076723 # miss rate for ReadReq accesses 977system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.101885 # miss rate for WriteReq accesses 978system.cpu0.dcache.WriteReq_miss_rate::total 0.101885 # miss rate for WriteReq accesses 979system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.773106 # miss rate for SoftPFReq accesses 980system.cpu0.dcache.SoftPFReq_miss_rate::total 0.773106 # miss rate for SoftPFReq accesses 981system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.761461 # miss rate for WriteLineReq accesses 982system.cpu0.dcache.WriteLineReq_miss_rate::total 0.761461 # miss rate for WriteLineReq accesses 983system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.123949 # miss rate for LoadLockedReq accesses 984system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.123949 # miss rate for LoadLockedReq accesses 985system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095821 # miss rate for StoreCondReq accesses 986system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095821 # miss rate for StoreCondReq accesses 987system.cpu0.dcache.demand_miss_rate::cpu0.data 0.088421 # miss rate for demand accesses 988system.cpu0.dcache.demand_miss_rate::total 0.088421 # miss rate for demand accesses 989system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092388 # miss rate for overall accesses 990system.cpu0.dcache.overall_miss_rate::total 0.092388 # miss rate for overall accesses 991system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17250.107824 # average ReadReq miss latency 992system.cpu0.dcache.ReadReq_avg_miss_latency::total 17250.107824 # average ReadReq miss latency 993system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23110.035803 # average WriteReq miss latency 994system.cpu0.dcache.WriteReq_avg_miss_latency::total 23110.035803 # average WriteReq miss latency 995system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 111447.190369 # average WriteLineReq miss latency 996system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 111447.190369 # average WriteLineReq miss latency 997system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15791.869044 # average LoadLockedReq miss latency 998system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15791.869044 # average LoadLockedReq miss latency 999system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28504.442060 # average StoreCondReq miss latency 1000system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28504.442060 # average StoreCondReq miss latency 1001system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 1002system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1003system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20389.344372 # average overall miss latency 1004system.cpu0.dcache.demand_avg_miss_latency::total 20389.344372 # average overall miss latency 1005system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19401.015055 # average overall miss latency 1006system.cpu0.dcache.overall_avg_miss_latency::total 19401.015055 # average overall miss latency 1007system.cpu0.dcache.blocked_cycles::no_mshrs 28956080 # number of cycles access was blocked 1008system.cpu0.dcache.blocked_cycles::no_targets 26869955 # number of cycles access was blocked 1009system.cpu0.dcache.blocked::no_mshrs 763930 # number of cycles access was blocked 1010system.cpu0.dcache.blocked::no_targets 756063 # number of cycles access was blocked 1011system.cpu0.dcache.avg_blocked_cycles::no_mshrs 37.904101 # average number of cycles each access was blocked 1012system.cpu0.dcache.avg_blocked_cycles::no_targets 35.539307 # average number of cycles each access was blocked 1013system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1014system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1015system.cpu0.dcache.writebacks::writebacks 6037757 # number of writebacks 1016system.cpu0.dcache.writebacks::total 6037757 # number of writebacks 1017system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3397304 # number of ReadReq MSHR hits 1018system.cpu0.dcache.ReadReq_mshr_hits::total 3397304 # number of ReadReq MSHR hits 1019system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6149640 # number of WriteReq MSHR hits 1020system.cpu0.dcache.WriteReq_mshr_hits::total 6149640 # number of WriteReq MSHR hits 1021system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4348 # number of WriteLineReq MSHR hits 1022system.cpu0.dcache.WriteLineReq_mshr_hits::total 4348 # number of WriteLineReq MSHR hits 1023system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 126499 # number of LoadLockedReq MSHR hits 1024system.cpu0.dcache.LoadLockedReq_mshr_hits::total 126499 # number of LoadLockedReq MSHR hits 1025system.cpu0.dcache.demand_mshr_hits::cpu0.data 9546944 # number of demand (read+write) MSHR hits 1026system.cpu0.dcache.demand_mshr_hits::total 9546944 # number of demand (read+write) MSHR hits 1027system.cpu0.dcache.overall_mshr_hits::cpu0.data 9546944 # number of overall MSHR hits 1028system.cpu0.dcache.overall_mshr_hits::total 9546944 # number of overall MSHR hits 1029system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3231575 # number of ReadReq MSHR misses 1030system.cpu0.dcache.ReadReq_mshr_misses::total 3231575 # number of ReadReq MSHR misses 1031system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1499011 # number of WriteReq MSHR misses 1032system.cpu0.dcache.WriteReq_mshr_misses::total 1499011 # number of WriteReq MSHR misses 1033system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 720499 # number of SoftPFReq MSHR misses 1034system.cpu0.dcache.SoftPFReq_mshr_misses::total 720499 # number of SoftPFReq MSHR misses 1035system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 819629 # number of WriteLineReq MSHR misses 1036system.cpu0.dcache.WriteLineReq_mshr_misses::total 819629 # number of WriteLineReq MSHR misses 1037system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 122623 # number of LoadLockedReq MSHR misses 1038system.cpu0.dcache.LoadLockedReq_mshr_misses::total 122623 # number of LoadLockedReq MSHR misses 1039system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 189214 # number of StoreCondReq MSHR misses 1040system.cpu0.dcache.StoreCondReq_mshr_misses::total 189214 # number of StoreCondReq MSHR misses 1041system.cpu0.dcache.demand_mshr_misses::cpu0.data 4730586 # number of demand (read+write) MSHR misses 1042system.cpu0.dcache.demand_mshr_misses::total 4730586 # number of demand (read+write) MSHR misses 1043system.cpu0.dcache.overall_mshr_misses::cpu0.data 5451085 # number of overall MSHR misses 1044system.cpu0.dcache.overall_mshr_misses::total 5451085 # number of overall MSHR misses 1045system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32157 # number of ReadReq MSHR uncacheable 1046system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32157 # number of ReadReq MSHR uncacheable 1047system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 31964 # number of WriteReq MSHR uncacheable 1048system.cpu0.dcache.WriteReq_mshr_uncacheable::total 31964 # number of WriteReq MSHR uncacheable 1049system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 64121 # number of overall MSHR uncacheable misses 1050system.cpu0.dcache.overall_mshr_uncacheable_misses::total 64121 # number of overall MSHR uncacheable misses 1051system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 51760022500 # number of ReadReq MSHR miss cycles 1052system.cpu0.dcache.ReadReq_mshr_miss_latency::total 51760022500 # number of ReadReq MSHR miss cycles 1053system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 40775562681 # number of WriteReq MSHR miss cycles 1054system.cpu0.dcache.WriteReq_mshr_miss_latency::total 40775562681 # number of WriteReq MSHR miss cycles 1055system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18675421500 # number of SoftPFReq MSHR miss cycles 1056system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18675421500 # number of SoftPFReq MSHR miss cycles 1057system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 90765682079 # number of WriteLineReq MSHR miss cycles 1058system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 90765682079 # number of WriteLineReq MSHR miss cycles 1059system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1771728000 # number of LoadLockedReq MSHR miss cycles 1060system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1771728000 # number of LoadLockedReq MSHR miss cycles 1061system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5204285500 # number of StoreCondReq MSHR miss cycles 1062system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5204285500 # number of StoreCondReq MSHR miss cycles 1063system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4541000 # number of StoreCondFailReq MSHR miss cycles 1064system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4541000 # number of StoreCondFailReq MSHR miss cycles 1065system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 92535585181 # number of demand (read+write) MSHR miss cycles 1066system.cpu0.dcache.demand_mshr_miss_latency::total 92535585181 # number of demand (read+write) MSHR miss cycles 1067system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 111211006681 # number of overall MSHR miss cycles 1068system.cpu0.dcache.overall_mshr_miss_latency::total 111211006681 # number of overall MSHR miss cycles 1069system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6175664000 # number of ReadReq MSHR uncacheable cycles 1070system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6175664000 # number of ReadReq MSHR uncacheable cycles 1071system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 6047364000 # number of WriteReq MSHR uncacheable cycles 1072system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6047364000 # number of WriteReq MSHR uncacheable cycles 1073system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12223028000 # number of overall MSHR uncacheable cycles 1074system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12223028000 # number of overall MSHR uncacheable cycles 1075system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037403 # mshr miss rate for ReadReq accesses 1076system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037403 # mshr miss rate for ReadReq accesses 1077system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019968 # mshr miss rate for WriteReq accesses 1078system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019968 # mshr miss rate for WriteReq accesses 1079system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.765847 # mshr miss rate for SoftPFReq accesses 1080system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.765847 # mshr miss rate for SoftPFReq accesses 1081system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.757443 # mshr miss rate for WriteLineReq accesses 1082system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.757443 # mshr miss rate for WriteLineReq accesses 1083system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061010 # mshr miss rate for LoadLockedReq accesses 1084system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061010 # mshr miss rate for LoadLockedReq accesses 1085system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095821 # mshr miss rate for StoreCondReq accesses 1086system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095821 # mshr miss rate for StoreCondReq accesses 1087system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029297 # mshr miss rate for demand accesses 1088system.cpu0.dcache.demand_mshr_miss_rate::total 0.029297 # mshr miss rate for demand accesses 1089system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.033563 # mshr miss rate for overall accesses 1090system.cpu0.dcache.overall_mshr_miss_rate::total 0.033563 # mshr miss rate for overall accesses 1091system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16016.964638 # average ReadReq mshr miss latency 1092system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16016.964638 # average ReadReq mshr miss latency 1093system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27201.643404 # average WriteReq mshr miss latency 1094system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27201.643404 # average WriteReq mshr miss latency 1095system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25920.121333 # average SoftPFReq mshr miss latency 1096system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25920.121333 # average SoftPFReq mshr miss latency 1097system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 110739.959273 # average WriteLineReq mshr miss latency 1098system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 110739.959273 # average WriteLineReq mshr miss latency 1099system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14448.578162 # average LoadLockedReq mshr miss latency 1100system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14448.578162 # average LoadLockedReq mshr miss latency 1101system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27504.759162 # average StoreCondReq mshr miss latency 1102system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27504.759162 # average StoreCondReq mshr miss latency 1103system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1104system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1105system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19561.125235 # average overall mshr miss latency 1106system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19561.125235 # average overall mshr miss latency 1107system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20401.627691 # average overall mshr miss latency 1108system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20401.627691 # average overall mshr miss latency 1109system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 192047.268091 # average ReadReq mshr uncacheable latency 1110system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192047.268091 # average ReadReq mshr uncacheable latency 1111system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189192.967088 # average WriteReq mshr uncacheable latency 1112system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189192.967088 # average WriteReq mshr uncacheable latency 1113system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 190624.413219 # average overall mshr uncacheable latency 1114system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190624.413219 # average overall mshr uncacheable latency 1115system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1116system.cpu0.icache.tags.replacements 5991449 # number of replacements 1117system.cpu0.icache.tags.tagsinuse 511.937020 # Cycle average of tags in use 1118system.cpu0.icache.tags.total_refs 207384617 # Total number of references to valid blocks. 1119system.cpu0.icache.tags.sampled_refs 5991961 # Sample count of references to valid blocks. 1120system.cpu0.icache.tags.avg_refs 34.610475 # Average number of references to valid blocks. 1121system.cpu0.icache.tags.warmup_cycle 21603135000 # Cycle when the warmup percentage was hit. 1122system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.937020 # Average occupied blocks per requestor 1123system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999877 # Average percentage of cache occupancy 1124system.cpu0.icache.tags.occ_percent::total 0.999877 # Average percentage of cache occupancy 1125system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1126system.cpu0.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 1127system.cpu0.icache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id 1128system.cpu0.icache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id 1129system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1130system.cpu0.icache.tags.tag_accesses 433456796 # Number of tag accesses 1131system.cpu0.icache.tags.data_accesses 433456796 # Number of data accesses 1132system.cpu0.icache.ReadReq_hits::cpu0.inst 207384617 # number of ReadReq hits 1133system.cpu0.icache.ReadReq_hits::total 207384617 # number of ReadReq hits 1134system.cpu0.icache.demand_hits::cpu0.inst 207384617 # number of demand (read+write) hits 1135system.cpu0.icache.demand_hits::total 207384617 # number of demand (read+write) hits 1136system.cpu0.icache.overall_hits::cpu0.inst 207384617 # number of overall hits 1137system.cpu0.icache.overall_hits::total 207384617 # number of overall hits 1138system.cpu0.icache.ReadReq_misses::cpu0.inst 6347783 # number of ReadReq misses 1139system.cpu0.icache.ReadReq_misses::total 6347783 # number of ReadReq misses 1140system.cpu0.icache.demand_misses::cpu0.inst 6347783 # number of demand (read+write) misses 1141system.cpu0.icache.demand_misses::total 6347783 # number of demand (read+write) misses 1142system.cpu0.icache.overall_misses::cpu0.inst 6347783 # number of overall misses 1143system.cpu0.icache.overall_misses::total 6347783 # number of overall misses 1144system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 72771579605 # number of ReadReq miss cycles 1145system.cpu0.icache.ReadReq_miss_latency::total 72771579605 # number of ReadReq miss cycles 1146system.cpu0.icache.demand_miss_latency::cpu0.inst 72771579605 # number of demand (read+write) miss cycles 1147system.cpu0.icache.demand_miss_latency::total 72771579605 # number of demand (read+write) miss cycles 1148system.cpu0.icache.overall_miss_latency::cpu0.inst 72771579605 # number of overall miss cycles 1149system.cpu0.icache.overall_miss_latency::total 72771579605 # number of overall miss cycles 1150system.cpu0.icache.ReadReq_accesses::cpu0.inst 213732400 # number of ReadReq accesses(hits+misses) 1151system.cpu0.icache.ReadReq_accesses::total 213732400 # number of ReadReq accesses(hits+misses) 1152system.cpu0.icache.demand_accesses::cpu0.inst 213732400 # number of demand (read+write) accesses 1153system.cpu0.icache.demand_accesses::total 213732400 # number of demand (read+write) accesses 1154system.cpu0.icache.overall_accesses::cpu0.inst 213732400 # number of overall (read+write) accesses 1155system.cpu0.icache.overall_accesses::total 213732400 # number of overall (read+write) accesses 1156system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029700 # miss rate for ReadReq accesses 1157system.cpu0.icache.ReadReq_miss_rate::total 0.029700 # miss rate for ReadReq accesses 1158system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029700 # miss rate for demand accesses 1159system.cpu0.icache.demand_miss_rate::total 0.029700 # miss rate for demand accesses 1160system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029700 # miss rate for overall accesses 1161system.cpu0.icache.overall_miss_rate::total 0.029700 # miss rate for overall accesses 1162system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11464.093780 # average ReadReq miss latency 1163system.cpu0.icache.ReadReq_avg_miss_latency::total 11464.093780 # average ReadReq miss latency 1164system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11464.093780 # average overall miss latency 1165system.cpu0.icache.demand_avg_miss_latency::total 11464.093780 # average overall miss latency 1166system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11464.093780 # average overall miss latency 1167system.cpu0.icache.overall_avg_miss_latency::total 11464.093780 # average overall miss latency 1168system.cpu0.icache.blocked_cycles::no_mshrs 11432767 # number of cycles access was blocked 1169system.cpu0.icache.blocked_cycles::no_targets 1960 # number of cycles access was blocked 1170system.cpu0.icache.blocked::no_mshrs 763504 # number of cycles access was blocked 1171system.cpu0.icache.blocked::no_targets 16 # number of cycles access was blocked 1172system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.974076 # average number of cycles each access was blocked 1173system.cpu0.icache.avg_blocked_cycles::no_targets 122.500000 # average number of cycles each access was blocked 1174system.cpu0.icache.fast_writes 0 # number of fast writes performed 1175system.cpu0.icache.cache_copies 0 # number of cache copies performed 1176system.cpu0.icache.writebacks::writebacks 5991449 # number of writebacks 1177system.cpu0.icache.writebacks::total 5991449 # number of writebacks 1178system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 355787 # number of ReadReq MSHR hits 1179system.cpu0.icache.ReadReq_mshr_hits::total 355787 # number of ReadReq MSHR hits 1180system.cpu0.icache.demand_mshr_hits::cpu0.inst 355787 # number of demand (read+write) MSHR hits 1181system.cpu0.icache.demand_mshr_hits::total 355787 # number of demand (read+write) MSHR hits 1182system.cpu0.icache.overall_mshr_hits::cpu0.inst 355787 # number of overall MSHR hits 1183system.cpu0.icache.overall_mshr_hits::total 355787 # number of overall MSHR hits 1184system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5991996 # number of ReadReq MSHR misses 1185system.cpu0.icache.ReadReq_mshr_misses::total 5991996 # number of ReadReq MSHR misses 1186system.cpu0.icache.demand_mshr_misses::cpu0.inst 5991996 # number of demand (read+write) MSHR misses 1187system.cpu0.icache.demand_mshr_misses::total 5991996 # number of demand (read+write) MSHR misses 1188system.cpu0.icache.overall_mshr_misses::cpu0.inst 5991996 # number of overall MSHR misses 1189system.cpu0.icache.overall_mshr_misses::total 5991996 # number of overall MSHR misses 1190system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable 1191system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable 1192system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses 1193system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses 1194system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 65359568752 # number of ReadReq MSHR miss cycles 1195system.cpu0.icache.ReadReq_mshr_miss_latency::total 65359568752 # number of ReadReq MSHR miss cycles 1196system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 65359568752 # number of demand (read+write) MSHR miss cycles 1197system.cpu0.icache.demand_mshr_miss_latency::total 65359568752 # number of demand (read+write) MSHR miss cycles 1198system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 65359568752 # number of overall MSHR miss cycles 1199system.cpu0.icache.overall_mshr_miss_latency::total 65359568752 # number of overall MSHR miss cycles 1200system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2939780998 # number of ReadReq MSHR uncacheable cycles 1201system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2939780998 # number of ReadReq MSHR uncacheable cycles 1202system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2939780998 # number of overall MSHR uncacheable cycles 1203system.cpu0.icache.overall_mshr_uncacheable_latency::total 2939780998 # number of overall MSHR uncacheable cycles 1204system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028035 # mshr miss rate for ReadReq accesses 1205system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028035 # mshr miss rate for ReadReq accesses 1206system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028035 # mshr miss rate for demand accesses 1207system.cpu0.icache.demand_mshr_miss_rate::total 0.028035 # mshr miss rate for demand accesses 1208system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028035 # mshr miss rate for overall accesses 1209system.cpu0.icache.overall_mshr_miss_rate::total 0.028035 # mshr miss rate for overall accesses 1210system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10907.812481 # average ReadReq mshr miss latency 1211system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10907.812481 # average ReadReq mshr miss latency 1212system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10907.812481 # average overall mshr miss latency 1213system.cpu0.icache.demand_avg_mshr_miss_latency::total 10907.812481 # average overall mshr miss latency 1214system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10907.812481 # average overall mshr miss latency 1215system.cpu0.icache.overall_avg_mshr_miss_latency::total 10907.812481 # average overall mshr miss latency 1216system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138063.260132 # average ReadReq mshr uncacheable latency 1217system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138063.260132 # average ReadReq mshr uncacheable latency 1218system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138063.260132 # average overall mshr uncacheable latency 1219system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138063.260132 # average overall mshr uncacheable latency 1220system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1221system.cpu0.l2cache.prefetcher.num_hwpf_issued 8312308 # number of hwpf issued 1222system.cpu0.l2cache.prefetcher.pfIdentified 8321741 # number of prefetch candidates identified 1223system.cpu0.l2cache.prefetcher.pfBufferHit 8453 # number of redundant prefetches already in prefetch queue 1224system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1225system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1226system.cpu0.l2cache.prefetcher.pfSpanPage 1049931 # number of prefetches not generated due to page crossing 1227system.cpu0.l2cache.tags.replacements 2736768 # number of replacements 1228system.cpu0.l2cache.tags.tagsinuse 15876.012159 # Cycle average of tags in use 1229system.cpu0.l2cache.tags.total_refs 17362528 # Total number of references to valid blocks. 1230system.cpu0.l2cache.tags.sampled_refs 2752871 # Sample count of references to valid blocks. 1231system.cpu0.l2cache.tags.avg_refs 6.307062 # Average number of references to valid blocks. 1232system.cpu0.l2cache.tags.warmup_cycle 3536776000 # Cycle when the warmup percentage was hit. 1233system.cpu0.l2cache.tags.occ_blocks::writebacks 14917.842100 # Average occupied blocks per requestor 1234system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 70.317341 # Average occupied blocks per requestor 1235system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 59.112590 # Average occupied blocks per requestor 1236system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 828.740128 # Average occupied blocks per requestor 1237system.cpu0.l2cache.tags.occ_percent::writebacks 0.910513 # Average percentage of cache occupancy 1238system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004292 # Average percentage of cache occupancy 1239system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003608 # Average percentage of cache occupancy 1240system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.050582 # Average percentage of cache occupancy 1241system.cpu0.l2cache.tags.occ_percent::total 0.968995 # Average percentage of cache occupancy 1242system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1213 # Occupied blocks per task id 1243system.cpu0.l2cache.tags.occ_task_id_blocks::1023 79 # Occupied blocks per task id 1244system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14811 # Occupied blocks per task id 1245system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 15 # Occupied blocks per task id 1246system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 186 # Occupied blocks per task id 1247system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 670 # Occupied blocks per task id 1248system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 342 # Occupied blocks per task id 1249system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 1250system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 47 # Occupied blocks per task id 1251system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id 1252system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id 1253system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id 1254system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1270 # Occupied blocks per task id 1255system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5895 # Occupied blocks per task id 1256system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4592 # Occupied blocks per task id 1257system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2939 # Occupied blocks per task id 1258system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.074036 # Percentage of cache occupancy per task id 1259system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004822 # Percentage of cache occupancy per task id 1260system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.903992 # Percentage of cache occupancy per task id 1261system.cpu0.l2cache.tags.tag_accesses 412851946 # Number of tag accesses 1262system.cpu0.l2cache.tags.data_accesses 412851946 # Number of data accesses 1263system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 601484 # number of ReadReq hits 1264system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 195644 # number of ReadReq hits 1265system.cpu0.l2cache.ReadReq_hits::total 797128 # number of ReadReq hits 1266system.cpu0.l2cache.WritebackDirty_hits::writebacks 3986432 # number of WritebackDirty hits 1267system.cpu0.l2cache.WritebackDirty_hits::total 3986432 # number of WritebackDirty hits 1268system.cpu0.l2cache.WritebackClean_hits::writebacks 8040621 # number of WritebackClean hits 1269system.cpu0.l2cache.WritebackClean_hits::total 8040621 # number of WritebackClean hits 1270system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 576 # number of UpgradeReq hits 1271system.cpu0.l2cache.UpgradeReq_hits::total 576 # number of UpgradeReq hits 1272system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits 1273system.cpu0.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits 1274system.cpu0.l2cache.ReadExReq_hits::cpu0.data 912887 # number of ReadExReq hits 1275system.cpu0.l2cache.ReadExReq_hits::total 912887 # number of ReadExReq hits 1276system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5408697 # number of ReadCleanReq hits 1277system.cpu0.l2cache.ReadCleanReq_hits::total 5408697 # number of ReadCleanReq hits 1278system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3048347 # number of ReadSharedReq hits 1279system.cpu0.l2cache.ReadSharedReq_hits::total 3048347 # number of ReadSharedReq hits 1280system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 196930 # number of InvalidateReq hits 1281system.cpu0.l2cache.InvalidateReq_hits::total 196930 # number of InvalidateReq hits 1282system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 601484 # number of demand (read+write) hits 1283system.cpu0.l2cache.demand_hits::cpu0.itb.walker 195644 # number of demand (read+write) hits 1284system.cpu0.l2cache.demand_hits::cpu0.inst 5408697 # number of demand (read+write) hits 1285system.cpu0.l2cache.demand_hits::cpu0.data 3961234 # number of demand (read+write) hits 1286system.cpu0.l2cache.demand_hits::total 10167059 # number of demand (read+write) hits 1287system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 601484 # number of overall hits 1288system.cpu0.l2cache.overall_hits::cpu0.itb.walker 195644 # number of overall hits 1289system.cpu0.l2cache.overall_hits::cpu0.inst 5408697 # number of overall hits 1290system.cpu0.l2cache.overall_hits::cpu0.data 3961234 # number of overall hits 1291system.cpu0.l2cache.overall_hits::total 10167059 # number of overall hits 1292system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12249 # number of ReadReq misses 1293system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9259 # number of ReadReq misses 1294system.cpu0.l2cache.ReadReq_misses::total 21508 # number of ReadReq misses 1295system.cpu0.l2cache.WritebackDirty_misses::writebacks 1 # number of WritebackDirty misses 1296system.cpu0.l2cache.WritebackDirty_misses::total 1 # number of WritebackDirty misses 1297system.cpu0.l2cache.WritebackClean_misses::writebacks 3 # number of WritebackClean misses 1298system.cpu0.l2cache.WritebackClean_misses::total 3 # number of WritebackClean misses 1299system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 258491 # number of UpgradeReq misses 1300system.cpu0.l2cache.UpgradeReq_misses::total 258491 # number of UpgradeReq misses 1301system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 189208 # number of SCUpgradeReq misses 1302system.cpu0.l2cache.SCUpgradeReq_misses::total 189208 # number of SCUpgradeReq misses 1303system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses 1304system.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses 1305system.cpu0.l2cache.ReadExReq_misses::cpu0.data 336496 # number of ReadExReq misses 1306system.cpu0.l2cache.ReadExReq_misses::total 336496 # number of ReadExReq misses 1307system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 583279 # number of ReadCleanReq misses 1308system.cpu0.l2cache.ReadCleanReq_misses::total 583279 # number of ReadCleanReq misses 1309system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1024126 # number of ReadSharedReq misses 1310system.cpu0.l2cache.ReadSharedReq_misses::total 1024126 # number of ReadSharedReq misses 1311system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 620872 # number of InvalidateReq misses 1312system.cpu0.l2cache.InvalidateReq_misses::total 620872 # number of InvalidateReq misses 1313system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12249 # number of demand (read+write) misses 1314system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9259 # number of demand (read+write) misses 1315system.cpu0.l2cache.demand_misses::cpu0.inst 583279 # number of demand (read+write) misses 1316system.cpu0.l2cache.demand_misses::cpu0.data 1360622 # number of demand (read+write) misses 1317system.cpu0.l2cache.demand_misses::total 1965409 # number of demand (read+write) misses 1318system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12249 # number of overall misses 1319system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9259 # number of overall misses 1320system.cpu0.l2cache.overall_misses::cpu0.inst 583279 # number of overall misses 1321system.cpu0.l2cache.overall_misses::cpu0.data 1360622 # number of overall misses 1322system.cpu0.l2cache.overall_misses::total 1965409 # number of overall misses 1323system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 599464000 # number of ReadReq miss cycles 1324system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 508507000 # number of ReadReq miss cycles 1325system.cpu0.l2cache.ReadReq_miss_latency::total 1107971000 # number of ReadReq miss cycles 1326system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3541175500 # number of UpgradeReq miss cycles 1327system.cpu0.l2cache.UpgradeReq_miss_latency::total 3541175500 # number of UpgradeReq miss cycles 1328system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2016705000 # number of SCUpgradeReq miss cycles 1329system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2016705000 # number of SCUpgradeReq miss cycles 1330system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4451000 # number of SCUpgradeFailReq miss cycles 1331system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4451000 # number of SCUpgradeFailReq miss cycles 1332system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 22474975499 # number of ReadExReq miss cycles 1333system.cpu0.l2cache.ReadExReq_miss_latency::total 22474975499 # number of ReadExReq miss cycles 1334system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 23599019498 # number of ReadCleanReq miss cycles 1335system.cpu0.l2cache.ReadCleanReq_miss_latency::total 23599019498 # number of ReadCleanReq miss cycles 1336system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 45762236974 # number of ReadSharedReq miss cycles 1337system.cpu0.l2cache.ReadSharedReq_miss_latency::total 45762236974 # number of ReadSharedReq miss cycles 1338system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 87223622986 # number of InvalidateReq miss cycles 1339system.cpu0.l2cache.InvalidateReq_miss_latency::total 87223622986 # number of InvalidateReq miss cycles 1340system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 599464000 # number of demand (read+write) miss cycles 1341system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 508507000 # number of demand (read+write) miss cycles 1342system.cpu0.l2cache.demand_miss_latency::cpu0.inst 23599019498 # number of demand (read+write) miss cycles 1343system.cpu0.l2cache.demand_miss_latency::cpu0.data 68237212473 # number of demand (read+write) miss cycles 1344system.cpu0.l2cache.demand_miss_latency::total 92944202971 # number of demand (read+write) miss cycles 1345system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 599464000 # number of overall miss cycles 1346system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 508507000 # number of overall miss cycles 1347system.cpu0.l2cache.overall_miss_latency::cpu0.inst 23599019498 # number of overall miss cycles 1348system.cpu0.l2cache.overall_miss_latency::cpu0.data 68237212473 # number of overall miss cycles 1349system.cpu0.l2cache.overall_miss_latency::total 92944202971 # number of overall miss cycles 1350system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 613733 # number of ReadReq accesses(hits+misses) 1351system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 204903 # number of ReadReq accesses(hits+misses) 1352system.cpu0.l2cache.ReadReq_accesses::total 818636 # number of ReadReq accesses(hits+misses) 1353system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3986433 # number of WritebackDirty accesses(hits+misses) 1354system.cpu0.l2cache.WritebackDirty_accesses::total 3986433 # number of WritebackDirty accesses(hits+misses) 1355system.cpu0.l2cache.WritebackClean_accesses::writebacks 8040624 # number of WritebackClean accesses(hits+misses) 1356system.cpu0.l2cache.WritebackClean_accesses::total 8040624 # number of WritebackClean accesses(hits+misses) 1357system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 259067 # number of UpgradeReq accesses(hits+misses) 1358system.cpu0.l2cache.UpgradeReq_accesses::total 259067 # number of UpgradeReq accesses(hits+misses) 1359system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 189210 # number of SCUpgradeReq accesses(hits+misses) 1360system.cpu0.l2cache.SCUpgradeReq_accesses::total 189210 # number of SCUpgradeReq accesses(hits+misses) 1361system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses) 1362system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) 1363system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1249383 # number of ReadExReq accesses(hits+misses) 1364system.cpu0.l2cache.ReadExReq_accesses::total 1249383 # number of ReadExReq accesses(hits+misses) 1365system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 5991976 # number of ReadCleanReq accesses(hits+misses) 1366system.cpu0.l2cache.ReadCleanReq_accesses::total 5991976 # number of ReadCleanReq accesses(hits+misses) 1367system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4072473 # number of ReadSharedReq accesses(hits+misses) 1368system.cpu0.l2cache.ReadSharedReq_accesses::total 4072473 # number of ReadSharedReq accesses(hits+misses) 1369system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 817802 # number of InvalidateReq accesses(hits+misses) 1370system.cpu0.l2cache.InvalidateReq_accesses::total 817802 # number of InvalidateReq accesses(hits+misses) 1371system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 613733 # number of demand (read+write) accesses 1372system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 204903 # number of demand (read+write) accesses 1373system.cpu0.l2cache.demand_accesses::cpu0.inst 5991976 # number of demand (read+write) accesses 1374system.cpu0.l2cache.demand_accesses::cpu0.data 5321856 # number of demand (read+write) accesses 1375system.cpu0.l2cache.demand_accesses::total 12132468 # number of demand (read+write) accesses 1376system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 613733 # number of overall (read+write) accesses 1377system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 204903 # number of overall (read+write) accesses 1378system.cpu0.l2cache.overall_accesses::cpu0.inst 5991976 # number of overall (read+write) accesses 1379system.cpu0.l2cache.overall_accesses::cpu0.data 5321856 # number of overall (read+write) accesses 1380system.cpu0.l2cache.overall_accesses::total 12132468 # number of overall (read+write) accesses 1381system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.019958 # miss rate for ReadReq accesses 1382system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.045187 # miss rate for ReadReq accesses 1383system.cpu0.l2cache.ReadReq_miss_rate::total 0.026273 # miss rate for ReadReq accesses 1384system.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000000 # miss rate for WritebackDirty accesses 1385system.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000000 # miss rate for WritebackDirty accesses 1386system.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses 1387system.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses 1388system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.997777 # miss rate for UpgradeReq accesses 1389system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.997777 # miss rate for UpgradeReq accesses 1390system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999989 # miss rate for SCUpgradeReq accesses 1391system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999989 # miss rate for SCUpgradeReq accesses 1392system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1393system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1394system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.269330 # miss rate for ReadExReq accesses 1395system.cpu0.l2cache.ReadExReq_miss_rate::total 0.269330 # miss rate for ReadExReq accesses 1396system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.097343 # miss rate for ReadCleanReq accesses 1397system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.097343 # miss rate for ReadCleanReq accesses 1398system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.251475 # miss rate for ReadSharedReq accesses 1399system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.251475 # miss rate for ReadSharedReq accesses 1400system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.759196 # miss rate for InvalidateReq accesses 1401system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.759196 # miss rate for InvalidateReq accesses 1402system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.019958 # miss rate for demand accesses 1403system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.045187 # miss rate for demand accesses 1404system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.097343 # miss rate for demand accesses 1405system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.255667 # miss rate for demand accesses 1406system.cpu0.l2cache.demand_miss_rate::total 0.161996 # miss rate for demand accesses 1407system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.019958 # miss rate for overall accesses 1408system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.045187 # miss rate for overall accesses 1409system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.097343 # miss rate for overall accesses 1410system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.255667 # miss rate for overall accesses 1411system.cpu0.l2cache.overall_miss_rate::total 0.161996 # miss rate for overall accesses 1412system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 48939.831823 # average ReadReq miss latency 1413system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 54920.293768 # average ReadReq miss latency 1414system.cpu0.l2cache.ReadReq_avg_miss_latency::total 51514.366747 # average ReadReq miss latency 1415system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13699.415067 # average UpgradeReq miss latency 1416system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13699.415067 # average UpgradeReq miss latency 1417system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10658.666653 # average SCUpgradeReq miss latency 1418system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10658.666653 # average SCUpgradeReq miss latency 1419system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 1112750 # average SCUpgradeFailReq miss latency 1420system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1112750 # average SCUpgradeFailReq miss latency 1421system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 66791.211482 # average ReadExReq miss latency 1422system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 66791.211482 # average ReadExReq miss latency 1423system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 40459.230485 # average ReadCleanReq miss latency 1424system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 40459.230485 # average ReadCleanReq miss latency 1425system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 44684.186295 # average ReadSharedReq miss latency 1426system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 44684.186295 # average ReadSharedReq miss latency 1427system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 140485.676574 # average InvalidateReq miss latency 1428system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 140485.676574 # average InvalidateReq miss latency 1429system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 48939.831823 # average overall miss latency 1430system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 54920.293768 # average overall miss latency 1431system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 40459.230485 # average overall miss latency 1432system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 50151.484007 # average overall miss latency 1433system.cpu0.l2cache.demand_avg_miss_latency::total 47290.005780 # average overall miss latency 1434system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 48939.831823 # average overall miss latency 1435system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 54920.293768 # average overall miss latency 1436system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 40459.230485 # average overall miss latency 1437system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 50151.484007 # average overall miss latency 1438system.cpu0.l2cache.overall_avg_miss_latency::total 47290.005780 # average overall miss latency 1439system.cpu0.l2cache.blocked_cycles::no_mshrs 2951 # number of cycles access was blocked 1440system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1441system.cpu0.l2cache.blocked::no_mshrs 31 # number of cycles access was blocked 1442system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1443system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 95.193548 # average number of cycles each access was blocked 1444system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1445system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1446system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1447system.cpu0.l2cache.writebacks::writebacks 1713705 # number of writebacks 1448system.cpu0.l2cache.writebacks::total 1713705 # number of writebacks 1449system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 4 # number of ReadReq MSHR hits 1450system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 178 # number of ReadReq MSHR hits 1451system.cpu0.l2cache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits 1452system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 63480 # number of ReadExReq MSHR hits 1453system.cpu0.l2cache.ReadExReq_mshr_hits::total 63480 # number of ReadExReq MSHR hits 1454system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 1 # number of ReadCleanReq MSHR hits 1455system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1456system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 6383 # number of ReadSharedReq MSHR hits 1457system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 6383 # number of ReadSharedReq MSHR hits 1458system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 5 # number of InvalidateReq MSHR hits 1459system.cpu0.l2cache.InvalidateReq_mshr_hits::total 5 # number of InvalidateReq MSHR hits 1460system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 4 # number of demand (read+write) MSHR hits 1461system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 178 # number of demand (read+write) MSHR hits 1462system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits 1463system.cpu0.l2cache.demand_mshr_hits::cpu0.data 69863 # number of demand (read+write) MSHR hits 1464system.cpu0.l2cache.demand_mshr_hits::total 70046 # number of demand (read+write) MSHR hits 1465system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 4 # number of overall MSHR hits 1466system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 178 # number of overall MSHR hits 1467system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits 1468system.cpu0.l2cache.overall_mshr_hits::cpu0.data 69863 # number of overall MSHR hits 1469system.cpu0.l2cache.overall_mshr_hits::total 70046 # number of overall MSHR hits 1470system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12245 # number of ReadReq MSHR misses 1471system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 9081 # number of ReadReq MSHR misses 1472system.cpu0.l2cache.ReadReq_mshr_misses::total 21326 # number of ReadReq MSHR misses 1473system.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 1 # number of WritebackDirty MSHR misses 1474system.cpu0.l2cache.WritebackDirty_mshr_misses::total 1 # number of WritebackDirty MSHR misses 1475system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 3 # number of WritebackClean MSHR misses 1476system.cpu0.l2cache.WritebackClean_mshr_misses::total 3 # number of WritebackClean MSHR misses 1477system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 867285 # number of HardPFReq MSHR misses 1478system.cpu0.l2cache.HardPFReq_mshr_misses::total 867285 # number of HardPFReq MSHR misses 1479system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 258491 # number of UpgradeReq MSHR misses 1480system.cpu0.l2cache.UpgradeReq_mshr_misses::total 258491 # number of UpgradeReq MSHR misses 1481system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 189208 # number of SCUpgradeReq MSHR misses 1482system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 189208 # number of SCUpgradeReq MSHR misses 1483system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 4 # number of SCUpgradeFailReq MSHR misses 1484system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses 1485system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 273016 # number of ReadExReq MSHR misses 1486system.cpu0.l2cache.ReadExReq_mshr_misses::total 273016 # number of ReadExReq MSHR misses 1487system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 583278 # number of ReadCleanReq MSHR misses 1488system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 583278 # number of ReadCleanReq MSHR misses 1489system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1017743 # number of ReadSharedReq MSHR misses 1490system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1017743 # number of ReadSharedReq MSHR misses 1491system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 620867 # number of InvalidateReq MSHR misses 1492system.cpu0.l2cache.InvalidateReq_mshr_misses::total 620867 # number of InvalidateReq MSHR misses 1493system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12245 # number of demand (read+write) MSHR misses 1494system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 9081 # number of demand (read+write) MSHR misses 1495system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 583278 # number of demand (read+write) MSHR misses 1496system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1290759 # number of demand (read+write) MSHR misses 1497system.cpu0.l2cache.demand_mshr_misses::total 1895363 # number of demand (read+write) MSHR misses 1498system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12245 # number of overall MSHR misses 1499system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 9081 # number of overall MSHR misses 1500system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 583278 # number of overall MSHR misses 1501system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1290759 # number of overall MSHR misses 1502system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 867285 # number of overall MSHR misses 1503system.cpu0.l2cache.overall_mshr_misses::total 2762648 # number of overall MSHR misses 1504system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable 1505system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32157 # number of ReadReq MSHR uncacheable 1506system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 53450 # number of ReadReq MSHR uncacheable 1507system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 31964 # number of WriteReq MSHR uncacheable 1508system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 31964 # number of WriteReq MSHR uncacheable 1509system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses 1510system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 64121 # number of overall MSHR uncacheable misses 1511system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 85414 # number of overall MSHR uncacheable misses 1512system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 525913500 # number of ReadReq MSHR miss cycles 1513system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 445082000 # number of ReadReq MSHR miss cycles 1514system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 970995500 # number of ReadReq MSHR miss cycles 1515system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 62672299402 # number of HardPFReq MSHR miss cycles 1516system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 62672299402 # number of HardPFReq MSHR miss cycles 1517system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7863725997 # number of UpgradeReq MSHR miss cycles 1518system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7863725997 # number of UpgradeReq MSHR miss cycles 1519system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3782122004 # number of SCUpgradeReq MSHR miss cycles 1520system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3782122004 # number of SCUpgradeReq MSHR miss cycles 1521system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4091000 # number of SCUpgradeFailReq MSHR miss cycles 1522system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4091000 # number of SCUpgradeFailReq MSHR miss cycles 1523system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 17017630999 # number of ReadExReq MSHR miss cycles 1524system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 17017630999 # number of ReadExReq MSHR miss cycles 1525system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 20099332998 # number of ReadCleanReq MSHR miss cycles 1526system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 20099332998 # number of ReadCleanReq MSHR miss cycles 1527system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 39175352474 # number of ReadSharedReq MSHR miss cycles 1528system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 39175352474 # number of ReadSharedReq MSHR miss cycles 1529system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 83498176486 # number of InvalidateReq MSHR miss cycles 1530system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 83498176486 # number of InvalidateReq MSHR miss cycles 1531system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 525913500 # number of demand (read+write) MSHR miss cycles 1532system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 445082000 # number of demand (read+write) MSHR miss cycles 1533system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 20099332998 # number of demand (read+write) MSHR miss cycles 1534system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 56192983473 # number of demand (read+write) MSHR miss cycles 1535system.cpu0.l2cache.demand_mshr_miss_latency::total 77263311971 # number of demand (read+write) MSHR miss cycles 1536system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 525913500 # number of overall MSHR miss cycles 1537system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 445082000 # number of overall MSHR miss cycles 1538system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 20099332998 # number of overall MSHR miss cycles 1539system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 56192983473 # number of overall MSHR miss cycles 1540system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 62672299402 # number of overall MSHR miss cycles 1541system.cpu0.l2cache.overall_mshr_miss_latency::total 139935611373 # number of overall MSHR miss cycles 1542system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2780082500 # number of ReadReq MSHR uncacheable cycles 1543system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5918259500 # number of ReadReq MSHR uncacheable cycles 1544system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8698342000 # number of ReadReq MSHR uncacheable cycles 1545system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5801825967 # number of WriteReq MSHR uncacheable cycles 1546system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5801825967 # number of WriteReq MSHR uncacheable cycles 1547system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 2780082500 # number of overall MSHR uncacheable cycles 1548system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11720085467 # number of overall MSHR uncacheable cycles 1549system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 14500167967 # number of overall MSHR uncacheable cycles 1550system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.019952 # mshr miss rate for ReadReq accesses 1551system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.044319 # mshr miss rate for ReadReq accesses 1552system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.026051 # mshr miss rate for ReadReq accesses 1553system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackDirty accesses 1554system.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackDirty accesses 1555system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses 1556system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses 1557system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1558system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1559system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.997777 # mshr miss rate for UpgradeReq accesses 1560system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.997777 # mshr miss rate for UpgradeReq accesses 1561system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999989 # mshr miss rate for SCUpgradeReq accesses 1562system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999989 # mshr miss rate for SCUpgradeReq accesses 1563system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1564system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1565system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.218521 # mshr miss rate for ReadExReq accesses 1566system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.218521 # mshr miss rate for ReadExReq accesses 1567system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.097343 # mshr miss rate for ReadCleanReq accesses 1568system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.097343 # mshr miss rate for ReadCleanReq accesses 1569system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.249908 # mshr miss rate for ReadSharedReq accesses 1570system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249908 # mshr miss rate for ReadSharedReq accesses 1571system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.759190 # mshr miss rate for InvalidateReq accesses 1572system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.759190 # mshr miss rate for InvalidateReq accesses 1573system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.019952 # mshr miss rate for demand accesses 1574system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.044319 # mshr miss rate for demand accesses 1575system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.097343 # mshr miss rate for demand accesses 1576system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.242539 # mshr miss rate for demand accesses 1577system.cpu0.l2cache.demand_mshr_miss_rate::total 0.156222 # mshr miss rate for demand accesses 1578system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.019952 # mshr miss rate for overall accesses 1579system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.044319 # mshr miss rate for overall accesses 1580system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.097343 # mshr miss rate for overall accesses 1581system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.242539 # mshr miss rate for overall accesses 1582system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1583system.cpu0.l2cache.overall_mshr_miss_rate::total 0.227707 # mshr miss rate for overall accesses 1584system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 42949.244590 # average ReadReq mshr miss latency 1585system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 49012.443563 # average ReadReq mshr miss latency 1586system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 45531.065366 # average ReadReq mshr miss latency 1587system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 72262.635007 # average HardPFReq mshr miss latency 1588system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 72262.635007 # average HardPFReq mshr miss latency 1589system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30421.662638 # average UpgradeReq mshr miss latency 1590system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30421.662638 # average UpgradeReq mshr miss latency 1591system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19989.228806 # average SCUpgradeReq mshr miss latency 1592system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19989.228806 # average SCUpgradeReq mshr miss latency 1593system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 1022750 # average SCUpgradeFailReq mshr miss latency 1594system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1022750 # average SCUpgradeFailReq mshr miss latency 1595system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 62331.991528 # average ReadExReq mshr miss latency 1596system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 62331.991528 # average ReadExReq mshr miss latency 1597system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 34459.268133 # average ReadCleanReq mshr miss latency 1598system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34459.268133 # average ReadCleanReq mshr miss latency 1599system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 38492.382138 # average ReadSharedReq mshr miss latency 1600system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 38492.382138 # average ReadSharedReq mshr miss latency 1601system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 134486.414137 # average InvalidateReq mshr miss latency 1602system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 134486.414137 # average InvalidateReq mshr miss latency 1603system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 42949.244590 # average overall mshr miss latency 1604system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 49012.443563 # average overall mshr miss latency 1605system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34459.268133 # average overall mshr miss latency 1606system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43534.837621 # average overall mshr miss latency 1607system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40764.387598 # average overall mshr miss latency 1608system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 42949.244590 # average overall mshr miss latency 1609system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 49012.443563 # average overall mshr miss latency 1610system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34459.268133 # average overall mshr miss latency 1611system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43534.837621 # average overall mshr miss latency 1612system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 72262.635007 # average overall mshr miss latency 1613system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50652.711230 # average overall mshr miss latency 1614system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263 # average ReadReq mshr uncacheable latency 1615system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184042.650123 # average ReadReq mshr uncacheable latency 1616system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162737.923293 # average ReadReq mshr uncacheable latency 1617system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181511.261638 # average WriteReq mshr uncacheable latency 1618system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181511.261638 # average WriteReq mshr uncacheable latency 1619system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263 # average overall mshr uncacheable latency 1620system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 182780.765537 # average overall mshr uncacheable latency 1621system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 169763.363933 # average overall mshr uncacheable latency 1622system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1623system.cpu0.toL2Bus.snoop_filter.tot_requests 24968942 # Total number of requests made to the snoop filter. 1624system.cpu0.toL2Bus.snoop_filter.hit_single_requests 12837433 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1625system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2144 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1626system.cpu0.toL2Bus.snoop_filter.tot_snoops 2067889 # Total number of snoops made to the snoop filter. 1627system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2067431 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1628system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 458 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1629system.cpu0.toL2Bus.trans_dist::ReadReq 957998 # Transaction distribution 1630system.cpu0.toL2Bus.trans_dist::ReadResp 11124580 # Transaction distribution 1631system.cpu0.toL2Bus.trans_dist::WriteReq 31965 # Transaction distribution 1632system.cpu0.toL2Bus.trans_dist::WriteResp 31964 # Transaction distribution 1633system.cpu0.toL2Bus.trans_dist::WritebackDirty 5704814 # Transaction distribution 1634system.cpu0.toL2Bus.trans_dist::WritebackClean 8040643 # Transaction distribution 1635system.cpu0.toL2Bus.trans_dist::CleanEvict 2700571 # Transaction distribution 1636system.cpu0.toL2Bus.trans_dist::HardPFReq 1106688 # Transaction distribution 1637system.cpu0.toL2Bus.trans_dist::HardPFResp 8 # Transaction distribution 1638system.cpu0.toL2Bus.trans_dist::UpgradeReq 482477 # Transaction distribution 1639system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 344108 # Transaction distribution 1640system.cpu0.toL2Bus.trans_dist::UpgradeResp 518232 # Transaction distribution 1641system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution 1642system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution 1643system.cpu0.toL2Bus.trans_dist::ReadExReq 1334424 # Transaction distribution 1644system.cpu0.toL2Bus.trans_dist::ReadExResp 1260303 # Transaction distribution 1645system.cpu0.toL2Bus.trans_dist::ReadCleanReq 5991996 # Transaction distribution 1646system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5072927 # Transaction distribution 1647system.cpu0.toL2Bus.trans_dist::InvalidateReq 824948 # Transaction distribution 1648system.cpu0.toL2Bus.trans_dist::InvalidateResp 817802 # Transaction distribution 1649system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18016682 # Packet count per connected master and slave (bytes) 1650system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19524167 # Packet count per connected master and slave (bytes) 1651system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 428300 # Packet count per connected master and slave (bytes) 1652system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1294882 # Packet count per connected master and slave (bytes) 1653system.cpu0.toL2Bus.pkt_count::total 39264031 # Packet count per connected master and slave (bytes) 1654system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 767195088 # Cumulative packet size per connected master and slave (bytes) 1655system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 734396467 # Cumulative packet size per connected master and slave (bytes) 1656system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1639224 # Cumulative packet size per connected master and slave (bytes) 1657system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4909864 # Cumulative packet size per connected master and slave (bytes) 1658system.cpu0.toL2Bus.pkt_size::total 1508140643 # Cumulative packet size per connected master and slave (bytes) 1659system.cpu0.toL2Bus.snoops 7265658 # Total snoops (count) 1660system.cpu0.toL2Bus.snoop_fanout::samples 20566582 # Request fanout histogram 1661system.cpu0.toL2Bus.snoop_fanout::mean 0.118168 # Request fanout histogram 1662system.cpu0.toL2Bus.snoop_fanout::stdev 0.322876 # Request fanout histogram 1663system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1664system.cpu0.toL2Bus.snoop_fanout::0 18136730 88.19% 88.19% # Request fanout histogram 1665system.cpu0.toL2Bus.snoop_fanout::1 2429394 11.81% 100.00% # Request fanout histogram 1666system.cpu0.toL2Bus.snoop_fanout::2 458 0.00% 100.00% # Request fanout histogram 1667system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1668system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1669system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1670system.cpu0.toL2Bus.snoop_fanout::total 20566582 # Request fanout histogram 1671system.cpu0.toL2Bus.reqLayer0.occupancy 24844807916 # Layer occupancy (ticks) 1672system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1673system.cpu0.toL2Bus.snoopLayer0.occupancy 204855996 # Layer occupancy (ticks) 1674system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1675system.cpu0.toL2Bus.respLayer0.occupancy 9015512485 # Layer occupancy (ticks) 1676system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1677system.cpu0.toL2Bus.respLayer1.occupancy 8672428624 # Layer occupancy (ticks) 1678system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1679system.cpu0.toL2Bus.respLayer2.occupancy 223891503 # Layer occupancy (ticks) 1680system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1681system.cpu0.toL2Bus.respLayer3.occupancy 681731807 # Layer occupancy (ticks) 1682system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1683system.cpu1.branchPred.lookups 134041815 # Number of BP lookups 1684system.cpu1.branchPred.condPredicted 89707660 # Number of conditional branches predicted 1685system.cpu1.branchPred.condIncorrect 6609017 # Number of conditional branches incorrect 1686system.cpu1.branchPred.BTBLookups 94187638 # Number of BTB lookups 1687system.cpu1.branchPred.BTBHits 61197396 # Number of BTB hits 1688system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1689system.cpu1.branchPred.BTBHitPct 64.973915 # BTB Hit Percentage 1690system.cpu1.branchPred.usedRAS 17950728 # Number of times the RAS was used to get a target. 1691system.cpu1.branchPred.RASInCorrect 175820 # Number of incorrect RAS predictions. 1692system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1693system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1694system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1695system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1696system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1697system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1698system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1699system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1700system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1701system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1702system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1703system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1704system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1705system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1706system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1707system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1708system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1709system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1710system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1711system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1712system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1713system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1714system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1715system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1716system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1717system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1718system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1719system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1720system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1721system.cpu1.dtb.walker.walks 567287 # Table walker walks requested 1722system.cpu1.dtb.walker.walksLong 567287 # Table walker walks initiated with long descriptors 1723system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11327 # Level at which table walker walks with long descriptors terminate 1724system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 89325 # Level at which table walker walks with long descriptors terminate 1725system.cpu1.dtb.walker.walksSquashedBefore 259417 # Table walks squashed before starting 1726system.cpu1.dtb.walker.walkWaitTime::samples 307870 # Table walker wait (enqueue to first request) latency 1727system.cpu1.dtb.walker.walkWaitTime::mean 2446.318251 # Table walker wait (enqueue to first request) latency 1728system.cpu1.dtb.walker.walkWaitTime::stdev 14947.483095 # Table walker wait (enqueue to first request) latency 1729system.cpu1.dtb.walker.walkWaitTime::0-65535 305492 99.23% 99.23% # Table walker wait (enqueue to first request) latency 1730system.cpu1.dtb.walker.walkWaitTime::65536-131071 1236 0.40% 99.63% # Table walker wait (enqueue to first request) latency 1731system.cpu1.dtb.walker.walkWaitTime::131072-196607 840 0.27% 99.90% # Table walker wait (enqueue to first request) latency 1732system.cpu1.dtb.walker.walkWaitTime::196608-262143 161 0.05% 99.95% # Table walker wait (enqueue to first request) latency 1733system.cpu1.dtb.walker.walkWaitTime::262144-327679 48 0.02% 99.97% # Table walker wait (enqueue to first request) latency 1734system.cpu1.dtb.walker.walkWaitTime::327680-393215 59 0.02% 99.99% # Table walker wait (enqueue to first request) latency 1735system.cpu1.dtb.walker.walkWaitTime::393216-458751 20 0.01% 100.00% # Table walker wait (enqueue to first request) latency 1736system.cpu1.dtb.walker.walkWaitTime::458752-524287 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1737system.cpu1.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1738system.cpu1.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1739system.cpu1.dtb.walker.walkWaitTime::total 307870 # Table walker wait (enqueue to first request) latency 1740system.cpu1.dtb.walker.walkCompletionTime::samples 284687 # Table walker service (enqueue to completion) latency 1741system.cpu1.dtb.walker.walkCompletionTime::mean 20644.869629 # Table walker service (enqueue to completion) latency 1742system.cpu1.dtb.walker.walkCompletionTime::gmean 17424.592515 # Table walker service (enqueue to completion) latency 1743system.cpu1.dtb.walker.walkCompletionTime::stdev 21452.651975 # Table walker service (enqueue to completion) latency 1744system.cpu1.dtb.walker.walkCompletionTime::0-65535 281397 98.84% 98.84% # Table walker service (enqueue to completion) latency 1745system.cpu1.dtb.walker.walkCompletionTime::65536-131071 951 0.33% 99.18% # Table walker service (enqueue to completion) latency 1746system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1579 0.55% 99.73% # Table walker service (enqueue to completion) latency 1747system.cpu1.dtb.walker.walkCompletionTime::196608-262143 108 0.04% 99.77% # Table walker service (enqueue to completion) latency 1748system.cpu1.dtb.walker.walkCompletionTime::262144-327679 394 0.14% 99.91% # Table walker service (enqueue to completion) latency 1749system.cpu1.dtb.walker.walkCompletionTime::327680-393215 106 0.04% 99.95% # Table walker service (enqueue to completion) latency 1750system.cpu1.dtb.walker.walkCompletionTime::393216-458751 102 0.04% 99.98% # Table walker service (enqueue to completion) latency 1751system.cpu1.dtb.walker.walkCompletionTime::458752-524287 31 0.01% 99.99% # Table walker service (enqueue to completion) latency 1752system.cpu1.dtb.walker.walkCompletionTime::524288-589823 9 0.00% 100.00% # Table walker service (enqueue to completion) latency 1753system.cpu1.dtb.walker.walkCompletionTime::589824-655359 8 0.00% 100.00% # Table walker service (enqueue to completion) latency 1754system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1755system.cpu1.dtb.walker.walkCompletionTime::total 284687 # Table walker service (enqueue to completion) latency 1756system.cpu1.dtb.walker.walksPending::samples 488633591384 # Table walker pending requests distribution 1757system.cpu1.dtb.walker.walksPending::mean 0.617867 # Table walker pending requests distribution 1758system.cpu1.dtb.walker.walksPending::stdev 0.545160 # Table walker pending requests distribution 1759system.cpu1.dtb.walker.walksPending::0-1 487382306384 99.74% 99.74% # Table walker pending requests distribution 1760system.cpu1.dtb.walker.walksPending::2-3 662548500 0.14% 99.88% # Table walker pending requests distribution 1761system.cpu1.dtb.walker.walksPending::4-5 271218500 0.06% 99.94% # Table walker pending requests distribution 1762system.cpu1.dtb.walker.walksPending::6-7 131442000 0.03% 99.96% # Table walker pending requests distribution 1763system.cpu1.dtb.walker.walksPending::8-9 92501000 0.02% 99.98% # Table walker pending requests distribution 1764system.cpu1.dtb.walker.walksPending::10-11 52739500 0.01% 99.99% # Table walker pending requests distribution 1765system.cpu1.dtb.walker.walksPending::12-13 15718500 0.00% 99.99% # Table walker pending requests distribution 1766system.cpu1.dtb.walker.walksPending::14-15 24644000 0.01% 100.00% # Table walker pending requests distribution 1767system.cpu1.dtb.walker.walksPending::16-17 457500 0.00% 100.00% # Table walker pending requests distribution 1768system.cpu1.dtb.walker.walksPending::18-19 9000 0.00% 100.00% # Table walker pending requests distribution 1769system.cpu1.dtb.walker.walksPending::20-21 1000 0.00% 100.00% # Table walker pending requests distribution 1770system.cpu1.dtb.walker.walksPending::22-23 1500 0.00% 100.00% # Table walker pending requests distribution 1771system.cpu1.dtb.walker.walksPending::24-25 1500 0.00% 100.00% # Table walker pending requests distribution 1772system.cpu1.dtb.walker.walksPending::26-27 2500 0.00% 100.00% # Table walker pending requests distribution 1773system.cpu1.dtb.walker.walksPending::total 488633591384 # Table walker pending requests distribution 1774system.cpu1.dtb.walker.walkPageSizes::4K 89326 88.75% 88.75% # Table walker page sizes translated 1775system.cpu1.dtb.walker.walkPageSizes::2M 11327 11.25% 100.00% # Table walker page sizes translated 1776system.cpu1.dtb.walker.walkPageSizes::total 100653 # Table walker page sizes translated 1777system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 567287 # Table walker requests started/completed, data/inst 1778system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1779system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 567287 # Table walker requests started/completed, data/inst 1780system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 100653 # Table walker requests started/completed, data/inst 1781system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1782system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 100653 # Table walker requests started/completed, data/inst 1783system.cpu1.dtb.walker.walkRequestOrigin::total 667940 # Table walker requests started/completed, data/inst 1784system.cpu1.dtb.inst_hits 0 # ITB inst hits 1785system.cpu1.dtb.inst_misses 0 # ITB inst misses 1786system.cpu1.dtb.read_hits 99577859 # DTB read hits 1787system.cpu1.dtb.read_misses 392921 # DTB read misses 1788system.cpu1.dtb.write_hits 81911984 # DTB write hits 1789system.cpu1.dtb.write_misses 174366 # DTB write misses 1790system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1791system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1792system.cpu1.dtb.flush_tlb_mva_asid 44673 # Number of times TLB was flushed by MVA & ASID 1793system.cpu1.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID 1794system.cpu1.dtb.flush_entries 37295 # Number of entries that have been flushed from TLB 1795system.cpu1.dtb.align_faults 442 # Number of TLB faults due to alignment restrictions 1796system.cpu1.dtb.prefetch_faults 6095 # Number of TLB faults due to prefetch 1797system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1798system.cpu1.dtb.perms_faults 38665 # Number of TLB faults due to permissions restrictions 1799system.cpu1.dtb.read_accesses 99970780 # DTB read accesses 1800system.cpu1.dtb.write_accesses 82086350 # DTB write accesses 1801system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1802system.cpu1.dtb.hits 181489843 # DTB hits 1803system.cpu1.dtb.misses 567287 # DTB misses 1804system.cpu1.dtb.accesses 182057130 # DTB accesses 1805system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1806system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1807system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1808system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1809system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1810system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1811system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1812system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1813system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1814system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1815system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1816system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1817system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1818system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1819system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1820system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1821system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1822system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1823system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1824system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1825system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1826system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1827system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1828system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1829system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1830system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1831system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1832system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1833system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1834system.cpu1.itb.walker.walks 85422 # Table walker walks requested 1835system.cpu1.itb.walker.walksLong 85422 # Table walker walks initiated with long descriptors 1836system.cpu1.itb.walker.walksLongTerminationLevel::Level2 706 # Level at which table walker walks with long descriptors terminate 1837system.cpu1.itb.walker.walksLongTerminationLevel::Level3 60440 # Level at which table walker walks with long descriptors terminate 1838system.cpu1.itb.walker.walksSquashedBefore 10533 # Table walks squashed before starting 1839system.cpu1.itb.walker.walkWaitTime::samples 74889 # Table walker wait (enqueue to first request) latency 1840system.cpu1.itb.walker.walkWaitTime::mean 1637.737184 # Table walker wait (enqueue to first request) latency 1841system.cpu1.itb.walker.walkWaitTime::stdev 12543.180008 # Table walker wait (enqueue to first request) latency 1842system.cpu1.itb.walker.walkWaitTime::0-65535 74488 99.46% 99.46% # Table walker wait (enqueue to first request) latency 1843system.cpu1.itb.walker.walkWaitTime::65536-131071 92 0.12% 99.59% # Table walker wait (enqueue to first request) latency 1844system.cpu1.itb.walker.walkWaitTime::131072-196607 279 0.37% 99.96% # Table walker wait (enqueue to first request) latency 1845system.cpu1.itb.walker.walkWaitTime::196608-262143 10 0.01% 99.97% # Table walker wait (enqueue to first request) latency 1846system.cpu1.itb.walker.walkWaitTime::262144-327679 13 0.02% 99.99% # Table walker wait (enqueue to first request) latency 1847system.cpu1.itb.walker.walkWaitTime::327680-393215 5 0.01% 100.00% # Table walker wait (enqueue to first request) latency 1848system.cpu1.itb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1849system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1850system.cpu1.itb.walker.walkWaitTime::total 74889 # Table walker wait (enqueue to first request) latency 1851system.cpu1.itb.walker.walkCompletionTime::samples 71679 # Table walker service (enqueue to completion) latency 1852system.cpu1.itb.walker.walkCompletionTime::mean 26447.767128 # Table walker service (enqueue to completion) latency 1853system.cpu1.itb.walker.walkCompletionTime::gmean 22834.132885 # Table walker service (enqueue to completion) latency 1854system.cpu1.itb.walker.walkCompletionTime::stdev 26054.956905 # Table walker service (enqueue to completion) latency 1855system.cpu1.itb.walker.walkCompletionTime::0-65535 70042 97.72% 97.72% # Table walker service (enqueue to completion) latency 1856system.cpu1.itb.walker.walkCompletionTime::65536-131071 124 0.17% 97.89% # Table walker service (enqueue to completion) latency 1857system.cpu1.itb.walker.walkCompletionTime::131072-196607 1290 1.80% 99.69% # Table walker service (enqueue to completion) latency 1858system.cpu1.itb.walker.walkCompletionTime::196608-262143 62 0.09% 99.78% # Table walker service (enqueue to completion) latency 1859system.cpu1.itb.walker.walkCompletionTime::262144-327679 94 0.13% 99.91% # Table walker service (enqueue to completion) latency 1860system.cpu1.itb.walker.walkCompletionTime::327680-393215 24 0.03% 99.94% # Table walker service (enqueue to completion) latency 1861system.cpu1.itb.walker.walkCompletionTime::393216-458751 27 0.04% 99.98% # Table walker service (enqueue to completion) latency 1862system.cpu1.itb.walker.walkCompletionTime::458752-524287 10 0.01% 99.99% # Table walker service (enqueue to completion) latency 1863system.cpu1.itb.walker.walkCompletionTime::524288-589823 4 0.01% 100.00% # Table walker service (enqueue to completion) latency 1864system.cpu1.itb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1865system.cpu1.itb.walker.walkCompletionTime::total 71679 # Table walker service (enqueue to completion) latency 1866system.cpu1.itb.walker.walksPending::samples 419883309648 # Table walker pending requests distribution 1867system.cpu1.itb.walker.walksPending::mean 0.857166 # Table walker pending requests distribution 1868system.cpu1.itb.walker.walksPending::stdev 0.350104 # Table walker pending requests distribution 1869system.cpu1.itb.walker.walksPending::0 59999474576 14.29% 14.29% # Table walker pending requests distribution 1870system.cpu1.itb.walker.walksPending::1 359861735072 85.71% 99.99% # Table walker pending requests distribution 1871system.cpu1.itb.walker.walksPending::2 18604000 0.00% 100.00% # Table walker pending requests distribution 1872system.cpu1.itb.walker.walksPending::3 3422000 0.00% 100.00% # Table walker pending requests distribution 1873system.cpu1.itb.walker.walksPending::4 61500 0.00% 100.00% # Table walker pending requests distribution 1874system.cpu1.itb.walker.walksPending::5 12500 0.00% 100.00% # Table walker pending requests distribution 1875system.cpu1.itb.walker.walksPending::total 419883309648 # Table walker pending requests distribution 1876system.cpu1.itb.walker.walkPageSizes::4K 60440 98.85% 98.85% # Table walker page sizes translated 1877system.cpu1.itb.walker.walkPageSizes::2M 706 1.15% 100.00% # Table walker page sizes translated 1878system.cpu1.itb.walker.walkPageSizes::total 61146 # Table walker page sizes translated 1879system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1880system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 85422 # Table walker requests started/completed, data/inst 1881system.cpu1.itb.walker.walkRequestOrigin_Requested::total 85422 # Table walker requests started/completed, data/inst 1882system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1883system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 61146 # Table walker requests started/completed, data/inst 1884system.cpu1.itb.walker.walkRequestOrigin_Completed::total 61146 # Table walker requests started/completed, data/inst 1885system.cpu1.itb.walker.walkRequestOrigin::total 146568 # Table walker requests started/completed, data/inst 1886system.cpu1.itb.inst_hits 210903230 # ITB inst hits 1887system.cpu1.itb.inst_misses 85422 # ITB inst misses 1888system.cpu1.itb.read_hits 0 # DTB read hits 1889system.cpu1.itb.read_misses 0 # DTB read misses 1890system.cpu1.itb.write_hits 0 # DTB write hits 1891system.cpu1.itb.write_misses 0 # DTB write misses 1892system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1893system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1894system.cpu1.itb.flush_tlb_mva_asid 44673 # Number of times TLB was flushed by MVA & ASID 1895system.cpu1.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID 1896system.cpu1.itb.flush_entries 26936 # Number of entries that have been flushed from TLB 1897system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1898system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1899system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1900system.cpu1.itb.perms_faults 219212 # Number of TLB faults due to permissions restrictions 1901system.cpu1.itb.read_accesses 0 # DTB read accesses 1902system.cpu1.itb.write_accesses 0 # DTB write accesses 1903system.cpu1.itb.inst_accesses 210988652 # ITB inst accesses 1904system.cpu1.itb.hits 210903230 # DTB hits 1905system.cpu1.itb.misses 85422 # DTB misses 1906system.cpu1.itb.accesses 210988652 # DTB accesses 1907system.cpu1.numCycles 739589068 # number of cpu cycles simulated 1908system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1909system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1910system.cpu1.fetch.icacheStallCycles 87179307 # Number of cycles fetch is stalled on an Icache miss 1911system.cpu1.fetch.Insts 594353675 # Number of instructions fetch has processed 1912system.cpu1.fetch.Branches 134041815 # Number of branches that fetch encountered 1913system.cpu1.fetch.predictedBranches 79148124 # Number of branches that fetch has predicted taken 1914system.cpu1.fetch.Cycles 611930141 # Number of cycles fetch has run and was not squashing or blocked 1915system.cpu1.fetch.SquashCycles 14224484 # Number of cycles fetch has spent squashing 1916system.cpu1.fetch.TlbCycles 1980961 # Number of cycles fetch has spent waiting for tlb 1917system.cpu1.fetch.MiscStallCycles 327085 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1918system.cpu1.fetch.PendingTrapStallCycles 6413771 # Number of stall cycles due to pending traps 1919system.cpu1.fetch.PendingQuiesceStallCycles 794469 # Number of stall cycles due to pending quiesce instructions 1920system.cpu1.fetch.IcacheWaitRetryStallCycles 836341 # Number of stall cycles due to full MSHR 1921system.cpu1.fetch.CacheLines 210662459 # Number of cache lines fetched 1922system.cpu1.fetch.IcacheSquashes 1674863 # Number of outstanding Icache misses that were squashed 1923system.cpu1.fetch.ItlbSquashes 29397 # Number of outstanding ITLB misses that were squashed 1924system.cpu1.fetch.rateDist::samples 716574317 # Number of instructions fetched each cycle (Total) 1925system.cpu1.fetch.rateDist::mean 0.975535 # Number of instructions fetched each cycle (Total) 1926system.cpu1.fetch.rateDist::stdev 1.220237 # Number of instructions fetched each cycle (Total) 1927system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1928system.cpu1.fetch.rateDist::0 382171132 53.33% 53.33% # Number of instructions fetched each cycle (Total) 1929system.cpu1.fetch.rateDist::1 130053591 18.15% 71.48% # Number of instructions fetched each cycle (Total) 1930system.cpu1.fetch.rateDist::2 44058900 6.15% 77.63% # Number of instructions fetched each cycle (Total) 1931system.cpu1.fetch.rateDist::3 160290694 22.37% 100.00% # Number of instructions fetched each cycle (Total) 1932system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1933system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1934system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 1935system.cpu1.fetch.rateDist::total 716574317 # Number of instructions fetched each cycle (Total) 1936system.cpu1.fetch.branchRate 0.181238 # Number of branch fetches per cycle 1937system.cpu1.fetch.rate 0.803627 # Number of inst fetches per cycle 1938system.cpu1.decode.IdleCycles 104297157 # Number of cycles decode is idle 1939system.cpu1.decode.BlockedCycles 348522347 # Number of cycles decode is blocked 1940system.cpu1.decode.RunCycles 221906314 # Number of cycles decode is running 1941system.cpu1.decode.UnblockCycles 36809016 # Number of cycles decode is unblocking 1942system.cpu1.decode.SquashCycles 5039483 # Number of cycles decode is squashing 1943system.cpu1.decode.BranchResolved 18926425 # Number of times decode resolved a branch 1944system.cpu1.decode.BranchMispred 2113724 # Number of times decode detected a branch misprediction 1945system.cpu1.decode.DecodedInsts 618028101 # Number of instructions handled by decode 1946system.cpu1.decode.SquashedInsts 22771231 # Number of squashed instructions handled by decode 1947system.cpu1.rename.SquashCycles 5039483 # Number of cycles rename is squashing 1948system.cpu1.rename.IdleCycles 138949493 # Number of cycles rename is idle 1949system.cpu1.rename.BlockCycles 52143991 # Number of cycles rename is blocking 1950system.cpu1.rename.serializeStallCycles 230343934 # count of cycles rename stalled for serializing inst 1951system.cpu1.rename.RunCycles 223632177 # Number of cycles rename is running 1952system.cpu1.rename.UnblockCycles 66465239 # Number of cycles rename is unblocking 1953system.cpu1.rename.RenamedInsts 601445820 # Number of instructions processed by rename 1954system.cpu1.rename.SquashedInsts 5788119 # Number of squashed instructions processed by rename 1955system.cpu1.rename.ROBFullEvents 10817316 # Number of times rename has blocked due to ROB full 1956system.cpu1.rename.IQFullEvents 260401 # Number of times rename has blocked due to IQ full 1957system.cpu1.rename.LQFullEvents 332552 # Number of times rename has blocked due to LQ full 1958system.cpu1.rename.SQFullEvents 31997393 # Number of times rename has blocked due to SQ full 1959system.cpu1.rename.FullRegisterEvents 11898 # Number of times there has been no free registers 1960system.cpu1.rename.RenamedOperands 571172784 # Number of destination operands rename has renamed 1961system.cpu1.rename.RenameLookups 925552885 # Number of register rename lookups that rename has made 1962system.cpu1.rename.int_rename_lookups 711516112 # Number of integer rename lookups 1963system.cpu1.rename.fp_rename_lookups 817303 # Number of floating rename lookups 1964system.cpu1.rename.CommittedMaps 514566329 # Number of HB maps that are committed 1965system.cpu1.rename.UndoneMaps 56606455 # Number of HB maps that are undone due to squashing 1966system.cpu1.rename.serializingInsts 15686724 # count of serializing insts renamed 1967system.cpu1.rename.tempSerializingInsts 13790746 # count of temporary serializing insts renamed 1968system.cpu1.rename.skidInsts 74346046 # count of insts added to the skid buffer 1969system.cpu1.memDep0.insertedLoads 99668213 # Number of loads inserted to the mem dependence unit. 1970system.cpu1.memDep0.insertedStores 85253354 # Number of stores inserted to the mem dependence unit. 1971system.cpu1.memDep0.conflictingLoads 9496006 # Number of conflicting loads. 1972system.cpu1.memDep0.conflictingStores 8106709 # Number of conflicting stores. 1973system.cpu1.iq.iqInstsAdded 579162522 # Number of instructions added to the IQ (excludes non-spec) 1974system.cpu1.iq.iqNonSpecInstsAdded 15985308 # Number of non-speculative instructions added to the IQ 1975system.cpu1.iq.iqInstsIssued 584188542 # Number of instructions issued 1976system.cpu1.iq.iqSquashedInstsIssued 2667167 # Number of squashed instructions issued 1977system.cpu1.iq.iqSquashedInstsExamined 53686437 # Number of squashed instructions iterated over during squash; mainly for profiling 1978system.cpu1.iq.iqSquashedOperandsExamined 34500302 # Number of squashed operands that are examined and possibly removed from graph 1979system.cpu1.iq.iqSquashedNonSpecRemoved 290258 # Number of squashed non-spec instructions that were removed 1980system.cpu1.iq.issued_per_cycle::samples 716574317 # Number of insts issued each cycle 1981system.cpu1.iq.issued_per_cycle::mean 0.815252 # Number of insts issued each cycle 1982system.cpu1.iq.issued_per_cycle::stdev 1.066417 # Number of insts issued each cycle 1983system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1984system.cpu1.iq.issued_per_cycle::0 397414827 55.46% 55.46% # Number of insts issued each cycle 1985system.cpu1.iq.issued_per_cycle::1 134713914 18.80% 74.26% # Number of insts issued each cycle 1986system.cpu1.iq.issued_per_cycle::2 111740906 15.59% 89.85% # Number of insts issued each cycle 1987system.cpu1.iq.issued_per_cycle::3 64830862 9.05% 98.90% # Number of insts issued each cycle 1988system.cpu1.iq.issued_per_cycle::4 7868810 1.10% 100.00% # Number of insts issued each cycle 1989system.cpu1.iq.issued_per_cycle::5 4998 0.00% 100.00% # Number of insts issued each cycle 1990system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1991system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1992system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1993system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1994system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 1995system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 1996system.cpu1.iq.issued_per_cycle::total 716574317 # Number of insts issued each cycle 1997system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 1998system.cpu1.iq.fu_full::IntAlu 59065524 44.03% 44.03% # attempts to use FU when none available 1999system.cpu1.iq.fu_full::IntMult 54166 0.04% 44.07% # attempts to use FU when none available 2000system.cpu1.iq.fu_full::IntDiv 19277 0.01% 44.09% # attempts to use FU when none available 2001system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.09% # attempts to use FU when none available 2002system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.09% # attempts to use FU when none available 2003system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.09% # attempts to use FU when none available 2004system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.09% # attempts to use FU when none available 2005system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.09% # attempts to use FU when none available 2006system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.09% # attempts to use FU when none available 2007system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.09% # attempts to use FU when none available 2008system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.09% # attempts to use FU when none available 2009system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.09% # attempts to use FU when none available 2010system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.09% # attempts to use FU when none available 2011system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.09% # attempts to use FU when none available 2012system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.09% # attempts to use FU when none available 2013system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.09% # attempts to use FU when none available 2014system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.09% # attempts to use FU when none available 2015system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.09% # attempts to use FU when none available 2016system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.09% # attempts to use FU when none available 2017system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.09% # attempts to use FU when none available 2018system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.09% # attempts to use FU when none available 2019system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.09% # attempts to use FU when none available 2020system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.09% # attempts to use FU when none available 2021system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.09% # attempts to use FU when none available 2022system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.09% # attempts to use FU when none available 2023system.cpu1.iq.fu_full::SimdFloatMisc 22 0.00% 44.09% # attempts to use FU when none available 2024system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.09% # attempts to use FU when none available 2025system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.09% # attempts to use FU when none available 2026system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.09% # attempts to use FU when none available 2027system.cpu1.iq.fu_full::MemRead 36039894 26.87% 70.95% # attempts to use FU when none available 2028system.cpu1.iq.fu_full::MemWrite 38965641 29.05% 100.00% # attempts to use FU when none available 2029system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2030system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 2031system.cpu1.iq.FU_type_0::No_OpClass 40 0.00% 0.00% # Type of FU issued 2032system.cpu1.iq.FU_type_0::IntAlu 396970173 67.95% 67.95% # Type of FU issued 2033system.cpu1.iq.FU_type_0::IntMult 1317793 0.23% 68.18% # Type of FU issued 2034system.cpu1.iq.FU_type_0::IntDiv 74565 0.01% 68.19% # Type of FU issued 2035system.cpu1.iq.FU_type_0::FloatAdd 1 0.00% 68.19% # Type of FU issued 2036system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.19% # Type of FU issued 2037system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.19% # Type of FU issued 2038system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.19% # Type of FU issued 2039system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.19% # Type of FU issued 2040system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.19% # Type of FU issued 2041system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.19% # Type of FU issued 2042system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.19% # Type of FU issued 2043system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.19% # Type of FU issued 2044system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.19% # Type of FU issued 2045system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.19% # Type of FU issued 2046system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.19% # Type of FU issued 2047system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.19% # Type of FU issued 2048system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.19% # Type of FU issued 2049system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.19% # Type of FU issued 2050system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.19% # Type of FU issued 2051system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.19% # Type of FU issued 2052system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.19% # Type of FU issued 2053system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.19% # Type of FU issued 2054system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.19% # Type of FU issued 2055system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.19% # Type of FU issued 2056system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.19% # Type of FU issued 2057system.cpu1.iq.FU_type_0::SimdFloatMisc 84907 0.01% 68.21% # Type of FU issued 2058system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.21% # Type of FU issued 2059system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.21% # Type of FU issued 2060system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.21% # Type of FU issued 2061system.cpu1.iq.FU_type_0::MemRead 102569706 17.56% 85.76% # Type of FU issued 2062system.cpu1.iq.FU_type_0::MemWrite 83171310 14.24% 100.00% # Type of FU issued 2063system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2064system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2065system.cpu1.iq.FU_type_0::total 584188542 # Type of FU issued 2066system.cpu1.iq.rate 0.789883 # Inst issue rate 2067system.cpu1.iq.fu_busy_cnt 134144524 # FU busy when requested 2068system.cpu1.iq.fu_busy_rate 0.229625 # FU busy rate (busy events/executed inst) 2069system.cpu1.iq.int_inst_queue_reads 2020390722 # Number of integer instruction queue reads 2070system.cpu1.iq.int_inst_queue_writes 648436438 # Number of integer instruction queue writes 2071system.cpu1.iq.int_inst_queue_wakeup_accesses 567390385 # Number of integer instruction queue wakeup accesses 2072system.cpu1.iq.fp_inst_queue_reads 1372370 # Number of floating instruction queue reads 2073system.cpu1.iq.fp_inst_queue_writes 557189 # Number of floating instruction queue writes 2074system.cpu1.iq.fp_inst_queue_wakeup_accesses 510457 # Number of floating instruction queue wakeup accesses 2075system.cpu1.iq.int_alu_accesses 717484509 # Number of integer alu accesses 2076system.cpu1.iq.fp_alu_accesses 848517 # Number of floating point alu accesses 2077system.cpu1.iew.lsq.thread0.forwLoads 2681981 # Number of loads that had data forwarded from stores 2078system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2079system.cpu1.iew.lsq.thread0.squashedLoads 12380566 # Number of loads squashed 2080system.cpu1.iew.lsq.thread0.ignoredResponses 16529 # Number of memory responses ignored because the instruction is squashed 2081system.cpu1.iew.lsq.thread0.memOrderViolation 160745 # Number of memory ordering violations 2082system.cpu1.iew.lsq.thread0.squashedStores 5876169 # Number of stores squashed 2083system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2084system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2085system.cpu1.iew.lsq.thread0.rescheduledLoads 2772484 # Number of loads that were rescheduled 2086system.cpu1.iew.lsq.thread0.cacheBlocked 4108210 # Number of times an access to memory failed due to the cache being blocked 2087system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2088system.cpu1.iew.iewSquashCycles 5039483 # Number of cycles IEW is squashing 2089system.cpu1.iew.iewBlockCycles 6511130 # Number of cycles IEW is blocking 2090system.cpu1.iew.iewUnblockCycles 2319208 # Number of cycles IEW is unblocking 2091system.cpu1.iew.iewDispatchedInsts 595271017 # Number of instructions dispatched to IQ 2092system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 2093system.cpu1.iew.iewDispLoadInsts 99668213 # Number of dispatched load instructions 2094system.cpu1.iew.iewDispStoreInsts 85253354 # Number of dispatched store instructions 2095system.cpu1.iew.iewDispNonSpecInsts 13572161 # Number of dispatched non-speculative instructions 2096system.cpu1.iew.iewIQFullEvents 64444 # Number of times the IQ has become full, causing a stall 2097system.cpu1.iew.iewLSQFullEvents 2193101 # Number of times the LSQ has become full, causing a stall 2098system.cpu1.iew.memOrderViolationEvents 160745 # Number of memory order violations 2099system.cpu1.iew.predictedTakenIncorrect 2023154 # Number of branches that were predicted taken incorrectly 2100system.cpu1.iew.predictedNotTakenIncorrect 2795718 # Number of branches that were predicted not taken incorrectly 2101system.cpu1.iew.branchMispredicts 4818872 # Number of branch mispredicts detected at execute 2102system.cpu1.iew.iewExecutedInsts 576621181 # Number of executed instructions 2103system.cpu1.iew.iewExecLoadInsts 99570735 # Number of load instructions executed 2104system.cpu1.iew.iewExecSquashedInsts 7012433 # Number of squashed instructions skipped in execute 2105system.cpu1.iew.exec_swp 0 # number of swp insts executed 2106system.cpu1.iew.exec_nop 123187 # number of nop insts executed 2107system.cpu1.iew.exec_refs 181482515 # number of memory reference insts executed 2108system.cpu1.iew.exec_branches 107903719 # Number of branches executed 2109system.cpu1.iew.exec_stores 81911780 # Number of stores executed 2110system.cpu1.iew.exec_rate 0.779651 # Inst execution rate 2111system.cpu1.iew.wb_sent 568628901 # cumulative count of insts sent to commit 2112system.cpu1.iew.wb_count 567900842 # cumulative count of insts written-back 2113system.cpu1.iew.wb_producers 274880956 # num instructions producing a value 2114system.cpu1.iew.wb_consumers 450165977 # num instructions consuming a value 2115system.cpu1.iew.wb_rate 0.767860 # insts written-back per cycle 2116system.cpu1.iew.wb_fanout 0.610621 # average fanout of values written-back 2117system.cpu1.commit.commitSquashedInsts 47031076 # The number of squashed insts skipped by commit 2118system.cpu1.commit.commitNonSpecStalls 15695050 # The number of times commit has been forced to stall to communicate backwards 2119system.cpu1.commit.branchMispredicts 4536258 # The number of times a branch was mispredicted 2120system.cpu1.commit.committed_per_cycle::samples 707685383 # Number of insts commited each cycle 2121system.cpu1.commit.committed_per_cycle::mean 0.765116 # Number of insts commited each cycle 2122system.cpu1.commit.committed_per_cycle::stdev 1.566861 # Number of insts commited each cycle 2123system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2124system.cpu1.commit.committed_per_cycle::0 470367960 66.47% 66.47% # Number of insts commited each cycle 2125system.cpu1.commit.committed_per_cycle::1 123401303 17.44% 83.90% # Number of insts commited each cycle 2126system.cpu1.commit.committed_per_cycle::2 52359305 7.40% 91.30% # Number of insts commited each cycle 2127system.cpu1.commit.committed_per_cycle::3 17652538 2.49% 93.80% # Number of insts commited each cycle 2128system.cpu1.commit.committed_per_cycle::4 12497517 1.77% 95.56% # Number of insts commited each cycle 2129system.cpu1.commit.committed_per_cycle::5 8502383 1.20% 96.76% # Number of insts commited each cycle 2130system.cpu1.commit.committed_per_cycle::6 5935480 0.84% 97.60% # Number of insts commited each cycle 2131system.cpu1.commit.committed_per_cycle::7 3482174 0.49% 98.09% # Number of insts commited each cycle 2132system.cpu1.commit.committed_per_cycle::8 13486723 1.91% 100.00% # Number of insts commited each cycle 2133system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2134system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2135system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2136system.cpu1.commit.committed_per_cycle::total 707685383 # Number of insts commited each cycle 2137system.cpu1.commit.committedInsts 459224264 # Number of instructions committed 2138system.cpu1.commit.committedOps 541461392 # Number of ops (including micro ops) committed 2139system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 2140system.cpu1.commit.refs 166664832 # Number of memory references committed 2141system.cpu1.commit.loads 87287647 # Number of loads committed 2142system.cpu1.commit.membars 3905531 # Number of memory barriers committed 2143system.cpu1.commit.branches 102374979 # Number of branches committed 2144system.cpu1.commit.fp_insts 497703 # Number of committed floating point instructions. 2145system.cpu1.commit.int_insts 497469676 # Number of committed integer instructions. 2146system.cpu1.commit.function_calls 13371734 # Number of function calls committed. 2147system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 2148system.cpu1.commit.op_class_0::IntAlu 373594883 69.00% 69.00% # Class of committed instruction 2149system.cpu1.commit.op_class_0::IntMult 1066183 0.20% 69.19% # Class of committed instruction 2150system.cpu1.commit.op_class_0::IntDiv 59540 0.01% 69.21% # Class of committed instruction 2151system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.21% # Class of committed instruction 2152system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.21% # Class of committed instruction 2153system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.21% # Class of committed instruction 2154system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.21% # Class of committed instruction 2155system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.21% # Class of committed instruction 2156system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.21% # Class of committed instruction 2157system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.21% # Class of committed instruction 2158system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.21% # Class of committed instruction 2159system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.21% # Class of committed instruction 2160system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.21% # Class of committed instruction 2161system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.21% # Class of committed instruction 2162system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.21% # Class of committed instruction 2163system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.21% # Class of committed instruction 2164system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.21% # Class of committed instruction 2165system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.21% # Class of committed instruction 2166system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.21% # Class of committed instruction 2167system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.21% # Class of committed instruction 2168system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.21% # Class of committed instruction 2169system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.21% # Class of committed instruction 2170system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.21% # Class of committed instruction 2171system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.21% # Class of committed instruction 2172system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.21% # Class of committed instruction 2173system.cpu1.commit.op_class_0::SimdFloatMisc 75912 0.01% 69.22% # Class of committed instruction 2174system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.22% # Class of committed instruction 2175system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.22% # Class of committed instruction 2176system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.22% # Class of committed instruction 2177system.cpu1.commit.op_class_0::MemRead 87287647 16.12% 85.34% # Class of committed instruction 2178system.cpu1.commit.op_class_0::MemWrite 79377185 14.66% 100.00% # Class of committed instruction 2179system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2180system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 2181system.cpu1.commit.op_class_0::total 541461392 # Class of committed instruction 2182system.cpu1.commit.bw_lim_events 13486723 # number cycles where commit BW limit reached 2183system.cpu1.rob.rob_reads 1278856692 # The number of ROB reads 2184system.cpu1.rob.rob_writes 1185834230 # The number of ROB writes 2185system.cpu1.timesIdled 958439 # Number of times that the entire CPU went into an idle state and unscheduled itself 2186system.cpu1.idleCycles 23014751 # Total number of cycles that the CPU has spent unscheduled due to idling 2187system.cpu1.quiesceCycles 94048355585 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2188system.cpu1.committedInsts 459224264 # Number of Instructions Simulated 2189system.cpu1.committedOps 541461392 # Number of Ops (including micro ops) Simulated 2190system.cpu1.cpi 1.610518 # CPI: Cycles Per Instruction 2191system.cpu1.cpi_total 1.610518 # CPI: Total CPI of All Threads 2192system.cpu1.ipc 0.620918 # IPC: Instructions Per Cycle 2193system.cpu1.ipc_total 0.620918 # IPC: Total IPC of All Threads 2194system.cpu1.int_regfile_reads 681935687 # number of integer regfile reads 2195system.cpu1.int_regfile_writes 403917801 # number of integer regfile writes 2196system.cpu1.fp_regfile_reads 803668 # number of floating regfile reads 2197system.cpu1.fp_regfile_writes 473340 # number of floating regfile writes 2198system.cpu1.cc_regfile_reads 122826591 # number of cc regfile reads 2199system.cpu1.cc_regfile_writes 123738784 # number of cc regfile writes 2200system.cpu1.misc_regfile_reads 1267794356 # number of misc regfile reads 2201system.cpu1.misc_regfile_writes 15807378 # number of misc regfile writes 2202system.cpu1.dcache.tags.replacements 5498905 # number of replacements 2203system.cpu1.dcache.tags.tagsinuse 458.394450 # Cycle average of tags in use 2204system.cpu1.dcache.tags.total_refs 155608106 # Total number of references to valid blocks. 2205system.cpu1.dcache.tags.sampled_refs 5499414 # Sample count of references to valid blocks. 2206system.cpu1.dcache.tags.avg_refs 28.295398 # Average number of references to valid blocks. 2207system.cpu1.dcache.tags.warmup_cycle 8486277940000 # Cycle when the warmup percentage was hit. 2208system.cpu1.dcache.tags.occ_blocks::cpu1.data 458.394450 # Average occupied blocks per requestor 2209system.cpu1.dcache.tags.occ_percent::cpu1.data 0.895302 # Average percentage of cache occupancy 2210system.cpu1.dcache.tags.occ_percent::total 0.895302 # Average percentage of cache occupancy 2211system.cpu1.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id 2212system.cpu1.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 2213system.cpu1.dcache.tags.age_task_id_blocks_1024::1 416 # Occupied blocks per task id 2214system.cpu1.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id 2215system.cpu1.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id 2216system.cpu1.dcache.tags.tag_accesses 345701865 # Number of tag accesses 2217system.cpu1.dcache.tags.data_accesses 345701865 # Number of data accesses 2218system.cpu1.dcache.ReadReq_hits::cpu1.data 81166944 # number of ReadReq hits 2219system.cpu1.dcache.ReadReq_hits::total 81166944 # number of ReadReq hits 2220system.cpu1.dcache.WriteReq_hits::cpu1.data 69652711 # number of WriteReq hits 2221system.cpu1.dcache.WriteReq_hits::total 69652711 # number of WriteReq hits 2222system.cpu1.dcache.SoftPFReq_hits::cpu1.data 179570 # number of SoftPFReq hits 2223system.cpu1.dcache.SoftPFReq_hits::total 179570 # number of SoftPFReq hits 2224system.cpu1.dcache.WriteLineReq_hits::cpu1.data 55554 # number of WriteLineReq hits 2225system.cpu1.dcache.WriteLineReq_hits::total 55554 # number of WriteLineReq hits 2226system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1867218 # number of LoadLockedReq hits 2227system.cpu1.dcache.LoadLockedReq_hits::total 1867218 # number of LoadLockedReq hits 2228system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1906025 # number of StoreCondReq hits 2229system.cpu1.dcache.StoreCondReq_hits::total 1906025 # number of StoreCondReq hits 2230system.cpu1.dcache.demand_hits::cpu1.data 150819655 # number of demand (read+write) hits 2231system.cpu1.dcache.demand_hits::total 150819655 # number of demand (read+write) hits 2232system.cpu1.dcache.overall_hits::cpu1.data 150999225 # number of overall hits 2233system.cpu1.dcache.overall_hits::total 150999225 # number of overall hits 2234system.cpu1.dcache.ReadReq_misses::cpu1.data 6513815 # number of ReadReq misses 2235system.cpu1.dcache.ReadReq_misses::total 6513815 # number of ReadReq misses 2236system.cpu1.dcache.WriteReq_misses::cpu1.data 7138740 # number of WriteReq misses 2237system.cpu1.dcache.WriteReq_misses::total 7138740 # number of WriteReq misses 2238system.cpu1.dcache.SoftPFReq_misses::cpu1.data 666746 # number of SoftPFReq misses 2239system.cpu1.dcache.SoftPFReq_misses::total 666746 # number of SoftPFReq misses 2240system.cpu1.dcache.WriteLineReq_misses::cpu1.data 433208 # number of WriteLineReq misses 2241system.cpu1.dcache.WriteLineReq_misses::total 433208 # number of WriteLineReq misses 2242system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 280157 # number of LoadLockedReq misses 2243system.cpu1.dcache.LoadLockedReq_misses::total 280157 # number of LoadLockedReq misses 2244system.cpu1.dcache.StoreCondReq_misses::cpu1.data 195063 # number of StoreCondReq misses 2245system.cpu1.dcache.StoreCondReq_misses::total 195063 # number of StoreCondReq misses 2246system.cpu1.dcache.demand_misses::cpu1.data 13652555 # number of demand (read+write) misses 2247system.cpu1.dcache.demand_misses::total 13652555 # number of demand (read+write) misses 2248system.cpu1.dcache.overall_misses::cpu1.data 14319301 # number of overall misses 2249system.cpu1.dcache.overall_misses::total 14319301 # number of overall misses 2250system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 107790302500 # number of ReadReq miss cycles 2251system.cpu1.dcache.ReadReq_miss_latency::total 107790302500 # number of ReadReq miss cycles 2252system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 154935306923 # number of WriteReq miss cycles 2253system.cpu1.dcache.WriteReq_miss_latency::total 154935306923 # number of WriteReq miss cycles 2254system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 17952138757 # number of WriteLineReq miss cycles 2255system.cpu1.dcache.WriteLineReq_miss_latency::total 17952138757 # number of WriteLineReq miss cycles 2256system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 4403404000 # number of LoadLockedReq miss cycles 2257system.cpu1.dcache.LoadLockedReq_miss_latency::total 4403404000 # number of LoadLockedReq miss cycles 2258system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5419622500 # number of StoreCondReq miss cycles 2259system.cpu1.dcache.StoreCondReq_miss_latency::total 5419622500 # number of StoreCondReq miss cycles 2260system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3200000 # number of StoreCondFailReq miss cycles 2261system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3200000 # number of StoreCondFailReq miss cycles 2262system.cpu1.dcache.demand_miss_latency::cpu1.data 262725609423 # number of demand (read+write) miss cycles 2263system.cpu1.dcache.demand_miss_latency::total 262725609423 # number of demand (read+write) miss cycles 2264system.cpu1.dcache.overall_miss_latency::cpu1.data 262725609423 # number of overall miss cycles 2265system.cpu1.dcache.overall_miss_latency::total 262725609423 # number of overall miss cycles 2266system.cpu1.dcache.ReadReq_accesses::cpu1.data 87680759 # number of ReadReq accesses(hits+misses) 2267system.cpu1.dcache.ReadReq_accesses::total 87680759 # number of ReadReq accesses(hits+misses) 2268system.cpu1.dcache.WriteReq_accesses::cpu1.data 76791451 # number of WriteReq accesses(hits+misses) 2269system.cpu1.dcache.WriteReq_accesses::total 76791451 # number of WriteReq accesses(hits+misses) 2270system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 846316 # number of SoftPFReq accesses(hits+misses) 2271system.cpu1.dcache.SoftPFReq_accesses::total 846316 # number of SoftPFReq accesses(hits+misses) 2272system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 488762 # number of WriteLineReq accesses(hits+misses) 2273system.cpu1.dcache.WriteLineReq_accesses::total 488762 # number of WriteLineReq accesses(hits+misses) 2274system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2147375 # number of LoadLockedReq accesses(hits+misses) 2275system.cpu1.dcache.LoadLockedReq_accesses::total 2147375 # number of LoadLockedReq accesses(hits+misses) 2276system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2101088 # number of StoreCondReq accesses(hits+misses) 2277system.cpu1.dcache.StoreCondReq_accesses::total 2101088 # number of StoreCondReq accesses(hits+misses) 2278system.cpu1.dcache.demand_accesses::cpu1.data 164472210 # number of demand (read+write) accesses 2279system.cpu1.dcache.demand_accesses::total 164472210 # number of demand (read+write) accesses 2280system.cpu1.dcache.overall_accesses::cpu1.data 165318526 # number of overall (read+write) accesses 2281system.cpu1.dcache.overall_accesses::total 165318526 # number of overall (read+write) accesses 2282system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074290 # miss rate for ReadReq accesses 2283system.cpu1.dcache.ReadReq_miss_rate::total 0.074290 # miss rate for ReadReq accesses 2284system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.092963 # miss rate for WriteReq accesses 2285system.cpu1.dcache.WriteReq_miss_rate::total 0.092963 # miss rate for WriteReq accesses 2286system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.787822 # miss rate for SoftPFReq accesses 2287system.cpu1.dcache.SoftPFReq_miss_rate::total 0.787822 # miss rate for SoftPFReq accesses 2288system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.886337 # miss rate for WriteLineReq accesses 2289system.cpu1.dcache.WriteLineReq_miss_rate::total 0.886337 # miss rate for WriteLineReq accesses 2290system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.130465 # miss rate for LoadLockedReq accesses 2291system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.130465 # miss rate for LoadLockedReq accesses 2292system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.092839 # miss rate for StoreCondReq accesses 2293system.cpu1.dcache.StoreCondReq_miss_rate::total 0.092839 # miss rate for StoreCondReq accesses 2294system.cpu1.dcache.demand_miss_rate::cpu1.data 0.083008 # miss rate for demand accesses 2295system.cpu1.dcache.demand_miss_rate::total 0.083008 # miss rate for demand accesses 2296system.cpu1.dcache.overall_miss_rate::cpu1.data 0.086616 # miss rate for overall accesses 2297system.cpu1.dcache.overall_miss_rate::total 0.086616 # miss rate for overall accesses 2298system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16547.952697 # average ReadReq miss latency 2299system.cpu1.dcache.ReadReq_avg_miss_latency::total 16547.952697 # average ReadReq miss latency 2300system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21703.452839 # average WriteReq miss latency 2301system.cpu1.dcache.WriteReq_avg_miss_latency::total 21703.452839 # average WriteReq miss latency 2302system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 41439.998239 # average WriteLineReq miss latency 2303system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 41439.998239 # average WriteLineReq miss latency 2304system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15717.629758 # average LoadLockedReq miss latency 2305system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15717.629758 # average LoadLockedReq miss latency 2306system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27783.959541 # average StoreCondReq miss latency 2307system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27783.959541 # average StoreCondReq miss latency 2308system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2309system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 2310system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19243.695369 # average overall miss latency 2311system.cpu1.dcache.demand_avg_miss_latency::total 19243.695369 # average overall miss latency 2312system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18347.656036 # average overall miss latency 2313system.cpu1.dcache.overall_avg_miss_latency::total 18347.656036 # average overall miss latency 2314system.cpu1.dcache.blocked_cycles::no_mshrs 4719493 # number of cycles access was blocked 2315system.cpu1.dcache.blocked_cycles::no_targets 24576154 # number of cycles access was blocked 2316system.cpu1.dcache.blocked::no_mshrs 351674 # number of cycles access was blocked 2317system.cpu1.dcache.blocked::no_targets 713575 # number of cycles access was blocked 2318system.cpu1.dcache.avg_blocked_cycles::no_mshrs 13.420079 # average number of cycles each access was blocked 2319system.cpu1.dcache.avg_blocked_cycles::no_targets 34.440884 # average number of cycles each access was blocked 2320system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2321system.cpu1.dcache.cache_copies 0 # number of cache copies performed 2322system.cpu1.dcache.writebacks::writebacks 5498938 # number of writebacks 2323system.cpu1.dcache.writebacks::total 5498938 # number of writebacks 2324system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3304670 # number of ReadReq MSHR hits 2325system.cpu1.dcache.ReadReq_mshr_hits::total 3304670 # number of ReadReq MSHR hits 2326system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5753104 # number of WriteReq MSHR hits 2327system.cpu1.dcache.WriteReq_mshr_hits::total 5753104 # number of WriteReq MSHR hits 2328system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3561 # number of WriteLineReq MSHR hits 2329system.cpu1.dcache.WriteLineReq_mshr_hits::total 3561 # number of WriteLineReq MSHR hits 2330system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 144550 # number of LoadLockedReq MSHR hits 2331system.cpu1.dcache.LoadLockedReq_mshr_hits::total 144550 # number of LoadLockedReq MSHR hits 2332system.cpu1.dcache.demand_mshr_hits::cpu1.data 9057774 # number of demand (read+write) MSHR hits 2333system.cpu1.dcache.demand_mshr_hits::total 9057774 # number of demand (read+write) MSHR hits 2334system.cpu1.dcache.overall_mshr_hits::cpu1.data 9057774 # number of overall MSHR hits 2335system.cpu1.dcache.overall_mshr_hits::total 9057774 # number of overall MSHR hits 2336system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3209145 # number of ReadReq MSHR misses 2337system.cpu1.dcache.ReadReq_mshr_misses::total 3209145 # number of ReadReq MSHR misses 2338system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1385636 # number of WriteReq MSHR misses 2339system.cpu1.dcache.WriteReq_mshr_misses::total 1385636 # number of WriteReq MSHR misses 2340system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 666638 # number of SoftPFReq MSHR misses 2341system.cpu1.dcache.SoftPFReq_mshr_misses::total 666638 # number of SoftPFReq MSHR misses 2342system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 429647 # number of WriteLineReq MSHR misses 2343system.cpu1.dcache.WriteLineReq_mshr_misses::total 429647 # number of WriteLineReq MSHR misses 2344system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 135607 # number of LoadLockedReq MSHR misses 2345system.cpu1.dcache.LoadLockedReq_mshr_misses::total 135607 # number of LoadLockedReq MSHR misses 2346system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195058 # number of StoreCondReq MSHR misses 2347system.cpu1.dcache.StoreCondReq_mshr_misses::total 195058 # number of StoreCondReq MSHR misses 2348system.cpu1.dcache.demand_mshr_misses::cpu1.data 4594781 # number of demand (read+write) MSHR misses 2349system.cpu1.dcache.demand_mshr_misses::total 4594781 # number of demand (read+write) MSHR misses 2350system.cpu1.dcache.overall_mshr_misses::cpu1.data 5261419 # number of overall MSHR misses 2351system.cpu1.dcache.overall_mshr_misses::total 5261419 # number of overall MSHR misses 2352system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 6299 # number of ReadReq MSHR uncacheable 2353system.cpu1.dcache.ReadReq_mshr_uncacheable::total 6299 # number of ReadReq MSHR uncacheable 2354system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 6428 # number of WriteReq MSHR uncacheable 2355system.cpu1.dcache.WriteReq_mshr_uncacheable::total 6428 # number of WriteReq MSHR uncacheable 2356system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 12727 # number of overall MSHR uncacheable misses 2357system.cpu1.dcache.overall_mshr_uncacheable_misses::total 12727 # number of overall MSHR uncacheable misses 2358system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 49159510500 # number of ReadReq MSHR miss cycles 2359system.cpu1.dcache.ReadReq_mshr_miss_latency::total 49159510500 # number of ReadReq MSHR miss cycles 2360system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 33253300624 # number of WriteReq MSHR miss cycles 2361system.cpu1.dcache.WriteReq_mshr_miss_latency::total 33253300624 # number of WriteReq MSHR miss cycles 2362system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15899737000 # number of SoftPFReq MSHR miss cycles 2363system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15899737000 # number of SoftPFReq MSHR miss cycles 2364system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 17350623757 # number of WriteLineReq MSHR miss cycles 2365system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 17350623757 # number of WriteLineReq MSHR miss cycles 2366system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1958308000 # number of LoadLockedReq MSHR miss cycles 2367system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1958308000 # number of LoadLockedReq MSHR miss cycles 2368system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5224605500 # number of StoreCondReq MSHR miss cycles 2369system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5224605500 # number of StoreCondReq MSHR miss cycles 2370system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3159000 # number of StoreCondFailReq MSHR miss cycles 2371system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3159000 # number of StoreCondFailReq MSHR miss cycles 2372system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 82412811124 # number of demand (read+write) MSHR miss cycles 2373system.cpu1.dcache.demand_mshr_miss_latency::total 82412811124 # number of demand (read+write) MSHR miss cycles 2374system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 98312548124 # number of overall MSHR miss cycles 2375system.cpu1.dcache.overall_mshr_miss_latency::total 98312548124 # number of overall MSHR miss cycles 2376system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 727883500 # number of ReadReq MSHR uncacheable cycles 2377system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 727883500 # number of ReadReq MSHR uncacheable cycles 2378system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 859834500 # number of WriteReq MSHR uncacheable cycles 2379system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 859834500 # number of WriteReq MSHR uncacheable cycles 2380system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1587718000 # number of overall MSHR uncacheable cycles 2381system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1587718000 # number of overall MSHR uncacheable cycles 2382system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036600 # mshr miss rate for ReadReq accesses 2383system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036600 # mshr miss rate for ReadReq accesses 2384system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018044 # mshr miss rate for WriteReq accesses 2385system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018044 # mshr miss rate for WriteReq accesses 2386system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.787694 # mshr miss rate for SoftPFReq accesses 2387system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.787694 # mshr miss rate for SoftPFReq accesses 2388system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.879052 # mshr miss rate for WriteLineReq accesses 2389system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.879052 # mshr miss rate for WriteLineReq accesses 2390system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063150 # mshr miss rate for LoadLockedReq accesses 2391system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063150 # mshr miss rate for LoadLockedReq accesses 2392system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.092837 # mshr miss rate for StoreCondReq accesses 2393system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.092837 # mshr miss rate for StoreCondReq accesses 2394system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027937 # mshr miss rate for demand accesses 2395system.cpu1.dcache.demand_mshr_miss_rate::total 0.027937 # mshr miss rate for demand accesses 2396system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031826 # mshr miss rate for overall accesses 2397system.cpu1.dcache.overall_mshr_miss_rate::total 0.031826 # mshr miss rate for overall accesses 2398system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15318.569432 # average ReadReq mshr miss latency 2399system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15318.569432 # average ReadReq mshr miss latency 2400system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23998.583051 # average WriteReq mshr miss latency 2401system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23998.583051 # average WriteReq mshr miss latency 2402system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23850.631077 # average SoftPFReq mshr miss latency 2403system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23850.631077 # average SoftPFReq mshr miss latency 2404system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 40383.439794 # average WriteLineReq mshr miss latency 2405system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 40383.439794 # average WriteLineReq mshr miss latency 2406system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14441.053928 # average LoadLockedReq mshr miss latency 2407system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14441.053928 # average LoadLockedReq mshr miss latency 2408system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26784.881933 # average StoreCondReq mshr miss latency 2409system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26784.881933 # average StoreCondReq mshr miss latency 2410system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2411system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 2412system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17936.178269 # average overall mshr miss latency 2413system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17936.178269 # average overall mshr miss latency 2414system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18685.557665 # average overall mshr miss latency 2415system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18685.557665 # average overall mshr miss latency 2416system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 115555.405620 # average ReadReq mshr uncacheable latency 2417system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 115555.405620 # average ReadReq mshr uncacheable latency 2418system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 133763.923460 # average WriteReq mshr uncacheable latency 2419system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 133763.923460 # average WriteReq mshr uncacheable latency 2420system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 124751.944685 # average overall mshr uncacheable latency 2421system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 124751.944685 # average overall mshr uncacheable latency 2422system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2423system.cpu1.icache.tags.replacements 5972259 # number of replacements 2424system.cpu1.icache.tags.tagsinuse 501.613786 # Cycle average of tags in use 2425system.cpu1.icache.tags.total_refs 204337040 # Total number of references to valid blocks. 2426system.cpu1.icache.tags.sampled_refs 5972771 # Sample count of references to valid blocks. 2427system.cpu1.icache.tags.avg_refs 34.211431 # Average number of references to valid blocks. 2428system.cpu1.icache.tags.warmup_cycle 8525956583000 # Cycle when the warmup percentage was hit. 2429system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.613786 # Average occupied blocks per requestor 2430system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979714 # Average percentage of cache occupancy 2431system.cpu1.icache.tags.occ_percent::total 0.979714 # Average percentage of cache occupancy 2432system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2433system.cpu1.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 2434system.cpu1.icache.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id 2435system.cpu1.icache.tags.age_task_id_blocks_1024::2 99 # Occupied blocks per task id 2436system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2437system.cpu1.icache.tags.tag_accesses 427283163 # Number of tag accesses 2438system.cpu1.icache.tags.data_accesses 427283163 # Number of data accesses 2439system.cpu1.icache.ReadReq_hits::cpu1.inst 204337040 # number of ReadReq hits 2440system.cpu1.icache.ReadReq_hits::total 204337040 # number of ReadReq hits 2441system.cpu1.icache.demand_hits::cpu1.inst 204337040 # number of demand (read+write) hits 2442system.cpu1.icache.demand_hits::total 204337040 # number of demand (read+write) hits 2443system.cpu1.icache.overall_hits::cpu1.inst 204337040 # number of overall hits 2444system.cpu1.icache.overall_hits::total 204337040 # number of overall hits 2445system.cpu1.icache.ReadReq_misses::cpu1.inst 6318152 # number of ReadReq misses 2446system.cpu1.icache.ReadReq_misses::total 6318152 # number of ReadReq misses 2447system.cpu1.icache.demand_misses::cpu1.inst 6318152 # number of demand (read+write) misses 2448system.cpu1.icache.demand_misses::total 6318152 # number of demand (read+write) misses 2449system.cpu1.icache.overall_misses::cpu1.inst 6318152 # number of overall misses 2450system.cpu1.icache.overall_misses::total 6318152 # number of overall misses 2451system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 69955140831 # number of ReadReq miss cycles 2452system.cpu1.icache.ReadReq_miss_latency::total 69955140831 # number of ReadReq miss cycles 2453system.cpu1.icache.demand_miss_latency::cpu1.inst 69955140831 # number of demand (read+write) miss cycles 2454system.cpu1.icache.demand_miss_latency::total 69955140831 # number of demand (read+write) miss cycles 2455system.cpu1.icache.overall_miss_latency::cpu1.inst 69955140831 # number of overall miss cycles 2456system.cpu1.icache.overall_miss_latency::total 69955140831 # number of overall miss cycles 2457system.cpu1.icache.ReadReq_accesses::cpu1.inst 210655192 # number of ReadReq accesses(hits+misses) 2458system.cpu1.icache.ReadReq_accesses::total 210655192 # number of ReadReq accesses(hits+misses) 2459system.cpu1.icache.demand_accesses::cpu1.inst 210655192 # number of demand (read+write) accesses 2460system.cpu1.icache.demand_accesses::total 210655192 # number of demand (read+write) accesses 2461system.cpu1.icache.overall_accesses::cpu1.inst 210655192 # number of overall (read+write) accesses 2462system.cpu1.icache.overall_accesses::total 210655192 # number of overall (read+write) accesses 2463system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029993 # miss rate for ReadReq accesses 2464system.cpu1.icache.ReadReq_miss_rate::total 0.029993 # miss rate for ReadReq accesses 2465system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029993 # miss rate for demand accesses 2466system.cpu1.icache.demand_miss_rate::total 0.029993 # miss rate for demand accesses 2467system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029993 # miss rate for overall accesses 2468system.cpu1.icache.overall_miss_rate::total 0.029993 # miss rate for overall accesses 2469system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11072.088932 # average ReadReq miss latency 2470system.cpu1.icache.ReadReq_avg_miss_latency::total 11072.088932 # average ReadReq miss latency 2471system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11072.088932 # average overall miss latency 2472system.cpu1.icache.demand_avg_miss_latency::total 11072.088932 # average overall miss latency 2473system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11072.088932 # average overall miss latency 2474system.cpu1.icache.overall_avg_miss_latency::total 11072.088932 # average overall miss latency 2475system.cpu1.icache.blocked_cycles::no_mshrs 10670268 # number of cycles access was blocked 2476system.cpu1.icache.blocked_cycles::no_targets 1157 # number of cycles access was blocked 2477system.cpu1.icache.blocked::no_mshrs 748022 # number of cycles access was blocked 2478system.cpu1.icache.blocked::no_targets 8 # number of cycles access was blocked 2479system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.264645 # average number of cycles each access was blocked 2480system.cpu1.icache.avg_blocked_cycles::no_targets 144.625000 # average number of cycles each access was blocked 2481system.cpu1.icache.fast_writes 0 # number of fast writes performed 2482system.cpu1.icache.cache_copies 0 # number of cache copies performed 2483system.cpu1.icache.writebacks::writebacks 5972259 # number of writebacks 2484system.cpu1.icache.writebacks::total 5972259 # number of writebacks 2485system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 345373 # number of ReadReq MSHR hits 2486system.cpu1.icache.ReadReq_mshr_hits::total 345373 # number of ReadReq MSHR hits 2487system.cpu1.icache.demand_mshr_hits::cpu1.inst 345373 # number of demand (read+write) MSHR hits 2488system.cpu1.icache.demand_mshr_hits::total 345373 # number of demand (read+write) MSHR hits 2489system.cpu1.icache.overall_mshr_hits::cpu1.inst 345373 # number of overall MSHR hits 2490system.cpu1.icache.overall_mshr_hits::total 345373 # number of overall MSHR hits 2491system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5972779 # number of ReadReq MSHR misses 2492system.cpu1.icache.ReadReq_mshr_misses::total 5972779 # number of ReadReq MSHR misses 2493system.cpu1.icache.demand_mshr_misses::cpu1.inst 5972779 # number of demand (read+write) MSHR misses 2494system.cpu1.icache.demand_mshr_misses::total 5972779 # number of demand (read+write) MSHR misses 2495system.cpu1.icache.overall_mshr_misses::cpu1.inst 5972779 # number of overall MSHR misses 2496system.cpu1.icache.overall_mshr_misses::total 5972779 # number of overall MSHR misses 2497system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 2498system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable 2499system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 2500system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses 2501system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 63045966777 # number of ReadReq MSHR miss cycles 2502system.cpu1.icache.ReadReq_mshr_miss_latency::total 63045966777 # number of ReadReq MSHR miss cycles 2503system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 63045966777 # number of demand (read+write) MSHR miss cycles 2504system.cpu1.icache.demand_mshr_miss_latency::total 63045966777 # number of demand (read+write) MSHR miss cycles 2505system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 63045966777 # number of overall MSHR miss cycles 2506system.cpu1.icache.overall_mshr_miss_latency::total 63045966777 # number of overall MSHR miss cycles 2507system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8835998 # number of ReadReq MSHR uncacheable cycles 2508system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8835998 # number of ReadReq MSHR uncacheable cycles 2509system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8835998 # number of overall MSHR uncacheable cycles 2510system.cpu1.icache.overall_mshr_uncacheable_latency::total 8835998 # number of overall MSHR uncacheable cycles 2511system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028353 # mshr miss rate for ReadReq accesses 2512system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028353 # mshr miss rate for ReadReq accesses 2513system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028353 # mshr miss rate for demand accesses 2514system.cpu1.icache.demand_mshr_miss_rate::total 0.028353 # mshr miss rate for demand accesses 2515system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028353 # mshr miss rate for overall accesses 2516system.cpu1.icache.overall_mshr_miss_rate::total 0.028353 # mshr miss rate for overall accesses 2517system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10555.549900 # average ReadReq mshr miss latency 2518system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10555.549900 # average ReadReq mshr miss latency 2519system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10555.549900 # average overall mshr miss latency 2520system.cpu1.icache.demand_avg_mshr_miss_latency::total 10555.549900 # average overall mshr miss latency 2521system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10555.549900 # average overall mshr miss latency 2522system.cpu1.icache.overall_avg_mshr_miss_latency::total 10555.549900 # average overall mshr miss latency 2523system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 131880.567164 # average ReadReq mshr uncacheable latency 2524system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 131880.567164 # average ReadReq mshr uncacheable latency 2525system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 131880.567164 # average overall mshr uncacheable latency 2526system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 131880.567164 # average overall mshr uncacheable latency 2527system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2528system.cpu1.l2cache.prefetcher.num_hwpf_issued 7501600 # number of hwpf issued 2529system.cpu1.l2cache.prefetcher.pfIdentified 7506319 # number of prefetch candidates identified 2530system.cpu1.l2cache.prefetcher.pfBufferHit 4330 # number of redundant prefetches already in prefetch queue 2531system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2532system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 2533system.cpu1.l2cache.prefetcher.pfSpanPage 900873 # number of prefetches not generated due to page crossing 2534system.cpu1.l2cache.tags.replacements 2224556 # number of replacements 2535system.cpu1.l2cache.tags.tagsinuse 13365.286062 # Cycle average of tags in use 2536system.cpu1.l2cache.tags.total_refs 17240330 # Total number of references to valid blocks. 2537system.cpu1.l2cache.tags.sampled_refs 2240308 # Sample count of references to valid blocks. 2538system.cpu1.l2cache.tags.avg_refs 7.695518 # Average number of references to valid blocks. 2539system.cpu1.l2cache.tags.warmup_cycle 10278781174500 # Cycle when the warmup percentage was hit. 2540system.cpu1.l2cache.tags.occ_blocks::writebacks 12562.638726 # Average occupied blocks per requestor 2541system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 67.088648 # Average occupied blocks per requestor 2542system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 68.405438 # Average occupied blocks per requestor 2543system.cpu1.l2cache.tags.occ_blocks::cpu1.data 0.000005 # Average occupied blocks per requestor 2544system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 667.153246 # Average occupied blocks per requestor 2545system.cpu1.l2cache.tags.occ_percent::writebacks 0.766763 # Average percentage of cache occupancy 2546system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004095 # Average percentage of cache occupancy 2547system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004175 # Average percentage of cache occupancy 2548system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.000000 # Average percentage of cache occupancy 2549system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.040720 # Average percentage of cache occupancy 2550system.cpu1.l2cache.tags.occ_percent::total 0.815752 # Average percentage of cache occupancy 2551system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1289 # Occupied blocks per task id 2552system.cpu1.l2cache.tags.occ_task_id_blocks::1023 98 # Occupied blocks per task id 2553system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14365 # Occupied blocks per task id 2554system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 78 # Occupied blocks per task id 2555system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 178 # Occupied blocks per task id 2556system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 616 # Occupied blocks per task id 2557system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 417 # Occupied blocks per task id 2558system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id 2559system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 79 # Occupied blocks per task id 2560system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 2561system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id 2562system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id 2563system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 949 # Occupied blocks per task id 2564system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4690 # Occupied blocks per task id 2565system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4883 # Occupied blocks per task id 2566system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3797 # Occupied blocks per task id 2567system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.078674 # Percentage of cache occupancy per task id 2568system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005981 # Percentage of cache occupancy per task id 2569system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.876770 # Percentage of cache occupancy per task id 2570system.cpu1.l2cache.tags.tag_accesses 393723429 # Number of tag accesses 2571system.cpu1.l2cache.tags.data_accesses 393723429 # Number of data accesses 2572system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 587134 # number of ReadReq hits 2573system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 192926 # number of ReadReq hits 2574system.cpu1.l2cache.ReadReq_hits::total 780060 # number of ReadReq hits 2575system.cpu1.l2cache.WritebackDirty_hits::writebacks 3457963 # number of WritebackDirty hits 2576system.cpu1.l2cache.WritebackDirty_hits::total 3457963 # number of WritebackDirty hits 2577system.cpu1.l2cache.WritebackClean_hits::writebacks 8011825 # number of WritebackClean hits 2578system.cpu1.l2cache.WritebackClean_hits::total 8011825 # number of WritebackClean hits 2579system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 813 # number of UpgradeReq hits 2580system.cpu1.l2cache.UpgradeReq_hits::total 813 # number of UpgradeReq hits 2581system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 2 # number of SCUpgradeReq hits 2582system.cpu1.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits 2583system.cpu1.l2cache.ReadExReq_hits::cpu1.data 855353 # number of ReadExReq hits 2584system.cpu1.l2cache.ReadExReq_hits::total 855353 # number of ReadExReq hits 2585system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5413940 # number of ReadCleanReq hits 2586system.cpu1.l2cache.ReadCleanReq_hits::total 5413940 # number of ReadCleanReq hits 2587system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3003863 # number of ReadSharedReq hits 2588system.cpu1.l2cache.ReadSharedReq_hits::total 3003863 # number of ReadSharedReq hits 2589system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 191485 # number of InvalidateReq hits 2590system.cpu1.l2cache.InvalidateReq_hits::total 191485 # number of InvalidateReq hits 2591system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 587134 # number of demand (read+write) hits 2592system.cpu1.l2cache.demand_hits::cpu1.itb.walker 192926 # number of demand (read+write) hits 2593system.cpu1.l2cache.demand_hits::cpu1.inst 5413940 # number of demand (read+write) hits 2594system.cpu1.l2cache.demand_hits::cpu1.data 3859216 # number of demand (read+write) hits 2595system.cpu1.l2cache.demand_hits::total 10053216 # number of demand (read+write) hits 2596system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 587134 # number of overall hits 2597system.cpu1.l2cache.overall_hits::cpu1.itb.walker 192926 # number of overall hits 2598system.cpu1.l2cache.overall_hits::cpu1.inst 5413940 # number of overall hits 2599system.cpu1.l2cache.overall_hits::cpu1.data 3859216 # number of overall hits 2600system.cpu1.l2cache.overall_hits::total 10053216 # number of overall hits 2601system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12541 # number of ReadReq misses 2602system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9429 # number of ReadReq misses 2603system.cpu1.l2cache.ReadReq_misses::total 21970 # number of ReadReq misses 2604system.cpu1.l2cache.WritebackDirty_misses::writebacks 4 # number of WritebackDirty misses 2605system.cpu1.l2cache.WritebackDirty_misses::total 4 # number of WritebackDirty misses 2606system.cpu1.l2cache.WritebackClean_misses::writebacks 2 # number of WritebackClean misses 2607system.cpu1.l2cache.WritebackClean_misses::total 2 # number of WritebackClean misses 2608system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 239265 # number of UpgradeReq misses 2609system.cpu1.l2cache.UpgradeReq_misses::total 239265 # number of UpgradeReq misses 2610system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 195055 # number of SCUpgradeReq misses 2611system.cpu1.l2cache.SCUpgradeReq_misses::total 195055 # number of SCUpgradeReq misses 2612system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses 2613system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses 2614system.cpu1.l2cache.ReadExReq_misses::cpu1.data 299638 # number of ReadExReq misses 2615system.cpu1.l2cache.ReadExReq_misses::total 299638 # number of ReadExReq misses 2616system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 558835 # number of ReadCleanReq misses 2617system.cpu1.l2cache.ReadCleanReq_misses::total 558835 # number of ReadCleanReq misses 2618system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1003530 # number of ReadSharedReq misses 2619system.cpu1.l2cache.ReadSharedReq_misses::total 1003530 # number of ReadSharedReq misses 2620system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 236473 # number of InvalidateReq misses 2621system.cpu1.l2cache.InvalidateReq_misses::total 236473 # number of InvalidateReq misses 2622system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12541 # number of demand (read+write) misses 2623system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9429 # number of demand (read+write) misses 2624system.cpu1.l2cache.demand_misses::cpu1.inst 558835 # number of demand (read+write) misses 2625system.cpu1.l2cache.demand_misses::cpu1.data 1303168 # number of demand (read+write) misses 2626system.cpu1.l2cache.demand_misses::total 1883973 # number of demand (read+write) misses 2627system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12541 # number of overall misses 2628system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9429 # number of overall misses 2629system.cpu1.l2cache.overall_misses::cpu1.inst 558835 # number of overall misses 2630system.cpu1.l2cache.overall_misses::cpu1.data 1303168 # number of overall misses 2631system.cpu1.l2cache.overall_misses::total 1883973 # number of overall misses 2632system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 648758500 # number of ReadReq miss cycles 2633system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 531765000 # number of ReadReq miss cycles 2634system.cpu1.l2cache.ReadReq_miss_latency::total 1180523500 # number of ReadReq miss cycles 2635system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3573774499 # number of UpgradeReq miss cycles 2636system.cpu1.l2cache.UpgradeReq_miss_latency::total 3573774499 # number of UpgradeReq miss cycles 2637system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1875778500 # number of SCUpgradeReq miss cycles 2638system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1875778500 # number of SCUpgradeReq miss cycles 2639system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3096999 # number of SCUpgradeFailReq miss cycles 2640system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3096999 # number of SCUpgradeFailReq miss cycles 2641system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 16089567500 # number of ReadExReq miss cycles 2642system.cpu1.l2cache.ReadExReq_miss_latency::total 16089567500 # number of ReadExReq miss cycles 2643system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 21287303500 # number of ReadCleanReq miss cycles 2644system.cpu1.l2cache.ReadCleanReq_miss_latency::total 21287303500 # number of ReadCleanReq miss cycles 2645system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 40947637491 # number of ReadSharedReq miss cycles 2646system.cpu1.l2cache.ReadSharedReq_miss_latency::total 40947637491 # number of ReadSharedReq miss cycles 2647system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 14994721499 # number of InvalidateReq miss cycles 2648system.cpu1.l2cache.InvalidateReq_miss_latency::total 14994721499 # number of InvalidateReq miss cycles 2649system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 648758500 # number of demand (read+write) miss cycles 2650system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 531765000 # number of demand (read+write) miss cycles 2651system.cpu1.l2cache.demand_miss_latency::cpu1.inst 21287303500 # number of demand (read+write) miss cycles 2652system.cpu1.l2cache.demand_miss_latency::cpu1.data 57037204991 # number of demand (read+write) miss cycles 2653system.cpu1.l2cache.demand_miss_latency::total 79505031991 # number of demand (read+write) miss cycles 2654system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 648758500 # number of overall miss cycles 2655system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 531765000 # number of overall miss cycles 2656system.cpu1.l2cache.overall_miss_latency::cpu1.inst 21287303500 # number of overall miss cycles 2657system.cpu1.l2cache.overall_miss_latency::cpu1.data 57037204991 # number of overall miss cycles 2658system.cpu1.l2cache.overall_miss_latency::total 79505031991 # number of overall miss cycles 2659system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 599675 # number of ReadReq accesses(hits+misses) 2660system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 202355 # number of ReadReq accesses(hits+misses) 2661system.cpu1.l2cache.ReadReq_accesses::total 802030 # number of ReadReq accesses(hits+misses) 2662system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3457967 # number of WritebackDirty accesses(hits+misses) 2663system.cpu1.l2cache.WritebackDirty_accesses::total 3457967 # number of WritebackDirty accesses(hits+misses) 2664system.cpu1.l2cache.WritebackClean_accesses::writebacks 8011827 # number of WritebackClean accesses(hits+misses) 2665system.cpu1.l2cache.WritebackClean_accesses::total 8011827 # number of WritebackClean accesses(hits+misses) 2666system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 240078 # number of UpgradeReq accesses(hits+misses) 2667system.cpu1.l2cache.UpgradeReq_accesses::total 240078 # number of UpgradeReq accesses(hits+misses) 2668system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 195057 # number of SCUpgradeReq accesses(hits+misses) 2669system.cpu1.l2cache.SCUpgradeReq_accesses::total 195057 # number of SCUpgradeReq accesses(hits+misses) 2670system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) 2671system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) 2672system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1154991 # number of ReadExReq accesses(hits+misses) 2673system.cpu1.l2cache.ReadExReq_accesses::total 1154991 # number of ReadExReq accesses(hits+misses) 2674system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5972775 # number of ReadCleanReq accesses(hits+misses) 2675system.cpu1.l2cache.ReadCleanReq_accesses::total 5972775 # number of ReadCleanReq accesses(hits+misses) 2676system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4007393 # number of ReadSharedReq accesses(hits+misses) 2677system.cpu1.l2cache.ReadSharedReq_accesses::total 4007393 # number of ReadSharedReq accesses(hits+misses) 2678system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 427958 # number of InvalidateReq accesses(hits+misses) 2679system.cpu1.l2cache.InvalidateReq_accesses::total 427958 # number of InvalidateReq accesses(hits+misses) 2680system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 599675 # number of demand (read+write) accesses 2681system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 202355 # number of demand (read+write) accesses 2682system.cpu1.l2cache.demand_accesses::cpu1.inst 5972775 # number of demand (read+write) accesses 2683system.cpu1.l2cache.demand_accesses::cpu1.data 5162384 # number of demand (read+write) accesses 2684system.cpu1.l2cache.demand_accesses::total 11937189 # number of demand (read+write) accesses 2685system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 599675 # number of overall (read+write) accesses 2686system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 202355 # number of overall (read+write) accesses 2687system.cpu1.l2cache.overall_accesses::cpu1.inst 5972775 # number of overall (read+write) accesses 2688system.cpu1.l2cache.overall_accesses::cpu1.data 5162384 # number of overall (read+write) accesses 2689system.cpu1.l2cache.overall_accesses::total 11937189 # number of overall (read+write) accesses 2690system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.020913 # miss rate for ReadReq accesses 2691system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.046596 # miss rate for ReadReq accesses 2692system.cpu1.l2cache.ReadReq_miss_rate::total 0.027393 # miss rate for ReadReq accesses 2693system.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses 2694system.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses 2695system.cpu1.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses 2696system.cpu1.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses 2697system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.996614 # miss rate for UpgradeReq accesses 2698system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.996614 # miss rate for UpgradeReq accesses 2699system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.999990 # miss rate for SCUpgradeReq accesses 2700system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.999990 # miss rate for SCUpgradeReq accesses 2701system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2702system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2703system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.259429 # miss rate for ReadExReq accesses 2704system.cpu1.l2cache.ReadExReq_miss_rate::total 0.259429 # miss rate for ReadExReq accesses 2705system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.093564 # miss rate for ReadCleanReq accesses 2706system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.093564 # miss rate for ReadCleanReq accesses 2707system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.250420 # miss rate for ReadSharedReq accesses 2708system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.250420 # miss rate for ReadSharedReq accesses 2709system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.552561 # miss rate for InvalidateReq accesses 2710system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.552561 # miss rate for InvalidateReq accesses 2711system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.020913 # miss rate for demand accesses 2712system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.046596 # miss rate for demand accesses 2713system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.093564 # miss rate for demand accesses 2714system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.252435 # miss rate for demand accesses 2715system.cpu1.l2cache.demand_miss_rate::total 0.157824 # miss rate for demand accesses 2716system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.020913 # miss rate for overall accesses 2717system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.046596 # miss rate for overall accesses 2718system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.093564 # miss rate for overall accesses 2719system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.252435 # miss rate for overall accesses 2720system.cpu1.l2cache.overall_miss_rate::total 0.157824 # miss rate for overall accesses 2721system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 51731.002312 # average ReadReq miss latency 2722system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 56396.754693 # average ReadReq miss latency 2723system.cpu1.l2cache.ReadReq_avg_miss_latency::total 53733.431953 # average ReadReq miss latency 2724system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 14936.470019 # average UpgradeReq miss latency 2725system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 14936.470019 # average UpgradeReq miss latency 2726system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9616.664531 # average SCUpgradeReq miss latency 2727system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9616.664531 # average SCUpgradeReq miss latency 2728system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 3096999 # average SCUpgradeFailReq miss latency 2729system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 3096999 # average SCUpgradeFailReq miss latency 2730system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53696.685667 # average ReadExReq miss latency 2731system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53696.685667 # average ReadExReq miss latency 2732system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 38092.287527 # average ReadCleanReq miss latency 2733system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 38092.287527 # average ReadCleanReq miss latency 2734system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 40803.600780 # average ReadSharedReq miss latency 2735system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 40803.600780 # average ReadSharedReq miss latency 2736system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 63409.867084 # average InvalidateReq miss latency 2737system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 63409.867084 # average InvalidateReq miss latency 2738system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 51731.002312 # average overall miss latency 2739system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 56396.754693 # average overall miss latency 2740system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 38092.287527 # average overall miss latency 2741system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 43768.113544 # average overall miss latency 2742system.cpu1.l2cache.demand_avg_miss_latency::total 42200.727925 # average overall miss latency 2743system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 51731.002312 # average overall miss latency 2744system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 56396.754693 # average overall miss latency 2745system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 38092.287527 # average overall miss latency 2746system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 43768.113544 # average overall miss latency 2747system.cpu1.l2cache.overall_avg_miss_latency::total 42200.727925 # average overall miss latency 2748system.cpu1.l2cache.blocked_cycles::no_mshrs 1276 # number of cycles access was blocked 2749system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2750system.cpu1.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked 2751system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2752system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 159.500000 # average number of cycles each access was blocked 2753system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2754system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2755system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2756system.cpu1.l2cache.writebacks::writebacks 1185134 # number of writebacks 2757system.cpu1.l2cache.writebacks::total 1185134 # number of writebacks 2758system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 3 # number of ReadReq MSHR hits 2759system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 196 # number of ReadReq MSHR hits 2760system.cpu1.l2cache.ReadReq_mshr_hits::total 199 # number of ReadReq MSHR hits 2761system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 42850 # number of ReadExReq MSHR hits 2762system.cpu1.l2cache.ReadExReq_mshr_hits::total 42850 # number of ReadExReq MSHR hits 2763system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 5641 # number of ReadSharedReq MSHR hits 2764system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 5641 # number of ReadSharedReq MSHR hits 2765system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 3 # number of InvalidateReq MSHR hits 2766system.cpu1.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits 2767system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 3 # number of demand (read+write) MSHR hits 2768system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 196 # number of demand (read+write) MSHR hits 2769system.cpu1.l2cache.demand_mshr_hits::cpu1.data 48491 # number of demand (read+write) MSHR hits 2770system.cpu1.l2cache.demand_mshr_hits::total 48690 # number of demand (read+write) MSHR hits 2771system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 3 # number of overall MSHR hits 2772system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 196 # number of overall MSHR hits 2773system.cpu1.l2cache.overall_mshr_hits::cpu1.data 48491 # number of overall MSHR hits 2774system.cpu1.l2cache.overall_mshr_hits::total 48690 # number of overall MSHR hits 2775system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12538 # number of ReadReq MSHR misses 2776system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9233 # number of ReadReq MSHR misses 2777system.cpu1.l2cache.ReadReq_mshr_misses::total 21771 # number of ReadReq MSHR misses 2778system.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 4 # number of WritebackDirty MSHR misses 2779system.cpu1.l2cache.WritebackDirty_mshr_misses::total 4 # number of WritebackDirty MSHR misses 2780system.cpu1.l2cache.WritebackClean_mshr_misses::writebacks 2 # number of WritebackClean MSHR misses 2781system.cpu1.l2cache.WritebackClean_mshr_misses::total 2 # number of WritebackClean MSHR misses 2782system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 776550 # number of HardPFReq MSHR misses 2783system.cpu1.l2cache.HardPFReq_mshr_misses::total 776550 # number of HardPFReq MSHR misses 2784system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 239265 # number of UpgradeReq MSHR misses 2785system.cpu1.l2cache.UpgradeReq_mshr_misses::total 239265 # number of UpgradeReq MSHR misses 2786system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 195055 # number of SCUpgradeReq MSHR misses 2787system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 195055 # number of SCUpgradeReq MSHR misses 2788system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses 2789system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses 2790system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 256788 # number of ReadExReq MSHR misses 2791system.cpu1.l2cache.ReadExReq_mshr_misses::total 256788 # number of ReadExReq MSHR misses 2792system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 558835 # number of ReadCleanReq MSHR misses 2793system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 558835 # number of ReadCleanReq MSHR misses 2794system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 997889 # number of ReadSharedReq MSHR misses 2795system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 997889 # number of ReadSharedReq MSHR misses 2796system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 236470 # number of InvalidateReq MSHR misses 2797system.cpu1.l2cache.InvalidateReq_mshr_misses::total 236470 # number of InvalidateReq MSHR misses 2798system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12538 # number of demand (read+write) MSHR misses 2799system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9233 # number of demand (read+write) MSHR misses 2800system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 558835 # number of demand (read+write) MSHR misses 2801system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1254677 # number of demand (read+write) MSHR misses 2802system.cpu1.l2cache.demand_mshr_misses::total 1835283 # number of demand (read+write) MSHR misses 2803system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12538 # number of overall MSHR misses 2804system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9233 # number of overall MSHR misses 2805system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 558835 # number of overall MSHR misses 2806system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1254677 # number of overall MSHR misses 2807system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 776550 # number of overall MSHR misses 2808system.cpu1.l2cache.overall_mshr_misses::total 2611833 # number of overall MSHR misses 2809system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 2810system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 6299 # number of ReadReq MSHR uncacheable 2811system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 6366 # number of ReadReq MSHR uncacheable 2812system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 6428 # number of WriteReq MSHR uncacheable 2813system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 6428 # number of WriteReq MSHR uncacheable 2814system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 2815system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 12727 # number of overall MSHR uncacheable misses 2816system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 12794 # number of overall MSHR uncacheable misses 2817system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 573471000 # number of ReadReq MSHR miss cycles 2818system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 464925500 # number of ReadReq MSHR miss cycles 2819system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1038396500 # number of ReadReq MSHR miss cycles 2820system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 46806898722 # number of HardPFReq MSHR miss cycles 2821system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 46806898722 # number of HardPFReq MSHR miss cycles 2822system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 7460497999 # number of UpgradeReq MSHR miss cycles 2823system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 7460497999 # number of UpgradeReq MSHR miss cycles 2824system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3758753499 # number of SCUpgradeReq MSHR miss cycles 2825system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3758753499 # number of SCUpgradeReq MSHR miss cycles 2826system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2850999 # number of SCUpgradeFailReq MSHR miss cycles 2827system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2850999 # number of SCUpgradeFailReq MSHR miss cycles 2828system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 12334341500 # number of ReadExReq MSHR miss cycles 2829system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 12334341500 # number of ReadExReq MSHR miss cycles 2830system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 17934293500 # number of ReadCleanReq MSHR miss cycles 2831system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 17934293500 # number of ReadCleanReq MSHR miss cycles 2832system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 34643944491 # number of ReadSharedReq MSHR miss cycles 2833system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 34643944491 # number of ReadSharedReq MSHR miss cycles 2834system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 13575517499 # number of InvalidateReq MSHR miss cycles 2835system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 13575517499 # number of InvalidateReq MSHR miss cycles 2836system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 573471000 # number of demand (read+write) MSHR miss cycles 2837system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 464925500 # number of demand (read+write) MSHR miss cycles 2838system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 17934293500 # number of demand (read+write) MSHR miss cycles 2839system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 46978285991 # number of demand (read+write) MSHR miss cycles 2840system.cpu1.l2cache.demand_mshr_miss_latency::total 65950975991 # number of demand (read+write) MSHR miss cycles 2841system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 573471000 # number of overall MSHR miss cycles 2842system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 464925500 # number of overall MSHR miss cycles 2843system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 17934293500 # number of overall MSHR miss cycles 2844system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 46978285991 # number of overall MSHR miss cycles 2845system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 46806898722 # number of overall MSHR miss cycles 2846system.cpu1.l2cache.overall_mshr_miss_latency::total 112757874713 # number of overall MSHR miss cycles 2847system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8332500 # number of ReadReq MSHR uncacheable cycles 2848system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 677372000 # number of ReadReq MSHR uncacheable cycles 2849system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 685704500 # number of ReadReq MSHR uncacheable cycles 2850system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 811538500 # number of WriteReq MSHR uncacheable cycles 2851system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 811538500 # number of WriteReq MSHR uncacheable cycles 2852system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8332500 # number of overall MSHR uncacheable cycles 2853system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1488910500 # number of overall MSHR uncacheable cycles 2854system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1497243000 # number of overall MSHR uncacheable cycles 2855system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.020908 # mshr miss rate for ReadReq accesses 2856system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.045628 # mshr miss rate for ReadReq accesses 2857system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.027145 # mshr miss rate for ReadReq accesses 2858system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses 2859system.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses 2860system.cpu1.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses 2861system.cpu1.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses 2862system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2863system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2864system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.996614 # mshr miss rate for UpgradeReq accesses 2865system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.996614 # mshr miss rate for UpgradeReq accesses 2866system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999990 # mshr miss rate for SCUpgradeReq accesses 2867system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999990 # mshr miss rate for SCUpgradeReq accesses 2868system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2869system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2870system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.222329 # mshr miss rate for ReadExReq accesses 2871system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.222329 # mshr miss rate for ReadExReq accesses 2872system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.093564 # mshr miss rate for ReadCleanReq accesses 2873system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.093564 # mshr miss rate for ReadCleanReq accesses 2874system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.249012 # mshr miss rate for ReadSharedReq accesses 2875system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249012 # mshr miss rate for ReadSharedReq accesses 2876system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.552554 # mshr miss rate for InvalidateReq accesses 2877system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.552554 # mshr miss rate for InvalidateReq accesses 2878system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.020908 # mshr miss rate for demand accesses 2879system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.045628 # mshr miss rate for demand accesses 2880system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.093564 # mshr miss rate for demand accesses 2881system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.243042 # mshr miss rate for demand accesses 2882system.cpu1.l2cache.demand_mshr_miss_rate::total 0.153745 # mshr miss rate for demand accesses 2883system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.020908 # mshr miss rate for overall accesses 2884system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.045628 # mshr miss rate for overall accesses 2885system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.093564 # mshr miss rate for overall accesses 2886system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.243042 # mshr miss rate for overall accesses 2887system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2888system.cpu1.l2cache.overall_mshr_miss_rate::total 0.218798 # mshr miss rate for overall accesses 2889system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 45738.634551 # average ReadReq mshr miss latency 2890system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 50354.760100 # average ReadReq mshr miss latency 2891system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 47696.316200 # average ReadReq mshr miss latency 2892system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 60275.447456 # average HardPFReq mshr miss latency 2893system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 60275.447456 # average HardPFReq mshr miss latency 2894system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31180.899835 # average UpgradeReq mshr miss latency 2895system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31180.899835 # average UpgradeReq mshr miss latency 2896system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19270.223778 # average SCUpgradeReq mshr miss latency 2897system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19270.223778 # average SCUpgradeReq mshr miss latency 2898system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 2850999 # average SCUpgradeFailReq mshr miss latency 2899system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 2850999 # average SCUpgradeFailReq mshr miss latency 2900system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 48033.169385 # average ReadExReq mshr miss latency 2901system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 48033.169385 # average ReadExReq mshr miss latency 2902system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32092.287527 # average ReadCleanReq mshr miss latency 2903system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32092.287527 # average ReadCleanReq mshr miss latency 2904system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 34717.232569 # average ReadSharedReq mshr miss latency 2905system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 34717.232569 # average ReadSharedReq mshr miss latency 2906system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 57409.047655 # average InvalidateReq mshr miss latency 2907system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 57409.047655 # average InvalidateReq mshr miss latency 2908system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 45738.634551 # average overall mshr miss latency 2909system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 50354.760100 # average overall mshr miss latency 2910system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32092.287527 # average overall mshr miss latency 2911system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 37442.533808 # average overall mshr miss latency 2912system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 35935.044345 # average overall mshr miss latency 2913system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 45738.634551 # average overall mshr miss latency 2914system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 50354.760100 # average overall mshr miss latency 2915system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32092.287527 # average overall mshr miss latency 2916system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 37442.533808 # average overall mshr miss latency 2917system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 60275.447456 # average overall mshr miss latency 2918system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 43171.931250 # average overall mshr miss latency 2919system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 124365.671642 # average ReadReq mshr uncacheable latency 2920system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 107536.434355 # average ReadReq mshr uncacheable latency 2921system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 107713.556393 # average ReadReq mshr uncacheable latency 2922system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 126250.544493 # average WriteReq mshr uncacheable latency 2923system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 126250.544493 # average WriteReq mshr uncacheable latency 2924system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 124365.671642 # average overall mshr uncacheable latency 2925system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 116988.331893 # average overall mshr uncacheable latency 2926system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 117026.965765 # average overall mshr uncacheable latency 2927system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2928system.cpu1.toL2Bus.snoop_filter.tot_requests 23835470 # Total number of requests made to the snoop filter. 2929system.cpu1.toL2Bus.snoop_filter.hit_single_requests 12272459 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2930system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1390 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2931system.cpu1.toL2Bus.snoop_filter.tot_snoops 2000895 # Total number of snoops made to the snoop filter. 2932system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2000561 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2933system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 334 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2934system.cpu1.toL2Bus.trans_dist::ReadReq 900425 # Transaction distribution 2935system.cpu1.toL2Bus.trans_dist::ReadResp 10970003 # Transaction distribution 2936system.cpu1.toL2Bus.trans_dist::WriteReq 6428 # Transaction distribution 2937system.cpu1.toL2Bus.trans_dist::WriteResp 6428 # Transaction distribution 2938system.cpu1.toL2Bus.trans_dist::WritebackDirty 4651207 # Transaction distribution 2939system.cpu1.toL2Bus.trans_dist::WritebackClean 8011843 # Transaction distribution 2940system.cpu1.toL2Bus.trans_dist::CleanEvict 2673516 # Transaction distribution 2941system.cpu1.toL2Bus.trans_dist::HardPFReq 976496 # Transaction distribution 2942system.cpu1.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution 2943system.cpu1.toL2Bus.trans_dist::UpgradeReq 442024 # Transaction distribution 2944system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 347278 # Transaction distribution 2945system.cpu1.toL2Bus.trans_dist::UpgradeResp 498740 # Transaction distribution 2946system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution 2947system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution 2948system.cpu1.toL2Bus.trans_dist::ReadExReq 1227372 # Transaction distribution 2949system.cpu1.toL2Bus.trans_dist::ReadExResp 1161574 # Transaction distribution 2950system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5972779 # Transaction distribution 2951system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4961310 # Transaction distribution 2952system.cpu1.toL2Bus.trans_dist::InvalidateReq 435892 # Transaction distribution 2953system.cpu1.toL2Bus.trans_dist::InvalidateResp 427958 # Transaction distribution 2954system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17917345 # Packet count per connected master and slave (bytes) 2955system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17734263 # Packet count per connected master and slave (bytes) 2956system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 424426 # Packet count per connected master and slave (bytes) 2957system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1271663 # Packet count per connected master and slave (bytes) 2958system.cpu1.toL2Bus.pkt_count::total 37347697 # Packet count per connected master and slave (bytes) 2959system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 764444720 # Cumulative packet size per connected master and slave (bytes) 2960system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 688461274 # Cumulative packet size per connected master and slave (bytes) 2961system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1618840 # Cumulative packet size per connected master and slave (bytes) 2962system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4797400 # Cumulative packet size per connected master and slave (bytes) 2963system.cpu1.toL2Bus.pkt_size::total 1459322234 # Cumulative packet size per connected master and slave (bytes) 2964system.cpu1.toL2Bus.snoops 6483444 # Total snoops (count) 2965system.cpu1.toL2Bus.snoop_fanout::samples 19136823 # Request fanout histogram 2966system.cpu1.toL2Bus.snoop_fanout::mean 0.123774 # Request fanout histogram 2967system.cpu1.toL2Bus.snoop_fanout::stdev 0.329377 # Request fanout histogram 2968system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2969system.cpu1.toL2Bus.snoop_fanout::0 16768514 87.62% 87.62% # Request fanout histogram 2970system.cpu1.toL2Bus.snoop_fanout::1 2367975 12.37% 100.00% # Request fanout histogram 2971system.cpu1.toL2Bus.snoop_fanout::2 334 0.00% 100.00% # Request fanout histogram 2972system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2973system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2974system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2975system.cpu1.toL2Bus.snoop_fanout::total 19136823 # Request fanout histogram 2976system.cpu1.toL2Bus.reqLayer0.occupancy 23662576976 # Layer occupancy (ticks) 2977system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2978system.cpu1.toL2Bus.snoopLayer0.occupancy 176028266 # Layer occupancy (ticks) 2979system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2980system.cpu1.toL2Bus.respLayer0.occupancy 8965097194 # Layer occupancy (ticks) 2981system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2982system.cpu1.toL2Bus.respLayer1.occupancy 8193842587 # Layer occupancy (ticks) 2983system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2984system.cpu1.toL2Bus.respLayer2.occupancy 222514103 # Layer occupancy (ticks) 2985system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2986system.cpu1.toL2Bus.respLayer3.occupancy 672743976 # Layer occupancy (ticks) 2987system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2988system.iobus.trans_dist::ReadReq 40336 # Transaction distribution 2989system.iobus.trans_dist::ReadResp 40336 # Transaction distribution 2990system.iobus.trans_dist::WriteReq 136625 # Transaction distribution 2991system.iobus.trans_dist::WriteResp 136625 # Transaction distribution 2992system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47628 # Packet count per connected master and slave (bytes) 2993system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2994system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2995system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2996system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2997system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2998system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2999system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 3000system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 3001system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 3002system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 3003system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 3004system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 3005system.iobus.pkt_count_system.bridge.master::total 122562 # Packet count per connected master and slave (bytes) 3006system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231280 # Packet count per connected master and slave (bytes) 3007system.iobus.pkt_count_system.realview.ide.dma::total 231280 # Packet count per connected master and slave (bytes) 3008system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 3009system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 3010system.iobus.pkt_count::total 353922 # Packet count per connected master and slave (bytes) 3011system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47648 # Cumulative packet size per connected master and slave (bytes) 3012system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 3013system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 3014system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 3015system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 3016system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 3017system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3018system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3019system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3020system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 3021system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3022system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 3023system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 3024system.iobus.pkt_size_system.bridge.master::total 155669 # Cumulative packet size per connected master and slave (bytes) 3025system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339136 # Cumulative packet size per connected master and slave (bytes) 3026system.iobus.pkt_size_system.realview.ide.dma::total 7339136 # Cumulative packet size per connected master and slave (bytes) 3027system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 3028system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 3029system.iobus.pkt_size::total 7496891 # Cumulative packet size per connected master and slave (bytes) 3030system.iobus.reqLayer0.occupancy 36916001 # Layer occupancy (ticks) 3031system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 3032system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) 3033system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 3034system.iobus.reqLayer2.occupancy 327000 # Layer occupancy (ticks) 3035system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 3036system.iobus.reqLayer3.occupancy 9000 # Layer occupancy (ticks) 3037system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 3038system.iobus.reqLayer4.occupancy 9000 # Layer occupancy (ticks) 3039system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 3040system.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) 3041system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 3042system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) 3043system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 3044system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) 3045system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 3046system.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) 3047system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 3048system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) 3049system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 3050system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) 3051system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 3052system.iobus.reqLayer23.occupancy 24643501 # Layer occupancy (ticks) 3053system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 3054system.iobus.reqLayer24.occupancy 36442501 # Layer occupancy (ticks) 3055system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 3056system.iobus.reqLayer25.occupancy 565518728 # Layer occupancy (ticks) 3057system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 3058system.iobus.respLayer0.occupancy 92668000 # Layer occupancy (ticks) 3059system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 3060system.iobus.respLayer3.occupancy 147976000 # Layer occupancy (ticks) 3061system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 3062system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 3063system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 3064system.iocache.tags.replacements 115636 # number of replacements 3065system.iocache.tags.tagsinuse 11.302848 # Cycle average of tags in use 3066system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 3067system.iocache.tags.sampled_refs 115652 # Sample count of references to valid blocks. 3068system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 3069system.iocache.tags.warmup_cycle 9125688591000 # Cycle when the warmup percentage was hit. 3070system.iocache.tags.occ_blocks::realview.ethernet 7.411882 # Average occupied blocks per requestor 3071system.iocache.tags.occ_blocks::realview.ide 3.890966 # Average occupied blocks per requestor 3072system.iocache.tags.occ_percent::realview.ethernet 0.463243 # Average percentage of cache occupancy 3073system.iocache.tags.occ_percent::realview.ide 0.243185 # Average percentage of cache occupancy 3074system.iocache.tags.occ_percent::total 0.706428 # Average percentage of cache occupancy 3075system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 3076system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 3077system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 3078system.iocache.tags.tag_accesses 1041117 # Number of tag accesses 3079system.iocache.tags.data_accesses 1041117 # Number of data accesses 3080system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 3081system.iocache.ReadReq_misses::realview.ide 8912 # number of ReadReq misses 3082system.iocache.ReadReq_misses::total 8949 # number of ReadReq misses 3083system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 3084system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 3085system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 3086system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 3087system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 3088system.iocache.demand_misses::realview.ide 8912 # number of demand (read+write) misses 3089system.iocache.demand_misses::total 8952 # number of demand (read+write) misses 3090system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 3091system.iocache.overall_misses::realview.ide 8912 # number of overall misses 3092system.iocache.overall_misses::total 8952 # number of overall misses 3093system.iocache.ReadReq_miss_latency::realview.ethernet 5200000 # number of ReadReq miss cycles 3094system.iocache.ReadReq_miss_latency::realview.ide 1705648493 # number of ReadReq miss cycles 3095system.iocache.ReadReq_miss_latency::total 1710848493 # number of ReadReq miss cycles 3096system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 3097system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 3098system.iocache.WriteLineReq_miss_latency::realview.ide 13974401235 # number of WriteLineReq miss cycles 3099system.iocache.WriteLineReq_miss_latency::total 13974401235 # number of WriteLineReq miss cycles 3100system.iocache.demand_miss_latency::realview.ethernet 5569000 # number of demand (read+write) miss cycles 3101system.iocache.demand_miss_latency::realview.ide 1705648493 # number of demand (read+write) miss cycles 3102system.iocache.demand_miss_latency::total 1711217493 # number of demand (read+write) miss cycles 3103system.iocache.overall_miss_latency::realview.ethernet 5569000 # number of overall miss cycles 3104system.iocache.overall_miss_latency::realview.ide 1705648493 # number of overall miss cycles 3105system.iocache.overall_miss_latency::total 1711217493 # number of overall miss cycles 3106system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 3107system.iocache.ReadReq_accesses::realview.ide 8912 # number of ReadReq accesses(hits+misses) 3108system.iocache.ReadReq_accesses::total 8949 # number of ReadReq accesses(hits+misses) 3109system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 3110system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 3111system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 3112system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 3113system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 3114system.iocache.demand_accesses::realview.ide 8912 # number of demand (read+write) accesses 3115system.iocache.demand_accesses::total 8952 # number of demand (read+write) accesses 3116system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 3117system.iocache.overall_accesses::realview.ide 8912 # number of overall (read+write) accesses 3118system.iocache.overall_accesses::total 8952 # number of overall (read+write) accesses 3119system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 3120system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 3121system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 3122system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 3123system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 3124system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 3125system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 3126system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 3127system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 3128system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 3129system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 3130system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 3131system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 3132system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140540.540541 # average ReadReq miss latency 3133system.iocache.ReadReq_avg_miss_latency::realview.ide 191387.847060 # average ReadReq miss latency 3134system.iocache.ReadReq_avg_miss_latency::total 191177.616829 # average ReadReq miss latency 3135system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 3136system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 3137system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130934.724112 # average WriteLineReq miss latency 3138system.iocache.WriteLineReq_avg_miss_latency::total 130934.724112 # average WriteLineReq miss latency 3139system.iocache.demand_avg_miss_latency::realview.ethernet 139225 # average overall miss latency 3140system.iocache.demand_avg_miss_latency::realview.ide 191387.847060 # average overall miss latency 3141system.iocache.demand_avg_miss_latency::total 191154.769102 # average overall miss latency 3142system.iocache.overall_avg_miss_latency::realview.ethernet 139225 # average overall miss latency 3143system.iocache.overall_avg_miss_latency::realview.ide 191387.847060 # average overall miss latency 3144system.iocache.overall_avg_miss_latency::total 191154.769102 # average overall miss latency 3145system.iocache.blocked_cycles::no_mshrs 35975 # number of cycles access was blocked 3146system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3147system.iocache.blocked::no_mshrs 3674 # number of cycles access was blocked 3148system.iocache.blocked::no_targets 0 # number of cycles access was blocked 3149system.iocache.avg_blocked_cycles::no_mshrs 9.791780 # average number of cycles each access was blocked 3150system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3151system.iocache.fast_writes 0 # number of fast writes performed 3152system.iocache.cache_copies 0 # number of cache copies performed 3153system.iocache.writebacks::writebacks 106694 # number of writebacks 3154system.iocache.writebacks::total 106694 # number of writebacks 3155system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 3156system.iocache.ReadReq_mshr_misses::realview.ide 8912 # number of ReadReq MSHR misses 3157system.iocache.ReadReq_mshr_misses::total 8949 # number of ReadReq MSHR misses 3158system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 3159system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 3160system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 3161system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 3162system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 3163system.iocache.demand_mshr_misses::realview.ide 8912 # number of demand (read+write) MSHR misses 3164system.iocache.demand_mshr_misses::total 8952 # number of demand (read+write) MSHR misses 3165system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 3166system.iocache.overall_mshr_misses::realview.ide 8912 # number of overall MSHR misses 3167system.iocache.overall_mshr_misses::total 8952 # number of overall MSHR misses 3168system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3350000 # number of ReadReq MSHR miss cycles 3169system.iocache.ReadReq_mshr_miss_latency::realview.ide 1260048493 # number of ReadReq MSHR miss cycles 3170system.iocache.ReadReq_mshr_miss_latency::total 1263398493 # number of ReadReq MSHR miss cycles 3171system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 3172system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 3173system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8638001235 # number of WriteLineReq MSHR miss cycles 3174system.iocache.WriteLineReq_mshr_miss_latency::total 8638001235 # number of WriteLineReq MSHR miss cycles 3175system.iocache.demand_mshr_miss_latency::realview.ethernet 3569000 # number of demand (read+write) MSHR miss cycles 3176system.iocache.demand_mshr_miss_latency::realview.ide 1260048493 # number of demand (read+write) MSHR miss cycles 3177system.iocache.demand_mshr_miss_latency::total 1263617493 # number of demand (read+write) MSHR miss cycles 3178system.iocache.overall_mshr_miss_latency::realview.ethernet 3569000 # number of overall MSHR miss cycles 3179system.iocache.overall_mshr_miss_latency::realview.ide 1260048493 # number of overall MSHR miss cycles 3180system.iocache.overall_mshr_miss_latency::total 1263617493 # number of overall MSHR miss cycles 3181system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 3182system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 3183system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 3184system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 3185system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 3186system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 3187system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 3188system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 3189system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 3190system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 3191system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 3192system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 3193system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 3194system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90540.540541 # average ReadReq mshr miss latency 3195system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 141387.847060 # average ReadReq mshr miss latency 3196system.iocache.ReadReq_avg_mshr_miss_latency::total 141177.616829 # average ReadReq mshr miss latency 3197system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 3198system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 3199system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80934.724112 # average WriteLineReq mshr miss latency 3200system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80934.724112 # average WriteLineReq mshr miss latency 3201system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89225 # average overall mshr miss latency 3202system.iocache.demand_avg_mshr_miss_latency::realview.ide 141387.847060 # average overall mshr miss latency 3203system.iocache.demand_avg_mshr_miss_latency::total 141154.769102 # average overall mshr miss latency 3204system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89225 # average overall mshr miss latency 3205system.iocache.overall_avg_mshr_miss_latency::realview.ide 141387.847060 # average overall mshr miss latency 3206system.iocache.overall_avg_mshr_miss_latency::total 141154.769102 # average overall mshr miss latency 3207system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 3208system.l2c.tags.replacements 1576044 # number of replacements 3209system.l2c.tags.tagsinuse 63242.380291 # Cycle average of tags in use 3210system.l2c.tags.total_refs 6232719 # Total number of references to valid blocks. 3211system.l2c.tags.sampled_refs 1635533 # Sample count of references to valid blocks. 3212system.l2c.tags.avg_refs 3.810818 # Average number of references to valid blocks. 3213system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3214system.l2c.tags.occ_blocks::writebacks 20333.059620 # Average occupied blocks per requestor 3215system.l2c.tags.occ_blocks::cpu0.dtb.walker 44.017365 # Average occupied blocks per requestor 3216system.l2c.tags.occ_blocks::cpu0.itb.walker 59.342117 # Average occupied blocks per requestor 3217system.l2c.tags.occ_blocks::cpu0.inst 3579.623644 # Average occupied blocks per requestor 3218system.l2c.tags.occ_blocks::cpu0.data 5086.228075 # Average occupied blocks per requestor 3219system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 3815.151087 # Average occupied blocks per requestor 3220system.l2c.tags.occ_blocks::cpu1.dtb.walker 296.252046 # Average occupied blocks per requestor 3221system.l2c.tags.occ_blocks::cpu1.itb.walker 450.100507 # Average occupied blocks per requestor 3222system.l2c.tags.occ_blocks::cpu1.inst 3644.907232 # Average occupied blocks per requestor 3223system.l2c.tags.occ_blocks::cpu1.data 8614.023056 # Average occupied blocks per requestor 3224system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17319.675542 # Average occupied blocks per requestor 3225system.l2c.tags.occ_percent::writebacks 0.310258 # Average percentage of cache occupancy 3226system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000672 # Average percentage of cache occupancy 3227system.l2c.tags.occ_percent::cpu0.itb.walker 0.000905 # Average percentage of cache occupancy 3228system.l2c.tags.occ_percent::cpu0.inst 0.054621 # Average percentage of cache occupancy 3229system.l2c.tags.occ_percent::cpu0.data 0.077610 # Average percentage of cache occupancy 3230system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.058215 # Average percentage of cache occupancy 3231system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004520 # Average percentage of cache occupancy 3232system.l2c.tags.occ_percent::cpu1.itb.walker 0.006868 # Average percentage of cache occupancy 3233system.l2c.tags.occ_percent::cpu1.inst 0.055617 # Average percentage of cache occupancy 3234system.l2c.tags.occ_percent::cpu1.data 0.131440 # Average percentage of cache occupancy 3235system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.264277 # Average percentage of cache occupancy 3236system.l2c.tags.occ_percent::total 0.965002 # Average percentage of cache occupancy 3237system.l2c.tags.occ_task_id_blocks::1022 9601 # Occupied blocks per task id 3238system.l2c.tags.occ_task_id_blocks::1023 201 # Occupied blocks per task id 3239system.l2c.tags.occ_task_id_blocks::1024 49687 # Occupied blocks per task id 3240system.l2c.tags.age_task_id_blocks_1022::2 1158 # Occupied blocks per task id 3241system.l2c.tags.age_task_id_blocks_1022::3 504 # Occupied blocks per task id 3242system.l2c.tags.age_task_id_blocks_1022::4 7939 # Occupied blocks per task id 3243system.l2c.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id 3244system.l2c.tags.age_task_id_blocks_1023::4 193 # Occupied blocks per task id 3245system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id 3246system.l2c.tags.age_task_id_blocks_1024::1 374 # Occupied blocks per task id 3247system.l2c.tags.age_task_id_blocks_1024::2 2840 # Occupied blocks per task id 3248system.l2c.tags.age_task_id_blocks_1024::3 5617 # Occupied blocks per task id 3249system.l2c.tags.age_task_id_blocks_1024::4 40824 # Occupied blocks per task id 3250system.l2c.tags.occ_task_id_percent::1022 0.146500 # Percentage of cache occupancy per task id 3251system.l2c.tags.occ_task_id_percent::1023 0.003067 # Percentage of cache occupancy per task id 3252system.l2c.tags.occ_task_id_percent::1024 0.758163 # Percentage of cache occupancy per task id 3253system.l2c.tags.tag_accesses 79314813 # Number of tag accesses 3254system.l2c.tags.data_accesses 79314813 # Number of data accesses 3255system.l2c.WritebackDirty_hits::writebacks 2898844 # number of WritebackDirty hits 3256system.l2c.WritebackDirty_hits::total 2898844 # number of WritebackDirty hits 3257system.l2c.WritebackClean_hits::writebacks 4 # number of WritebackClean hits 3258system.l2c.WritebackClean_hits::total 4 # number of WritebackClean hits 3259system.l2c.UpgradeReq_hits::cpu0.data 171467 # number of UpgradeReq hits 3260system.l2c.UpgradeReq_hits::cpu1.data 140817 # number of UpgradeReq hits 3261system.l2c.UpgradeReq_hits::total 312284 # number of UpgradeReq hits 3262system.l2c.SCUpgradeReq_hits::cpu0.data 39034 # number of SCUpgradeReq hits 3263system.l2c.SCUpgradeReq_hits::cpu1.data 42272 # number of SCUpgradeReq hits 3264system.l2c.SCUpgradeReq_hits::total 81306 # number of SCUpgradeReq hits 3265system.l2c.ReadExReq_hits::cpu0.data 165571 # number of ReadExReq hits 3266system.l2c.ReadExReq_hits::cpu1.data 166162 # number of ReadExReq hits 3267system.l2c.ReadExReq_hits::total 331733 # number of ReadExReq hits 3268system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 6582 # number of ReadSharedReq hits 3269system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4549 # number of ReadSharedReq hits 3270system.l2c.ReadSharedReq_hits::cpu0.inst 520761 # number of ReadSharedReq hits 3271system.l2c.ReadSharedReq_hits::cpu0.data 620991 # number of ReadSharedReq hits 3272system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 302233 # number of ReadSharedReq hits 3273system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6543 # number of ReadSharedReq hits 3274system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4534 # number of ReadSharedReq hits 3275system.l2c.ReadSharedReq_hits::cpu1.inst 509705 # number of ReadSharedReq hits 3276system.l2c.ReadSharedReq_hits::cpu1.data 595476 # number of ReadSharedReq hits 3277system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 292636 # number of ReadSharedReq hits 3278system.l2c.ReadSharedReq_hits::total 2864010 # number of ReadSharedReq hits 3279system.l2c.demand_hits::cpu0.dtb.walker 6582 # number of demand (read+write) hits 3280system.l2c.demand_hits::cpu0.itb.walker 4549 # number of demand (read+write) hits 3281system.l2c.demand_hits::cpu0.inst 520761 # number of demand (read+write) hits 3282system.l2c.demand_hits::cpu0.data 786562 # number of demand (read+write) hits 3283system.l2c.demand_hits::cpu0.l2cache.prefetcher 302233 # number of demand (read+write) hits 3284system.l2c.demand_hits::cpu1.dtb.walker 6543 # number of demand (read+write) hits 3285system.l2c.demand_hits::cpu1.itb.walker 4534 # number of demand (read+write) hits 3286system.l2c.demand_hits::cpu1.inst 509705 # number of demand (read+write) hits 3287system.l2c.demand_hits::cpu1.data 761638 # number of demand (read+write) hits 3288system.l2c.demand_hits::cpu1.l2cache.prefetcher 292636 # number of demand (read+write) hits 3289system.l2c.demand_hits::total 3195743 # number of demand (read+write) hits 3290system.l2c.overall_hits::cpu0.dtb.walker 6582 # number of overall hits 3291system.l2c.overall_hits::cpu0.itb.walker 4549 # number of overall hits 3292system.l2c.overall_hits::cpu0.inst 520761 # number of overall hits 3293system.l2c.overall_hits::cpu0.data 786562 # number of overall hits 3294system.l2c.overall_hits::cpu0.l2cache.prefetcher 302233 # number of overall hits 3295system.l2c.overall_hits::cpu1.dtb.walker 6543 # number of overall hits 3296system.l2c.overall_hits::cpu1.itb.walker 4534 # number of overall hits 3297system.l2c.overall_hits::cpu1.inst 509705 # number of overall hits 3298system.l2c.overall_hits::cpu1.data 761638 # number of overall hits 3299system.l2c.overall_hits::cpu1.l2cache.prefetcher 292636 # number of overall hits 3300system.l2c.overall_hits::total 3195743 # number of overall hits 3301system.l2c.UpgradeReq_misses::cpu0.data 62046 # number of UpgradeReq misses 3302system.l2c.UpgradeReq_misses::cpu1.data 61831 # number of UpgradeReq misses 3303system.l2c.UpgradeReq_misses::total 123877 # number of UpgradeReq misses 3304system.l2c.SCUpgradeReq_misses::cpu0.data 12641 # number of SCUpgradeReq misses 3305system.l2c.SCUpgradeReq_misses::cpu1.data 11279 # number of SCUpgradeReq misses 3306system.l2c.SCUpgradeReq_misses::total 23920 # number of SCUpgradeReq misses 3307system.l2c.ReadExReq_misses::cpu0.data 543765 # number of ReadExReq misses 3308system.l2c.ReadExReq_misses::cpu1.data 121378 # number of ReadExReq misses 3309system.l2c.ReadExReq_misses::total 665143 # number of ReadExReq misses 3310system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2350 # number of ReadSharedReq misses 3311system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2224 # number of ReadSharedReq misses 3312system.l2c.ReadSharedReq_misses::cpu0.inst 62516 # number of ReadSharedReq misses 3313system.l2c.ReadSharedReq_misses::cpu0.data 155884 # number of ReadSharedReq misses 3314system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 318351 # number of ReadSharedReq misses 3315system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2672 # number of ReadSharedReq misses 3316system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2379 # number of ReadSharedReq misses 3317system.l2c.ReadSharedReq_misses::cpu1.inst 49130 # number of ReadSharedReq misses 3318system.l2c.ReadSharedReq_misses::cpu1.data 126625 # number of ReadSharedReq misses 3319system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 232724 # number of ReadSharedReq misses 3320system.l2c.ReadSharedReq_misses::total 954855 # number of ReadSharedReq misses 3321system.l2c.demand_misses::cpu0.dtb.walker 2350 # number of demand (read+write) misses 3322system.l2c.demand_misses::cpu0.itb.walker 2224 # number of demand (read+write) misses 3323system.l2c.demand_misses::cpu0.inst 62516 # number of demand (read+write) misses 3324system.l2c.demand_misses::cpu0.data 699649 # number of demand (read+write) misses 3325system.l2c.demand_misses::cpu0.l2cache.prefetcher 318351 # number of demand (read+write) misses 3326system.l2c.demand_misses::cpu1.dtb.walker 2672 # number of demand (read+write) misses 3327system.l2c.demand_misses::cpu1.itb.walker 2379 # number of demand (read+write) misses 3328system.l2c.demand_misses::cpu1.inst 49130 # number of demand (read+write) misses 3329system.l2c.demand_misses::cpu1.data 248003 # number of demand (read+write) misses 3330system.l2c.demand_misses::cpu1.l2cache.prefetcher 232724 # number of demand (read+write) misses 3331system.l2c.demand_misses::total 1619998 # number of demand (read+write) misses 3332system.l2c.overall_misses::cpu0.dtb.walker 2350 # number of overall misses 3333system.l2c.overall_misses::cpu0.itb.walker 2224 # number of overall misses 3334system.l2c.overall_misses::cpu0.inst 62516 # number of overall misses 3335system.l2c.overall_misses::cpu0.data 699649 # number of overall misses 3336system.l2c.overall_misses::cpu0.l2cache.prefetcher 318351 # number of overall misses 3337system.l2c.overall_misses::cpu1.dtb.walker 2672 # number of overall misses 3338system.l2c.overall_misses::cpu1.itb.walker 2379 # number of overall misses 3339system.l2c.overall_misses::cpu1.inst 49130 # number of overall misses 3340system.l2c.overall_misses::cpu1.data 248003 # number of overall misses 3341system.l2c.overall_misses::cpu1.l2cache.prefetcher 232724 # number of overall misses 3342system.l2c.overall_misses::total 1619998 # number of overall misses 3343system.l2c.UpgradeReq_miss_latency::cpu0.data 1024631500 # number of UpgradeReq miss cycles 3344system.l2c.UpgradeReq_miss_latency::cpu1.data 1063145500 # number of UpgradeReq miss cycles 3345system.l2c.UpgradeReq_miss_latency::total 2087777000 # number of UpgradeReq miss cycles 3346system.l2c.SCUpgradeReq_miss_latency::cpu0.data 193873000 # number of SCUpgradeReq miss cycles 3347system.l2c.SCUpgradeReq_miss_latency::cpu1.data 194795500 # number of SCUpgradeReq miss cycles 3348system.l2c.SCUpgradeReq_miss_latency::total 388668500 # number of SCUpgradeReq miss cycles 3349system.l2c.ReadExReq_miss_latency::cpu0.data 89836611997 # number of ReadExReq miss cycles 3350system.l2c.ReadExReq_miss_latency::cpu1.data 17865168996 # number of ReadExReq miss cycles 3351system.l2c.ReadExReq_miss_latency::total 107701780993 # number of ReadExReq miss cycles 3352system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 337305500 # number of ReadSharedReq miss cycles 3353system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 317505000 # number of ReadSharedReq miss cycles 3354system.l2c.ReadSharedReq_miss_latency::cpu0.inst 8570748002 # number of ReadSharedReq miss cycles 3355system.l2c.ReadSharedReq_miss_latency::cpu0.data 22562577998 # number of ReadSharedReq miss cycles 3356system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 57125544763 # number of ReadSharedReq miss cycles 3357system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 382906000 # number of ReadSharedReq miss cycles 3358system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 336227500 # number of ReadSharedReq miss cycles 3359system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6715379500 # number of ReadSharedReq miss cycles 3360system.l2c.ReadSharedReq_miss_latency::cpu1.data 18141536999 # number of ReadSharedReq miss cycles 3361system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 41393713140 # number of ReadSharedReq miss cycles 3362system.l2c.ReadSharedReq_miss_latency::total 155883444402 # number of ReadSharedReq miss cycles 3363system.l2c.demand_miss_latency::cpu0.dtb.walker 337305500 # number of demand (read+write) miss cycles 3364system.l2c.demand_miss_latency::cpu0.itb.walker 317505000 # number of demand (read+write) miss cycles 3365system.l2c.demand_miss_latency::cpu0.inst 8570748002 # number of demand (read+write) miss cycles 3366system.l2c.demand_miss_latency::cpu0.data 112399189995 # number of demand (read+write) miss cycles 3367system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 57125544763 # number of demand (read+write) miss cycles 3368system.l2c.demand_miss_latency::cpu1.dtb.walker 382906000 # number of demand (read+write) miss cycles 3369system.l2c.demand_miss_latency::cpu1.itb.walker 336227500 # number of demand (read+write) miss cycles 3370system.l2c.demand_miss_latency::cpu1.inst 6715379500 # number of demand (read+write) miss cycles 3371system.l2c.demand_miss_latency::cpu1.data 36006705995 # number of demand (read+write) miss cycles 3372system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 41393713140 # number of demand (read+write) miss cycles 3373system.l2c.demand_miss_latency::total 263585225395 # number of demand (read+write) miss cycles 3374system.l2c.overall_miss_latency::cpu0.dtb.walker 337305500 # number of overall miss cycles 3375system.l2c.overall_miss_latency::cpu0.itb.walker 317505000 # number of overall miss cycles 3376system.l2c.overall_miss_latency::cpu0.inst 8570748002 # number of overall miss cycles 3377system.l2c.overall_miss_latency::cpu0.data 112399189995 # number of overall miss cycles 3378system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 57125544763 # number of overall miss cycles 3379system.l2c.overall_miss_latency::cpu1.dtb.walker 382906000 # number of overall miss cycles 3380system.l2c.overall_miss_latency::cpu1.itb.walker 336227500 # number of overall miss cycles 3381system.l2c.overall_miss_latency::cpu1.inst 6715379500 # number of overall miss cycles 3382system.l2c.overall_miss_latency::cpu1.data 36006705995 # number of overall miss cycles 3383system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 41393713140 # number of overall miss cycles 3384system.l2c.overall_miss_latency::total 263585225395 # number of overall miss cycles 3385system.l2c.WritebackDirty_accesses::writebacks 2898844 # number of WritebackDirty accesses(hits+misses) 3386system.l2c.WritebackDirty_accesses::total 2898844 # number of WritebackDirty accesses(hits+misses) 3387system.l2c.WritebackClean_accesses::writebacks 4 # number of WritebackClean accesses(hits+misses) 3388system.l2c.WritebackClean_accesses::total 4 # number of WritebackClean accesses(hits+misses) 3389system.l2c.UpgradeReq_accesses::cpu0.data 233513 # number of UpgradeReq accesses(hits+misses) 3390system.l2c.UpgradeReq_accesses::cpu1.data 202648 # number of UpgradeReq accesses(hits+misses) 3391system.l2c.UpgradeReq_accesses::total 436161 # number of UpgradeReq accesses(hits+misses) 3392system.l2c.SCUpgradeReq_accesses::cpu0.data 51675 # number of SCUpgradeReq accesses(hits+misses) 3393system.l2c.SCUpgradeReq_accesses::cpu1.data 53551 # number of SCUpgradeReq accesses(hits+misses) 3394system.l2c.SCUpgradeReq_accesses::total 105226 # number of SCUpgradeReq accesses(hits+misses) 3395system.l2c.ReadExReq_accesses::cpu0.data 709336 # number of ReadExReq accesses(hits+misses) 3396system.l2c.ReadExReq_accesses::cpu1.data 287540 # number of ReadExReq accesses(hits+misses) 3397system.l2c.ReadExReq_accesses::total 996876 # number of ReadExReq accesses(hits+misses) 3398system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8932 # number of ReadSharedReq accesses(hits+misses) 3399system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 6773 # number of ReadSharedReq accesses(hits+misses) 3400system.l2c.ReadSharedReq_accesses::cpu0.inst 583277 # number of ReadSharedReq accesses(hits+misses) 3401system.l2c.ReadSharedReq_accesses::cpu0.data 776875 # number of ReadSharedReq accesses(hits+misses) 3402system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 620584 # number of ReadSharedReq accesses(hits+misses) 3403system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 9215 # number of ReadSharedReq accesses(hits+misses) 3404system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6913 # number of ReadSharedReq accesses(hits+misses) 3405system.l2c.ReadSharedReq_accesses::cpu1.inst 558835 # number of ReadSharedReq accesses(hits+misses) 3406system.l2c.ReadSharedReq_accesses::cpu1.data 722101 # number of ReadSharedReq accesses(hits+misses) 3407system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 525360 # number of ReadSharedReq accesses(hits+misses) 3408system.l2c.ReadSharedReq_accesses::total 3818865 # number of ReadSharedReq accesses(hits+misses) 3409system.l2c.demand_accesses::cpu0.dtb.walker 8932 # number of demand (read+write) accesses 3410system.l2c.demand_accesses::cpu0.itb.walker 6773 # number of demand (read+write) accesses 3411system.l2c.demand_accesses::cpu0.inst 583277 # number of demand (read+write) accesses 3412system.l2c.demand_accesses::cpu0.data 1486211 # number of demand (read+write) accesses 3413system.l2c.demand_accesses::cpu0.l2cache.prefetcher 620584 # number of demand (read+write) accesses 3414system.l2c.demand_accesses::cpu1.dtb.walker 9215 # number of demand (read+write) accesses 3415system.l2c.demand_accesses::cpu1.itb.walker 6913 # number of demand (read+write) accesses 3416system.l2c.demand_accesses::cpu1.inst 558835 # number of demand (read+write) accesses 3417system.l2c.demand_accesses::cpu1.data 1009641 # number of demand (read+write) accesses 3418system.l2c.demand_accesses::cpu1.l2cache.prefetcher 525360 # number of demand (read+write) accesses 3419system.l2c.demand_accesses::total 4815741 # number of demand (read+write) accesses 3420system.l2c.overall_accesses::cpu0.dtb.walker 8932 # number of overall (read+write) accesses 3421system.l2c.overall_accesses::cpu0.itb.walker 6773 # number of overall (read+write) accesses 3422system.l2c.overall_accesses::cpu0.inst 583277 # number of overall (read+write) accesses 3423system.l2c.overall_accesses::cpu0.data 1486211 # number of overall (read+write) accesses 3424system.l2c.overall_accesses::cpu0.l2cache.prefetcher 620584 # number of overall (read+write) accesses 3425system.l2c.overall_accesses::cpu1.dtb.walker 9215 # number of overall (read+write) accesses 3426system.l2c.overall_accesses::cpu1.itb.walker 6913 # number of overall (read+write) accesses 3427system.l2c.overall_accesses::cpu1.inst 558835 # number of overall (read+write) accesses 3428system.l2c.overall_accesses::cpu1.data 1009641 # number of overall (read+write) accesses 3429system.l2c.overall_accesses::cpu1.l2cache.prefetcher 525360 # number of overall (read+write) accesses 3430system.l2c.overall_accesses::total 4815741 # number of overall (read+write) accesses 3431system.l2c.UpgradeReq_miss_rate::cpu0.data 0.265707 # miss rate for UpgradeReq accesses 3432system.l2c.UpgradeReq_miss_rate::cpu1.data 0.305115 # miss rate for UpgradeReq accesses 3433system.l2c.UpgradeReq_miss_rate::total 0.284017 # miss rate for UpgradeReq accesses 3434system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.244625 # miss rate for SCUpgradeReq accesses 3435system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.210622 # miss rate for SCUpgradeReq accesses 3436system.l2c.SCUpgradeReq_miss_rate::total 0.227320 # miss rate for SCUpgradeReq accesses 3437system.l2c.ReadExReq_miss_rate::cpu0.data 0.766583 # miss rate for ReadExReq accesses 3438system.l2c.ReadExReq_miss_rate::cpu1.data 0.422126 # miss rate for ReadExReq accesses 3439system.l2c.ReadExReq_miss_rate::total 0.667227 # miss rate for ReadExReq accesses 3440system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.263099 # miss rate for ReadSharedReq accesses 3441system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.328363 # miss rate for ReadSharedReq accesses 3442system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.107181 # miss rate for ReadSharedReq accesses 3443system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.200655 # miss rate for ReadSharedReq accesses 3444system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.512986 # miss rate for ReadSharedReq accesses 3445system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.289962 # miss rate for ReadSharedReq accesses 3446system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.344134 # miss rate for ReadSharedReq accesses 3447system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.087915 # miss rate for ReadSharedReq accesses 3448system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.175356 # miss rate for ReadSharedReq accesses 3449system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.442980 # miss rate for ReadSharedReq accesses 3450system.l2c.ReadSharedReq_miss_rate::total 0.250036 # miss rate for ReadSharedReq accesses 3451system.l2c.demand_miss_rate::cpu0.dtb.walker 0.263099 # miss rate for demand accesses 3452system.l2c.demand_miss_rate::cpu0.itb.walker 0.328363 # miss rate for demand accesses 3453system.l2c.demand_miss_rate::cpu0.inst 0.107181 # miss rate for demand accesses 3454system.l2c.demand_miss_rate::cpu0.data 0.470760 # miss rate for demand accesses 3455system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.512986 # miss rate for demand accesses 3456system.l2c.demand_miss_rate::cpu1.dtb.walker 0.289962 # miss rate for demand accesses 3457system.l2c.demand_miss_rate::cpu1.itb.walker 0.344134 # miss rate for demand accesses 3458system.l2c.demand_miss_rate::cpu1.inst 0.087915 # miss rate for demand accesses 3459system.l2c.demand_miss_rate::cpu1.data 0.245635 # miss rate for demand accesses 3460system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.442980 # miss rate for demand accesses 3461system.l2c.demand_miss_rate::total 0.336396 # miss rate for demand accesses 3462system.l2c.overall_miss_rate::cpu0.dtb.walker 0.263099 # miss rate for overall accesses 3463system.l2c.overall_miss_rate::cpu0.itb.walker 0.328363 # miss rate for overall accesses 3464system.l2c.overall_miss_rate::cpu0.inst 0.107181 # miss rate for overall accesses 3465system.l2c.overall_miss_rate::cpu0.data 0.470760 # miss rate for overall accesses 3466system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.512986 # miss rate for overall accesses 3467system.l2c.overall_miss_rate::cpu1.dtb.walker 0.289962 # miss rate for overall accesses 3468system.l2c.overall_miss_rate::cpu1.itb.walker 0.344134 # miss rate for overall accesses 3469system.l2c.overall_miss_rate::cpu1.inst 0.087915 # miss rate for overall accesses 3470system.l2c.overall_miss_rate::cpu1.data 0.245635 # miss rate for overall accesses 3471system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.442980 # miss rate for overall accesses 3472system.l2c.overall_miss_rate::total 0.336396 # miss rate for overall accesses 3473system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16514.062147 # average UpgradeReq miss latency 3474system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17194.376607 # average UpgradeReq miss latency 3475system.l2c.UpgradeReq_avg_miss_latency::total 16853.629003 # average UpgradeReq miss latency 3476system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15336.840440 # average SCUpgradeReq miss latency 3477system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 17270.635695 # average SCUpgradeReq miss latency 3478system.l2c.SCUpgradeReq_avg_miss_latency::total 16248.683110 # average SCUpgradeReq miss latency 3479system.l2c.ReadExReq_avg_miss_latency::cpu0.data 165212.200118 # average ReadExReq miss latency 3480system.l2c.ReadExReq_avg_miss_latency::cpu1.data 147186.219875 # average ReadExReq miss latency 3481system.l2c.ReadExReq_avg_miss_latency::total 161922.745925 # average ReadExReq miss latency 3482system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 143534.255319 # average ReadSharedReq miss latency 3483system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 142763.039568 # average ReadSharedReq miss latency 3484system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 137096.871233 # average ReadSharedReq miss latency 3485system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 144739.537079 # average ReadSharedReq miss latency 3486system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 179442.014515 # average ReadSharedReq miss latency 3487system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 143303.143713 # average ReadSharedReq miss latency 3488system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 141331.441782 # average ReadSharedReq miss latency 3489system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 136685.925097 # average ReadSharedReq miss latency 3490system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 143269.788738 # average ReadSharedReq miss latency 3491system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 177866.112391 # average ReadSharedReq miss latency 3492system.l2c.ReadSharedReq_avg_miss_latency::total 163253.524778 # average ReadSharedReq miss latency 3493system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 143534.255319 # average overall miss latency 3494system.l2c.demand_avg_miss_latency::cpu0.itb.walker 142763.039568 # average overall miss latency 3495system.l2c.demand_avg_miss_latency::cpu0.inst 137096.871233 # average overall miss latency 3496system.l2c.demand_avg_miss_latency::cpu0.data 160650.826336 # average overall miss latency 3497system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 179442.014515 # average overall miss latency 3498system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 143303.143713 # average overall miss latency 3499system.l2c.demand_avg_miss_latency::cpu1.itb.walker 141331.441782 # average overall miss latency 3500system.l2c.demand_avg_miss_latency::cpu1.inst 136685.925097 # average overall miss latency 3501system.l2c.demand_avg_miss_latency::cpu1.data 145186.574336 # average overall miss latency 3502system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 177866.112391 # average overall miss latency 3503system.l2c.demand_avg_miss_latency::total 162707.130129 # average overall miss latency 3504system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 143534.255319 # average overall miss latency 3505system.l2c.overall_avg_miss_latency::cpu0.itb.walker 142763.039568 # average overall miss latency 3506system.l2c.overall_avg_miss_latency::cpu0.inst 137096.871233 # average overall miss latency 3507system.l2c.overall_avg_miss_latency::cpu0.data 160650.826336 # average overall miss latency 3508system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 179442.014515 # average overall miss latency 3509system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 143303.143713 # average overall miss latency 3510system.l2c.overall_avg_miss_latency::cpu1.itb.walker 141331.441782 # average overall miss latency 3511system.l2c.overall_avg_miss_latency::cpu1.inst 136685.925097 # average overall miss latency 3512system.l2c.overall_avg_miss_latency::cpu1.data 145186.574336 # average overall miss latency 3513system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 177866.112391 # average overall miss latency 3514system.l2c.overall_avg_miss_latency::total 162707.130129 # average overall miss latency 3515system.l2c.blocked_cycles::no_mshrs 17532 # number of cycles access was blocked 3516system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 3517system.l2c.blocked::no_mshrs 141 # number of cycles access was blocked 3518system.l2c.blocked::no_targets 0 # number of cycles access was blocked 3519system.l2c.avg_blocked_cycles::no_mshrs 124.340426 # average number of cycles each access was blocked 3520system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3521system.l2c.fast_writes 0 # number of fast writes performed 3522system.l2c.cache_copies 0 # number of cache copies performed 3523system.l2c.writebacks::writebacks 1238890 # number of writebacks 3524system.l2c.writebacks::total 1238890 # number of writebacks 3525system.l2c.ReadExReq_mshr_hits::cpu0.data 1 # number of ReadExReq MSHR hits 3526system.l2c.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits 3527system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 219 # number of ReadSharedReq MSHR hits 3528system.l2c.ReadSharedReq_mshr_hits::cpu0.data 33 # number of ReadSharedReq MSHR hits 3529system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 244 # number of ReadSharedReq MSHR hits 3530system.l2c.ReadSharedReq_mshr_hits::cpu1.data 32 # number of ReadSharedReq MSHR hits 3531system.l2c.ReadSharedReq_mshr_hits::total 528 # number of ReadSharedReq MSHR hits 3532system.l2c.demand_mshr_hits::cpu0.inst 219 # number of demand (read+write) MSHR hits 3533system.l2c.demand_mshr_hits::cpu0.data 34 # number of demand (read+write) MSHR hits 3534system.l2c.demand_mshr_hits::cpu1.inst 244 # number of demand (read+write) MSHR hits 3535system.l2c.demand_mshr_hits::cpu1.data 32 # number of demand (read+write) MSHR hits 3536system.l2c.demand_mshr_hits::total 529 # number of demand (read+write) MSHR hits 3537system.l2c.overall_mshr_hits::cpu0.inst 219 # number of overall MSHR hits 3538system.l2c.overall_mshr_hits::cpu0.data 34 # number of overall MSHR hits 3539system.l2c.overall_mshr_hits::cpu1.inst 244 # number of overall MSHR hits 3540system.l2c.overall_mshr_hits::cpu1.data 32 # number of overall MSHR hits 3541system.l2c.overall_mshr_hits::total 529 # number of overall MSHR hits 3542system.l2c.CleanEvict_mshr_misses::writebacks 60450 # number of CleanEvict MSHR misses 3543system.l2c.CleanEvict_mshr_misses::total 60450 # number of CleanEvict MSHR misses 3544system.l2c.UpgradeReq_mshr_misses::cpu0.data 62046 # number of UpgradeReq MSHR misses 3545system.l2c.UpgradeReq_mshr_misses::cpu1.data 61831 # number of UpgradeReq MSHR misses 3546system.l2c.UpgradeReq_mshr_misses::total 123877 # number of UpgradeReq MSHR misses 3547system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 12641 # number of SCUpgradeReq MSHR misses 3548system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11279 # number of SCUpgradeReq MSHR misses 3549system.l2c.SCUpgradeReq_mshr_misses::total 23920 # number of SCUpgradeReq MSHR misses 3550system.l2c.ReadExReq_mshr_misses::cpu0.data 543764 # number of ReadExReq MSHR misses 3551system.l2c.ReadExReq_mshr_misses::cpu1.data 121378 # number of ReadExReq MSHR misses 3552system.l2c.ReadExReq_mshr_misses::total 665142 # number of ReadExReq MSHR misses 3553system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2350 # number of ReadSharedReq MSHR misses 3554system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2224 # number of ReadSharedReq MSHR misses 3555system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 62297 # number of ReadSharedReq MSHR misses 3556system.l2c.ReadSharedReq_mshr_misses::cpu0.data 155851 # number of ReadSharedReq MSHR misses 3557system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 318351 # number of ReadSharedReq MSHR misses 3558system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2672 # number of ReadSharedReq MSHR misses 3559system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2379 # number of ReadSharedReq MSHR misses 3560system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 48886 # number of ReadSharedReq MSHR misses 3561system.l2c.ReadSharedReq_mshr_misses::cpu1.data 126593 # number of ReadSharedReq MSHR misses 3562system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 232724 # number of ReadSharedReq MSHR misses 3563system.l2c.ReadSharedReq_mshr_misses::total 954327 # number of ReadSharedReq MSHR misses 3564system.l2c.demand_mshr_misses::cpu0.dtb.walker 2350 # number of demand (read+write) MSHR misses 3565system.l2c.demand_mshr_misses::cpu0.itb.walker 2224 # number of demand (read+write) MSHR misses 3566system.l2c.demand_mshr_misses::cpu0.inst 62297 # number of demand (read+write) MSHR misses 3567system.l2c.demand_mshr_misses::cpu0.data 699615 # number of demand (read+write) MSHR misses 3568system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 318351 # number of demand (read+write) MSHR misses 3569system.l2c.demand_mshr_misses::cpu1.dtb.walker 2672 # number of demand (read+write) MSHR misses 3570system.l2c.demand_mshr_misses::cpu1.itb.walker 2379 # number of demand (read+write) MSHR misses 3571system.l2c.demand_mshr_misses::cpu1.inst 48886 # number of demand (read+write) MSHR misses 3572system.l2c.demand_mshr_misses::cpu1.data 247971 # number of demand (read+write) MSHR misses 3573system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 232724 # number of demand (read+write) MSHR misses 3574system.l2c.demand_mshr_misses::total 1619469 # number of demand (read+write) MSHR misses 3575system.l2c.overall_mshr_misses::cpu0.dtb.walker 2350 # number of overall MSHR misses 3576system.l2c.overall_mshr_misses::cpu0.itb.walker 2224 # number of overall MSHR misses 3577system.l2c.overall_mshr_misses::cpu0.inst 62297 # number of overall MSHR misses 3578system.l2c.overall_mshr_misses::cpu0.data 699615 # number of overall MSHR misses 3579system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 318351 # number of overall MSHR misses 3580system.l2c.overall_mshr_misses::cpu1.dtb.walker 2672 # number of overall MSHR misses 3581system.l2c.overall_mshr_misses::cpu1.itb.walker 2379 # number of overall MSHR misses 3582system.l2c.overall_mshr_misses::cpu1.inst 48886 # number of overall MSHR misses 3583system.l2c.overall_mshr_misses::cpu1.data 247971 # number of overall MSHR misses 3584system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 232724 # number of overall MSHR misses 3585system.l2c.overall_mshr_misses::total 1619469 # number of overall MSHR misses 3586system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable 3587system.l2c.ReadReq_mshr_uncacheable::cpu0.data 32157 # number of ReadReq MSHR uncacheable 3588system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 3589system.l2c.ReadReq_mshr_uncacheable::cpu1.data 6297 # number of ReadReq MSHR uncacheable 3590system.l2c.ReadReq_mshr_uncacheable::total 59814 # number of ReadReq MSHR uncacheable 3591system.l2c.WriteReq_mshr_uncacheable::cpu0.data 31964 # number of WriteReq MSHR uncacheable 3592system.l2c.WriteReq_mshr_uncacheable::cpu1.data 6428 # number of WriteReq MSHR uncacheable 3593system.l2c.WriteReq_mshr_uncacheable::total 38392 # number of WriteReq MSHR uncacheable 3594system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses 3595system.l2c.overall_mshr_uncacheable_misses::cpu0.data 64121 # number of overall MSHR uncacheable misses 3596system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 3597system.l2c.overall_mshr_uncacheable_misses::cpu1.data 12725 # number of overall MSHR uncacheable misses 3598system.l2c.overall_mshr_uncacheable_misses::total 98206 # number of overall MSHR uncacheable misses 3599system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 4564244502 # number of UpgradeReq MSHR miss cycles 3600system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4544780000 # number of UpgradeReq MSHR miss cycles 3601system.l2c.UpgradeReq_mshr_miss_latency::total 9109024502 # number of UpgradeReq MSHR miss cycles 3602system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 967924994 # number of SCUpgradeReq MSHR miss cycles 3603system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 862182998 # number of SCUpgradeReq MSHR miss cycles 3604system.l2c.SCUpgradeReq_mshr_miss_latency::total 1830107992 # number of SCUpgradeReq MSHR miss cycles 3605system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 84398895997 # number of ReadExReq MSHR miss cycles 3606system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 16651388996 # number of ReadExReq MSHR miss cycles 3607system.l2c.ReadExReq_mshr_miss_latency::total 101050284993 # number of ReadExReq MSHR miss cycles 3608system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 313805500 # number of ReadSharedReq MSHR miss cycles 3609system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 295265000 # number of ReadSharedReq MSHR miss cycles 3610system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 7922359002 # number of ReadSharedReq MSHR miss cycles 3611system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 21000185498 # number of ReadSharedReq MSHR miss cycles 3612system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 53942034763 # number of ReadSharedReq MSHR miss cycles 3613system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 356186000 # number of ReadSharedReq MSHR miss cycles 3614system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 312437500 # number of ReadSharedReq MSHR miss cycles 3615system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 6197673000 # number of ReadSharedReq MSHR miss cycles 3616system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 16871940499 # number of ReadSharedReq MSHR miss cycles 3617system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 39066473140 # number of ReadSharedReq MSHR miss cycles 3618system.l2c.ReadSharedReq_mshr_miss_latency::total 146278359902 # number of ReadSharedReq MSHR miss cycles 3619system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 313805500 # number of demand (read+write) MSHR miss cycles 3620system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 295265000 # number of demand (read+write) MSHR miss cycles 3621system.l2c.demand_mshr_miss_latency::cpu0.inst 7922359002 # number of demand (read+write) MSHR miss cycles 3622system.l2c.demand_mshr_miss_latency::cpu0.data 105399081495 # number of demand (read+write) MSHR miss cycles 3623system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 53942034763 # number of demand (read+write) MSHR miss cycles 3624system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 356186000 # number of demand (read+write) MSHR miss cycles 3625system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 312437500 # number of demand (read+write) MSHR miss cycles 3626system.l2c.demand_mshr_miss_latency::cpu1.inst 6197673000 # number of demand (read+write) MSHR miss cycles 3627system.l2c.demand_mshr_miss_latency::cpu1.data 33523329495 # number of demand (read+write) MSHR miss cycles 3628system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 39066473140 # number of demand (read+write) MSHR miss cycles 3629system.l2c.demand_mshr_miss_latency::total 247328644895 # number of demand (read+write) MSHR miss cycles 3630system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 313805500 # number of overall MSHR miss cycles 3631system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 295265000 # number of overall MSHR miss cycles 3632system.l2c.overall_mshr_miss_latency::cpu0.inst 7922359002 # number of overall MSHR miss cycles 3633system.l2c.overall_mshr_miss_latency::cpu0.data 105399081495 # number of overall MSHR miss cycles 3634system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 53942034763 # number of overall MSHR miss cycles 3635system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 356186000 # number of overall MSHR miss cycles 3636system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 312437500 # number of overall MSHR miss cycles 3637system.l2c.overall_mshr_miss_latency::cpu1.inst 6197673000 # number of overall MSHR miss cycles 3638system.l2c.overall_mshr_miss_latency::cpu1.data 33523329495 # number of overall MSHR miss cycles 3639system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 39066473140 # number of overall MSHR miss cycles 3640system.l2c.overall_mshr_miss_latency::total 247328644895 # number of overall MSHR miss cycles 3641system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2396808000 # number of ReadReq MSHR uncacheable cycles 3642system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5339273500 # number of ReadReq MSHR uncacheable cycles 3643system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7124500 # number of ReadReq MSHR uncacheable cycles 3644system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 563876500 # number of ReadReq MSHR uncacheable cycles 3645system.l2c.ReadReq_mshr_uncacheable_latency::total 8307082500 # number of ReadReq MSHR uncacheable cycles 3646system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 5257909033 # number of WriteReq MSHR uncacheable cycles 3647system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 701977500 # number of WriteReq MSHR uncacheable cycles 3648system.l2c.WriteReq_mshr_uncacheable_latency::total 5959886533 # number of WriteReq MSHR uncacheable cycles 3649system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2396808000 # number of overall MSHR uncacheable cycles 3650system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10597182533 # number of overall MSHR uncacheable cycles 3651system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7124500 # number of overall MSHR uncacheable cycles 3652system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1265854000 # number of overall MSHR uncacheable cycles 3653system.l2c.overall_mshr_uncacheable_latency::total 14266969033 # number of overall MSHR uncacheable cycles 3654system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3655system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3656system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.265707 # mshr miss rate for UpgradeReq accesses 3657system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.305115 # mshr miss rate for UpgradeReq accesses 3658system.l2c.UpgradeReq_mshr_miss_rate::total 0.284017 # mshr miss rate for UpgradeReq accesses 3659system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.244625 # mshr miss rate for SCUpgradeReq accesses 3660system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.210622 # mshr miss rate for SCUpgradeReq accesses 3661system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.227320 # mshr miss rate for SCUpgradeReq accesses 3662system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.766582 # mshr miss rate for ReadExReq accesses 3663system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.422126 # mshr miss rate for ReadExReq accesses 3664system.l2c.ReadExReq_mshr_miss_rate::total 0.667226 # mshr miss rate for ReadExReq accesses 3665system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.263099 # mshr miss rate for ReadSharedReq accesses 3666system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.328363 # mshr miss rate for ReadSharedReq accesses 3667system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.106805 # mshr miss rate for ReadSharedReq accesses 3668system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.200613 # mshr miss rate for ReadSharedReq accesses 3669system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.512986 # mshr miss rate for ReadSharedReq accesses 3670system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.289962 # mshr miss rate for ReadSharedReq accesses 3671system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.344134 # mshr miss rate for ReadSharedReq accesses 3672system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.087478 # mshr miss rate for ReadSharedReq accesses 3673system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.175312 # mshr miss rate for ReadSharedReq accesses 3674system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.442980 # mshr miss rate for ReadSharedReq accesses 3675system.l2c.ReadSharedReq_mshr_miss_rate::total 0.249898 # mshr miss rate for ReadSharedReq accesses 3676system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.263099 # mshr miss rate for demand accesses 3677system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.328363 # mshr miss rate for demand accesses 3678system.l2c.demand_mshr_miss_rate::cpu0.inst 0.106805 # mshr miss rate for demand accesses 3679system.l2c.demand_mshr_miss_rate::cpu0.data 0.470737 # mshr miss rate for demand accesses 3680system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.512986 # mshr miss rate for demand accesses 3681system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.289962 # mshr miss rate for demand accesses 3682system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.344134 # mshr miss rate for demand accesses 3683system.l2c.demand_mshr_miss_rate::cpu1.inst 0.087478 # mshr miss rate for demand accesses 3684system.l2c.demand_mshr_miss_rate::cpu1.data 0.245603 # mshr miss rate for demand accesses 3685system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.442980 # mshr miss rate for demand accesses 3686system.l2c.demand_mshr_miss_rate::total 0.336287 # mshr miss rate for demand accesses 3687system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.263099 # mshr miss rate for overall accesses 3688system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.328363 # mshr miss rate for overall accesses 3689system.l2c.overall_mshr_miss_rate::cpu0.inst 0.106805 # mshr miss rate for overall accesses 3690system.l2c.overall_mshr_miss_rate::cpu0.data 0.470737 # mshr miss rate for overall accesses 3691system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.512986 # mshr miss rate for overall accesses 3692system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.289962 # mshr miss rate for overall accesses 3693system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.344134 # mshr miss rate for overall accesses 3694system.l2c.overall_mshr_miss_rate::cpu1.inst 0.087478 # mshr miss rate for overall accesses 3695system.l2c.overall_mshr_miss_rate::cpu1.data 0.245603 # mshr miss rate for overall accesses 3696system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.442980 # mshr miss rate for overall accesses 3697system.l2c.overall_mshr_miss_rate::total 0.336287 # mshr miss rate for overall accesses 3698system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73562.268349 # average UpgradeReq mshr miss latency 3699system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73503.258883 # average UpgradeReq mshr miss latency 3700system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73532.814824 # average UpgradeReq mshr miss latency 3701system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76570.286686 # average SCUpgradeReq mshr miss latency 3702system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76441.439667 # average SCUpgradeReq mshr miss latency 3703system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76509.531438 # average SCUpgradeReq mshr miss latency 3704system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 155212.364182 # average ReadExReq mshr miss latency 3705system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 137186.219875 # average ReadExReq mshr miss latency 3706system.l2c.ReadExReq_avg_mshr_miss_latency::total 151922.875105 # average ReadExReq mshr miss latency 3707system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 133534.255319 # average ReadSharedReq mshr miss latency 3708system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 132763.039568 # average ReadSharedReq mshr miss latency 3709system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 127170.794773 # average ReadSharedReq mshr miss latency 3710system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 134745.272716 # average ReadSharedReq mshr miss latency 3711system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 169442.014515 # average ReadSharedReq mshr miss latency 3712system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 133303.143713 # average ReadSharedReq mshr miss latency 3713system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 131331.441782 # average ReadSharedReq mshr miss latency 3714system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 126778.075523 # average ReadSharedReq mshr miss latency 3715system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 133277.041377 # average ReadSharedReq mshr miss latency 3716system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167866.112391 # average ReadSharedReq mshr miss latency 3717system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 153279.075099 # average ReadSharedReq mshr miss latency 3718system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 133534.255319 # average overall mshr miss latency 3719system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 132763.039568 # average overall mshr miss latency 3720system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 127170.794773 # average overall mshr miss latency 3721system.l2c.demand_avg_mshr_miss_latency::cpu0.data 150652.975558 # average overall mshr miss latency 3722system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 169442.014515 # average overall mshr miss latency 3723system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 133303.143713 # average overall mshr miss latency 3724system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 131331.441782 # average overall mshr miss latency 3725system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 126778.075523 # average overall mshr miss latency 3726system.l2c.demand_avg_mshr_miss_latency::cpu1.data 135190.524275 # average overall mshr miss latency 3727system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167866.112391 # average overall mshr miss latency 3728system.l2c.demand_avg_mshr_miss_latency::total 152722.061920 # average overall mshr miss latency 3729system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 133534.255319 # average overall mshr miss latency 3730system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 132763.039568 # average overall mshr miss latency 3731system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 127170.794773 # average overall mshr miss latency 3732system.l2c.overall_avg_mshr_miss_latency::cpu0.data 150652.975558 # average overall mshr miss latency 3733system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 169442.014515 # average overall mshr miss latency 3734system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 133303.143713 # average overall mshr miss latency 3735system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 131331.441782 # average overall mshr miss latency 3736system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 126778.075523 # average overall mshr miss latency 3737system.l2c.overall_avg_mshr_miss_latency::cpu1.data 135190.524275 # average overall mshr miss latency 3738system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 167866.112391 # average overall mshr miss latency 3739system.l2c.overall_avg_mshr_miss_latency::total 152722.061920 # average overall mshr miss latency 3740system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781 # average ReadReq mshr uncacheable latency 3741system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166037.674534 # average ReadReq mshr uncacheable latency 3742system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 106335.820896 # average ReadReq mshr uncacheable latency 3743system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 89546.847705 # average ReadReq mshr uncacheable latency 3744system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 138881.908918 # average ReadReq mshr uncacheable latency 3745system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164494.713834 # average WriteReq mshr uncacheable latency 3746system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 109206.207218 # average WriteReq mshr uncacheable latency 3747system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155237.719655 # average WriteReq mshr uncacheable latency 3748system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781 # average overall mshr uncacheable latency 3749system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 165268.516290 # average overall mshr uncacheable latency 3750system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 106335.820896 # average overall mshr uncacheable latency 3751system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 99477.721022 # average overall mshr uncacheable latency 3752system.l2c.overall_avg_mshr_uncacheable_latency::total 145275.940706 # average overall mshr uncacheable latency 3753system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3754system.membus.trans_dist::ReadReq 59814 # Transaction distribution 3755system.membus.trans_dist::ReadResp 1023090 # Transaction distribution 3756system.membus.trans_dist::WriteReq 38392 # Transaction distribution 3757system.membus.trans_dist::WriteResp 38392 # Transaction distribution 3758system.membus.trans_dist::WritebackDirty 1345584 # Transaction distribution 3759system.membus.trans_dist::CleanEvict 266165 # Transaction distribution 3760system.membus.trans_dist::UpgradeReq 443726 # Transaction distribution 3761system.membus.trans_dist::SCUpgradeReq 302861 # Transaction distribution 3762system.membus.trans_dist::UpgradeResp 156448 # Transaction distribution 3763system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution 3764system.membus.trans_dist::ReadExReq 676664 # Transaction distribution 3765system.membus.trans_dist::ReadExResp 656494 # Transaction distribution 3766system.membus.trans_dist::ReadSharedReq 963276 # Transaction distribution 3767system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution 3768system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution 3769system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122562 # Packet count per connected master and slave (bytes) 3770system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) 3771system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25910 # Packet count per connected master and slave (bytes) 3772system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5690514 # Packet count per connected master and slave (bytes) 3773system.membus.pkt_count_system.l2c.mem_side::total 5839062 # Packet count per connected master and slave (bytes) 3774system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342298 # Packet count per connected master and slave (bytes) 3775system.membus.pkt_count_system.iocache.mem_side::total 342298 # Packet count per connected master and slave (bytes) 3776system.membus.pkt_count::total 6181360 # Packet count per connected master and slave (bytes) 3777system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155669 # Cumulative packet size per connected master and slave (bytes) 3778system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes) 3779system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51820 # Cumulative packet size per connected master and slave (bytes) 3780system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 182696832 # Cumulative packet size per connected master and slave (bytes) 3781system.membus.pkt_size_system.l2c.mem_side::total 182904877 # Cumulative packet size per connected master and slave (bytes) 3782system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7257216 # Cumulative packet size per connected master and slave (bytes) 3783system.membus.pkt_size_system.iocache.mem_side::total 7257216 # Cumulative packet size per connected master and slave (bytes) 3784system.membus.pkt_size::total 190162093 # Cumulative packet size per connected master and slave (bytes) 3785system.membus.snoops 613313 # Total snoops (count) 3786system.membus.snoop_fanout::samples 4205672 # Request fanout histogram 3787system.membus.snoop_fanout::mean 1 # Request fanout histogram 3788system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3789system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3790system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3791system.membus.snoop_fanout::1 4205672 100.00% 100.00% # Request fanout histogram 3792system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3793system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3794system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3795system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3796system.membus.snoop_fanout::total 4205672 # Request fanout histogram 3797system.membus.reqLayer0.occupancy 98421997 # Layer occupancy (ticks) 3798system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3799system.membus.reqLayer1.occupancy 53000 # Layer occupancy (ticks) 3800system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3801system.membus.reqLayer2.occupancy 21914471 # Layer occupancy (ticks) 3802system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3803system.membus.reqLayer5.occupancy 9436458556 # Layer occupancy (ticks) 3804system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3805system.membus.respLayer2.occupancy 8880795227 # Layer occupancy (ticks) 3806system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3807system.membus.respLayer3.occupancy 228859415 # Layer occupancy (ticks) 3808system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3809system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3810system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3811system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3812system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3813system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3814system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3815system.realview.ethernet.txBytes 966 # Bytes Transmitted 3816system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3817system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3818system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3819system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3820system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3821system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3822system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3823system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3824system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3825system.realview.ethernet.totPackets 3 # Total Packets 3826system.realview.ethernet.totBytes 966 # Total Bytes 3827system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3828system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3829system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3830system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3831system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3832system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3833system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3834system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3835system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3836system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3837system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3838system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3839system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3840system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3841system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3842system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3843system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3844system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3845system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3846system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3847system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3848system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3849system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3850system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3851system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3852system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3853system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3854system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3855system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3856system.realview.ethernet.droppedPackets 0 # number of packets dropped 3857system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3858system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3859system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3860system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3861system.toL2Bus.snoop_filter.tot_requests 12199905 # Total number of requests made to the snoop filter. 3862system.toL2Bus.snoop_filter.hit_single_requests 6623903 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3863system.toL2Bus.snoop_filter.hit_multi_requests 1949036 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3864system.toL2Bus.snoop_filter.tot_snoops 168152 # Total number of snoops made to the snoop filter. 3865system.toL2Bus.snoop_filter.hit_single_snoops 152817 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3866system.toL2Bus.snoop_filter.hit_multi_snoops 15335 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3867system.toL2Bus.trans_dist::ReadReq 59816 # Transaction distribution 3868system.toL2Bus.trans_dist::ReadResp 4662380 # Transaction distribution 3869system.toL2Bus.trans_dist::WriteReq 38392 # Transaction distribution 3870system.toL2Bus.trans_dist::WriteResp 38392 # Transaction distribution 3871system.toL2Bus.trans_dist::WritebackDirty 4244441 # Transaction distribution 3872system.toL2Bus.trans_dist::WritebackClean 4 # Transaction distribution 3873system.toL2Bus.trans_dist::CleanEvict 1619343 # Transaction distribution 3874system.toL2Bus.trans_dist::UpgradeReq 747362 # Transaction distribution 3875system.toL2Bus.trans_dist::SCUpgradeReq 384167 # Transaction distribution 3876system.toL2Bus.trans_dist::UpgradeResp 1131529 # Transaction distribution 3877system.toL2Bus.trans_dist::SCUpgradeFailReq 101 # Transaction distribution 3878system.toL2Bus.trans_dist::UpgradeFailResp 101 # Transaction distribution 3879system.toL2Bus.trans_dist::ReadExReq 1137603 # Transaction distribution 3880system.toL2Bus.trans_dist::ReadExResp 1137603 # Transaction distribution 3881system.toL2Bus.trans_dist::ReadSharedReq 4609811 # Transaction distribution 3882system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution 3883system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9241165 # Packet count per connected master and slave (bytes) 3884system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7356268 # Packet count per connected master and slave (bytes) 3885system.toL2Bus.pkt_count::total 16597433 # Packet count per connected master and slave (bytes) 3886system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 283441843 # Cumulative packet size per connected master and slave (bytes) 3887system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 210970938 # Cumulative packet size per connected master and slave (bytes) 3888system.toL2Bus.pkt_size::total 494412781 # Cumulative packet size per connected master and slave (bytes) 3889system.toL2Bus.snoops 3322045 # Total snoops (count) 3890system.toL2Bus.snoop_fanout::samples 8775737 # Request fanout histogram 3891system.toL2Bus.snoop_fanout::mean 0.344900 # Request fanout histogram 3892system.toL2Bus.snoop_fanout::stdev 0.478998 # Request fanout histogram 3893system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3894system.toL2Bus.snoop_fanout::0 5764320 65.68% 65.68% # Request fanout histogram 3895system.toL2Bus.snoop_fanout::1 2996082 34.14% 99.83% # Request fanout histogram 3896system.toL2Bus.snoop_fanout::2 15335 0.17% 100.00% # Request fanout histogram 3897system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3898system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3899system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3900system.toL2Bus.snoop_fanout::total 8775737 # Request fanout histogram 3901system.toL2Bus.reqLayer0.occupancy 9513972562 # Layer occupancy (ticks) 3902system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3903system.toL2Bus.snoopLayer0.occupancy 2693663 # Layer occupancy (ticks) 3904system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3905system.toL2Bus.respLayer0.occupancy 5075177047 # Layer occupancy (ticks) 3906system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3907system.toL2Bus.respLayer1.occupancy 4195991011 # Layer occupancy (ticks) 3908system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3909system.cpu0.kern.inst.arm 0 # number of arm instructions executed 3910system.cpu0.kern.inst.quiesce 12889 # number of quiesce instructions executed 3911system.cpu1.kern.inst.arm 0 # number of arm instructions executed 3912system.cpu1.kern.inst.quiesce 5680 # number of quiesce instructions executed 3913 3914---------- End Simulation Statistics ---------- 3915