stats.txt revision 11167:207d6f2f1d53
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.395178 # Number of seconds simulated 4sim_ticks 47395178174000 # Number of ticks simulated 5final_tick 47395178174000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 85380 # Simulator instruction rate (inst/s) 8host_op_rate 100389 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 4378207332 # Simulator tick rate (ticks/s) 10host_mem_usage 733200 # Number of bytes of host memory used 11host_seconds 10825.25 # Real time elapsed on the host 12sim_insts 924259255 # Number of instructions simulated 13sim_ops 1086731985 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 173952 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 172224 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 5051936 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 46751112 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 21558016 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 154688 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 128576 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 2266144 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 13742800 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 14572608 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 453056 # Number of bytes read from this memory 27system.physmem.bytes_read::total 105025112 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 5051936 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 2266144 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 7318080 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 87763520 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 34system.physmem.bytes_written::total 87784104 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 2718 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 2691 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 94889 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 730499 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 336844 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 2417 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 2009 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 35452 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 214744 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 227697 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 7079 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 1657039 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 1371305 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 50system.physmem.num_writes::total 1373879 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 3670 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 3634 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 106592 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 986411 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 454857 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 3264 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 2713 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 47814 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 289962 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 307470 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 9559 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 2215945 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 106592 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 47814 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 154406 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1851739 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::total 1852174 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1851739 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 3670 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 3634 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 106592 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 986845 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 454857 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 3264 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 2713 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 47814 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 289962 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 307470 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 9559 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 4068119 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 1657039 # Number of read requests accepted 84system.physmem.writeReqs 1373879 # Number of write requests accepted 85system.physmem.readBursts 1657039 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 1373879 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 106020736 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 29760 # Total number of bytes read from write queue 89system.physmem.bytesWritten 87783296 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 105025112 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 87784104 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 465 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 224488 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 100246 # Per bank write bursts 96system.physmem.perBankRdBursts::1 102501 # Per bank write bursts 97system.physmem.perBankRdBursts::2 99063 # Per bank write bursts 98system.physmem.perBankRdBursts::3 111016 # Per bank write bursts 99system.physmem.perBankRdBursts::4 103342 # Per bank write bursts 100system.physmem.perBankRdBursts::5 111704 # Per bank write bursts 101system.physmem.perBankRdBursts::6 101938 # Per bank write bursts 102system.physmem.perBankRdBursts::7 100431 # Per bank write bursts 103system.physmem.perBankRdBursts::8 95106 # Per bank write bursts 104system.physmem.perBankRdBursts::9 125245 # Per bank write bursts 105system.physmem.perBankRdBursts::10 101573 # Per bank write bursts 106system.physmem.perBankRdBursts::11 106068 # Per bank write bursts 107system.physmem.perBankRdBursts::12 95582 # Per bank write bursts 108system.physmem.perBankRdBursts::13 100418 # Per bank write bursts 109system.physmem.perBankRdBursts::14 101028 # Per bank write bursts 110system.physmem.perBankRdBursts::15 101313 # Per bank write bursts 111system.physmem.perBankWrBursts::0 83566 # Per bank write bursts 112system.physmem.perBankWrBursts::1 87156 # Per bank write bursts 113system.physmem.perBankWrBursts::2 83944 # Per bank write bursts 114system.physmem.perBankWrBursts::3 90509 # Per bank write bursts 115system.physmem.perBankWrBursts::4 85224 # Per bank write bursts 116system.physmem.perBankWrBursts::5 91500 # Per bank write bursts 117system.physmem.perBankWrBursts::6 84276 # Per bank write bursts 118system.physmem.perBankWrBursts::7 85215 # Per bank write bursts 119system.physmem.perBankWrBursts::8 82233 # Per bank write bursts 120system.physmem.perBankWrBursts::9 88133 # Per bank write bursts 121system.physmem.perBankWrBursts::10 85317 # Per bank write bursts 122system.physmem.perBankWrBursts::11 88722 # Per bank write bursts 123system.physmem.perBankWrBursts::12 80882 # Per bank write bursts 124system.physmem.perBankWrBursts::13 85628 # Per bank write bursts 125system.physmem.perBankWrBursts::14 84824 # Per bank write bursts 126system.physmem.perBankWrBursts::15 84485 # Per bank write bursts 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 128system.physmem.numWrRetry 14 # Number of times write queue was full causing retry 129system.physmem.totGap 47395176675500 # Total gap between requests 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 0 # Read request sizes (log2) 133system.physmem.readPktSize::3 25 # Read request sizes (log2) 134system.physmem.readPktSize::4 21333 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) 136system.physmem.readPktSize::6 1635681 # Read request sizes (log2) 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) 140system.physmem.writePktSize::3 2572 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) 143system.physmem.writePktSize::6 1371305 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 618737 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 421038 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 166212 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 166706 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 103650 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 63464 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 34359 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 32178 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 28455 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 8186 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 4495 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 2867 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 1852 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 1478 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 956 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 670 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 561 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 434 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 150 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 106 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 2 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 1 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::15 20142 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 22530 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 34959 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 43149 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 52927 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 61801 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 71450 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 78161 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 85169 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 89148 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 92391 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 98600 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 97124 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 100685 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 113079 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 104553 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 98049 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 87257 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 5674 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 3301 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 2066 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 1381 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 974 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 793 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 580 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 491 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 458 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 389 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 368 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 356 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 330 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 291 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 355 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 317 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 381 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 276 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 259 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 205 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 248 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 190 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 159 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 125 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 122 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 65 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 72 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 71 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 71 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 42 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 34 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 1046566 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 185.180531 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 114.222366 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 242.012748 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 630659 60.26% 60.26% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 204416 19.53% 79.79% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 66292 6.33% 86.13% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 36110 3.45% 89.58% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 25913 2.48% 92.05% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 14303 1.37% 93.42% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 14388 1.37% 94.79% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 7964 0.76% 95.55% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 46521 4.45% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 1046566 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 78027 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 21.230689 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 247.022438 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-4095 78024 100.00% 100.00% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::8192-12287 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::65536-69631 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::total 78027 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 78027 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 17.578710 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 17.107570 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 6.499017 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::16-19 72603 93.05% 93.05% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::20-23 2990 3.83% 96.88% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::24-27 480 0.62% 97.50% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::28-31 334 0.43% 97.92% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::32-35 81 0.10% 98.03% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::36-39 301 0.39% 98.41% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::40-43 173 0.22% 98.64% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::44-47 106 0.14% 98.77% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::48-51 88 0.11% 98.88% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::52-55 126 0.16% 99.05% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::56-59 37 0.05% 99.09% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::60-63 56 0.07% 99.16% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::64-67 406 0.52% 99.68% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::68-71 31 0.04% 99.72% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::72-75 24 0.03% 99.76% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::76-79 123 0.16% 99.91% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::80-83 13 0.02% 99.93% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::84-87 1 0.00% 99.93% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::92-95 4 0.01% 99.94% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::96-99 5 0.01% 99.94% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::100-103 1 0.00% 99.94% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::104-107 2 0.00% 99.95% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::112-115 2 0.00% 99.95% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::124-127 1 0.00% 99.95% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::128-131 17 0.02% 99.97% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::136-139 1 0.00% 99.97% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::140-143 5 0.01% 99.98% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::144-147 2 0.00% 99.98% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::152-155 6 0.01% 99.99% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::156-159 2 0.00% 99.99% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::164-167 3 0.00% 100.00% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::168-171 1 0.00% 100.00% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::236-239 2 0.00% 100.00% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::total 78027 # Writes before turning the bus around for reads 300system.physmem.totQLat 82234419314 # Total ticks spent queuing 301system.physmem.totMemAccLat 113295181814 # Total ticks spent from burst creation until serviced by the DRAM 302system.physmem.totBusLat 8282870000 # Total ticks spent in databus transfers 303system.physmem.avgQLat 49641.26 # Average queueing delay per DRAM burst 304system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 305system.physmem.avgMemAccLat 68391.26 # Average memory access latency per DRAM burst 306system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s 307system.physmem.avgWrBW 1.85 # Average achieved write bandwidth in MiByte/s 308system.physmem.avgRdBWSys 2.22 # Average system read bandwidth in MiByte/s 309system.physmem.avgWrBWSys 1.85 # Average system write bandwidth in MiByte/s 310system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 311system.physmem.busUtil 0.03 # Data bus utilization in percentage 312system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 313system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 314system.physmem.avgRdQLen 1.27 # Average read queue length when enqueuing 315system.physmem.avgWrQLen 24.73 # Average write queue length when enqueuing 316system.physmem.readRowHits 1332435 # Number of row buffer hits during reads 317system.physmem.writeRowHits 649185 # Number of row buffer hits during writes 318system.physmem.readRowHitRate 80.43 # Row buffer hit rate for reads 319system.physmem.writeRowHitRate 47.33 # Row buffer hit rate for writes 320system.physmem.avgGap 15637234.88 # Average gap between requests 321system.physmem.pageHitRate 65.44 # Row buffer hit rate, read and write combined 322system.physmem_0.actEnergy 4004169120 # Energy for activate commands per rank (pJ) 323system.physmem_0.preEnergy 2184814500 # Energy for precharge commands per rank (pJ) 324system.physmem_0.readEnergy 6475833000 # Energy for read commands per rank (pJ) 325system.physmem_0.writeEnergy 4480207200 # Energy for write commands per rank (pJ) 326system.physmem_0.refreshEnergy 3095622519600 # Energy for refresh commands per rank (pJ) 327system.physmem_0.actBackEnergy 1180796903550 # Energy for active background per rank (pJ) 328system.physmem_0.preBackEnergy 27401319159750 # Energy for precharge background per rank (pJ) 329system.physmem_0.totalEnergy 31694883606720 # Total energy per rank (pJ) 330system.physmem_0.averagePower 668.736482 # Core power per rank (mW) 331system.physmem_0.memoryStateTime::IDLE 45584100048214 # Time in different power states 332system.physmem_0.memoryStateTime::REF 1582629100000 # Time in different power states 333system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 334system.physmem_0.memoryStateTime::ACT 228448334286 # Time in different power states 335system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 336system.physmem_1.actEnergy 3907869840 # Energy for activate commands per rank (pJ) 337system.physmem_1.preEnergy 2132270250 # Energy for precharge commands per rank (pJ) 338system.physmem_1.readEnergy 6445397400 # Energy for read commands per rank (pJ) 339system.physmem_1.writeEnergy 4407851520 # Energy for write commands per rank (pJ) 340system.physmem_1.refreshEnergy 3095622519600 # Energy for refresh commands per rank (pJ) 341system.physmem_1.actBackEnergy 1181668397355 # Energy for active background per rank (pJ) 342system.physmem_1.preBackEnergy 27400554691500 # Energy for precharge background per rank (pJ) 343system.physmem_1.totalEnergy 31694738997465 # Total energy per rank (pJ) 344system.physmem_1.averagePower 668.733431 # Core power per rank (mW) 345system.physmem_1.memoryStateTime::IDLE 45582807436264 # Time in different power states 346system.physmem_1.memoryStateTime::REF 1582629100000 # Time in different power states 347system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 348system.physmem_1.memoryStateTime::ACT 229740006236 # Time in different power states 349system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 350system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory 351system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 352system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory 353system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 354system.realview.nvmem.bytes_read::total 572 # Number of bytes read from this memory 355system.realview.nvmem.bytes_inst_read::cpu0.inst 384 # Number of instructions bytes read from this memory 356system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory 357system.realview.nvmem.bytes_inst_read::total 528 # Number of instructions bytes read from this memory 358system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 359system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 360system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory 361system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 362system.realview.nvmem.num_reads::total 39 # Number of read requests responded to by this memory 363system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) 364system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 365system.realview.nvmem.bw_read::cpu1.inst 3 # Total read bandwidth from this memory (bytes/s) 366system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 367system.realview.nvmem.bw_read::total 12 # Total read bandwidth from this memory (bytes/s) 368system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) 369system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s) 370system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s) 371system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) 372system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 373system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) 374system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 375system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) 376system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 377system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 378system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 379system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 380system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 381system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 382system.cpu0.branchPred.lookups 146971248 # Number of BP lookups 383system.cpu0.branchPred.condPredicted 97492286 # Number of conditional branches predicted 384system.cpu0.branchPred.condIncorrect 7372479 # Number of conditional branches incorrect 385system.cpu0.branchPred.BTBLookups 103605243 # Number of BTB lookups 386system.cpu0.branchPred.BTBHits 68020426 # Number of BTB hits 387system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 388system.cpu0.branchPred.BTBHitPct 65.653459 # BTB Hit Percentage 389system.cpu0.branchPred.usedRAS 20148210 # Number of times the RAS was used to get a target. 390system.cpu0.branchPred.RASInCorrect 220615 # Number of incorrect RAS predictions. 391system.cpu_clk_domain.clock 500 # Clock period in ticks 392system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 393system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 394system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 396system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 397system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 398system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 399system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 400system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 401system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 402system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 403system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 404system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 405system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 406system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 407system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 408system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 409system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 410system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 411system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 412system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 413system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 414system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 415system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 416system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 417system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 418system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 419system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 420system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 421system.cpu0.dtb.walker.walks 621589 # Table walker walks requested 422system.cpu0.dtb.walker.walksLong 621589 # Table walker walks initiated with long descriptors 423system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13120 # Level at which table walker walks with long descriptors terminate 424system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 97816 # Level at which table walker walks with long descriptors terminate 425system.cpu0.dtb.walker.walksSquashedBefore 286624 # Table walks squashed before starting 426system.cpu0.dtb.walker.walkWaitTime::samples 334965 # Table walker wait (enqueue to first request) latency 427system.cpu0.dtb.walker.walkWaitTime::mean 2330.974878 # Table walker wait (enqueue to first request) latency 428system.cpu0.dtb.walker.walkWaitTime::stdev 14719.833023 # Table walker wait (enqueue to first request) latency 429system.cpu0.dtb.walker.walkWaitTime::0-65535 332297 99.20% 99.20% # Table walker wait (enqueue to first request) latency 430system.cpu0.dtb.walker.walkWaitTime::65536-131071 1432 0.43% 99.63% # Table walker wait (enqueue to first request) latency 431system.cpu0.dtb.walker.walkWaitTime::131072-196607 943 0.28% 99.91% # Table walker wait (enqueue to first request) latency 432system.cpu0.dtb.walker.walkWaitTime::196608-262143 131 0.04% 99.95% # Table walker wait (enqueue to first request) latency 433system.cpu0.dtb.walker.walkWaitTime::262144-327679 57 0.02% 99.97% # Table walker wait (enqueue to first request) latency 434system.cpu0.dtb.walker.walkWaitTime::327680-393215 84 0.03% 99.99% # Table walker wait (enqueue to first request) latency 435system.cpu0.dtb.walker.walkWaitTime::393216-458751 13 0.00% 100.00% # Table walker wait (enqueue to first request) latency 436system.cpu0.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 437system.cpu0.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency 438system.cpu0.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 439system.cpu0.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 440system.cpu0.dtb.walker.walkWaitTime::total 334965 # Table walker wait (enqueue to first request) latency 441system.cpu0.dtb.walker.walkCompletionTime::samples 317874 # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walkCompletionTime::mean 20050.667875 # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::gmean 16636.288203 # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::stdev 22186.320011 # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walkCompletionTime::0-65535 314157 98.83% 98.83% # Table walker service (enqueue to completion) latency 446system.cpu0.dtb.walker.walkCompletionTime::65536-131071 825 0.26% 99.09% # Table walker service (enqueue to completion) latency 447system.cpu0.dtb.walker.walkCompletionTime::131072-196607 2043 0.64% 99.73% # Table walker service (enqueue to completion) latency 448system.cpu0.dtb.walker.walkCompletionTime::196608-262143 147 0.05% 99.78% # Table walker service (enqueue to completion) latency 449system.cpu0.dtb.walker.walkCompletionTime::262144-327679 407 0.13% 99.91% # Table walker service (enqueue to completion) latency 450system.cpu0.dtb.walker.walkCompletionTime::327680-393215 108 0.03% 99.94% # Table walker service (enqueue to completion) latency 451system.cpu0.dtb.walker.walkCompletionTime::393216-458751 100 0.03% 99.97% # Table walker service (enqueue to completion) latency 452system.cpu0.dtb.walker.walkCompletionTime::458752-524287 42 0.01% 99.99% # Table walker service (enqueue to completion) latency 453system.cpu0.dtb.walker.walkCompletionTime::524288-589823 23 0.01% 99.99% # Table walker service (enqueue to completion) latency 454system.cpu0.dtb.walker.walkCompletionTime::589824-655359 13 0.00% 100.00% # Table walker service (enqueue to completion) latency 455system.cpu0.dtb.walker.walkCompletionTime::655360-720895 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 456system.cpu0.dtb.walker.walkCompletionTime::720896-786431 5 0.00% 100.00% # Table walker service (enqueue to completion) latency 457system.cpu0.dtb.walker.walkCompletionTime::total 317874 # Table walker service (enqueue to completion) latency 458system.cpu0.dtb.walker.walksPending::samples 575732613804 # Table walker pending requests distribution 459system.cpu0.dtb.walker.walksPending::mean 0.609948 # Table walker pending requests distribution 460system.cpu0.dtb.walker.walksPending::stdev 0.538779 # Table walker pending requests distribution 461system.cpu0.dtb.walker.walksPending::0-1 574368413804 99.76% 99.76% # Table walker pending requests distribution 462system.cpu0.dtb.walker.walksPending::2-3 774580000 0.13% 99.90% # Table walker pending requests distribution 463system.cpu0.dtb.walker.walksPending::4-5 276702000 0.05% 99.95% # Table walker pending requests distribution 464system.cpu0.dtb.walker.walksPending::6-7 125012500 0.02% 99.97% # Table walker pending requests distribution 465system.cpu0.dtb.walker.walksPending::8-9 99386000 0.02% 99.98% # Table walker pending requests distribution 466system.cpu0.dtb.walker.walksPending::10-11 49877000 0.01% 99.99% # Table walker pending requests distribution 467system.cpu0.dtb.walker.walksPending::12-13 16787500 0.00% 100.00% # Table walker pending requests distribution 468system.cpu0.dtb.walker.walksPending::14-15 21052000 0.00% 100.00% # Table walker pending requests distribution 469system.cpu0.dtb.walker.walksPending::16-17 785500 0.00% 100.00% # Table walker pending requests distribution 470system.cpu0.dtb.walker.walksPending::18-19 17500 0.00% 100.00% # Table walker pending requests distribution 471system.cpu0.dtb.walker.walksPending::total 575732613804 # Table walker pending requests distribution 472system.cpu0.dtb.walker.walkPageSizes::4K 97816 88.17% 88.17% # Table walker page sizes translated 473system.cpu0.dtb.walker.walkPageSizes::2M 13120 11.83% 100.00% # Table walker page sizes translated 474system.cpu0.dtb.walker.walkPageSizes::total 110936 # Table walker page sizes translated 475system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 621589 # Table walker requests started/completed, data/inst 476system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 477system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 621589 # Table walker requests started/completed, data/inst 478system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 110936 # Table walker requests started/completed, data/inst 479system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 480system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 110936 # Table walker requests started/completed, data/inst 481system.cpu0.dtb.walker.walkRequestOrigin::total 732525 # Table walker requests started/completed, data/inst 482system.cpu0.dtb.inst_hits 0 # ITB inst hits 483system.cpu0.dtb.inst_misses 0 # ITB inst misses 484system.cpu0.dtb.read_hits 106854280 # DTB read hits 485system.cpu0.dtb.read_misses 451291 # DTB read misses 486system.cpu0.dtb.write_hits 87452638 # DTB write hits 487system.cpu0.dtb.write_misses 170298 # DTB write misses 488system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 489system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 490system.cpu0.dtb.flush_tlb_mva_asid 44894 # Number of times TLB was flushed by MVA & ASID 491system.cpu0.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID 492system.cpu0.dtb.flush_entries 41576 # Number of entries that have been flushed from TLB 493system.cpu0.dtb.align_faults 658 # Number of TLB faults due to alignment restrictions 494system.cpu0.dtb.prefetch_faults 7382 # Number of TLB faults due to prefetch 495system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 496system.cpu0.dtb.perms_faults 40291 # Number of TLB faults due to permissions restrictions 497system.cpu0.dtb.read_accesses 107305571 # DTB read accesses 498system.cpu0.dtb.write_accesses 87622936 # DTB write accesses 499system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 500system.cpu0.dtb.hits 194306918 # DTB hits 501system.cpu0.dtb.misses 621589 # DTB misses 502system.cpu0.dtb.accesses 194928507 # DTB accesses 503system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 504system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 505system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 506system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 507system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 508system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 509system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 510system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 511system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 512system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 513system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 514system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 515system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 516system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 517system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 518system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 519system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 520system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 521system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 522system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 523system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 524system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 525system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 526system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 527system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 528system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 529system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 530system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 531system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 532system.cpu0.itb.walker.walks 88821 # Table walker walks requested 533system.cpu0.itb.walker.walksLong 88821 # Table walker walks initiated with long descriptors 534system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1050 # Level at which table walker walks with long descriptors terminate 535system.cpu0.itb.walker.walksLongTerminationLevel::Level3 63713 # Level at which table walker walks with long descriptors terminate 536system.cpu0.itb.walker.walksSquashedBefore 10161 # Table walks squashed before starting 537system.cpu0.itb.walker.walkWaitTime::samples 78660 # Table walker wait (enqueue to first request) latency 538system.cpu0.itb.walker.walkWaitTime::mean 1640.999237 # Table walker wait (enqueue to first request) latency 539system.cpu0.itb.walker.walkWaitTime::stdev 13001.605750 # Table walker wait (enqueue to first request) latency 540system.cpu0.itb.walker.walkWaitTime::0-32767 77771 98.87% 98.87% # Table walker wait (enqueue to first request) latency 541system.cpu0.itb.walker.walkWaitTime::32768-65535 446 0.57% 99.44% # Table walker wait (enqueue to first request) latency 542system.cpu0.itb.walker.walkWaitTime::65536-98303 46 0.06% 99.50% # Table walker wait (enqueue to first request) latency 543system.cpu0.itb.walker.walkWaitTime::98304-131071 60 0.08% 99.57% # Table walker wait (enqueue to first request) latency 544system.cpu0.itb.walker.walkWaitTime::131072-163839 236 0.30% 99.87% # Table walker wait (enqueue to first request) latency 545system.cpu0.itb.walker.walkWaitTime::163840-196607 63 0.08% 99.95% # Table walker wait (enqueue to first request) latency 546system.cpu0.itb.walker.walkWaitTime::196608-229375 4 0.01% 99.96% # Table walker wait (enqueue to first request) latency 547system.cpu0.itb.walker.walkWaitTime::229376-262143 4 0.01% 99.96% # Table walker wait (enqueue to first request) latency 548system.cpu0.itb.walker.walkWaitTime::262144-294911 12 0.02% 99.98% # Table walker wait (enqueue to first request) latency 549system.cpu0.itb.walker.walkWaitTime::294912-327679 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency 550system.cpu0.itb.walker.walkWaitTime::327680-360447 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency 551system.cpu0.itb.walker.walkWaitTime::360448-393215 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency 552system.cpu0.itb.walker.walkWaitTime::393216-425983 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 553system.cpu0.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 554system.cpu0.itb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 555system.cpu0.itb.walker.walkWaitTime::total 78660 # Table walker wait (enqueue to first request) latency 556system.cpu0.itb.walker.walkCompletionTime::samples 74924 # Table walker service (enqueue to completion) latency 557system.cpu0.itb.walker.walkCompletionTime::mean 26158.080188 # Table walker service (enqueue to completion) latency 558system.cpu0.itb.walker.walkCompletionTime::gmean 21735.719179 # Table walker service (enqueue to completion) latency 559system.cpu0.itb.walker.walkCompletionTime::stdev 28586.196281 # Table walker service (enqueue to completion) latency 560system.cpu0.itb.walker.walkCompletionTime::0-65535 72785 97.15% 97.15% # Table walker service (enqueue to completion) latency 561system.cpu0.itb.walker.walkCompletionTime::65536-131071 128 0.17% 97.32% # Table walker service (enqueue to completion) latency 562system.cpu0.itb.walker.walkCompletionTime::131072-196607 1706 2.28% 99.59% # Table walker service (enqueue to completion) latency 563system.cpu0.itb.walker.walkCompletionTime::196608-262143 120 0.16% 99.75% # Table walker service (enqueue to completion) latency 564system.cpu0.itb.walker.walkCompletionTime::262144-327679 108 0.14% 99.90% # Table walker service (enqueue to completion) latency 565system.cpu0.itb.walker.walkCompletionTime::327680-393215 38 0.05% 99.95% # Table walker service (enqueue to completion) latency 566system.cpu0.itb.walker.walkCompletionTime::393216-458751 23 0.03% 99.98% # Table walker service (enqueue to completion) latency 567system.cpu0.itb.walker.walkCompletionTime::458752-524287 11 0.01% 99.99% # Table walker service (enqueue to completion) latency 568system.cpu0.itb.walker.walkCompletionTime::524288-589823 5 0.01% 100.00% # Table walker service (enqueue to completion) latency 569system.cpu0.itb.walker.walkCompletionTime::total 74924 # Table walker service (enqueue to completion) latency 570system.cpu0.itb.walker.walksPending::samples 438261516832 # Table walker pending requests distribution 571system.cpu0.itb.walker.walksPending::mean 0.857100 # Table walker pending requests distribution 572system.cpu0.itb.walker.walksPending::stdev 0.350244 # Table walker pending requests distribution 573system.cpu0.itb.walker.walksPending::0 62664607652 14.30% 14.30% # Table walker pending requests distribution 574system.cpu0.itb.walker.walksPending::1 375564750680 85.69% 99.99% # Table walker pending requests distribution 575system.cpu0.itb.walker.walksPending::2 27774000 0.01% 100.00% # Table walker pending requests distribution 576system.cpu0.itb.walker.walksPending::3 4139500 0.00% 100.00% # Table walker pending requests distribution 577system.cpu0.itb.walker.walksPending::4 188000 0.00% 100.00% # Table walker pending requests distribution 578system.cpu0.itb.walker.walksPending::5 57000 0.00% 100.00% # Table walker pending requests distribution 579system.cpu0.itb.walker.walksPending::total 438261516832 # Table walker pending requests distribution 580system.cpu0.itb.walker.walkPageSizes::4K 63713 98.38% 98.38% # Table walker page sizes translated 581system.cpu0.itb.walker.walkPageSizes::2M 1050 1.62% 100.00% # Table walker page sizes translated 582system.cpu0.itb.walker.walkPageSizes::total 64763 # Table walker page sizes translated 583system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 584system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 88821 # Table walker requests started/completed, data/inst 585system.cpu0.itb.walker.walkRequestOrigin_Requested::total 88821 # Table walker requests started/completed, data/inst 586system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 587system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64763 # Table walker requests started/completed, data/inst 588system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64763 # Table walker requests started/completed, data/inst 589system.cpu0.itb.walker.walkRequestOrigin::total 153584 # Table walker requests started/completed, data/inst 590system.cpu0.itb.inst_hits 231690538 # ITB inst hits 591system.cpu0.itb.inst_misses 88821 # ITB inst misses 592system.cpu0.itb.read_hits 0 # DTB read hits 593system.cpu0.itb.read_misses 0 # DTB read misses 594system.cpu0.itb.write_hits 0 # DTB write hits 595system.cpu0.itb.write_misses 0 # DTB write misses 596system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 597system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 598system.cpu0.itb.flush_tlb_mva_asid 44894 # Number of times TLB was flushed by MVA & ASID 599system.cpu0.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID 600system.cpu0.itb.flush_entries 30101 # Number of entries that have been flushed from TLB 601system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 602system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 603system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 604system.cpu0.itb.perms_faults 229340 # Number of TLB faults due to permissions restrictions 605system.cpu0.itb.read_accesses 0 # DTB read accesses 606system.cpu0.itb.write_accesses 0 # DTB write accesses 607system.cpu0.itb.inst_accesses 231779359 # ITB inst accesses 608system.cpu0.itb.hits 231690538 # DTB hits 609system.cpu0.itb.misses 88821 # DTB misses 610system.cpu0.itb.accesses 231779359 # DTB accesses 611system.cpu0.numCycles 863793222 # number of cpu cycles simulated 612system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 613system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 614system.cpu0.fetch.icacheStallCycles 99193613 # Number of cycles fetch is stalled on an Icache miss 615system.cpu0.fetch.Insts 650316460 # Number of instructions fetch has processed 616system.cpu0.fetch.Branches 146971248 # Number of branches that fetch encountered 617system.cpu0.fetch.predictedBranches 88168636 # Number of branches that fetch has predicted taken 618system.cpu0.fetch.Cycles 710473999 # Number of cycles fetch has run and was not squashing or blocked 619system.cpu0.fetch.SquashCycles 15870286 # Number of cycles fetch has spent squashing 620system.cpu0.fetch.TlbCycles 2085677 # Number of cycles fetch has spent waiting for tlb 621system.cpu0.fetch.MiscStallCycles 375453 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 622system.cpu0.fetch.PendingTrapStallCycles 6582690 # Number of stall cycles due to pending traps 623system.cpu0.fetch.PendingQuiesceStallCycles 821108 # Number of stall cycles due to pending quiesce instructions 624system.cpu0.fetch.IcacheWaitRetryStallCycles 973136 # Number of stall cycles due to full MSHR 625system.cpu0.fetch.CacheLines 231460528 # Number of cache lines fetched 626system.cpu0.fetch.IcacheSquashes 1900058 # Number of outstanding Icache misses that were squashed 627system.cpu0.fetch.ItlbSquashes 29560 # Number of outstanding ITLB misses that were squashed 628system.cpu0.fetch.rateDist::samples 828440819 # Number of instructions fetched each cycle (Total) 629system.cpu0.fetch.rateDist::mean 0.919217 # Number of instructions fetched each cycle (Total) 630system.cpu0.fetch.rateDist::stdev 1.204961 # Number of instructions fetched each cycle (Total) 631system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 632system.cpu0.fetch.rateDist::0 463819781 55.99% 55.99% # Number of instructions fetched each cycle (Total) 633system.cpu0.fetch.rateDist::1 141489715 17.08% 73.07% # Number of instructions fetched each cycle (Total) 634system.cpu0.fetch.rateDist::2 49366419 5.96% 79.03% # Number of instructions fetched each cycle (Total) 635system.cpu0.fetch.rateDist::3 173764904 20.97% 100.00% # Number of instructions fetched each cycle (Total) 636system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 637system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 638system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 639system.cpu0.fetch.rateDist::total 828440819 # Number of instructions fetched each cycle (Total) 640system.cpu0.fetch.branchRate 0.170146 # Number of branch fetches per cycle 641system.cpu0.fetch.rate 0.752861 # Number of inst fetches per cycle 642system.cpu0.decode.IdleCycles 116939951 # Number of cycles decode is idle 643system.cpu0.decode.BlockedCycles 422028211 # Number of cycles decode is blocked 644system.cpu0.decode.RunCycles 244586455 # Number of cycles decode is running 645system.cpu0.decode.UnblockCycles 39268558 # Number of cycles decode is unblocking 646system.cpu0.decode.SquashCycles 5617644 # Number of cycles decode is squashing 647system.cpu0.decode.BranchResolved 21189817 # Number of times decode resolved a branch 648system.cpu0.decode.BranchMispred 2362286 # Number of times decode detected a branch misprediction 649system.cpu0.decode.DecodedInsts 672848975 # Number of instructions handled by decode 650system.cpu0.decode.SquashedInsts 25418616 # Number of squashed instructions handled by decode 651system.cpu0.rename.SquashCycles 5617644 # Number of cycles rename is squashing 652system.cpu0.rename.IdleCycles 154577177 # Number of cycles rename is idle 653system.cpu0.rename.BlockCycles 70595603 # Number of cycles rename is blocking 654system.cpu0.rename.serializeStallCycles 261705373 # count of cycles rename stalled for serializing inst 655system.cpu0.rename.RunCycles 245642920 # Number of cycles rename is running 656system.cpu0.rename.UnblockCycles 90302102 # Number of cycles rename is unblocking 657system.cpu0.rename.RenamedInsts 654266166 # Number of instructions processed by rename 658system.cpu0.rename.SquashedInsts 6467849 # Number of squashed instructions processed by rename 659system.cpu0.rename.ROBFullEvents 11101204 # Number of times rename has blocked due to ROB full 660system.cpu0.rename.IQFullEvents 403453 # Number of times rename has blocked due to IQ full 661system.cpu0.rename.LQFullEvents 928162 # Number of times rename has blocked due to LQ full 662system.cpu0.rename.SQFullEvents 53323892 # Number of times rename has blocked due to SQ full 663system.cpu0.rename.FullRegisterEvents 11721 # Number of times there has been no free registers 664system.cpu0.rename.RenamedOperands 625141147 # Number of destination operands rename has renamed 665system.cpu0.rename.RenameLookups 1009026275 # Number of register rename lookups that rename has made 666system.cpu0.rename.int_rename_lookups 772228505 # Number of integer rename lookups 667system.cpu0.rename.fp_rename_lookups 892399 # Number of floating rename lookups 668system.cpu0.rename.CommittedMaps 562735066 # Number of HB maps that are committed 669system.cpu0.rename.UndoneMaps 62406074 # Number of HB maps that are undone due to squashing 670system.cpu0.rename.serializingInsts 16247606 # count of serializing insts renamed 671system.cpu0.rename.tempSerializingInsts 14088158 # count of temporary serializing insts renamed 672system.cpu0.rename.skidInsts 79534921 # count of insts added to the skid buffer 673system.cpu0.memDep0.insertedLoads 107241964 # Number of loads inserted to the mem dependence unit. 674system.cpu0.memDep0.insertedStores 91079408 # Number of stores inserted to the mem dependence unit. 675system.cpu0.memDep0.conflictingLoads 9519471 # Number of conflicting loads. 676system.cpu0.memDep0.conflictingStores 8265411 # Number of conflicting stores. 677system.cpu0.iq.iqInstsAdded 630985849 # Number of instructions added to the IQ (excludes non-spec) 678system.cpu0.iq.iqNonSpecInstsAdded 16282634 # Number of non-speculative instructions added to the IQ 679system.cpu0.iq.iqInstsIssued 634912655 # Number of instructions issued 680system.cpu0.iq.iqSquashedInstsIssued 2916139 # Number of squashed instructions issued 681system.cpu0.iq.iqSquashedInstsExamined 58420750 # Number of squashed instructions iterated over during squash; mainly for profiling 682system.cpu0.iq.iqSquashedOperandsExamined 38187791 # Number of squashed operands that are examined and possibly removed from graph 683system.cpu0.iq.iqSquashedNonSpecRemoved 288602 # Number of squashed non-spec instructions that were removed 684system.cpu0.iq.issued_per_cycle::samples 828440819 # Number of insts issued each cycle 685system.cpu0.iq.issued_per_cycle::mean 0.766395 # Number of insts issued each cycle 686system.cpu0.iq.issued_per_cycle::stdev 1.051588 # Number of insts issued each cycle 687system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 688system.cpu0.iq.issued_per_cycle::0 482464203 58.24% 58.24% # Number of insts issued each cycle 689system.cpu0.iq.issued_per_cycle::1 143786503 17.36% 75.59% # Number of insts issued each cycle 690system.cpu0.iq.issued_per_cycle::2 123657330 14.93% 90.52% # Number of insts issued each cycle 691system.cpu0.iq.issued_per_cycle::3 70325398 8.49% 99.01% # Number of insts issued each cycle 692system.cpu0.iq.issued_per_cycle::4 8201627 0.99% 100.00% # Number of insts issued each cycle 693system.cpu0.iq.issued_per_cycle::5 5758 0.00% 100.00% # Number of insts issued each cycle 694system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 695system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 696system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 697system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 698system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 699system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 700system.cpu0.iq.issued_per_cycle::total 828440819 # Number of insts issued each cycle 701system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 702system.cpu0.iq.fu_full::IntAlu 65751499 45.58% 45.58% # attempts to use FU when none available 703system.cpu0.iq.fu_full::IntMult 72629 0.05% 45.63% # attempts to use FU when none available 704system.cpu0.iq.fu_full::IntDiv 24296 0.02% 45.64% # attempts to use FU when none available 705system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.64% # attempts to use FU when none available 706system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.64% # attempts to use FU when none available 707system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.64% # attempts to use FU when none available 708system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.64% # attempts to use FU when none available 709system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.64% # attempts to use FU when none available 710system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.64% # attempts to use FU when none available 711system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.64% # attempts to use FU when none available 712system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.64% # attempts to use FU when none available 713system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.64% # attempts to use FU when none available 714system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.64% # attempts to use FU when none available 715system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.64% # attempts to use FU when none available 716system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.64% # attempts to use FU when none available 717system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.64% # attempts to use FU when none available 718system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.64% # attempts to use FU when none available 719system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.64% # attempts to use FU when none available 720system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.64% # attempts to use FU when none available 721system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.64% # attempts to use FU when none available 722system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.64% # attempts to use FU when none available 723system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.64% # attempts to use FU when none available 724system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.64% # attempts to use FU when none available 725system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.64% # attempts to use FU when none available 726system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.64% # attempts to use FU when none available 727system.cpu0.iq.fu_full::SimdFloatMisc 30 0.00% 45.64% # attempts to use FU when none available 728system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.64% # attempts to use FU when none available 729system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.64% # attempts to use FU when none available 730system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.64% # attempts to use FU when none available 731system.cpu0.iq.fu_full::MemRead 37784970 26.19% 71.84% # attempts to use FU when none available 732system.cpu0.iq.fu_full::MemWrite 40630472 28.16% 100.00% # attempts to use FU when none available 733system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 734system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 735system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 736system.cpu0.iq.FU_type_0::IntAlu 434162938 68.38% 68.38% # Type of FU issued 737system.cpu0.iq.FU_type_0::IntMult 1557110 0.25% 68.63% # Type of FU issued 738system.cpu0.iq.FU_type_0::IntDiv 85116 0.01% 68.64% # Type of FU issued 739system.cpu0.iq.FU_type_0::FloatAdd 3 0.00% 68.64% # Type of FU issued 740system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.64% # Type of FU issued 741system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.64% # Type of FU issued 742system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.64% # Type of FU issued 743system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.64% # Type of FU issued 744system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.64% # Type of FU issued 745system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.64% # Type of FU issued 746system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.64% # Type of FU issued 747system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.64% # Type of FU issued 748system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.64% # Type of FU issued 749system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.64% # Type of FU issued 750system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.64% # Type of FU issued 751system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.64% # Type of FU issued 752system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.64% # Type of FU issued 753system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.64% # Type of FU issued 754system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.64% # Type of FU issued 755system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.64% # Type of FU issued 756system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.64% # Type of FU issued 757system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.64% # Type of FU issued 758system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.64% # Type of FU issued 759system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.64% # Type of FU issued 760system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.64% # Type of FU issued 761system.cpu0.iq.FU_type_0::SimdFloatMisc 85507 0.01% 68.65% # Type of FU issued 762system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.65% # Type of FU issued 763system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.65% # Type of FU issued 764system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.65% # Type of FU issued 765system.cpu0.iq.FU_type_0::MemRead 110176891 17.35% 86.01% # Type of FU issued 766system.cpu0.iq.FU_type_0::MemWrite 88845090 13.99% 100.00% # Type of FU issued 767system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 768system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 769system.cpu0.iq.FU_type_0::total 634912655 # Type of FU issued 770system.cpu0.iq.rate 0.735029 # Inst issue rate 771system.cpu0.iq.fu_busy_cnt 144263896 # FU busy when requested 772system.cpu0.iq.fu_busy_rate 0.227218 # FU busy rate (busy events/executed inst) 773system.cpu0.iq.int_inst_queue_reads 2243978291 # Number of integer instruction queue reads 774system.cpu0.iq.int_inst_queue_writes 705234549 # Number of integer instruction queue writes 775system.cpu0.iq.int_inst_queue_wakeup_accesses 616677073 # Number of integer instruction queue wakeup accesses 776system.cpu0.iq.fp_inst_queue_reads 1467869 # Number of floating instruction queue reads 777system.cpu0.iq.fp_inst_queue_writes 599303 # Number of floating instruction queue writes 778system.cpu0.iq.fp_inst_queue_wakeup_accesses 545442 # Number of floating instruction queue wakeup accesses 779system.cpu0.iq.int_alu_accesses 778270494 # Number of integer alu accesses 780system.cpu0.iq.fp_alu_accesses 906057 # Number of floating point alu accesses 781system.cpu0.iew.lsq.thread0.forwLoads 2895519 # Number of loads that had data forwarded from stores 782system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 783system.cpu0.iew.lsq.thread0.squashedLoads 13298175 # Number of loads squashed 784system.cpu0.iew.lsq.thread0.ignoredResponses 18246 # Number of memory responses ignored because the instruction is squashed 785system.cpu0.iew.lsq.thread0.memOrderViolation 145606 # Number of memory ordering violations 786system.cpu0.iew.lsq.thread0.squashedStores 6202009 # Number of stores squashed 787system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 788system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 789system.cpu0.iew.lsq.thread0.rescheduledLoads 2767326 # Number of loads that were rescheduled 790system.cpu0.iew.lsq.thread0.cacheBlocked 4824800 # Number of times an access to memory failed due to the cache being blocked 791system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 792system.cpu0.iew.iewSquashCycles 5617644 # Number of cycles IEW is squashing 793system.cpu0.iew.iewBlockCycles 8735359 # Number of cycles IEW is blocking 794system.cpu0.iew.iewUnblockCycles 7907130 # Number of cycles IEW is unblocking 795system.cpu0.iew.iewDispatchedInsts 647396791 # Number of instructions dispatched to IQ 796system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 797system.cpu0.iew.iewDispLoadInsts 107241964 # Number of dispatched load instructions 798system.cpu0.iew.iewDispStoreInsts 91079408 # Number of dispatched store instructions 799system.cpu0.iew.iewDispNonSpecInsts 13794371 # Number of dispatched non-speculative instructions 800system.cpu0.iew.iewIQFullEvents 59022 # Number of times the IQ has become full, causing a stall 801system.cpu0.iew.iewLSQFullEvents 7772545 # Number of times the LSQ has become full, causing a stall 802system.cpu0.iew.memOrderViolationEvents 145606 # Number of memory order violations 803system.cpu0.iew.predictedTakenIncorrect 2195305 # Number of branches that were predicted taken incorrectly 804system.cpu0.iew.predictedNotTakenIncorrect 3186569 # Number of branches that were predicted not taken incorrectly 805system.cpu0.iew.branchMispredicts 5381874 # Number of branch mispredicts detected at execute 806system.cpu0.iew.iewExecutedInsts 626447733 # Number of executed instructions 807system.cpu0.iew.iewExecLoadInsts 106847652 # Number of load instructions executed 808system.cpu0.iew.iewExecSquashedInsts 7850968 # Number of squashed instructions skipped in execute 809system.cpu0.iew.exec_swp 0 # number of swp insts executed 810system.cpu0.iew.exec_nop 128308 # number of nop insts executed 811system.cpu0.iew.exec_refs 194298385 # number of memory reference insts executed 812system.cpu0.iew.exec_branches 118240799 # Number of branches executed 813system.cpu0.iew.exec_stores 87450733 # Number of stores executed 814system.cpu0.iew.exec_rate 0.725229 # Inst execution rate 815system.cpu0.iew.wb_sent 618051464 # cumulative count of insts sent to commit 816system.cpu0.iew.wb_count 617222515 # cumulative count of insts written-back 817system.cpu0.iew.wb_producers 300479191 # num instructions producing a value 818system.cpu0.iew.wb_consumers 493067457 # num instructions consuming a value 819system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 820system.cpu0.iew.wb_rate 0.714549 # insts written-back per cycle 821system.cpu0.iew.wb_fanout 0.609408 # average fanout of values written-back 822system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 823system.cpu0.commit.commitSquashedInsts 50926327 # The number of squashed insts skipped by commit 824system.cpu0.commit.commitNonSpecStalls 15994032 # The number of times commit has been forced to stall to communicate backwards 825system.cpu0.commit.branchMispredicts 5054980 # The number of times a branch was mispredicted 826system.cpu0.commit.committed_per_cycle::samples 818740070 # Number of insts commited each cycle 827system.cpu0.commit.committed_per_cycle::mean 0.719212 # Number of insts commited each cycle 828system.cpu0.commit.committed_per_cycle::stdev 1.525829 # Number of insts commited each cycle 829system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 830system.cpu0.commit.committed_per_cycle::0 561213375 68.55% 68.55% # Number of insts commited each cycle 831system.cpu0.commit.committed_per_cycle::1 132109065 16.14% 84.68% # Number of insts commited each cycle 832system.cpu0.commit.committed_per_cycle::2 58113446 7.10% 91.78% # Number of insts commited each cycle 833system.cpu0.commit.committed_per_cycle::3 19548895 2.39% 94.17% # Number of insts commited each cycle 834system.cpu0.commit.committed_per_cycle::4 13854430 1.69% 95.86% # Number of insts commited each cycle 835system.cpu0.commit.committed_per_cycle::5 9447713 1.15% 97.01% # Number of insts commited each cycle 836system.cpu0.commit.committed_per_cycle::6 6268110 0.77% 97.78% # Number of insts commited each cycle 837system.cpu0.commit.committed_per_cycle::7 3880157 0.47% 98.25% # Number of insts commited each cycle 838system.cpu0.commit.committed_per_cycle::8 14304879 1.75% 100.00% # Number of insts commited each cycle 839system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 840system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 841system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 842system.cpu0.commit.committed_per_cycle::total 818740070 # Number of insts commited each cycle 843system.cpu0.commit.committedInsts 501771314 # Number of instructions committed 844system.cpu0.commit.committedOps 588847718 # Number of ops (including micro ops) committed 845system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 846system.cpu0.commit.refs 178821180 # Number of memory references committed 847system.cpu0.commit.loads 93943789 # Number of loads committed 848system.cpu0.commit.membars 3938709 # Number of memory barriers committed 849system.cpu0.commit.branches 112215548 # Number of branches committed 850system.cpu0.commit.fp_insts 531565 # Number of committed floating point instructions. 851system.cpu0.commit.int_insts 540152053 # Number of committed integer instructions. 852system.cpu0.commit.function_calls 14962116 # Number of function calls committed. 853system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 854system.cpu0.commit.op_class_0::IntAlu 408576800 69.39% 69.39% # Class of committed instruction 855system.cpu0.commit.op_class_0::IntMult 1307130 0.22% 69.61% # Class of committed instruction 856system.cpu0.commit.op_class_0::IntDiv 67517 0.01% 69.62% # Class of committed instruction 857system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.62% # Class of committed instruction 858system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.62% # Class of committed instruction 859system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.62% # Class of committed instruction 860system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.62% # Class of committed instruction 861system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.62% # Class of committed instruction 862system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.62% # Class of committed instruction 863system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.62% # Class of committed instruction 864system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.62% # Class of committed instruction 865system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.62% # Class of committed instruction 866system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.62% # Class of committed instruction 867system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.62% # Class of committed instruction 868system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.62% # Class of committed instruction 869system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.62% # Class of committed instruction 870system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.62% # Class of committed instruction 871system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.62% # Class of committed instruction 872system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.62% # Class of committed instruction 873system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.62% # Class of committed instruction 874system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.62% # Class of committed instruction 875system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.62% # Class of committed instruction 876system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.62% # Class of committed instruction 877system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.62% # Class of committed instruction 878system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.62% # Class of committed instruction 879system.cpu0.commit.op_class_0::SimdFloatMisc 75091 0.01% 69.63% # Class of committed instruction 880system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.63% # Class of committed instruction 881system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.63% # Class of committed instruction 882system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.63% # Class of committed instruction 883system.cpu0.commit.op_class_0::MemRead 93943789 15.95% 85.59% # Class of committed instruction 884system.cpu0.commit.op_class_0::MemWrite 84877391 14.41% 100.00% # Class of committed instruction 885system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 886system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 887system.cpu0.commit.op_class_0::total 588847718 # Class of committed instruction 888system.cpu0.commit.bw_lim_events 14304879 # number cycles where commit BW limit reached 889system.cpu0.rob.rob_reads 1439565573 # The number of ROB reads 890system.cpu0.rob.rob_writes 1289210941 # The number of ROB writes 891system.cpu0.timesIdled 1140163 # Number of times that the entire CPU went into an idle state and unscheduled itself 892system.cpu0.idleCycles 35352403 # Total number of cycles that the CPU has spent unscheduled due to idling 893system.cpu0.quiesceCycles 93926563172 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 894system.cpu0.committedInsts 501771314 # Number of Instructions Simulated 895system.cpu0.committedOps 588847718 # Number of Ops (including micro ops) Simulated 896system.cpu0.cpi 1.721488 # CPI: Cycles Per Instruction 897system.cpu0.cpi_total 1.721488 # CPI: Total CPI of All Threads 898system.cpu0.ipc 0.580893 # IPC: Instructions Per Cycle 899system.cpu0.ipc_total 0.580893 # IPC: Total IPC of All Threads 900system.cpu0.int_regfile_reads 739095549 # number of integer regfile reads 901system.cpu0.int_regfile_writes 439787902 # number of integer regfile writes 902system.cpu0.fp_regfile_reads 872002 # number of floating regfile reads 903system.cpu0.fp_regfile_writes 484356 # number of floating regfile writes 904system.cpu0.cc_regfile_reads 137161341 # number of cc regfile reads 905system.cpu0.cc_regfile_writes 137881500 # number of cc regfile writes 906system.cpu0.misc_regfile_reads 1443535644 # number of misc regfile reads 907system.cpu0.misc_regfile_writes 16079939 # number of misc regfile writes 908system.cpu0.dcache.tags.replacements 6407370 # number of replacements 909system.cpu0.dcache.tags.tagsinuse 508.018138 # Cycle average of tags in use 910system.cpu0.dcache.tags.total_refs 166146345 # Total number of references to valid blocks. 911system.cpu0.dcache.tags.sampled_refs 6407881 # Sample count of references to valid blocks. 912system.cpu0.dcache.tags.avg_refs 25.928438 # Average number of references to valid blocks. 913system.cpu0.dcache.tags.warmup_cycle 2962355000 # Cycle when the warmup percentage was hit. 914system.cpu0.dcache.tags.occ_blocks::cpu0.data 508.018138 # Average occupied blocks per requestor 915system.cpu0.dcache.tags.occ_percent::cpu0.data 0.992223 # Average percentage of cache occupancy 916system.cpu0.dcache.tags.occ_percent::total 0.992223 # Average percentage of cache occupancy 917system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 918system.cpu0.dcache.tags.age_task_id_blocks_1024::0 248 # Occupied blocks per task id 919system.cpu0.dcache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id 920system.cpu0.dcache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id 921system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 922system.cpu0.dcache.tags.tag_accesses 371124901 # Number of tag accesses 923system.cpu0.dcache.tags.data_accesses 371124901 # Number of data accesses 924system.cpu0.dcache.ReadReq_hits::cpu0.data 87218466 # number of ReadReq hits 925system.cpu0.dcache.ReadReq_hits::total 87218466 # number of ReadReq hits 926system.cpu0.dcache.WriteReq_hits::cpu0.data 73809320 # number of WriteReq hits 927system.cpu0.dcache.WriteReq_hits::total 73809320 # number of WriteReq hits 928system.cpu0.dcache.SoftPFReq_hits::cpu0.data 228978 # number of SoftPFReq hits 929system.cpu0.dcache.SoftPFReq_hits::total 228978 # number of SoftPFReq hits 930system.cpu0.dcache.WriteLineReq_hits::cpu0.data 263867 # number of WriteLineReq hits 931system.cpu0.dcache.WriteLineReq_hits::total 263867 # number of WriteLineReq hits 932system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1900288 # number of LoadLockedReq hits 933system.cpu0.dcache.LoadLockedReq_hits::total 1900288 # number of LoadLockedReq hits 934system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1938762 # number of StoreCondReq hits 935system.cpu0.dcache.StoreCondReq_hits::total 1938762 # number of StoreCondReq hits 936system.cpu0.dcache.demand_hits::cpu0.data 161027786 # number of demand (read+write) hits 937system.cpu0.dcache.demand_hits::total 161027786 # number of demand (read+write) hits 938system.cpu0.dcache.overall_hits::cpu0.data 161256764 # number of overall hits 939system.cpu0.dcache.overall_hits::total 161256764 # number of overall hits 940system.cpu0.dcache.ReadReq_misses::cpu0.data 7088028 # number of ReadReq misses 941system.cpu0.dcache.ReadReq_misses::total 7088028 # number of ReadReq misses 942system.cpu0.dcache.WriteReq_misses::cpu0.data 7798635 # number of WriteReq misses 943system.cpu0.dcache.WriteReq_misses::total 7798635 # number of WriteReq misses 944system.cpu0.dcache.SoftPFReq_misses::cpu0.data 740346 # number of SoftPFReq misses 945system.cpu0.dcache.SoftPFReq_misses::total 740346 # number of SoftPFReq misses 946system.cpu0.dcache.WriteLineReq_misses::cpu0.data 850980 # number of WriteLineReq misses 947system.cpu0.dcache.WriteLineReq_misses::total 850980 # number of WriteLineReq misses 948system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 273336 # number of LoadLockedReq misses 949system.cpu0.dcache.LoadLockedReq_misses::total 273336 # number of LoadLockedReq misses 950system.cpu0.dcache.StoreCondReq_misses::cpu0.data 194663 # number of StoreCondReq misses 951system.cpu0.dcache.StoreCondReq_misses::total 194663 # number of StoreCondReq misses 952system.cpu0.dcache.demand_misses::cpu0.data 14886663 # number of demand (read+write) misses 953system.cpu0.dcache.demand_misses::total 14886663 # number of demand (read+write) misses 954system.cpu0.dcache.overall_misses::cpu0.data 15627009 # number of overall misses 955system.cpu0.dcache.overall_misses::total 15627009 # number of overall misses 956system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 124519522000 # number of ReadReq miss cycles 957system.cpu0.dcache.ReadReq_miss_latency::total 124519522000 # number of ReadReq miss cycles 958system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 171455239141 # number of WriteReq miss cycles 959system.cpu0.dcache.WriteReq_miss_latency::total 171455239141 # number of WriteReq miss cycles 960system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 101116390498 # number of WriteLineReq miss cycles 961system.cpu0.dcache.WriteLineReq_miss_latency::total 101116390498 # number of WriteLineReq miss cycles 962system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4428125500 # number of LoadLockedReq miss cycles 963system.cpu0.dcache.LoadLockedReq_miss_latency::total 4428125500 # number of LoadLockedReq miss cycles 964system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4749567500 # number of StoreCondReq miss cycles 965system.cpu0.dcache.StoreCondReq_miss_latency::total 4749567500 # number of StoreCondReq miss cycles 966system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 4799500 # number of StoreCondFailReq miss cycles 967system.cpu0.dcache.StoreCondFailReq_miss_latency::total 4799500 # number of StoreCondFailReq miss cycles 968system.cpu0.dcache.demand_miss_latency::cpu0.data 295974761141 # number of demand (read+write) miss cycles 969system.cpu0.dcache.demand_miss_latency::total 295974761141 # number of demand (read+write) miss cycles 970system.cpu0.dcache.overall_miss_latency::cpu0.data 295974761141 # number of overall miss cycles 971system.cpu0.dcache.overall_miss_latency::total 295974761141 # number of overall miss cycles 972system.cpu0.dcache.ReadReq_accesses::cpu0.data 94306494 # number of ReadReq accesses(hits+misses) 973system.cpu0.dcache.ReadReq_accesses::total 94306494 # number of ReadReq accesses(hits+misses) 974system.cpu0.dcache.WriteReq_accesses::cpu0.data 81607955 # number of WriteReq accesses(hits+misses) 975system.cpu0.dcache.WriteReq_accesses::total 81607955 # number of WriteReq accesses(hits+misses) 976system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 969324 # number of SoftPFReq accesses(hits+misses) 977system.cpu0.dcache.SoftPFReq_accesses::total 969324 # number of SoftPFReq accesses(hits+misses) 978system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1114847 # number of WriteLineReq accesses(hits+misses) 979system.cpu0.dcache.WriteLineReq_accesses::total 1114847 # number of WriteLineReq accesses(hits+misses) 980system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2173624 # number of LoadLockedReq accesses(hits+misses) 981system.cpu0.dcache.LoadLockedReq_accesses::total 2173624 # number of LoadLockedReq accesses(hits+misses) 982system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2133425 # number of StoreCondReq accesses(hits+misses) 983system.cpu0.dcache.StoreCondReq_accesses::total 2133425 # number of StoreCondReq accesses(hits+misses) 984system.cpu0.dcache.demand_accesses::cpu0.data 175914449 # number of demand (read+write) accesses 985system.cpu0.dcache.demand_accesses::total 175914449 # number of demand (read+write) accesses 986system.cpu0.dcache.overall_accesses::cpu0.data 176883773 # number of overall (read+write) accesses 987system.cpu0.dcache.overall_accesses::total 176883773 # number of overall (read+write) accesses 988system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.075159 # miss rate for ReadReq accesses 989system.cpu0.dcache.ReadReq_miss_rate::total 0.075159 # miss rate for ReadReq accesses 990system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.095562 # miss rate for WriteReq accesses 991system.cpu0.dcache.WriteReq_miss_rate::total 0.095562 # miss rate for WriteReq accesses 992system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.763776 # miss rate for SoftPFReq accesses 993system.cpu0.dcache.SoftPFReq_miss_rate::total 0.763776 # miss rate for SoftPFReq accesses 994system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.763316 # miss rate for WriteLineReq accesses 995system.cpu0.dcache.WriteLineReq_miss_rate::total 0.763316 # miss rate for WriteLineReq accesses 996system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.125751 # miss rate for LoadLockedReq accesses 997system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.125751 # miss rate for LoadLockedReq accesses 998system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.091244 # miss rate for StoreCondReq accesses 999system.cpu0.dcache.StoreCondReq_miss_rate::total 0.091244 # miss rate for StoreCondReq accesses 1000system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084624 # miss rate for demand accesses 1001system.cpu0.dcache.demand_miss_rate::total 0.084624 # miss rate for demand accesses 1002system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088346 # miss rate for overall accesses 1003system.cpu0.dcache.overall_miss_rate::total 0.088346 # miss rate for overall accesses 1004system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17567.583254 # average ReadReq miss latency 1005system.cpu0.dcache.ReadReq_avg_miss_latency::total 17567.583254 # average ReadReq miss latency 1006system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21985.288341 # average WriteReq miss latency 1007system.cpu0.dcache.WriteReq_avg_miss_latency::total 21985.288341 # average WriteReq miss latency 1008system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 118823.462946 # average WriteLineReq miss latency 1009system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 118823.462946 # average WriteLineReq miss latency 1010system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16200.301095 # average LoadLockedReq miss latency 1011system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16200.301095 # average LoadLockedReq miss latency 1012system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24398.922754 # average StoreCondReq miss latency 1013system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24398.922754 # average StoreCondReq miss latency 1014system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 1015system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1016system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19881.874208 # average overall miss latency 1017system.cpu0.dcache.demand_avg_miss_latency::total 19881.874208 # average overall miss latency 1018system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18939.949490 # average overall miss latency 1019system.cpu0.dcache.overall_avg_miss_latency::total 18939.949490 # average overall miss latency 1020system.cpu0.dcache.blocked_cycles::no_mshrs 31639371 # number of cycles access was blocked 1021system.cpu0.dcache.blocked_cycles::no_targets 26128725 # number of cycles access was blocked 1022system.cpu0.dcache.blocked::no_mshrs 779388 # number of cycles access was blocked 1023system.cpu0.dcache.blocked::no_targets 763893 # number of cycles access was blocked 1024system.cpu0.dcache.avg_blocked_cycles::no_mshrs 40.595148 # average number of cycles each access was blocked 1025system.cpu0.dcache.avg_blocked_cycles::no_targets 34.204692 # average number of cycles each access was blocked 1026system.cpu0.dcache.fast_writes 0 # number of fast writes performed 1027system.cpu0.dcache.cache_copies 0 # number of cache copies performed 1028system.cpu0.dcache.writebacks::writebacks 4315919 # number of writebacks 1029system.cpu0.dcache.writebacks::total 4315919 # number of writebacks 1030system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3584647 # number of ReadReq MSHR hits 1031system.cpu0.dcache.ReadReq_mshr_hits::total 3584647 # number of ReadReq MSHR hits 1032system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6264689 # number of WriteReq MSHR hits 1033system.cpu0.dcache.WriteReq_mshr_hits::total 6264689 # number of WriteReq MSHR hits 1034system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4628 # number of WriteLineReq MSHR hits 1035system.cpu0.dcache.WriteLineReq_mshr_hits::total 4628 # number of WriteLineReq MSHR hits 1036system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 139100 # number of LoadLockedReq MSHR hits 1037system.cpu0.dcache.LoadLockedReq_mshr_hits::total 139100 # number of LoadLockedReq MSHR hits 1038system.cpu0.dcache.demand_mshr_hits::cpu0.data 9849336 # number of demand (read+write) MSHR hits 1039system.cpu0.dcache.demand_mshr_hits::total 9849336 # number of demand (read+write) MSHR hits 1040system.cpu0.dcache.overall_mshr_hits::cpu0.data 9849336 # number of overall MSHR hits 1041system.cpu0.dcache.overall_mshr_hits::total 9849336 # number of overall MSHR hits 1042system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3503381 # number of ReadReq MSHR misses 1043system.cpu0.dcache.ReadReq_mshr_misses::total 3503381 # number of ReadReq MSHR misses 1044system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1533946 # number of WriteReq MSHR misses 1045system.cpu0.dcache.WriteReq_mshr_misses::total 1533946 # number of WriteReq MSHR misses 1046system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 733362 # number of SoftPFReq MSHR misses 1047system.cpu0.dcache.SoftPFReq_mshr_misses::total 733362 # number of SoftPFReq MSHR misses 1048system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 846352 # number of WriteLineReq MSHR misses 1049system.cpu0.dcache.WriteLineReq_mshr_misses::total 846352 # number of WriteLineReq MSHR misses 1050system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 134236 # number of LoadLockedReq MSHR misses 1051system.cpu0.dcache.LoadLockedReq_mshr_misses::total 134236 # number of LoadLockedReq MSHR misses 1052system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 194661 # number of StoreCondReq MSHR misses 1053system.cpu0.dcache.StoreCondReq_mshr_misses::total 194661 # number of StoreCondReq MSHR misses 1054system.cpu0.dcache.demand_mshr_misses::cpu0.data 5037327 # number of demand (read+write) MSHR misses 1055system.cpu0.dcache.demand_mshr_misses::total 5037327 # number of demand (read+write) MSHR misses 1056system.cpu0.dcache.overall_mshr_misses::cpu0.data 5770689 # number of overall MSHR misses 1057system.cpu0.dcache.overall_mshr_misses::total 5770689 # number of overall MSHR misses 1058system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 33238 # number of ReadReq MSHR uncacheable 1059system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33238 # number of ReadReq MSHR uncacheable 1060system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 33405 # number of WriteReq MSHR uncacheable 1061system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33405 # number of WriteReq MSHR uncacheable 1062system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 66643 # number of overall MSHR uncacheable misses 1063system.cpu0.dcache.overall_mshr_uncacheable_misses::total 66643 # number of overall MSHR uncacheable misses 1064system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 56780867000 # number of ReadReq MSHR miss cycles 1065system.cpu0.dcache.ReadReq_mshr_miss_latency::total 56780867000 # number of ReadReq MSHR miss cycles 1066system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 38418617555 # number of WriteReq MSHR miss cycles 1067system.cpu0.dcache.WriteReq_mshr_miss_latency::total 38418617555 # number of WriteReq MSHR miss cycles 1068system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 19943250500 # number of SoftPFReq MSHR miss cycles 1069system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 19943250500 # number of SoftPFReq MSHR miss cycles 1070system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 100022529998 # number of WriteLineReq MSHR miss cycles 1071system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 100022529998 # number of WriteLineReq MSHR miss cycles 1072system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1962249500 # number of LoadLockedReq MSHR miss cycles 1073system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1962249500 # number of LoadLockedReq MSHR miss cycles 1074system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4554969500 # number of StoreCondReq MSHR miss cycles 1075system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4554969500 # number of StoreCondReq MSHR miss cycles 1076system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 4736500 # number of StoreCondFailReq MSHR miss cycles 1077system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 4736500 # number of StoreCondFailReq MSHR miss cycles 1078system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 95199484555 # number of demand (read+write) MSHR miss cycles 1079system.cpu0.dcache.demand_mshr_miss_latency::total 95199484555 # number of demand (read+write) MSHR miss cycles 1080system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 115142735055 # number of overall MSHR miss cycles 1081system.cpu0.dcache.overall_mshr_miss_latency::total 115142735055 # number of overall MSHR miss cycles 1082system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5997592500 # number of ReadReq MSHR uncacheable cycles 1083system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5997592500 # number of ReadReq MSHR uncacheable cycles 1084system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5944742000 # number of WriteReq MSHR uncacheable cycles 1085system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5944742000 # number of WriteReq MSHR uncacheable cycles 1086system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11942334500 # number of overall MSHR uncacheable cycles 1087system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11942334500 # number of overall MSHR uncacheable cycles 1088system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037149 # mshr miss rate for ReadReq accesses 1089system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037149 # mshr miss rate for ReadReq accesses 1090system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018797 # mshr miss rate for WriteReq accesses 1091system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018797 # mshr miss rate for WriteReq accesses 1092system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.756571 # mshr miss rate for SoftPFReq accesses 1093system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.756571 # mshr miss rate for SoftPFReq accesses 1094system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.759164 # mshr miss rate for WriteLineReq accesses 1095system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.759164 # mshr miss rate for WriteLineReq accesses 1096system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061757 # mshr miss rate for LoadLockedReq accesses 1097system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061757 # mshr miss rate for LoadLockedReq accesses 1098system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.091243 # mshr miss rate for StoreCondReq accesses 1099system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.091243 # mshr miss rate for StoreCondReq accesses 1100system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028635 # mshr miss rate for demand accesses 1101system.cpu0.dcache.demand_mshr_miss_rate::total 0.028635 # mshr miss rate for demand accesses 1102system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032624 # mshr miss rate for overall accesses 1103system.cpu0.dcache.overall_mshr_miss_rate::total 0.032624 # mshr miss rate for overall accesses 1104system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 16207.448462 # average ReadReq mshr miss latency 1105system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 16207.448462 # average ReadReq mshr miss latency 1106system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25045.612789 # average WriteReq mshr miss latency 1107system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25045.612789 # average WriteReq mshr miss latency 1108system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 27194.278542 # average SoftPFReq mshr miss latency 1109system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 27194.278542 # average SoftPFReq mshr miss latency 1110system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 118180.768756 # average WriteLineReq mshr miss latency 1111system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 118180.768756 # average WriteLineReq mshr miss latency 1112system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14617.908013 # average LoadLockedReq mshr miss latency 1113system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14617.908013 # average LoadLockedReq mshr miss latency 1114system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23399.497074 # average StoreCondReq mshr miss latency 1115system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23399.497074 # average StoreCondReq mshr miss latency 1116system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1117system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1118system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18898.809737 # average overall mshr miss latency 1119system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18898.809737 # average overall mshr miss latency 1120system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19953.030748 # average overall mshr miss latency 1121system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19953.030748 # average overall mshr miss latency 1122system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 180443.844395 # average ReadReq mshr uncacheable latency 1123system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 180443.844395 # average ReadReq mshr uncacheable latency 1124system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 177959.646759 # average WriteReq mshr uncacheable latency 1125system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 177959.646759 # average WriteReq mshr uncacheable latency 1126system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 179198.633015 # average overall mshr uncacheable latency 1127system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 179198.633015 # average overall mshr uncacheable latency 1128system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1129system.cpu0.icache.tags.replacements 6757482 # number of replacements 1130system.cpu0.icache.tags.tagsinuse 511.935144 # Cycle average of tags in use 1131system.cpu0.icache.tags.total_refs 224272608 # Total number of references to valid blocks. 1132system.cpu0.icache.tags.sampled_refs 6757994 # Sample count of references to valid blocks. 1133system.cpu0.icache.tags.avg_refs 33.186269 # Average number of references to valid blocks. 1134system.cpu0.icache.tags.warmup_cycle 22852216000 # Cycle when the warmup percentage was hit. 1135system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.935144 # Average occupied blocks per requestor 1136system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999873 # Average percentage of cache occupancy 1137system.cpu0.icache.tags.occ_percent::total 0.999873 # Average percentage of cache occupancy 1138system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1139system.cpu0.icache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id 1140system.cpu0.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id 1141system.cpu0.icache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id 1142system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1143system.cpu0.icache.tags.tag_accesses 469620349 # Number of tag accesses 1144system.cpu0.icache.tags.data_accesses 469620349 # Number of data accesses 1145system.cpu0.icache.ReadReq_hits::cpu0.inst 224272608 # number of ReadReq hits 1146system.cpu0.icache.ReadReq_hits::total 224272608 # number of ReadReq hits 1147system.cpu0.icache.demand_hits::cpu0.inst 224272608 # number of demand (read+write) hits 1148system.cpu0.icache.demand_hits::total 224272608 # number of demand (read+write) hits 1149system.cpu0.icache.overall_hits::cpu0.inst 224272608 # number of overall hits 1150system.cpu0.icache.overall_hits::total 224272608 # number of overall hits 1151system.cpu0.icache.ReadReq_misses::cpu0.inst 7158551 # number of ReadReq misses 1152system.cpu0.icache.ReadReq_misses::total 7158551 # number of ReadReq misses 1153system.cpu0.icache.demand_misses::cpu0.inst 7158551 # number of demand (read+write) misses 1154system.cpu0.icache.demand_misses::total 7158551 # number of demand (read+write) misses 1155system.cpu0.icache.overall_misses::cpu0.inst 7158551 # number of overall misses 1156system.cpu0.icache.overall_misses::total 7158551 # number of overall misses 1157system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 82703845756 # number of ReadReq miss cycles 1158system.cpu0.icache.ReadReq_miss_latency::total 82703845756 # number of ReadReq miss cycles 1159system.cpu0.icache.demand_miss_latency::cpu0.inst 82703845756 # number of demand (read+write) miss cycles 1160system.cpu0.icache.demand_miss_latency::total 82703845756 # number of demand (read+write) miss cycles 1161system.cpu0.icache.overall_miss_latency::cpu0.inst 82703845756 # number of overall miss cycles 1162system.cpu0.icache.overall_miss_latency::total 82703845756 # number of overall miss cycles 1163system.cpu0.icache.ReadReq_accesses::cpu0.inst 231431159 # number of ReadReq accesses(hits+misses) 1164system.cpu0.icache.ReadReq_accesses::total 231431159 # number of ReadReq accesses(hits+misses) 1165system.cpu0.icache.demand_accesses::cpu0.inst 231431159 # number of demand (read+write) accesses 1166system.cpu0.icache.demand_accesses::total 231431159 # number of demand (read+write) accesses 1167system.cpu0.icache.overall_accesses::cpu0.inst 231431159 # number of overall (read+write) accesses 1168system.cpu0.icache.overall_accesses::total 231431159 # number of overall (read+write) accesses 1169system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.030932 # miss rate for ReadReq accesses 1170system.cpu0.icache.ReadReq_miss_rate::total 0.030932 # miss rate for ReadReq accesses 1171system.cpu0.icache.demand_miss_rate::cpu0.inst 0.030932 # miss rate for demand accesses 1172system.cpu0.icache.demand_miss_rate::total 0.030932 # miss rate for demand accesses 1173system.cpu0.icache.overall_miss_rate::cpu0.inst 0.030932 # miss rate for overall accesses 1174system.cpu0.icache.overall_miss_rate::total 0.030932 # miss rate for overall accesses 1175system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11553.154508 # average ReadReq miss latency 1176system.cpu0.icache.ReadReq_avg_miss_latency::total 11553.154508 # average ReadReq miss latency 1177system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11553.154508 # average overall miss latency 1178system.cpu0.icache.demand_avg_miss_latency::total 11553.154508 # average overall miss latency 1179system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11553.154508 # average overall miss latency 1180system.cpu0.icache.overall_avg_miss_latency::total 11553.154508 # average overall miss latency 1181system.cpu0.icache.blocked_cycles::no_mshrs 13180342 # number of cycles access was blocked 1182system.cpu0.icache.blocked_cycles::no_targets 1608 # number of cycles access was blocked 1183system.cpu0.icache.blocked::no_mshrs 863819 # number of cycles access was blocked 1184system.cpu0.icache.blocked::no_targets 14 # number of cycles access was blocked 1185system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.258222 # average number of cycles each access was blocked 1186system.cpu0.icache.avg_blocked_cycles::no_targets 114.857143 # average number of cycles each access was blocked 1187system.cpu0.icache.fast_writes 0 # number of fast writes performed 1188system.cpu0.icache.cache_copies 0 # number of cache copies performed 1189system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 400520 # number of ReadReq MSHR hits 1190system.cpu0.icache.ReadReq_mshr_hits::total 400520 # number of ReadReq MSHR hits 1191system.cpu0.icache.demand_mshr_hits::cpu0.inst 400520 # number of demand (read+write) MSHR hits 1192system.cpu0.icache.demand_mshr_hits::total 400520 # number of demand (read+write) MSHR hits 1193system.cpu0.icache.overall_mshr_hits::cpu0.inst 400520 # number of overall MSHR hits 1194system.cpu0.icache.overall_mshr_hits::total 400520 # number of overall MSHR hits 1195system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6758031 # number of ReadReq MSHR misses 1196system.cpu0.icache.ReadReq_mshr_misses::total 6758031 # number of ReadReq MSHR misses 1197system.cpu0.icache.demand_mshr_misses::cpu0.inst 6758031 # number of demand (read+write) MSHR misses 1198system.cpu0.icache.demand_mshr_misses::total 6758031 # number of demand (read+write) MSHR misses 1199system.cpu0.icache.overall_mshr_misses::cpu0.inst 6758031 # number of overall MSHR misses 1200system.cpu0.icache.overall_mshr_misses::total 6758031 # number of overall MSHR misses 1201system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21294 # number of ReadReq MSHR uncacheable 1202system.cpu0.icache.ReadReq_mshr_uncacheable::total 21294 # number of ReadReq MSHR uncacheable 1203system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21294 # number of overall MSHR uncacheable misses 1204system.cpu0.icache.overall_mshr_uncacheable_misses::total 21294 # number of overall MSHR uncacheable misses 1205system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 74295068991 # number of ReadReq MSHR miss cycles 1206system.cpu0.icache.ReadReq_mshr_miss_latency::total 74295068991 # number of ReadReq MSHR miss cycles 1207system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 74295068991 # number of demand (read+write) MSHR miss cycles 1208system.cpu0.icache.demand_mshr_miss_latency::total 74295068991 # number of demand (read+write) MSHR miss cycles 1209system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 74295068991 # number of overall MSHR miss cycles 1210system.cpu0.icache.overall_mshr_miss_latency::total 74295068991 # number of overall MSHR miss cycles 1211system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2939725498 # number of ReadReq MSHR uncacheable cycles 1212system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2939725498 # number of ReadReq MSHR uncacheable cycles 1213system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2939725498 # number of overall MSHR uncacheable cycles 1214system.cpu0.icache.overall_mshr_uncacheable_latency::total 2939725498 # number of overall MSHR uncacheable cycles 1215system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.029201 # mshr miss rate for ReadReq accesses 1216system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.029201 # mshr miss rate for ReadReq accesses 1217system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.029201 # mshr miss rate for demand accesses 1218system.cpu0.icache.demand_mshr_miss_rate::total 0.029201 # mshr miss rate for demand accesses 1219system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.029201 # mshr miss rate for overall accesses 1220system.cpu0.icache.overall_mshr_miss_rate::total 0.029201 # mshr miss rate for overall accesses 1221system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10993.596950 # average ReadReq mshr miss latency 1222system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10993.596950 # average ReadReq mshr miss latency 1223system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10993.596950 # average overall mshr miss latency 1224system.cpu0.icache.demand_avg_mshr_miss_latency::total 10993.596950 # average overall mshr miss latency 1225system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10993.596950 # average overall mshr miss latency 1226system.cpu0.icache.overall_avg_mshr_miss_latency::total 10993.596950 # average overall mshr miss latency 1227system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138054.170095 # average ReadReq mshr uncacheable latency 1228system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138054.170095 # average ReadReq mshr uncacheable latency 1229system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138054.170095 # average overall mshr uncacheable latency 1230system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138054.170095 # average overall mshr uncacheable latency 1231system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1232system.cpu0.l2cache.prefetcher.num_hwpf_issued 8609545 # number of hwpf issued 1233system.cpu0.l2cache.prefetcher.pfIdentified 8618519 # number of prefetch candidates identified 1234system.cpu0.l2cache.prefetcher.pfBufferHit 8045 # number of redundant prefetches already in prefetch queue 1235system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1236system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1237system.cpu0.l2cache.prefetcher.pfSpanPage 1094401 # number of prefetches not generated due to page crossing 1238system.cpu0.l2cache.tags.replacements 2903307 # number of replacements 1239system.cpu0.l2cache.tags.tagsinuse 16246.409963 # Cycle average of tags in use 1240system.cpu0.l2cache.tags.total_refs 22353900 # Total number of references to valid blocks. 1241system.cpu0.l2cache.tags.sampled_refs 2918996 # Sample count of references to valid blocks. 1242system.cpu0.l2cache.tags.avg_refs 7.658078 # Average number of references to valid blocks. 1243system.cpu0.l2cache.tags.warmup_cycle 21271828500 # Cycle when the warmup percentage was hit. 1244system.cpu0.l2cache.tags.occ_blocks::writebacks 7113.964436 # Average occupied blocks per requestor 1245system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 80.712375 # Average occupied blocks per requestor 1246system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 97.665127 # Average occupied blocks per requestor 1247system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4225.088231 # Average occupied blocks per requestor 1248system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3888.580421 # Average occupied blocks per requestor 1249system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 840.399372 # Average occupied blocks per requestor 1250system.cpu0.l2cache.tags.occ_percent::writebacks 0.434202 # Average percentage of cache occupancy 1251system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004926 # Average percentage of cache occupancy 1252system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005961 # Average percentage of cache occupancy 1253system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.257879 # Average percentage of cache occupancy 1254system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.237340 # Average percentage of cache occupancy 1255system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.051294 # Average percentage of cache occupancy 1256system.cpu0.l2cache.tags.occ_percent::total 0.991602 # Average percentage of cache occupancy 1257system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1391 # Occupied blocks per task id 1258system.cpu0.l2cache.tags.occ_task_id_blocks::1023 88 # Occupied blocks per task id 1259system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14210 # Occupied blocks per task id 1260system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 4 # Occupied blocks per task id 1261system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 134 # Occupied blocks per task id 1262system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 197 # Occupied blocks per task id 1263system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 595 # Occupied blocks per task id 1264system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 461 # Occupied blocks per task id 1265system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id 1266system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 66 # Occupied blocks per task id 1267system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id 1268system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id 1269system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id 1270system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 745 # Occupied blocks per task id 1271system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4851 # Occupied blocks per task id 1272system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4773 # Occupied blocks per task id 1273system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3664 # Occupied blocks per task id 1274system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.084900 # Percentage of cache occupancy per task id 1275system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005371 # Percentage of cache occupancy per task id 1276system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.867310 # Percentage of cache occupancy per task id 1277system.cpu0.l2cache.tags.tag_accesses 448966117 # Number of tag accesses 1278system.cpu0.l2cache.tags.data_accesses 448966117 # Number of data accesses 1279system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 605202 # number of ReadReq hits 1280system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 189837 # number of ReadReq hits 1281system.cpu0.l2cache.ReadReq_hits::total 795039 # number of ReadReq hits 1282system.cpu0.l2cache.Writeback_hits::writebacks 4315912 # number of Writeback hits 1283system.cpu0.l2cache.Writeback_hits::total 4315912 # number of Writeback hits 1284system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 110882 # number of UpgradeReq hits 1285system.cpu0.l2cache.UpgradeReq_hits::total 110882 # number of UpgradeReq hits 1286system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 36120 # number of SCUpgradeReq hits 1287system.cpu0.l2cache.SCUpgradeReq_hits::total 36120 # number of SCUpgradeReq hits 1288system.cpu0.l2cache.ReadExReq_hits::cpu0.data 962986 # number of ReadExReq hits 1289system.cpu0.l2cache.ReadExReq_hits::total 962986 # number of ReadExReq hits 1290system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 6062865 # number of ReadCleanReq hits 1291system.cpu0.l2cache.ReadCleanReq_hits::total 6062865 # number of ReadCleanReq hits 1292system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3276140 # number of ReadSharedReq hits 1293system.cpu0.l2cache.ReadSharedReq_hits::total 3276140 # number of ReadSharedReq hits 1294system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 213470 # number of InvalidateReq hits 1295system.cpu0.l2cache.InvalidateReq_hits::total 213470 # number of InvalidateReq hits 1296system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 605202 # number of demand (read+write) hits 1297system.cpu0.l2cache.demand_hits::cpu0.itb.walker 189837 # number of demand (read+write) hits 1298system.cpu0.l2cache.demand_hits::cpu0.inst 6062865 # number of demand (read+write) hits 1299system.cpu0.l2cache.demand_hits::cpu0.data 4239126 # number of demand (read+write) hits 1300system.cpu0.l2cache.demand_hits::total 11097030 # number of demand (read+write) hits 1301system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 605202 # number of overall hits 1302system.cpu0.l2cache.overall_hits::cpu0.itb.walker 189837 # number of overall hits 1303system.cpu0.l2cache.overall_hits::cpu0.inst 6062865 # number of overall hits 1304system.cpu0.l2cache.overall_hits::cpu0.data 4239126 # number of overall hits 1305system.cpu0.l2cache.overall_hits::total 11097030 # number of overall hits 1306system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 13783 # number of ReadReq misses 1307system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 10250 # number of ReadReq misses 1308system.cpu0.l2cache.ReadReq_misses::total 24033 # number of ReadReq misses 1309system.cpu0.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses 1310system.cpu0.l2cache.Writeback_misses::total 1 # number of Writeback misses 1311system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 133626 # number of UpgradeReq misses 1312system.cpu0.l2cache.UpgradeReq_misses::total 133626 # number of UpgradeReq misses 1313system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 158531 # number of SCUpgradeReq misses 1314system.cpu0.l2cache.SCUpgradeReq_misses::total 158531 # number of SCUpgradeReq misses 1315system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 10 # number of SCUpgradeFailReq misses 1316system.cpu0.l2cache.SCUpgradeFailReq_misses::total 10 # number of SCUpgradeFailReq misses 1317system.cpu0.l2cache.ReadExReq_misses::cpu0.data 336962 # number of ReadExReq misses 1318system.cpu0.l2cache.ReadExReq_misses::total 336962 # number of ReadExReq misses 1319system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 695135 # number of ReadCleanReq misses 1320system.cpu0.l2cache.ReadCleanReq_misses::total 695135 # number of ReadCleanReq misses 1321system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1092519 # number of ReadSharedReq misses 1322system.cpu0.l2cache.ReadSharedReq_misses::total 1092519 # number of ReadSharedReq misses 1323system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 631427 # number of InvalidateReq misses 1324system.cpu0.l2cache.InvalidateReq_misses::total 631427 # number of InvalidateReq misses 1325system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 13783 # number of demand (read+write) misses 1326system.cpu0.l2cache.demand_misses::cpu0.itb.walker 10250 # number of demand (read+write) misses 1327system.cpu0.l2cache.demand_misses::cpu0.inst 695135 # number of demand (read+write) misses 1328system.cpu0.l2cache.demand_misses::cpu0.data 1429481 # number of demand (read+write) misses 1329system.cpu0.l2cache.demand_misses::total 2148649 # number of demand (read+write) misses 1330system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 13783 # number of overall misses 1331system.cpu0.l2cache.overall_misses::cpu0.itb.walker 10250 # number of overall misses 1332system.cpu0.l2cache.overall_misses::cpu0.inst 695135 # number of overall misses 1333system.cpu0.l2cache.overall_misses::cpu0.data 1429481 # number of overall misses 1334system.cpu0.l2cache.overall_misses::total 2148649 # number of overall misses 1335system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 679881500 # number of ReadReq miss cycles 1336system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 586856000 # number of ReadReq miss cycles 1337system.cpu0.l2cache.ReadReq_miss_latency::total 1266737500 # number of ReadReq miss cycles 1338system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 4146846499 # number of UpgradeReq miss cycles 1339system.cpu0.l2cache.UpgradeReq_miss_latency::total 4146846499 # number of UpgradeReq miss cycles 1340system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3851336998 # number of SCUpgradeReq miss cycles 1341system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3851336998 # number of SCUpgradeReq miss cycles 1342system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4641499 # number of SCUpgradeFailReq miss cycles 1343system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4641499 # number of SCUpgradeFailReq miss cycles 1344system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 22977113499 # number of ReadExReq miss cycles 1345system.cpu0.l2cache.ReadExReq_miss_latency::total 22977113499 # number of ReadExReq miss cycles 1346system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 27999451498 # number of ReadCleanReq miss cycles 1347system.cpu0.l2cache.ReadCleanReq_miss_latency::total 27999451498 # number of ReadCleanReq miss cycles 1348system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 50408930969 # number of ReadSharedReq miss cycles 1349system.cpu0.l2cache.ReadSharedReq_miss_latency::total 50408930969 # number of ReadSharedReq miss cycles 1350system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 96428495994 # number of InvalidateReq miss cycles 1351system.cpu0.l2cache.InvalidateReq_miss_latency::total 96428495994 # number of InvalidateReq miss cycles 1352system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 679881500 # number of demand (read+write) miss cycles 1353system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 586856000 # number of demand (read+write) miss cycles 1354system.cpu0.l2cache.demand_miss_latency::cpu0.inst 27999451498 # number of demand (read+write) miss cycles 1355system.cpu0.l2cache.demand_miss_latency::cpu0.data 73386044468 # number of demand (read+write) miss cycles 1356system.cpu0.l2cache.demand_miss_latency::total 102652233466 # number of demand (read+write) miss cycles 1357system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 679881500 # number of overall miss cycles 1358system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 586856000 # number of overall miss cycles 1359system.cpu0.l2cache.overall_miss_latency::cpu0.inst 27999451498 # number of overall miss cycles 1360system.cpu0.l2cache.overall_miss_latency::cpu0.data 73386044468 # number of overall miss cycles 1361system.cpu0.l2cache.overall_miss_latency::total 102652233466 # number of overall miss cycles 1362system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 618985 # number of ReadReq accesses(hits+misses) 1363system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 200087 # number of ReadReq accesses(hits+misses) 1364system.cpu0.l2cache.ReadReq_accesses::total 819072 # number of ReadReq accesses(hits+misses) 1365system.cpu0.l2cache.Writeback_accesses::writebacks 4315913 # number of Writeback accesses(hits+misses) 1366system.cpu0.l2cache.Writeback_accesses::total 4315913 # number of Writeback accesses(hits+misses) 1367system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 244508 # number of UpgradeReq accesses(hits+misses) 1368system.cpu0.l2cache.UpgradeReq_accesses::total 244508 # number of UpgradeReq accesses(hits+misses) 1369system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 194651 # number of SCUpgradeReq accesses(hits+misses) 1370system.cpu0.l2cache.SCUpgradeReq_accesses::total 194651 # number of SCUpgradeReq accesses(hits+misses) 1371system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 10 # number of SCUpgradeFailReq accesses(hits+misses) 1372system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 10 # number of SCUpgradeFailReq accesses(hits+misses) 1373system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1299948 # number of ReadExReq accesses(hits+misses) 1374system.cpu0.l2cache.ReadExReq_accesses::total 1299948 # number of ReadExReq accesses(hits+misses) 1375system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6758000 # number of ReadCleanReq accesses(hits+misses) 1376system.cpu0.l2cache.ReadCleanReq_accesses::total 6758000 # number of ReadCleanReq accesses(hits+misses) 1377system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4368659 # number of ReadSharedReq accesses(hits+misses) 1378system.cpu0.l2cache.ReadSharedReq_accesses::total 4368659 # number of ReadSharedReq accesses(hits+misses) 1379system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 844897 # number of InvalidateReq accesses(hits+misses) 1380system.cpu0.l2cache.InvalidateReq_accesses::total 844897 # number of InvalidateReq accesses(hits+misses) 1381system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 618985 # number of demand (read+write) accesses 1382system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 200087 # number of demand (read+write) accesses 1383system.cpu0.l2cache.demand_accesses::cpu0.inst 6758000 # number of demand (read+write) accesses 1384system.cpu0.l2cache.demand_accesses::cpu0.data 5668607 # number of demand (read+write) accesses 1385system.cpu0.l2cache.demand_accesses::total 13245679 # number of demand (read+write) accesses 1386system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 618985 # number of overall (read+write) accesses 1387system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 200087 # number of overall (read+write) accesses 1388system.cpu0.l2cache.overall_accesses::cpu0.inst 6758000 # number of overall (read+write) accesses 1389system.cpu0.l2cache.overall_accesses::cpu0.data 5668607 # number of overall (read+write) accesses 1390system.cpu0.l2cache.overall_accesses::total 13245679 # number of overall (read+write) accesses 1391system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.022267 # miss rate for ReadReq accesses 1392system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.051228 # miss rate for ReadReq accesses 1393system.cpu0.l2cache.ReadReq_miss_rate::total 0.029342 # miss rate for ReadReq accesses 1394system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses 1395system.cpu0.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses 1396system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.546510 # miss rate for UpgradeReq accesses 1397system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.546510 # miss rate for UpgradeReq accesses 1398system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.814437 # miss rate for SCUpgradeReq accesses 1399system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.814437 # miss rate for SCUpgradeReq accesses 1400system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1401system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1402system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.259212 # miss rate for ReadExReq accesses 1403system.cpu0.l2cache.ReadExReq_miss_rate::total 0.259212 # miss rate for ReadExReq accesses 1404system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.102861 # miss rate for ReadCleanReq accesses 1405system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.102861 # miss rate for ReadCleanReq accesses 1406system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.250081 # miss rate for ReadSharedReq accesses 1407system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.250081 # miss rate for ReadSharedReq accesses 1408system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.747342 # miss rate for InvalidateReq accesses 1409system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.747342 # miss rate for InvalidateReq accesses 1410system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.022267 # miss rate for demand accesses 1411system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.051228 # miss rate for demand accesses 1412system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.102861 # miss rate for demand accesses 1413system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.252175 # miss rate for demand accesses 1414system.cpu0.l2cache.demand_miss_rate::total 0.162215 # miss rate for demand accesses 1415system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.022267 # miss rate for overall accesses 1416system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.051228 # miss rate for overall accesses 1417system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.102861 # miss rate for overall accesses 1418system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.252175 # miss rate for overall accesses 1419system.cpu0.l2cache.overall_miss_rate::total 0.162215 # miss rate for overall accesses 1420system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 49327.541174 # average ReadReq miss latency 1421system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 57254.243902 # average ReadReq miss latency 1422system.cpu0.l2cache.ReadReq_avg_miss_latency::total 52708.255316 # average ReadReq miss latency 1423system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 31033.230801 # average UpgradeReq miss latency 1424system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 31033.230801 # average UpgradeReq miss latency 1425system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 24293.904650 # average SCUpgradeReq miss latency 1426system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 24293.904650 # average SCUpgradeReq miss latency 1427system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 464149.900000 # average SCUpgradeFailReq miss latency 1428system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 464149.900000 # average SCUpgradeFailReq miss latency 1429system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 68189.034666 # average ReadExReq miss latency 1430system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 68189.034666 # average ReadExReq miss latency 1431system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 40279.156564 # average ReadCleanReq miss latency 1432system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 40279.156564 # average ReadCleanReq miss latency 1433system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 46140.095476 # average ReadSharedReq miss latency 1434system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 46140.095476 # average ReadSharedReq miss latency 1435system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 152715.192721 # average InvalidateReq miss latency 1436system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 152715.192721 # average InvalidateReq miss latency 1437system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 49327.541174 # average overall miss latency 1438system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 57254.243902 # average overall miss latency 1439system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 40279.156564 # average overall miss latency 1440system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 51337.544513 # average overall miss latency 1441system.cpu0.l2cache.demand_avg_miss_latency::total 47775.245499 # average overall miss latency 1442system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 49327.541174 # average overall miss latency 1443system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 57254.243902 # average overall miss latency 1444system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 40279.156564 # average overall miss latency 1445system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 51337.544513 # average overall miss latency 1446system.cpu0.l2cache.overall_avg_miss_latency::total 47775.245499 # average overall miss latency 1447system.cpu0.l2cache.blocked_cycles::no_mshrs 4122 # number of cycles access was blocked 1448system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1449system.cpu0.l2cache.blocked::no_mshrs 26 # number of cycles access was blocked 1450system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1451system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 158.538462 # average number of cycles each access was blocked 1452system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1453system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1454system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1455system.cpu0.l2cache.writebacks::writebacks 1567709 # number of writebacks 1456system.cpu0.l2cache.writebacks::total 1567709 # number of writebacks 1457system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 6 # number of ReadReq MSHR hits 1458system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 165 # number of ReadReq MSHR hits 1459system.cpu0.l2cache.ReadReq_mshr_hits::total 171 # number of ReadReq MSHR hits 1460system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 67086 # number of ReadExReq MSHR hits 1461system.cpu0.l2cache.ReadExReq_mshr_hits::total 67086 # number of ReadExReq MSHR hits 1462system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 4 # number of ReadCleanReq MSHR hits 1463system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits 1464system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 8307 # number of ReadSharedReq MSHR hits 1465system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 8307 # number of ReadSharedReq MSHR hits 1466system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 6 # number of demand (read+write) MSHR hits 1467system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 165 # number of demand (read+write) MSHR hits 1468system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits 1469system.cpu0.l2cache.demand_mshr_hits::cpu0.data 75393 # number of demand (read+write) MSHR hits 1470system.cpu0.l2cache.demand_mshr_hits::total 75568 # number of demand (read+write) MSHR hits 1471system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 6 # number of overall MSHR hits 1472system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 165 # number of overall MSHR hits 1473system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits 1474system.cpu0.l2cache.overall_mshr_hits::cpu0.data 75393 # number of overall MSHR hits 1475system.cpu0.l2cache.overall_mshr_hits::total 75568 # number of overall MSHR hits 1476system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 13777 # number of ReadReq MSHR misses 1477system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 10085 # number of ReadReq MSHR misses 1478system.cpu0.l2cache.ReadReq_mshr_misses::total 23862 # number of ReadReq MSHR misses 1479system.cpu0.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses 1480system.cpu0.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses 1481system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 118847 # number of CleanEvict MSHR misses 1482system.cpu0.l2cache.CleanEvict_mshr_misses::total 118847 # number of CleanEvict MSHR misses 1483system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 832278 # number of HardPFReq MSHR misses 1484system.cpu0.l2cache.HardPFReq_mshr_misses::total 832278 # number of HardPFReq MSHR misses 1485system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 133626 # number of UpgradeReq MSHR misses 1486system.cpu0.l2cache.UpgradeReq_mshr_misses::total 133626 # number of UpgradeReq MSHR misses 1487system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 158531 # number of SCUpgradeReq MSHR misses 1488system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 158531 # number of SCUpgradeReq MSHR misses 1489system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 10 # number of SCUpgradeFailReq MSHR misses 1490system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 10 # number of SCUpgradeFailReq MSHR misses 1491system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 269876 # number of ReadExReq MSHR misses 1492system.cpu0.l2cache.ReadExReq_mshr_misses::total 269876 # number of ReadExReq MSHR misses 1493system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 695131 # number of ReadCleanReq MSHR misses 1494system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 695131 # number of ReadCleanReq MSHR misses 1495system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1084212 # number of ReadSharedReq MSHR misses 1496system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1084212 # number of ReadSharedReq MSHR misses 1497system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 631427 # number of InvalidateReq MSHR misses 1498system.cpu0.l2cache.InvalidateReq_mshr_misses::total 631427 # number of InvalidateReq MSHR misses 1499system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 13777 # number of demand (read+write) MSHR misses 1500system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 10085 # number of demand (read+write) MSHR misses 1501system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 695131 # number of demand (read+write) MSHR misses 1502system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1354088 # number of demand (read+write) MSHR misses 1503system.cpu0.l2cache.demand_mshr_misses::total 2073081 # number of demand (read+write) MSHR misses 1504system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 13777 # number of overall MSHR misses 1505system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 10085 # number of overall MSHR misses 1506system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 695131 # number of overall MSHR misses 1507system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1354088 # number of overall MSHR misses 1508system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 832278 # number of overall MSHR misses 1509system.cpu0.l2cache.overall_mshr_misses::total 2905359 # number of overall MSHR misses 1510system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21294 # number of ReadReq MSHR uncacheable 1511system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 33238 # number of ReadReq MSHR uncacheable 1512system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 54532 # number of ReadReq MSHR uncacheable 1513system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 33405 # number of WriteReq MSHR uncacheable 1514system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 33405 # number of WriteReq MSHR uncacheable 1515system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21294 # number of overall MSHR uncacheable misses 1516system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 66643 # number of overall MSHR uncacheable misses 1517system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 87937 # number of overall MSHR uncacheable misses 1518system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 597098000 # number of ReadReq MSHR miss cycles 1519system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 519597500 # number of ReadReq MSHR miss cycles 1520system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1116695500 # number of ReadReq MSHR miss cycles 1521system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 67202265861 # number of HardPFReq MSHR miss cycles 1522system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 67202265861 # number of HardPFReq MSHR miss cycles 1523system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4741207495 # number of UpgradeReq MSHR miss cycles 1524system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4741207495 # number of UpgradeReq MSHR miss cycles 1525system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3076689494 # number of SCUpgradeReq MSHR miss cycles 1526system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3076689494 # number of SCUpgradeReq MSHR miss cycles 1527system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4263499 # number of SCUpgradeFailReq MSHR miss cycles 1528system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4263499 # number of SCUpgradeFailReq MSHR miss cycles 1529system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 17260521499 # number of ReadExReq MSHR miss cycles 1530system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 17260521499 # number of ReadExReq MSHR miss cycles 1531system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 23828492498 # number of ReadCleanReq MSHR miss cycles 1532system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 23828492498 # number of ReadCleanReq MSHR miss cycles 1533system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 43284601971 # number of ReadSharedReq MSHR miss cycles 1534system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 43284601971 # number of ReadSharedReq MSHR miss cycles 1535system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 92639933994 # number of InvalidateReq MSHR miss cycles 1536system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 92639933994 # number of InvalidateReq MSHR miss cycles 1537system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 597098000 # number of demand (read+write) MSHR miss cycles 1538system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 519597500 # number of demand (read+write) MSHR miss cycles 1539system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 23828492498 # number of demand (read+write) MSHR miss cycles 1540system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 60545123470 # number of demand (read+write) MSHR miss cycles 1541system.cpu0.l2cache.demand_mshr_miss_latency::total 85490311468 # number of demand (read+write) MSHR miss cycles 1542system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 597098000 # number of overall MSHR miss cycles 1543system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 519597500 # number of overall MSHR miss cycles 1544system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 23828492498 # number of overall MSHR miss cycles 1545system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 60545123470 # number of overall MSHR miss cycles 1546system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 67202265861 # number of overall MSHR miss cycles 1547system.cpu0.l2cache.overall_mshr_miss_latency::total 152692577329 # number of overall MSHR miss cycles 1548system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2780019500 # number of ReadReq MSHR uncacheable cycles 1549system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5731623000 # number of ReadReq MSHR uncacheable cycles 1550system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8511642500 # number of ReadReq MSHR uncacheable cycles 1551system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5688753467 # number of WriteReq MSHR uncacheable cycles 1552system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5688753467 # number of WriteReq MSHR uncacheable cycles 1553system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 2780019500 # number of overall MSHR uncacheable cycles 1554system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11420376467 # number of overall MSHR uncacheable cycles 1555system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 14200395967 # number of overall MSHR uncacheable cycles 1556system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.022257 # mshr miss rate for ReadReq accesses 1557system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.050403 # mshr miss rate for ReadReq accesses 1558system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.029133 # mshr miss rate for ReadReq accesses 1559system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses 1560system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses 1561system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1562system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1563system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1564system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1565system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.546510 # mshr miss rate for UpgradeReq accesses 1566system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.546510 # mshr miss rate for UpgradeReq accesses 1567system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.814437 # mshr miss rate for SCUpgradeReq accesses 1568system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.814437 # mshr miss rate for SCUpgradeReq accesses 1569system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1570system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1571system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.207605 # mshr miss rate for ReadExReq accesses 1572system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.207605 # mshr miss rate for ReadExReq accesses 1573system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.102860 # mshr miss rate for ReadCleanReq accesses 1574system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.102860 # mshr miss rate for ReadCleanReq accesses 1575system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.248180 # mshr miss rate for ReadSharedReq accesses 1576system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.248180 # mshr miss rate for ReadSharedReq accesses 1577system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.747342 # mshr miss rate for InvalidateReq accesses 1578system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.747342 # mshr miss rate for InvalidateReq accesses 1579system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.022257 # mshr miss rate for demand accesses 1580system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.050403 # mshr miss rate for demand accesses 1581system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.102860 # mshr miss rate for demand accesses 1582system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.238875 # mshr miss rate for demand accesses 1583system.cpu0.l2cache.demand_mshr_miss_rate::total 0.156510 # mshr miss rate for demand accesses 1584system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.022257 # mshr miss rate for overall accesses 1585system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.050403 # mshr miss rate for overall accesses 1586system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.102860 # mshr miss rate for overall accesses 1587system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.238875 # mshr miss rate for overall accesses 1588system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1589system.cpu0.l2cache.overall_mshr_miss_rate::total 0.219344 # mshr miss rate for overall accesses 1590system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 43340.204689 # average ReadReq mshr miss latency 1591system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 51521.814576 # average ReadReq mshr miss latency 1592system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 46798.068058 # average ReadReq mshr miss latency 1593system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 80744.974469 # average HardPFReq mshr miss latency 1594system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 80744.974469 # average HardPFReq mshr miss latency 1595system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 35481.175033 # average UpgradeReq mshr miss latency 1596system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 35481.175033 # average UpgradeReq mshr miss latency 1597system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 19407.494395 # average SCUpgradeReq mshr miss latency 1598system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19407.494395 # average SCUpgradeReq mshr miss latency 1599system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 426349.900000 # average SCUpgradeFailReq mshr miss latency 1600system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 426349.900000 # average SCUpgradeFailReq mshr miss latency 1601system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 63957.230354 # average ReadExReq mshr miss latency 1602system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 63957.230354 # average ReadExReq mshr miss latency 1603system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 34279.139469 # average ReadCleanReq mshr miss latency 1604system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34279.139469 # average ReadCleanReq mshr miss latency 1605system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 39922.636875 # average ReadSharedReq mshr miss latency 1606system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 39922.636875 # average ReadSharedReq mshr miss latency 1607system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 146715.192721 # average InvalidateReq mshr miss latency 1608system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 146715.192721 # average InvalidateReq mshr miss latency 1609system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 43340.204689 # average overall mshr miss latency 1610system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 51521.814576 # average overall mshr miss latency 1611system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34279.139469 # average overall mshr miss latency 1612system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 44712.842496 # average overall mshr miss latency 1613system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 41238.288069 # average overall mshr miss latency 1614system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 43340.204689 # average overall mshr miss latency 1615system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 51521.814576 # average overall mshr miss latency 1616system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34279.139469 # average overall mshr miss latency 1617system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 44712.842496 # average overall mshr miss latency 1618system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 80744.974469 # average overall mshr miss latency 1619system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 52555.493944 # average overall mshr miss latency 1620system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130554.123227 # average ReadReq mshr uncacheable latency 1621system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 172441.873759 # average ReadReq mshr uncacheable latency 1622system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 156085.280202 # average ReadReq mshr uncacheable latency 1623system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170296.466607 # average WriteReq mshr uncacheable latency 1624system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 170296.466607 # average WriteReq mshr uncacheable latency 1625system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130554.123227 # average overall mshr uncacheable latency 1626system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 171366.482106 # average overall mshr uncacheable latency 1627system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 161483.743669 # average overall mshr uncacheable latency 1628system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1629system.cpu0.toL2Bus.snoop_filter.tot_requests 27252548 # Total number of requests made to the snoop filter. 1630system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13981170 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1631system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2244 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1632system.cpu0.toL2Bus.snoop_filter.tot_snoops 570842 # Total number of snoops made to the snoop filter. 1633system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 570828 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1634system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 14 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1635system.cpu0.toL2Bus.trans_dist::ReadReq 1016473 # Transaction distribution 1636system.cpu0.toL2Bus.trans_dist::ReadResp 12252394 # Transaction distribution 1637system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 1638system.cpu0.toL2Bus.trans_dist::WriteReq 33406 # Transaction distribution 1639system.cpu0.toL2Bus.trans_dist::WriteResp 33405 # Transaction distribution 1640system.cpu0.toL2Bus.trans_dist::Writeback 5923375 # Transaction distribution 1641system.cpu0.toL2Bus.trans_dist::CleanEvict 10861944 # Transaction distribution 1642system.cpu0.toL2Bus.trans_dist::HardPFReq 1063583 # Transaction distribution 1643system.cpu0.toL2Bus.trans_dist::HardPFResp 5 # Transaction distribution 1644system.cpu0.toL2Bus.trans_dist::UpgradeReq 463812 # Transaction distribution 1645system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 352945 # Transaction distribution 1646system.cpu0.toL2Bus.trans_dist::UpgradeResp 515465 # Transaction distribution 1647system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution 1648system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution 1649system.cpu0.toL2Bus.trans_dist::ReadExReq 1384026 # Transaction distribution 1650system.cpu0.toL2Bus.trans_dist::ReadExResp 1310731 # Transaction distribution 1651system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6758031 # Transaction distribution 1652system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5399513 # Transaction distribution 1653system.cpu0.toL2Bus.trans_dist::InvalidateReq 852147 # Transaction distribution 1654system.cpu0.toL2Bus.trans_dist::InvalidateResp 844897 # Transaction distribution 1655system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20314687 # Packet count per connected master and slave (bytes) 1656system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20641650 # Packet count per connected master and slave (bytes) 1657system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 432749 # Packet count per connected master and slave (bytes) 1658system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1348262 # Packet count per connected master and slave (bytes) 1659system.cpu0.toL2Bus.pkt_count::total 42737348 # Packet count per connected master and slave (bytes) 1660system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 432852704 # Cumulative packet size per connected master and slave (bytes) 1661system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 646893668 # Cumulative packet size per connected master and slave (bytes) 1662system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1600696 # Cumulative packet size per connected master and slave (bytes) 1663system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4951880 # Cumulative packet size per connected master and slave (bytes) 1664system.cpu0.toL2Bus.pkt_size::total 1086298948 # Cumulative packet size per connected master and slave (bytes) 1665system.cpu0.toL2Bus.snoops 6525445 # Total snoops (count) 1666system.cpu0.toL2Bus.snoop_fanout::samples 34111599 # Request fanout histogram 1667system.cpu0.toL2Bus.snoop_fanout::mean 0.027918 # Request fanout histogram 1668system.cpu0.toL2Bus.snoop_fanout::stdev 0.164740 # Request fanout histogram 1669system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1670system.cpu0.toL2Bus.snoop_fanout::0 33159285 97.21% 97.21% # Request fanout histogram 1671system.cpu0.toL2Bus.snoop_fanout::1 952300 2.79% 100.00% # Request fanout histogram 1672system.cpu0.toL2Bus.snoop_fanout::2 14 0.00% 100.00% # Request fanout histogram 1673system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1674system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1675system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1676system.cpu0.toL2Bus.snoop_fanout::total 34111599 # Request fanout histogram 1677system.cpu0.toL2Bus.reqLayer0.occupancy 18295414402 # Layer occupancy (ticks) 1678system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1679system.cpu0.toL2Bus.snoopLayer0.occupancy 218599021 # Layer occupancy (ticks) 1680system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1681system.cpu0.toL2Bus.respLayer0.occupancy 10163463729 # Layer occupancy (ticks) 1682system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1683system.cpu0.toL2Bus.respLayer1.occupancy 9200637125 # Layer occupancy (ticks) 1684system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1685system.cpu0.toL2Bus.respLayer2.occupancy 233049222 # Layer occupancy (ticks) 1686system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1687system.cpu0.toL2Bus.respLayer3.occupancy 729789968 # Layer occupancy (ticks) 1688system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1689system.cpu1.branchPred.lookups 123149965 # Number of BP lookups 1690system.cpu1.branchPred.condPredicted 82495484 # Number of conditional branches predicted 1691system.cpu1.branchPred.condIncorrect 5956200 # Number of conditional branches incorrect 1692system.cpu1.branchPred.BTBLookups 86779618 # Number of BTB lookups 1693system.cpu1.branchPred.BTBHits 56690061 # Number of BTB hits 1694system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1695system.cpu1.branchPred.BTBHitPct 65.326470 # BTB Hit Percentage 1696system.cpu1.branchPred.usedRAS 16440472 # Number of times the RAS was used to get a target. 1697system.cpu1.branchPred.RASInCorrect 156518 # Number of incorrect RAS predictions. 1698system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1699system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1700system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1701system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1702system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1703system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1704system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1705system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1706system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1707system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1708system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1709system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1710system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1711system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1712system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1713system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1714system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1715system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1716system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1717system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1718system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1719system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1720system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1721system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1722system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1723system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1724system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1725system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1726system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1727system.cpu1.dtb.walker.walks 527411 # Table walker walks requested 1728system.cpu1.dtb.walker.walksLong 527411 # Table walker walks initiated with long descriptors 1729system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 10595 # Level at which table walker walks with long descriptors terminate 1730system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 86487 # Level at which table walker walks with long descriptors terminate 1731system.cpu1.dtb.walker.walksSquashedBefore 240409 # Table walks squashed before starting 1732system.cpu1.dtb.walker.walkWaitTime::samples 287002 # Table walker wait (enqueue to first request) latency 1733system.cpu1.dtb.walker.walkWaitTime::mean 2359.187392 # Table walker wait (enqueue to first request) latency 1734system.cpu1.dtb.walker.walkWaitTime::stdev 14719.861354 # Table walker wait (enqueue to first request) latency 1735system.cpu1.dtb.walker.walkWaitTime::0-65535 284807 99.24% 99.24% # Table walker wait (enqueue to first request) latency 1736system.cpu1.dtb.walker.walkWaitTime::65536-131071 1123 0.39% 99.63% # Table walker wait (enqueue to first request) latency 1737system.cpu1.dtb.walker.walkWaitTime::131072-196607 785 0.27% 99.90% # Table walker wait (enqueue to first request) latency 1738system.cpu1.dtb.walker.walkWaitTime::196608-262143 158 0.06% 99.96% # Table walker wait (enqueue to first request) latency 1739system.cpu1.dtb.walker.walkWaitTime::262144-327679 41 0.01% 99.97% # Table walker wait (enqueue to first request) latency 1740system.cpu1.dtb.walker.walkWaitTime::327680-393215 63 0.02% 99.99% # Table walker wait (enqueue to first request) latency 1741system.cpu1.dtb.walker.walkWaitTime::393216-458751 20 0.01% 100.00% # Table walker wait (enqueue to first request) latency 1742system.cpu1.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1743system.cpu1.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1744system.cpu1.dtb.walker.walkWaitTime::total 287002 # Table walker wait (enqueue to first request) latency 1745system.cpu1.dtb.walker.walkCompletionTime::samples 269681 # Table walker service (enqueue to completion) latency 1746system.cpu1.dtb.walker.walkCompletionTime::mean 19234.134032 # Table walker service (enqueue to completion) latency 1747system.cpu1.dtb.walker.walkCompletionTime::gmean 15959.440473 # Table walker service (enqueue to completion) latency 1748system.cpu1.dtb.walker.walkCompletionTime::stdev 20416.372217 # Table walker service (enqueue to completion) latency 1749system.cpu1.dtb.walker.walkCompletionTime::0-65535 266977 99.00% 99.00% # Table walker service (enqueue to completion) latency 1750system.cpu1.dtb.walker.walkCompletionTime::65536-131071 731 0.27% 99.27% # Table walker service (enqueue to completion) latency 1751system.cpu1.dtb.walker.walkCompletionTime::131072-196607 1349 0.50% 99.77% # Table walker service (enqueue to completion) latency 1752system.cpu1.dtb.walker.walkCompletionTime::196608-262143 143 0.05% 99.82% # Table walker service (enqueue to completion) latency 1753system.cpu1.dtb.walker.walkCompletionTime::262144-327679 295 0.11% 99.93% # Table walker service (enqueue to completion) latency 1754system.cpu1.dtb.walker.walkCompletionTime::327680-393215 58 0.02% 99.95% # Table walker service (enqueue to completion) latency 1755system.cpu1.dtb.walker.walkCompletionTime::393216-458751 94 0.03% 99.99% # Table walker service (enqueue to completion) latency 1756system.cpu1.dtb.walker.walkCompletionTime::458752-524287 19 0.01% 99.99% # Table walker service (enqueue to completion) latency 1757system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 1758system.cpu1.dtb.walker.walkCompletionTime::589824-655359 6 0.00% 100.00% # Table walker service (enqueue to completion) latency 1759system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1760system.cpu1.dtb.walker.walkCompletionTime::786432-851967 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1761system.cpu1.dtb.walker.walkCompletionTime::851968-917503 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1762system.cpu1.dtb.walker.walkCompletionTime::total 269681 # Table walker service (enqueue to completion) latency 1763system.cpu1.dtb.walker.walksPending::samples 429707115240 # Table walker pending requests distribution 1764system.cpu1.dtb.walker.walksPending::mean 0.574612 # Table walker pending requests distribution 1765system.cpu1.dtb.walker.walksPending::stdev 0.551988 # Table walker pending requests distribution 1766system.cpu1.dtb.walker.walksPending::0-1 428613446240 99.75% 99.75% # Table walker pending requests distribution 1767system.cpu1.dtb.walker.walksPending::2-3 584261000 0.14% 99.88% # Table walker pending requests distribution 1768system.cpu1.dtb.walker.walksPending::4-5 233148000 0.05% 99.94% # Table walker pending requests distribution 1769system.cpu1.dtb.walker.walksPending::6-7 115723000 0.03% 99.96% # Table walker pending requests distribution 1770system.cpu1.dtb.walker.walksPending::8-9 78401000 0.02% 99.98% # Table walker pending requests distribution 1771system.cpu1.dtb.walker.walksPending::10-11 45162000 0.01% 99.99% # Table walker pending requests distribution 1772system.cpu1.dtb.walker.walksPending::12-13 15712000 0.00% 100.00% # Table walker pending requests distribution 1773system.cpu1.dtb.walker.walksPending::14-15 20912500 0.00% 100.00% # Table walker pending requests distribution 1774system.cpu1.dtb.walker.walksPending::16-17 347500 0.00% 100.00% # Table walker pending requests distribution 1775system.cpu1.dtb.walker.walksPending::18-19 2000 0.00% 100.00% # Table walker pending requests distribution 1776system.cpu1.dtb.walker.walksPending::total 429707115240 # Table walker pending requests distribution 1777system.cpu1.dtb.walker.walkPageSizes::4K 86487 89.09% 89.09% # Table walker page sizes translated 1778system.cpu1.dtb.walker.walkPageSizes::2M 10595 10.91% 100.00% # Table walker page sizes translated 1779system.cpu1.dtb.walker.walkPageSizes::total 97082 # Table walker page sizes translated 1780system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 527411 # Table walker requests started/completed, data/inst 1781system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1782system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 527411 # Table walker requests started/completed, data/inst 1783system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97082 # Table walker requests started/completed, data/inst 1784system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1785system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97082 # Table walker requests started/completed, data/inst 1786system.cpu1.dtb.walker.walkRequestOrigin::total 624493 # Table walker requests started/completed, data/inst 1787system.cpu1.dtb.inst_hits 0 # ITB inst hits 1788system.cpu1.dtb.inst_misses 0 # ITB inst misses 1789system.cpu1.dtb.read_hits 91393564 # DTB read hits 1790system.cpu1.dtb.read_misses 362569 # DTB read misses 1791system.cpu1.dtb.write_hits 75279430 # DTB write hits 1792system.cpu1.dtb.write_misses 164842 # DTB write misses 1793system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1794system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1795system.cpu1.dtb.flush_tlb_mva_asid 44894 # Number of times TLB was flushed by MVA & ASID 1796system.cpu1.dtb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID 1797system.cpu1.dtb.flush_entries 36642 # Number of entries that have been flushed from TLB 1798system.cpu1.dtb.align_faults 200 # Number of TLB faults due to alignment restrictions 1799system.cpu1.dtb.prefetch_faults 5827 # Number of TLB faults due to prefetch 1800system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1801system.cpu1.dtb.perms_faults 40054 # Number of TLB faults due to permissions restrictions 1802system.cpu1.dtb.read_accesses 91756133 # DTB read accesses 1803system.cpu1.dtb.write_accesses 75444272 # DTB write accesses 1804system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1805system.cpu1.dtb.hits 166672994 # DTB hits 1806system.cpu1.dtb.misses 527411 # DTB misses 1807system.cpu1.dtb.accesses 167200405 # DTB accesses 1808system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1809system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1810system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1811system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1812system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1813system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1814system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1815system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1816system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1817system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1818system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1819system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1820system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1821system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1822system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1823system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1824system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1825system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1826system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1827system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1828system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1829system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1830system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1831system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1832system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1833system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1834system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1835system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1836system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1837system.cpu1.itb.walker.walks 82282 # Table walker walks requested 1838system.cpu1.itb.walker.walksLong 82282 # Table walker walks initiated with long descriptors 1839system.cpu1.itb.walker.walksLongTerminationLevel::Level2 773 # Level at which table walker walks with long descriptors terminate 1840system.cpu1.itb.walker.walksLongTerminationLevel::Level3 59282 # Level at which table walker walks with long descriptors terminate 1841system.cpu1.itb.walker.walksSquashedBefore 9946 # Table walks squashed before starting 1842system.cpu1.itb.walker.walkWaitTime::samples 72336 # Table walker wait (enqueue to first request) latency 1843system.cpu1.itb.walker.walkWaitTime::mean 1446.824541 # Table walker wait (enqueue to first request) latency 1844system.cpu1.itb.walker.walkWaitTime::stdev 11538.500060 # Table walker wait (enqueue to first request) latency 1845system.cpu1.itb.walker.walkWaitTime::0-65535 71995 99.53% 99.53% # Table walker wait (enqueue to first request) latency 1846system.cpu1.itb.walker.walkWaitTime::65536-131071 83 0.11% 99.64% # Table walker wait (enqueue to first request) latency 1847system.cpu1.itb.walker.walkWaitTime::131072-196607 237 0.33% 99.97% # Table walker wait (enqueue to first request) latency 1848system.cpu1.itb.walker.walkWaitTime::196608-262143 12 0.02% 99.99% # Table walker wait (enqueue to first request) latency 1849system.cpu1.itb.walker.walkWaitTime::262144-327679 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency 1850system.cpu1.itb.walker.walkWaitTime::327680-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1851system.cpu1.itb.walker.walkWaitTime::393216-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1852system.cpu1.itb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1853system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1854system.cpu1.itb.walker.walkWaitTime::total 72336 # Table walker wait (enqueue to first request) latency 1855system.cpu1.itb.walker.walkCompletionTime::samples 70001 # Table walker service (enqueue to completion) latency 1856system.cpu1.itb.walker.walkCompletionTime::mean 24228.861016 # Table walker service (enqueue to completion) latency 1857system.cpu1.itb.walker.walkCompletionTime::gmean 20738.037138 # Table walker service (enqueue to completion) latency 1858system.cpu1.itb.walker.walkCompletionTime::stdev 24674.307569 # Table walker service (enqueue to completion) latency 1859system.cpu1.itb.walker.walkCompletionTime::0-65535 68717 98.17% 98.17% # Table walker service (enqueue to completion) latency 1860system.cpu1.itb.walker.walkCompletionTime::65536-131071 87 0.12% 98.29% # Table walker service (enqueue to completion) latency 1861system.cpu1.itb.walker.walkCompletionTime::131072-196607 984 1.41% 99.70% # Table walker service (enqueue to completion) latency 1862system.cpu1.itb.walker.walkCompletionTime::196608-262143 73 0.10% 99.80% # Table walker service (enqueue to completion) latency 1863system.cpu1.itb.walker.walkCompletionTime::262144-327679 83 0.12% 99.92% # Table walker service (enqueue to completion) latency 1864system.cpu1.itb.walker.walkCompletionTime::327680-393215 23 0.03% 99.95% # Table walker service (enqueue to completion) latency 1865system.cpu1.itb.walker.walkCompletionTime::393216-458751 22 0.03% 99.98% # Table walker service (enqueue to completion) latency 1866system.cpu1.itb.walker.walkCompletionTime::458752-524287 4 0.01% 99.99% # Table walker service (enqueue to completion) latency 1867system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 99.99% # Table walker service (enqueue to completion) latency 1868system.cpu1.itb.walker.walkCompletionTime::589824-655359 4 0.01% 100.00% # Table walker service (enqueue to completion) latency 1869system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1870system.cpu1.itb.walker.walkCompletionTime::917504-983039 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 1871system.cpu1.itb.walker.walkCompletionTime::total 70001 # Table walker service (enqueue to completion) latency 1872system.cpu1.itb.walker.walksPending::samples 391052327076 # Table walker pending requests distribution 1873system.cpu1.itb.walker.walksPending::mean 0.846616 # Table walker pending requests distribution 1874system.cpu1.itb.walker.walksPending::stdev 0.360520 # Table walker pending requests distribution 1875system.cpu1.itb.walker.walksPending::0 60001678208 15.34% 15.34% # Table walker pending requests distribution 1876system.cpu1.itb.walker.walksPending::1 331032470368 84.65% 100.00% # Table walker pending requests distribution 1877system.cpu1.itb.walker.walksPending::2 15971500 0.00% 100.00% # Table walker pending requests distribution 1878system.cpu1.itb.walker.walksPending::3 2073000 0.00% 100.00% # Table walker pending requests distribution 1879system.cpu1.itb.walker.walksPending::4 134000 0.00% 100.00% # Table walker pending requests distribution 1880system.cpu1.itb.walker.walksPending::total 391052327076 # Table walker pending requests distribution 1881system.cpu1.itb.walker.walkPageSizes::4K 59282 98.71% 98.71% # Table walker page sizes translated 1882system.cpu1.itb.walker.walkPageSizes::2M 773 1.29% 100.00% # Table walker page sizes translated 1883system.cpu1.itb.walker.walkPageSizes::total 60055 # Table walker page sizes translated 1884system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1885system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 82282 # Table walker requests started/completed, data/inst 1886system.cpu1.itb.walker.walkRequestOrigin_Requested::total 82282 # Table walker requests started/completed, data/inst 1887system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1888system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 60055 # Table walker requests started/completed, data/inst 1889system.cpu1.itb.walker.walkRequestOrigin_Completed::total 60055 # Table walker requests started/completed, data/inst 1890system.cpu1.itb.walker.walkRequestOrigin::total 142337 # Table walker requests started/completed, data/inst 1891system.cpu1.itb.inst_hits 193960223 # ITB inst hits 1892system.cpu1.itb.inst_misses 82282 # ITB inst misses 1893system.cpu1.itb.read_hits 0 # DTB read hits 1894system.cpu1.itb.read_misses 0 # DTB read misses 1895system.cpu1.itb.write_hits 0 # DTB write hits 1896system.cpu1.itb.write_misses 0 # DTB write misses 1897system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1898system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1899system.cpu1.itb.flush_tlb_mva_asid 44894 # Number of times TLB was flushed by MVA & ASID 1900system.cpu1.itb.flush_tlb_asid 1069 # Number of times TLB was flushed by ASID 1901system.cpu1.itb.flush_entries 26113 # Number of entries that have been flushed from TLB 1902system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1903system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1904system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1905system.cpu1.itb.perms_faults 206259 # Number of TLB faults due to permissions restrictions 1906system.cpu1.itb.read_accesses 0 # DTB read accesses 1907system.cpu1.itb.write_accesses 0 # DTB write accesses 1908system.cpu1.itb.inst_accesses 194042505 # ITB inst accesses 1909system.cpu1.itb.hits 193960223 # DTB hits 1910system.cpu1.itb.misses 82282 # DTB misses 1911system.cpu1.itb.accesses 194042505 # DTB accesses 1912system.cpu1.numCycles 680051209 # number of cpu cycles simulated 1913system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1914system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1915system.cpu1.fetch.icacheStallCycles 76309039 # Number of cycles fetch is stalled on an Icache miss 1916system.cpu1.fetch.Insts 545586843 # Number of instructions fetch has processed 1917system.cpu1.fetch.Branches 123149965 # Number of branches that fetch encountered 1918system.cpu1.fetch.predictedBranches 73130533 # Number of branches that fetch has predicted taken 1919system.cpu1.fetch.Cycles 567094976 # Number of cycles fetch has run and was not squashing or blocked 1920system.cpu1.fetch.SquashCycles 12846360 # Number of cycles fetch has spent squashing 1921system.cpu1.fetch.TlbCycles 1862646 # Number of cycles fetch has spent waiting for tlb 1922system.cpu1.fetch.MiscStallCycles 285569 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1923system.cpu1.fetch.PendingTrapStallCycles 6032568 # Number of stall cycles due to pending traps 1924system.cpu1.fetch.PendingQuiesceStallCycles 729307 # Number of stall cycles due to pending quiesce instructions 1925system.cpu1.fetch.IcacheWaitRetryStallCycles 772817 # Number of stall cycles due to full MSHR 1926system.cpu1.fetch.CacheLines 193732934 # Number of cache lines fetched 1927system.cpu1.fetch.IcacheSquashes 1488213 # Number of outstanding Icache misses that were squashed 1928system.cpu1.fetch.ItlbSquashes 27982 # Number of outstanding ITLB misses that were squashed 1929system.cpu1.fetch.rateDist::samples 659510102 # Number of instructions fetched each cycle (Total) 1930system.cpu1.fetch.rateDist::mean 0.972600 # Number of instructions fetched each cycle (Total) 1931system.cpu1.fetch.rateDist::stdev 1.218843 # Number of instructions fetched each cycle (Total) 1932system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1933system.cpu1.fetch.rateDist::0 352323655 53.42% 53.42% # Number of instructions fetched each cycle (Total) 1934system.cpu1.fetch.rateDist::1 119769188 18.16% 71.58% # Number of instructions fetched each cycle (Total) 1935system.cpu1.fetch.rateDist::2 40581175 6.15% 77.74% # Number of instructions fetched each cycle (Total) 1936system.cpu1.fetch.rateDist::3 146836084 22.26% 100.00% # Number of instructions fetched each cycle (Total) 1937system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1938system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1939system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 1940system.cpu1.fetch.rateDist::total 659510102 # Number of instructions fetched each cycle (Total) 1941system.cpu1.fetch.branchRate 0.181089 # Number of branch fetches per cycle 1942system.cpu1.fetch.rate 0.802273 # Number of inst fetches per cycle 1943system.cpu1.decode.IdleCycles 93216709 # Number of cycles decode is idle 1944system.cpu1.decode.BlockedCycles 325116567 # Number of cycles decode is blocked 1945system.cpu1.decode.RunCycles 201438015 # Number of cycles decode is running 1946system.cpu1.decode.UnblockCycles 35171632 # Number of cycles decode is unblocking 1947system.cpu1.decode.SquashCycles 4567179 # Number of cycles decode is squashing 1948system.cpu1.decode.BranchResolved 17405067 # Number of times decode resolved a branch 1949system.cpu1.decode.BranchMispred 1892222 # Number of times decode detected a branch misprediction 1950system.cpu1.decode.DecodedInsts 567399835 # Number of instructions handled by decode 1951system.cpu1.decode.SquashedInsts 20537774 # Number of squashed instructions handled by decode 1952system.cpu1.rename.SquashCycles 4567179 # Number of cycles rename is squashing 1953system.cpu1.rename.IdleCycles 125466899 # Number of cycles rename is idle 1954system.cpu1.rename.BlockCycles 47033211 # Number of cycles rename is blocking 1955system.cpu1.rename.serializeStallCycles 215743407 # count of cycles rename stalled for serializing inst 1956system.cpu1.rename.RunCycles 203915656 # Number of cycles rename is running 1957system.cpu1.rename.UnblockCycles 62783750 # Number of cycles rename is unblocking 1958system.cpu1.rename.RenamedInsts 552356795 # Number of instructions processed by rename 1959system.cpu1.rename.SquashedInsts 5241539 # Number of squashed instructions processed by rename 1960system.cpu1.rename.ROBFullEvents 9909237 # Number of times rename has blocked due to ROB full 1961system.cpu1.rename.IQFullEvents 240791 # Number of times rename has blocked due to IQ full 1962system.cpu1.rename.LQFullEvents 292344 # Number of times rename has blocked due to LQ full 1963system.cpu1.rename.SQFullEvents 29944703 # Number of times rename has blocked due to SQ full 1964system.cpu1.rename.FullRegisterEvents 11393 # Number of times there has been no free registers 1965system.cpu1.rename.RenamedOperands 524936389 # Number of destination operands rename has renamed 1966system.cpu1.rename.RenameLookups 854810992 # Number of register rename lookups that rename has made 1967system.cpu1.rename.int_rename_lookups 653637843 # Number of integer rename lookups 1968system.cpu1.rename.fp_rename_lookups 615050 # Number of floating rename lookups 1969system.cpu1.rename.CommittedMaps 473696954 # Number of HB maps that are committed 1970system.cpu1.rename.UndoneMaps 51239429 # Number of HB maps that are undone due to squashing 1971system.cpu1.rename.serializingInsts 15119385 # count of serializing insts renamed 1972system.cpu1.rename.tempSerializingInsts 13351935 # count of temporary serializing insts renamed 1973system.cpu1.rename.skidInsts 70628253 # count of insts added to the skid buffer 1974system.cpu1.memDep0.insertedLoads 91219643 # Number of loads inserted to the mem dependence unit. 1975system.cpu1.memDep0.insertedStores 78311402 # Number of stores inserted to the mem dependence unit. 1976system.cpu1.memDep0.conflictingLoads 8799360 # Number of conflicting loads. 1977system.cpu1.memDep0.conflictingStores 7480777 # Number of conflicting stores. 1978system.cpu1.iq.iqInstsAdded 531265202 # Number of instructions added to the IQ (excludes non-spec) 1979system.cpu1.iq.iqNonSpecInstsAdded 15384643 # Number of non-speculative instructions added to the IQ 1980system.cpu1.iq.iqInstsIssued 536975559 # Number of instructions issued 1981system.cpu1.iq.iqSquashedInstsIssued 2409415 # Number of squashed instructions issued 1982system.cpu1.iq.iqSquashedInstsExamined 48765571 # Number of squashed instructions iterated over during squash; mainly for profiling 1983system.cpu1.iq.iqSquashedOperandsExamined 31310459 # Number of squashed operands that are examined and possibly removed from graph 1984system.cpu1.iq.iqSquashedNonSpecRemoved 261406 # Number of squashed non-spec instructions that were removed 1985system.cpu1.iq.issued_per_cycle::samples 659510102 # Number of insts issued each cycle 1986system.cpu1.iq.issued_per_cycle::mean 0.814204 # Number of insts issued each cycle 1987system.cpu1.iq.issued_per_cycle::stdev 1.064087 # Number of insts issued each cycle 1988system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 1989system.cpu1.iq.issued_per_cycle::0 364889522 55.33% 55.33% # Number of insts issued each cycle 1990system.cpu1.iq.issued_per_cycle::1 126119203 19.12% 74.45% # Number of insts issued each cycle 1991system.cpu1.iq.issued_per_cycle::2 101926801 15.45% 89.91% # Number of insts issued each cycle 1992system.cpu1.iq.issued_per_cycle::3 59299384 8.99% 98.90% # Number of insts issued each cycle 1993system.cpu1.iq.issued_per_cycle::4 7271358 1.10% 100.00% # Number of insts issued each cycle 1994system.cpu1.iq.issued_per_cycle::5 3834 0.00% 100.00% # Number of insts issued each cycle 1995system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 1996system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 1997system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 1998system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 1999system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 2000system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 2001system.cpu1.iq.issued_per_cycle::total 659510102 # Number of insts issued each cycle 2002system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 2003system.cpu1.iq.fu_full::IntAlu 53688772 43.65% 43.65% # attempts to use FU when none available 2004system.cpu1.iq.fu_full::IntMult 42849 0.03% 43.69% # attempts to use FU when none available 2005system.cpu1.iq.fu_full::IntDiv 9758 0.01% 43.69% # attempts to use FU when none available 2006system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.69% # attempts to use FU when none available 2007system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.69% # attempts to use FU when none available 2008system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.69% # attempts to use FU when none available 2009system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.69% # attempts to use FU when none available 2010system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.69% # attempts to use FU when none available 2011system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.69% # attempts to use FU when none available 2012system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.69% # attempts to use FU when none available 2013system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.69% # attempts to use FU when none available 2014system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.69% # attempts to use FU when none available 2015system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.69% # attempts to use FU when none available 2016system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.69% # attempts to use FU when none available 2017system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.69% # attempts to use FU when none available 2018system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.69% # attempts to use FU when none available 2019system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.69% # attempts to use FU when none available 2020system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.69% # attempts to use FU when none available 2021system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.69% # attempts to use FU when none available 2022system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.69% # attempts to use FU when none available 2023system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.69% # attempts to use FU when none available 2024system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.69% # attempts to use FU when none available 2025system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.69% # attempts to use FU when none available 2026system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.69% # attempts to use FU when none available 2027system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.69% # attempts to use FU when none available 2028system.cpu1.iq.fu_full::SimdFloatMisc 12 0.00% 43.69% # attempts to use FU when none available 2029system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.69% # attempts to use FU when none available 2030system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.69% # attempts to use FU when none available 2031system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.69% # attempts to use FU when none available 2032system.cpu1.iq.fu_full::MemRead 33350405 27.12% 70.81% # attempts to use FU when none available 2033system.cpu1.iq.fu_full::MemWrite 35903096 29.19% 100.00% # attempts to use FU when none available 2034system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2035system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 2036system.cpu1.iq.FU_type_0::No_OpClass 84 0.00% 0.00% # Type of FU issued 2037system.cpu1.iq.FU_type_0::IntAlu 365127801 68.00% 68.00% # Type of FU issued 2038system.cpu1.iq.FU_type_0::IntMult 1207443 0.22% 68.22% # Type of FU issued 2039system.cpu1.iq.FU_type_0::IntDiv 64356 0.01% 68.23% # Type of FU issued 2040system.cpu1.iq.FU_type_0::FloatAdd 5 0.00% 68.23% # Type of FU issued 2041system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.23% # Type of FU issued 2042system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.23% # Type of FU issued 2043system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.23% # Type of FU issued 2044system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.23% # Type of FU issued 2045system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.23% # Type of FU issued 2046system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.23% # Type of FU issued 2047system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.23% # Type of FU issued 2048system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.23% # Type of FU issued 2049system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.23% # Type of FU issued 2050system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.23% # Type of FU issued 2051system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.23% # Type of FU issued 2052system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.23% # Type of FU issued 2053system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.23% # Type of FU issued 2054system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.23% # Type of FU issued 2055system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.23% # Type of FU issued 2056system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.23% # Type of FU issued 2057system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.23% # Type of FU issued 2058system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.23% # Type of FU issued 2059system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.23% # Type of FU issued 2060system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.23% # Type of FU issued 2061system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.23% # Type of FU issued 2062system.cpu1.iq.FU_type_0::SimdFloatMisc 40592 0.01% 68.24% # Type of FU issued 2063system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.24% # Type of FU issued 2064system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.24% # Type of FU issued 2065system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.24% # Type of FU issued 2066system.cpu1.iq.FU_type_0::MemRead 94109837 17.53% 85.77% # Type of FU issued 2067system.cpu1.iq.FU_type_0::MemWrite 76425394 14.23% 100.00% # Type of FU issued 2068system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2069system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2070system.cpu1.iq.FU_type_0::total 536975559 # Type of FU issued 2071system.cpu1.iq.rate 0.789610 # Inst issue rate 2072system.cpu1.iq.fu_busy_cnt 122994892 # FU busy when requested 2073system.cpu1.iq.fu_busy_rate 0.229051 # FU busy rate (busy events/executed inst) 2074system.cpu1.iq.int_inst_queue_reads 1857852304 # Number of integer instruction queue reads 2075system.cpu1.iq.int_inst_queue_writes 595160433 # Number of integer instruction queue writes 2076system.cpu1.iq.int_inst_queue_wakeup_accesses 521544916 # Number of integer instruction queue wakeup accesses 2077system.cpu1.iq.fp_inst_queue_reads 1013221 # Number of floating instruction queue reads 2078system.cpu1.iq.fp_inst_queue_writes 400944 # Number of floating instruction queue writes 2079system.cpu1.iq.fp_inst_queue_wakeup_accesses 372548 # Number of floating instruction queue wakeup accesses 2080system.cpu1.iq.int_alu_accesses 659338375 # Number of integer alu accesses 2081system.cpu1.iq.fp_alu_accesses 631992 # Number of floating point alu accesses 2082system.cpu1.iew.lsq.thread0.forwLoads 2462766 # Number of loads that had data forwarded from stores 2083system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2084system.cpu1.iew.lsq.thread0.squashedLoads 11273364 # Number of loads squashed 2085system.cpu1.iew.lsq.thread0.ignoredResponses 14330 # Number of memory responses ignored because the instruction is squashed 2086system.cpu1.iew.lsq.thread0.memOrderViolation 146929 # Number of memory ordering violations 2087system.cpu1.iew.lsq.thread0.squashedStores 5363484 # Number of stores squashed 2088system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2089system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2090system.cpu1.iew.lsq.thread0.rescheduledLoads 2532880 # Number of loads that were rescheduled 2091system.cpu1.iew.lsq.thread0.cacheBlocked 4046276 # Number of times an access to memory failed due to the cache being blocked 2092system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2093system.cpu1.iew.iewSquashCycles 4567179 # Number of cycles IEW is squashing 2094system.cpu1.iew.iewBlockCycles 5912411 # Number of cycles IEW is blocking 2095system.cpu1.iew.iewUnblockCycles 2185508 # Number of cycles IEW is unblocking 2096system.cpu1.iew.iewDispatchedInsts 546765447 # Number of instructions dispatched to IQ 2097system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 2098system.cpu1.iew.iewDispLoadInsts 91219643 # Number of dispatched load instructions 2099system.cpu1.iew.iewDispStoreInsts 78311402 # Number of dispatched store instructions 2100system.cpu1.iew.iewDispNonSpecInsts 13149679 # Number of dispatched non-speculative instructions 2101system.cpu1.iew.iewIQFullEvents 62909 # Number of times the IQ has become full, causing a stall 2102system.cpu1.iew.iewLSQFullEvents 2062449 # Number of times the LSQ has become full, causing a stall 2103system.cpu1.iew.memOrderViolationEvents 146929 # Number of memory order violations 2104system.cpu1.iew.predictedTakenIncorrect 1850208 # Number of branches that were predicted taken incorrectly 2105system.cpu1.iew.predictedNotTakenIncorrect 2506307 # Number of branches that were predicted not taken incorrectly 2106system.cpu1.iew.branchMispredicts 4356515 # Number of branch mispredicts detected at execute 2107system.cpu1.iew.iewExecutedInsts 530131647 # Number of executed instructions 2108system.cpu1.iew.iewExecLoadInsts 91388835 # Number of load instructions executed 2109system.cpu1.iew.iewExecSquashedInsts 6328626 # Number of squashed instructions skipped in execute 2110system.cpu1.iew.exec_swp 0 # number of swp insts executed 2111system.cpu1.iew.exec_nop 115602 # number of nop insts executed 2112system.cpu1.iew.exec_refs 166669354 # number of memory reference insts executed 2113system.cpu1.iew.exec_branches 99325061 # Number of branches executed 2114system.cpu1.iew.exec_stores 75280519 # Number of stores executed 2115system.cpu1.iew.exec_rate 0.779547 # Inst execution rate 2116system.cpu1.iew.wb_sent 522591798 # cumulative count of insts sent to commit 2117system.cpu1.iew.wb_count 521917464 # cumulative count of insts written-back 2118system.cpu1.iew.wb_producers 252132377 # num instructions producing a value 2119system.cpu1.iew.wb_consumers 413034686 # num instructions consuming a value 2120system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 2121system.cpu1.iew.wb_rate 0.767468 # insts written-back per cycle 2122system.cpu1.iew.wb_fanout 0.610439 # average fanout of values written-back 2123system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 2124system.cpu1.commit.commitSquashedInsts 42738935 # The number of squashed insts skipped by commit 2125system.cpu1.commit.commitNonSpecStalls 15123237 # The number of times commit has been forced to stall to communicate backwards 2126system.cpu1.commit.branchMispredicts 4100199 # The number of times a branch was mispredicted 2127system.cpu1.commit.committed_per_cycle::samples 651431241 # Number of insts commited each cycle 2128system.cpu1.commit.committed_per_cycle::mean 0.764293 # Number of insts commited each cycle 2129system.cpu1.commit.committed_per_cycle::stdev 1.565341 # Number of insts commited each cycle 2130system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2131system.cpu1.commit.committed_per_cycle::0 432003686 66.32% 66.32% # Number of insts commited each cycle 2132system.cpu1.commit.committed_per_cycle::1 115523895 17.73% 84.05% # Number of insts commited each cycle 2133system.cpu1.commit.committed_per_cycle::2 47761812 7.33% 91.38% # Number of insts commited each cycle 2134system.cpu1.commit.committed_per_cycle::3 15857432 2.43% 93.82% # Number of insts commited each cycle 2135system.cpu1.commit.committed_per_cycle::4 11422302 1.75% 95.57% # Number of insts commited each cycle 2136system.cpu1.commit.committed_per_cycle::5 7738049 1.19% 96.76% # Number of insts commited each cycle 2137system.cpu1.commit.committed_per_cycle::6 5451213 0.84% 97.59% # Number of insts commited each cycle 2138system.cpu1.commit.committed_per_cycle::7 3205095 0.49% 98.09% # Number of insts commited each cycle 2139system.cpu1.commit.committed_per_cycle::8 12467757 1.91% 100.00% # Number of insts commited each cycle 2140system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2141system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2142system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2143system.cpu1.commit.committed_per_cycle::total 651431241 # Number of insts commited each cycle 2144system.cpu1.commit.committedInsts 422487941 # Number of instructions committed 2145system.cpu1.commit.committedOps 497884267 # Number of ops (including micro ops) committed 2146system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 2147system.cpu1.commit.refs 152894196 # Number of memory references committed 2148system.cpu1.commit.loads 79946278 # Number of loads committed 2149system.cpu1.commit.membars 3616952 # Number of memory barriers committed 2150system.cpu1.commit.branches 94285217 # Number of branches committed 2151system.cpu1.commit.fp_insts 364520 # Number of committed floating point instructions. 2152system.cpu1.commit.int_insts 457066504 # Number of committed integer instructions. 2153system.cpu1.commit.function_calls 12254498 # Number of function calls committed. 2154system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 2155system.cpu1.commit.op_class_0::IntAlu 343931170 69.08% 69.08% # Class of committed instruction 2156system.cpu1.commit.op_class_0::IntMult 972359 0.20% 69.27% # Class of committed instruction 2157system.cpu1.commit.op_class_0::IntDiv 50623 0.01% 69.28% # Class of committed instruction 2158system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.28% # Class of committed instruction 2159system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.28% # Class of committed instruction 2160system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.28% # Class of committed instruction 2161system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.28% # Class of committed instruction 2162system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.28% # Class of committed instruction 2163system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.28% # Class of committed instruction 2164system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.28% # Class of committed instruction 2165system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.28% # Class of committed instruction 2166system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.28% # Class of committed instruction 2167system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.28% # Class of committed instruction 2168system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.28% # Class of committed instruction 2169system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.28% # Class of committed instruction 2170system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.28% # Class of committed instruction 2171system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.28% # Class of committed instruction 2172system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.28% # Class of committed instruction 2173system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.28% # Class of committed instruction 2174system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.28% # Class of committed instruction 2175system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.28% # Class of committed instruction 2176system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.28% # Class of committed instruction 2177system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.28% # Class of committed instruction 2178system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.28% # Class of committed instruction 2179system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.28% # Class of committed instruction 2180system.cpu1.commit.op_class_0::SimdFloatMisc 35877 0.01% 69.29% # Class of committed instruction 2181system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.29% # Class of committed instruction 2182system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.29% # Class of committed instruction 2183system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.29% # Class of committed instruction 2184system.cpu1.commit.op_class_0::MemRead 79946278 16.06% 85.35% # Class of committed instruction 2185system.cpu1.commit.op_class_0::MemWrite 72947918 14.65% 100.00% # Class of committed instruction 2186system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2187system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 2188system.cpu1.commit.op_class_0::total 497884267 # Class of committed instruction 2189system.cpu1.commit.bw_lim_events 12467757 # number cycles where commit BW limit reached 2190system.cpu1.rob.rob_reads 1176002301 # The number of ROB reads 2191system.cpu1.rob.rob_writes 1089287670 # The number of ROB writes 2192system.cpu1.timesIdled 891748 # Number of times that the entire CPU went into an idle state and unscheduled itself 2193system.cpu1.idleCycles 20541107 # Total number of cycles that the CPU has spent unscheduled due to idling 2194system.cpu1.quiesceCycles 94110305176 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2195system.cpu1.committedInsts 422487941 # Number of Instructions Simulated 2196system.cpu1.committedOps 497884267 # Number of Ops (including micro ops) Simulated 2197system.cpu1.cpi 1.609635 # CPI: Cycles Per Instruction 2198system.cpu1.cpi_total 1.609635 # CPI: Total CPI of All Threads 2199system.cpu1.ipc 0.621259 # IPC: Instructions Per Cycle 2200system.cpu1.ipc_total 0.621259 # IPC: Total IPC of All Threads 2201system.cpu1.int_regfile_reads 627139214 # number of integer regfile reads 2202system.cpu1.int_regfile_writes 370414988 # number of integer regfile writes 2203system.cpu1.fp_regfile_reads 604419 # number of floating regfile reads 2204system.cpu1.fp_regfile_writes 299356 # number of floating regfile writes 2205system.cpu1.cc_regfile_reads 113711382 # number of cc regfile reads 2206system.cpu1.cc_regfile_writes 114470989 # number of cc regfile writes 2207system.cpu1.misc_regfile_reads 1170516156 # number of misc regfile reads 2208system.cpu1.misc_regfile_writes 15242864 # number of misc regfile writes 2209system.cpu1.dcache.tags.replacements 5157965 # number of replacements 2210system.cpu1.dcache.tags.tagsinuse 429.133488 # Cycle average of tags in use 2211system.cpu1.dcache.tags.total_refs 142089244 # Total number of references to valid blocks. 2212system.cpu1.dcache.tags.sampled_refs 5158477 # Sample count of references to valid blocks. 2213system.cpu1.dcache.tags.avg_refs 27.544805 # Average number of references to valid blocks. 2214system.cpu1.dcache.tags.warmup_cycle 8487531137500 # Cycle when the warmup percentage was hit. 2215system.cpu1.dcache.tags.occ_blocks::cpu1.data 429.133488 # Average occupied blocks per requestor 2216system.cpu1.dcache.tags.occ_percent::cpu1.data 0.838151 # Average percentage of cache occupancy 2217system.cpu1.dcache.tags.occ_percent::total 0.838151 # Average percentage of cache occupancy 2218system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2219system.cpu1.dcache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id 2220system.cpu1.dcache.tags.age_task_id_blocks_1024::1 378 # Occupied blocks per task id 2221system.cpu1.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id 2222system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2223system.cpu1.dcache.tags.tag_accesses 317144363 # Number of tag accesses 2224system.cpu1.dcache.tags.data_accesses 317144363 # Number of data accesses 2225system.cpu1.dcache.ReadReq_hits::cpu1.data 74103111 # number of ReadReq hits 2226system.cpu1.dcache.ReadReq_hits::total 74103111 # number of ReadReq hits 2227system.cpu1.dcache.WriteReq_hits::cpu1.data 63551574 # number of WriteReq hits 2228system.cpu1.dcache.WriteReq_hits::total 63551574 # number of WriteReq hits 2229system.cpu1.dcache.SoftPFReq_hits::cpu1.data 164336 # number of SoftPFReq hits 2230system.cpu1.dcache.SoftPFReq_hits::total 164336 # number of SoftPFReq hits 2231system.cpu1.dcache.WriteLineReq_hits::cpu1.data 50299 # number of WriteLineReq hits 2232system.cpu1.dcache.WriteLineReq_hits::total 50299 # number of WriteLineReq hits 2233system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1740316 # number of LoadLockedReq hits 2234system.cpu1.dcache.LoadLockedReq_hits::total 1740316 # number of LoadLockedReq hits 2235system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1762571 # number of StoreCondReq hits 2236system.cpu1.dcache.StoreCondReq_hits::total 1762571 # number of StoreCondReq hits 2237system.cpu1.dcache.demand_hits::cpu1.data 137654685 # number of demand (read+write) hits 2238system.cpu1.dcache.demand_hits::total 137654685 # number of demand (read+write) hits 2239system.cpu1.dcache.overall_hits::cpu1.data 137819021 # number of overall hits 2240system.cpu1.dcache.overall_hits::total 137819021 # number of overall hits 2241system.cpu1.dcache.ReadReq_misses::cpu1.data 6065944 # number of ReadReq misses 2242system.cpu1.dcache.ReadReq_misses::total 6065944 # number of ReadReq misses 2243system.cpu1.dcache.WriteReq_misses::cpu1.data 6987777 # number of WriteReq misses 2244system.cpu1.dcache.WriteReq_misses::total 6987777 # number of WriteReq misses 2245system.cpu1.dcache.SoftPFReq_misses::cpu1.data 664365 # number of SoftPFReq misses 2246system.cpu1.dcache.SoftPFReq_misses::total 664365 # number of SoftPFReq misses 2247system.cpu1.dcache.WriteLineReq_misses::cpu1.data 405961 # number of WriteLineReq misses 2248system.cpu1.dcache.WriteLineReq_misses::total 405961 # number of WriteLineReq misses 2249system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 258244 # number of LoadLockedReq misses 2250system.cpu1.dcache.LoadLockedReq_misses::total 258244 # number of LoadLockedReq misses 2251system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193910 # number of StoreCondReq misses 2252system.cpu1.dcache.StoreCondReq_misses::total 193910 # number of StoreCondReq misses 2253system.cpu1.dcache.demand_misses::cpu1.data 13053721 # number of demand (read+write) misses 2254system.cpu1.dcache.demand_misses::total 13053721 # number of demand (read+write) misses 2255system.cpu1.dcache.overall_misses::cpu1.data 13718086 # number of overall misses 2256system.cpu1.dcache.overall_misses::total 13718086 # number of overall misses 2257system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 97739183000 # number of ReadReq miss cycles 2258system.cpu1.dcache.ReadReq_miss_latency::total 97739183000 # number of ReadReq miss cycles 2259system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 145756860728 # number of WriteReq miss cycles 2260system.cpu1.dcache.WriteReq_miss_latency::total 145756860728 # number of WriteReq miss cycles 2261system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 16103531712 # number of WriteLineReq miss cycles 2262system.cpu1.dcache.WriteLineReq_miss_latency::total 16103531712 # number of WriteLineReq miss cycles 2263system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 4003848500 # number of LoadLockedReq miss cycles 2264system.cpu1.dcache.LoadLockedReq_miss_latency::total 4003848500 # number of LoadLockedReq miss cycles 2265system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4624613000 # number of StoreCondReq miss cycles 2266system.cpu1.dcache.StoreCondReq_miss_latency::total 4624613000 # number of StoreCondReq miss cycles 2267system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 5341000 # number of StoreCondFailReq miss cycles 2268system.cpu1.dcache.StoreCondFailReq_miss_latency::total 5341000 # number of StoreCondFailReq miss cycles 2269system.cpu1.dcache.demand_miss_latency::cpu1.data 243496043728 # number of demand (read+write) miss cycles 2270system.cpu1.dcache.demand_miss_latency::total 243496043728 # number of demand (read+write) miss cycles 2271system.cpu1.dcache.overall_miss_latency::cpu1.data 243496043728 # number of overall miss cycles 2272system.cpu1.dcache.overall_miss_latency::total 243496043728 # number of overall miss cycles 2273system.cpu1.dcache.ReadReq_accesses::cpu1.data 80169055 # number of ReadReq accesses(hits+misses) 2274system.cpu1.dcache.ReadReq_accesses::total 80169055 # number of ReadReq accesses(hits+misses) 2275system.cpu1.dcache.WriteReq_accesses::cpu1.data 70539351 # number of WriteReq accesses(hits+misses) 2276system.cpu1.dcache.WriteReq_accesses::total 70539351 # number of WriteReq accesses(hits+misses) 2277system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 828701 # number of SoftPFReq accesses(hits+misses) 2278system.cpu1.dcache.SoftPFReq_accesses::total 828701 # number of SoftPFReq accesses(hits+misses) 2279system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 456260 # number of WriteLineReq accesses(hits+misses) 2280system.cpu1.dcache.WriteLineReq_accesses::total 456260 # number of WriteLineReq accesses(hits+misses) 2281system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1998560 # number of LoadLockedReq accesses(hits+misses) 2282system.cpu1.dcache.LoadLockedReq_accesses::total 1998560 # number of LoadLockedReq accesses(hits+misses) 2283system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1956481 # number of StoreCondReq accesses(hits+misses) 2284system.cpu1.dcache.StoreCondReq_accesses::total 1956481 # number of StoreCondReq accesses(hits+misses) 2285system.cpu1.dcache.demand_accesses::cpu1.data 150708406 # number of demand (read+write) accesses 2286system.cpu1.dcache.demand_accesses::total 150708406 # number of demand (read+write) accesses 2287system.cpu1.dcache.overall_accesses::cpu1.data 151537107 # number of overall (read+write) accesses 2288system.cpu1.dcache.overall_accesses::total 151537107 # number of overall (read+write) accesses 2289system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.075664 # miss rate for ReadReq accesses 2290system.cpu1.dcache.ReadReq_miss_rate::total 0.075664 # miss rate for ReadReq accesses 2291system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.099062 # miss rate for WriteReq accesses 2292system.cpu1.dcache.WriteReq_miss_rate::total 0.099062 # miss rate for WriteReq accesses 2293system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.801694 # miss rate for SoftPFReq accesses 2294system.cpu1.dcache.SoftPFReq_miss_rate::total 0.801694 # miss rate for SoftPFReq accesses 2295system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.889758 # miss rate for WriteLineReq accesses 2296system.cpu1.dcache.WriteLineReq_miss_rate::total 0.889758 # miss rate for WriteLineReq accesses 2297system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.129215 # miss rate for LoadLockedReq accesses 2298system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.129215 # miss rate for LoadLockedReq accesses 2299system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.099112 # miss rate for StoreCondReq accesses 2300system.cpu1.dcache.StoreCondReq_miss_rate::total 0.099112 # miss rate for StoreCondReq accesses 2301system.cpu1.dcache.demand_miss_rate::cpu1.data 0.086616 # miss rate for demand accesses 2302system.cpu1.dcache.demand_miss_rate::total 0.086616 # miss rate for demand accesses 2303system.cpu1.dcache.overall_miss_rate::cpu1.data 0.090526 # miss rate for overall accesses 2304system.cpu1.dcache.overall_miss_rate::total 0.090526 # miss rate for overall accesses 2305system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16112.773708 # average ReadReq miss latency 2306system.cpu1.dcache.ReadReq_avg_miss_latency::total 16112.773708 # average ReadReq miss latency 2307system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20858.831174 # average WriteReq miss latency 2308system.cpu1.dcache.WriteReq_avg_miss_latency::total 20858.831174 # average WriteReq miss latency 2309system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 39667.681654 # average WriteLineReq miss latency 2310system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 39667.681654 # average WriteLineReq miss latency 2311system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15504.129815 # average LoadLockedReq miss latency 2312system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15504.129815 # average LoadLockedReq miss latency 2313system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23849.275437 # average StoreCondReq miss latency 2314system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23849.275437 # average StoreCondReq miss latency 2315system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2316system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 2317system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18653.381954 # average overall miss latency 2318system.cpu1.dcache.demand_avg_miss_latency::total 18653.381954 # average overall miss latency 2319system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17750.001256 # average overall miss latency 2320system.cpu1.dcache.overall_avg_miss_latency::total 17750.001256 # average overall miss latency 2321system.cpu1.dcache.blocked_cycles::no_mshrs 4190229 # number of cycles access was blocked 2322system.cpu1.dcache.blocked_cycles::no_targets 23645788 # number of cycles access was blocked 2323system.cpu1.dcache.blocked::no_mshrs 332306 # number of cycles access was blocked 2324system.cpu1.dcache.blocked::no_targets 708476 # number of cycles access was blocked 2325system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12.609550 # average number of cycles each access was blocked 2326system.cpu1.dcache.avg_blocked_cycles::no_targets 33.375567 # average number of cycles each access was blocked 2327system.cpu1.dcache.fast_writes 0 # number of fast writes performed 2328system.cpu1.dcache.cache_copies 0 # number of cache copies performed 2329system.cpu1.dcache.writebacks::writebacks 3362559 # number of writebacks 2330system.cpu1.dcache.writebacks::total 3362559 # number of writebacks 2331system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3121386 # number of ReadReq MSHR hits 2332system.cpu1.dcache.ReadReq_mshr_hits::total 3121386 # number of ReadReq MSHR hits 2333system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5664444 # number of WriteReq MSHR hits 2334system.cpu1.dcache.WriteReq_mshr_hits::total 5664444 # number of WriteReq MSHR hits 2335system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3068 # number of WriteLineReq MSHR hits 2336system.cpu1.dcache.WriteLineReq_mshr_hits::total 3068 # number of WriteLineReq MSHR hits 2337system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 133009 # number of LoadLockedReq MSHR hits 2338system.cpu1.dcache.LoadLockedReq_mshr_hits::total 133009 # number of LoadLockedReq MSHR hits 2339system.cpu1.dcache.demand_mshr_hits::cpu1.data 8785830 # number of demand (read+write) MSHR hits 2340system.cpu1.dcache.demand_mshr_hits::total 8785830 # number of demand (read+write) MSHR hits 2341system.cpu1.dcache.overall_mshr_hits::cpu1.data 8785830 # number of overall MSHR hits 2342system.cpu1.dcache.overall_mshr_hits::total 8785830 # number of overall MSHR hits 2343system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2944558 # number of ReadReq MSHR misses 2344system.cpu1.dcache.ReadReq_mshr_misses::total 2944558 # number of ReadReq MSHR misses 2345system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1323333 # number of WriteReq MSHR misses 2346system.cpu1.dcache.WriteReq_mshr_misses::total 1323333 # number of WriteReq MSHR misses 2347system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 664291 # number of SoftPFReq MSHR misses 2348system.cpu1.dcache.SoftPFReq_mshr_misses::total 664291 # number of SoftPFReq MSHR misses 2349system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 402893 # number of WriteLineReq MSHR misses 2350system.cpu1.dcache.WriteLineReq_mshr_misses::total 402893 # number of WriteLineReq MSHR misses 2351system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 125235 # number of LoadLockedReq MSHR misses 2352system.cpu1.dcache.LoadLockedReq_mshr_misses::total 125235 # number of LoadLockedReq MSHR misses 2353system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193904 # number of StoreCondReq MSHR misses 2354system.cpu1.dcache.StoreCondReq_mshr_misses::total 193904 # number of StoreCondReq MSHR misses 2355system.cpu1.dcache.demand_mshr_misses::cpu1.data 4267891 # number of demand (read+write) MSHR misses 2356system.cpu1.dcache.demand_mshr_misses::total 4267891 # number of demand (read+write) MSHR misses 2357system.cpu1.dcache.overall_mshr_misses::cpu1.data 4932182 # number of overall MSHR misses 2358system.cpu1.dcache.overall_mshr_misses::total 4932182 # number of overall MSHR misses 2359system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5159 # number of ReadReq MSHR uncacheable 2360system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5159 # number of ReadReq MSHR uncacheable 2361system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 4882 # number of WriteReq MSHR uncacheable 2362system.cpu1.dcache.WriteReq_mshr_uncacheable::total 4882 # number of WriteReq MSHR uncacheable 2363system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10041 # number of overall MSHR uncacheable misses 2364system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10041 # number of overall MSHR uncacheable misses 2365system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 44629208000 # number of ReadReq MSHR miss cycles 2366system.cpu1.dcache.ReadReq_mshr_miss_latency::total 44629208000 # number of ReadReq MSHR miss cycles 2367system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 29351732295 # number of WriteReq MSHR miss cycles 2368system.cpu1.dcache.WriteReq_mshr_miss_latency::total 29351732295 # number of WriteReq MSHR miss cycles 2369system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15227596000 # number of SoftPFReq MSHR miss cycles 2370system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15227596000 # number of SoftPFReq MSHR miss cycles 2371system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 15536076712 # number of WriteLineReq MSHR miss cycles 2372system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 15536076712 # number of WriteLineReq MSHR miss cycles 2373system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1817525500 # number of LoadLockedReq MSHR miss cycles 2374system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1817525500 # number of LoadLockedReq MSHR miss cycles 2375system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4430771000 # number of StoreCondReq MSHR miss cycles 2376system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4430771000 # number of StoreCondReq MSHR miss cycles 2377system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5279000 # number of StoreCondFailReq MSHR miss cycles 2378system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5279000 # number of StoreCondFailReq MSHR miss cycles 2379system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 73980940295 # number of demand (read+write) MSHR miss cycles 2380system.cpu1.dcache.demand_mshr_miss_latency::total 73980940295 # number of demand (read+write) MSHR miss cycles 2381system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 89208536295 # number of overall MSHR miss cycles 2382system.cpu1.dcache.overall_mshr_miss_latency::total 89208536295 # number of overall MSHR miss cycles 2383system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 520581000 # number of ReadReq MSHR uncacheable cycles 2384system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 520581000 # number of ReadReq MSHR uncacheable cycles 2385system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 549653500 # number of WriteReq MSHR uncacheable cycles 2386system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 549653500 # number of WriteReq MSHR uncacheable cycles 2387system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1070234500 # number of overall MSHR uncacheable cycles 2388system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1070234500 # number of overall MSHR uncacheable cycles 2389system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036729 # mshr miss rate for ReadReq accesses 2390system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036729 # mshr miss rate for ReadReq accesses 2391system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018760 # mshr miss rate for WriteReq accesses 2392system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018760 # mshr miss rate for WriteReq accesses 2393system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.801605 # mshr miss rate for SoftPFReq accesses 2394system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.801605 # mshr miss rate for SoftPFReq accesses 2395system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.883034 # mshr miss rate for WriteLineReq accesses 2396system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.883034 # mshr miss rate for WriteLineReq accesses 2397system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.062663 # mshr miss rate for LoadLockedReq accesses 2398system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.062663 # mshr miss rate for LoadLockedReq accesses 2399system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.099109 # mshr miss rate for StoreCondReq accesses 2400system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.099109 # mshr miss rate for StoreCondReq accesses 2401system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028319 # mshr miss rate for demand accesses 2402system.cpu1.dcache.demand_mshr_miss_rate::total 0.028319 # mshr miss rate for demand accesses 2403system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032548 # mshr miss rate for overall accesses 2404system.cpu1.dcache.overall_mshr_miss_rate::total 0.032548 # mshr miss rate for overall accesses 2405system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15156.504983 # average ReadReq mshr miss latency 2406system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15156.504983 # average ReadReq mshr miss latency 2407system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22180.155936 # average WriteReq mshr miss latency 2408system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22180.155936 # average WriteReq mshr miss latency 2409system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 22923.080397 # average SoftPFReq mshr miss latency 2410system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 22923.080397 # average SoftPFReq mshr miss latency 2411system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 38561.297198 # average WriteLineReq mshr miss latency 2412system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 38561.297198 # average WriteLineReq mshr miss latency 2413system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14512.919711 # average LoadLockedReq mshr miss latency 2414system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14512.919711 # average LoadLockedReq mshr miss latency 2415system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22850.333155 # average StoreCondReq mshr miss latency 2416system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22850.333155 # average StoreCondReq mshr miss latency 2417system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2418system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 2419system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17334.308748 # average overall mshr miss latency 2420system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17334.308748 # average overall mshr miss latency 2421system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18087.032533 # average overall mshr miss latency 2422system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18087.032533 # average overall mshr miss latency 2423system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 100907.346385 # average ReadReq mshr uncacheable latency 2424system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 100907.346385 # average ReadReq mshr uncacheable latency 2425system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 112587.771405 # average WriteReq mshr uncacheable latency 2426system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 112587.771405 # average WriteReq mshr uncacheable latency 2427system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 106586.445573 # average overall mshr uncacheable latency 2428system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 106586.445573 # average overall mshr uncacheable latency 2429system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 2430system.cpu1.icache.tags.replacements 5202817 # number of replacements 2431system.cpu1.icache.tags.tagsinuse 501.771617 # Cycle average of tags in use 2432system.cpu1.icache.tags.total_refs 188211208 # Total number of references to valid blocks. 2433system.cpu1.icache.tags.sampled_refs 5203329 # Sample count of references to valid blocks. 2434system.cpu1.icache.tags.avg_refs 36.171306 # Average number of references to valid blocks. 2435system.cpu1.icache.tags.warmup_cycle 8527218243000 # Cycle when the warmup percentage was hit. 2436system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.771617 # Average occupied blocks per requestor 2437system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980023 # Average percentage of cache occupancy 2438system.cpu1.icache.tags.occ_percent::total 0.980023 # Average percentage of cache occupancy 2439system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2440system.cpu1.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id 2441system.cpu1.icache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id 2442system.cpu1.icache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id 2443system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2444system.cpu1.icache.tags.tag_accesses 392655056 # Number of tag accesses 2445system.cpu1.icache.tags.data_accesses 392655056 # Number of data accesses 2446system.cpu1.icache.ReadReq_hits::cpu1.inst 188211208 # number of ReadReq hits 2447system.cpu1.icache.ReadReq_hits::total 188211208 # number of ReadReq hits 2448system.cpu1.icache.demand_hits::cpu1.inst 188211208 # number of demand (read+write) hits 2449system.cpu1.icache.demand_hits::total 188211208 # number of demand (read+write) hits 2450system.cpu1.icache.overall_hits::cpu1.inst 188211208 # number of overall hits 2451system.cpu1.icache.overall_hits::total 188211208 # number of overall hits 2452system.cpu1.icache.ReadReq_misses::cpu1.inst 5514651 # number of ReadReq misses 2453system.cpu1.icache.ReadReq_misses::total 5514651 # number of ReadReq misses 2454system.cpu1.icache.demand_misses::cpu1.inst 5514651 # number of demand (read+write) misses 2455system.cpu1.icache.demand_misses::total 5514651 # number of demand (read+write) misses 2456system.cpu1.icache.overall_misses::cpu1.inst 5514651 # number of overall misses 2457system.cpu1.icache.overall_misses::total 5514651 # number of overall misses 2458system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 61642094935 # number of ReadReq miss cycles 2459system.cpu1.icache.ReadReq_miss_latency::total 61642094935 # number of ReadReq miss cycles 2460system.cpu1.icache.demand_miss_latency::cpu1.inst 61642094935 # number of demand (read+write) miss cycles 2461system.cpu1.icache.demand_miss_latency::total 61642094935 # number of demand (read+write) miss cycles 2462system.cpu1.icache.overall_miss_latency::cpu1.inst 61642094935 # number of overall miss cycles 2463system.cpu1.icache.overall_miss_latency::total 61642094935 # number of overall miss cycles 2464system.cpu1.icache.ReadReq_accesses::cpu1.inst 193725859 # number of ReadReq accesses(hits+misses) 2465system.cpu1.icache.ReadReq_accesses::total 193725859 # number of ReadReq accesses(hits+misses) 2466system.cpu1.icache.demand_accesses::cpu1.inst 193725859 # number of demand (read+write) accesses 2467system.cpu1.icache.demand_accesses::total 193725859 # number of demand (read+write) accesses 2468system.cpu1.icache.overall_accesses::cpu1.inst 193725859 # number of overall (read+write) accesses 2469system.cpu1.icache.overall_accesses::total 193725859 # number of overall (read+write) accesses 2470system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.028466 # miss rate for ReadReq accesses 2471system.cpu1.icache.ReadReq_miss_rate::total 0.028466 # miss rate for ReadReq accesses 2472system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028466 # miss rate for demand accesses 2473system.cpu1.icache.demand_miss_rate::total 0.028466 # miss rate for demand accesses 2474system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028466 # miss rate for overall accesses 2475system.cpu1.icache.overall_miss_rate::total 0.028466 # miss rate for overall accesses 2476system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11177.877790 # average ReadReq miss latency 2477system.cpu1.icache.ReadReq_avg_miss_latency::total 11177.877790 # average ReadReq miss latency 2478system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11177.877790 # average overall miss latency 2479system.cpu1.icache.demand_avg_miss_latency::total 11177.877790 # average overall miss latency 2480system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11177.877790 # average overall miss latency 2481system.cpu1.icache.overall_avg_miss_latency::total 11177.877790 # average overall miss latency 2482system.cpu1.icache.blocked_cycles::no_mshrs 9398442 # number of cycles access was blocked 2483system.cpu1.icache.blocked_cycles::no_targets 360 # number of cycles access was blocked 2484system.cpu1.icache.blocked::no_mshrs 665033 # number of cycles access was blocked 2485system.cpu1.icache.blocked::no_targets 6 # number of cycles access was blocked 2486system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.132294 # average number of cycles each access was blocked 2487system.cpu1.icache.avg_blocked_cycles::no_targets 60 # average number of cycles each access was blocked 2488system.cpu1.icache.fast_writes 0 # number of fast writes performed 2489system.cpu1.icache.cache_copies 0 # number of cache copies performed 2490system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 311313 # number of ReadReq MSHR hits 2491system.cpu1.icache.ReadReq_mshr_hits::total 311313 # number of ReadReq MSHR hits 2492system.cpu1.icache.demand_mshr_hits::cpu1.inst 311313 # number of demand (read+write) MSHR hits 2493system.cpu1.icache.demand_mshr_hits::total 311313 # number of demand (read+write) MSHR hits 2494system.cpu1.icache.overall_mshr_hits::cpu1.inst 311313 # number of overall MSHR hits 2495system.cpu1.icache.overall_mshr_hits::total 311313 # number of overall MSHR hits 2496system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5203338 # number of ReadReq MSHR misses 2497system.cpu1.icache.ReadReq_mshr_misses::total 5203338 # number of ReadReq MSHR misses 2498system.cpu1.icache.demand_mshr_misses::cpu1.inst 5203338 # number of demand (read+write) MSHR misses 2499system.cpu1.icache.demand_mshr_misses::total 5203338 # number of demand (read+write) MSHR misses 2500system.cpu1.icache.overall_mshr_misses::cpu1.inst 5203338 # number of overall MSHR misses 2501system.cpu1.icache.overall_mshr_misses::total 5203338 # number of overall MSHR misses 2502system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 2503system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable 2504system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 2505system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses 2506system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 55550609345 # number of ReadReq MSHR miss cycles 2507system.cpu1.icache.ReadReq_mshr_miss_latency::total 55550609345 # number of ReadReq MSHR miss cycles 2508system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 55550609345 # number of demand (read+write) MSHR miss cycles 2509system.cpu1.icache.demand_mshr_miss_latency::total 55550609345 # number of demand (read+write) MSHR miss cycles 2510system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 55550609345 # number of overall MSHR miss cycles 2511system.cpu1.icache.overall_mshr_miss_latency::total 55550609345 # number of overall MSHR miss cycles 2512system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8907998 # number of ReadReq MSHR uncacheable cycles 2513system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8907998 # number of ReadReq MSHR uncacheable cycles 2514system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8907998 # number of overall MSHR uncacheable cycles 2515system.cpu1.icache.overall_mshr_uncacheable_latency::total 8907998 # number of overall MSHR uncacheable cycles 2516system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.026859 # mshr miss rate for ReadReq accesses 2517system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.026859 # mshr miss rate for ReadReq accesses 2518system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.026859 # mshr miss rate for demand accesses 2519system.cpu1.icache.demand_mshr_miss_rate::total 0.026859 # mshr miss rate for demand accesses 2520system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.026859 # mshr miss rate for overall accesses 2521system.cpu1.icache.overall_mshr_miss_rate::total 0.026859 # mshr miss rate for overall accesses 2522system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10675.956347 # average ReadReq mshr miss latency 2523system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10675.956347 # average ReadReq mshr miss latency 2524system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10675.956347 # average overall mshr miss latency 2525system.cpu1.icache.demand_avg_mshr_miss_latency::total 10675.956347 # average overall mshr miss latency 2526system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10675.956347 # average overall mshr miss latency 2527system.cpu1.icache.overall_avg_mshr_miss_latency::total 10675.956347 # average overall mshr miss latency 2528system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 132955.194030 # average ReadReq mshr uncacheable latency 2529system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 132955.194030 # average ReadReq mshr uncacheable latency 2530system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 132955.194030 # average overall mshr uncacheable latency 2531system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 132955.194030 # average overall mshr uncacheable latency 2532system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 2533system.cpu1.l2cache.prefetcher.num_hwpf_issued 7284852 # number of hwpf issued 2534system.cpu1.l2cache.prefetcher.pfIdentified 7288644 # number of prefetch candidates identified 2535system.cpu1.l2cache.prefetcher.pfBufferHit 3499 # number of redundant prefetches already in prefetch queue 2536system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2537system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 2538system.cpu1.l2cache.prefetcher.pfSpanPage 858524 # number of prefetches not generated due to page crossing 2539system.cpu1.l2cache.tags.replacements 2147738 # number of replacements 2540system.cpu1.l2cache.tags.tagsinuse 13168.263726 # Cycle average of tags in use 2541system.cpu1.l2cache.tags.total_refs 17929780 # Total number of references to valid blocks. 2542system.cpu1.l2cache.tags.sampled_refs 2163721 # Sample count of references to valid blocks. 2543system.cpu1.l2cache.tags.avg_refs 8.286549 # Average number of references to valid blocks. 2544system.cpu1.l2cache.tags.warmup_cycle 10234175062500 # Cycle when the warmup percentage was hit. 2545system.cpu1.l2cache.tags.occ_blocks::writebacks 5935.884902 # Average occupied blocks per requestor 2546system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 83.839548 # Average occupied blocks per requestor 2547system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 89.493119 # Average occupied blocks per requestor 2548system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2981.742674 # Average occupied blocks per requestor 2549system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3164.985598 # Average occupied blocks per requestor 2550system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 912.317885 # Average occupied blocks per requestor 2551system.cpu1.l2cache.tags.occ_percent::writebacks 0.362298 # Average percentage of cache occupancy 2552system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.005117 # Average percentage of cache occupancy 2553system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005462 # Average percentage of cache occupancy 2554system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.181991 # Average percentage of cache occupancy 2555system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.193175 # Average percentage of cache occupancy 2556system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.055683 # Average percentage of cache occupancy 2557system.cpu1.l2cache.tags.occ_percent::total 0.803727 # Average percentage of cache occupancy 2558system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1279 # Occupied blocks per task id 2559system.cpu1.l2cache.tags.occ_task_id_blocks::1023 76 # Occupied blocks per task id 2560system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14628 # Occupied blocks per task id 2561system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 14 # Occupied blocks per task id 2562system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 228 # Occupied blocks per task id 2563system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 605 # Occupied blocks per task id 2564system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 432 # Occupied blocks per task id 2565system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 36 # Occupied blocks per task id 2566system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 24 # Occupied blocks per task id 2567system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id 2568system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id 2569system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1303 # Occupied blocks per task id 2570system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5317 # Occupied blocks per task id 2571system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4591 # Occupied blocks per task id 2572system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3288 # Occupied blocks per task id 2573system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.078064 # Percentage of cache occupancy per task id 2574system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004639 # Percentage of cache occupancy per task id 2575system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.892822 # Percentage of cache occupancy per task id 2576system.cpu1.l2cache.tags.tag_accesses 355115319 # Number of tag accesses 2577system.cpu1.l2cache.tags.data_accesses 355115319 # Number of data accesses 2578system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 503903 # number of ReadReq hits 2579system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 170407 # number of ReadReq hits 2580system.cpu1.l2cache.ReadReq_hits::total 674310 # number of ReadReq hits 2581system.cpu1.l2cache.Writeback_hits::writebacks 3362546 # number of Writeback hits 2582system.cpu1.l2cache.Writeback_hits::total 3362546 # number of Writeback hits 2583system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 76168 # number of UpgradeReq hits 2584system.cpu1.l2cache.UpgradeReq_hits::total 76168 # number of UpgradeReq hits 2585system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 33807 # number of SCUpgradeReq hits 2586system.cpu1.l2cache.SCUpgradeReq_hits::total 33807 # number of SCUpgradeReq hits 2587system.cpu1.l2cache.ReadExReq_hits::cpu1.data 827137 # number of ReadExReq hits 2588system.cpu1.l2cache.ReadExReq_hits::total 827137 # number of ReadExReq hits 2589system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 4627973 # number of ReadCleanReq hits 2590system.cpu1.l2cache.ReadCleanReq_hits::total 4627973 # number of ReadCleanReq hits 2591system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2745456 # number of ReadSharedReq hits 2592system.cpu1.l2cache.ReadSharedReq_hits::total 2745456 # number of ReadSharedReq hits 2593system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 178495 # number of InvalidateReq hits 2594system.cpu1.l2cache.InvalidateReq_hits::total 178495 # number of InvalidateReq hits 2595system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 503903 # number of demand (read+write) hits 2596system.cpu1.l2cache.demand_hits::cpu1.itb.walker 170407 # number of demand (read+write) hits 2597system.cpu1.l2cache.demand_hits::cpu1.inst 4627973 # number of demand (read+write) hits 2598system.cpu1.l2cache.demand_hits::cpu1.data 3572593 # number of demand (read+write) hits 2599system.cpu1.l2cache.demand_hits::total 8874876 # number of demand (read+write) hits 2600system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 503903 # number of overall hits 2601system.cpu1.l2cache.overall_hits::cpu1.itb.walker 170407 # number of overall hits 2602system.cpu1.l2cache.overall_hits::cpu1.inst 4627973 # number of overall hits 2603system.cpu1.l2cache.overall_hits::cpu1.data 3572593 # number of overall hits 2604system.cpu1.l2cache.overall_hits::total 8874876 # number of overall hits 2605system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 11662 # number of ReadReq misses 2606system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8601 # number of ReadReq misses 2607system.cpu1.l2cache.ReadReq_misses::total 20263 # number of ReadReq misses 2608system.cpu1.l2cache.Writeback_misses::writebacks 12 # number of Writeback misses 2609system.cpu1.l2cache.Writeback_misses::total 12 # number of Writeback misses 2610system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 140170 # number of UpgradeReq misses 2611system.cpu1.l2cache.UpgradeReq_misses::total 140170 # number of UpgradeReq misses 2612system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 160091 # number of SCUpgradeReq misses 2613system.cpu1.l2cache.SCUpgradeReq_misses::total 160091 # number of SCUpgradeReq misses 2614system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses 2615system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses 2616system.cpu1.l2cache.ReadExReq_misses::cpu1.data 288732 # number of ReadExReq misses 2617system.cpu1.l2cache.ReadExReq_misses::total 288732 # number of ReadExReq misses 2618system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 575353 # number of ReadCleanReq misses 2619system.cpu1.l2cache.ReadCleanReq_misses::total 575353 # number of ReadCleanReq misses 2620system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 984374 # number of ReadSharedReq misses 2621system.cpu1.l2cache.ReadSharedReq_misses::total 984374 # number of ReadSharedReq misses 2622system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 223283 # number of InvalidateReq misses 2623system.cpu1.l2cache.InvalidateReq_misses::total 223283 # number of InvalidateReq misses 2624system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 11662 # number of demand (read+write) misses 2625system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8601 # number of demand (read+write) misses 2626system.cpu1.l2cache.demand_misses::cpu1.inst 575353 # number of demand (read+write) misses 2627system.cpu1.l2cache.demand_misses::cpu1.data 1273106 # number of demand (read+write) misses 2628system.cpu1.l2cache.demand_misses::total 1868722 # number of demand (read+write) misses 2629system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 11662 # number of overall misses 2630system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8601 # number of overall misses 2631system.cpu1.l2cache.overall_misses::cpu1.inst 575353 # number of overall misses 2632system.cpu1.l2cache.overall_misses::cpu1.data 1273106 # number of overall misses 2633system.cpu1.l2cache.overall_misses::total 1868722 # number of overall misses 2634system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 594160000 # number of ReadReq miss cycles 2635system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 468390500 # number of ReadReq miss cycles 2636system.cpu1.l2cache.ReadReq_miss_latency::total 1062550500 # number of ReadReq miss cycles 2637system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 4210266499 # number of UpgradeReq miss cycles 2638system.cpu1.l2cache.UpgradeReq_miss_latency::total 4210266499 # number of UpgradeReq miss cycles 2639system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3771249000 # number of SCUpgradeReq miss cycles 2640system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3771249000 # number of SCUpgradeReq miss cycles 2641system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 5184498 # number of SCUpgradeFailReq miss cycles 2642system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 5184498 # number of SCUpgradeFailReq miss cycles 2643system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 15534540997 # number of ReadExReq miss cycles 2644system.cpu1.l2cache.ReadExReq_miss_latency::total 15534540997 # number of ReadExReq miss cycles 2645system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 20167259000 # number of ReadCleanReq miss cycles 2646system.cpu1.l2cache.ReadCleanReq_miss_latency::total 20167259000 # number of ReadCleanReq miss cycles 2647system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 37839552480 # number of ReadSharedReq miss cycles 2648system.cpu1.l2cache.ReadSharedReq_miss_latency::total 37839552480 # number of ReadSharedReq miss cycles 2649system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 13425130499 # number of InvalidateReq miss cycles 2650system.cpu1.l2cache.InvalidateReq_miss_latency::total 13425130499 # number of InvalidateReq miss cycles 2651system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 594160000 # number of demand (read+write) miss cycles 2652system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 468390500 # number of demand (read+write) miss cycles 2653system.cpu1.l2cache.demand_miss_latency::cpu1.inst 20167259000 # number of demand (read+write) miss cycles 2654system.cpu1.l2cache.demand_miss_latency::cpu1.data 53374093477 # number of demand (read+write) miss cycles 2655system.cpu1.l2cache.demand_miss_latency::total 74603902977 # number of demand (read+write) miss cycles 2656system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 594160000 # number of overall miss cycles 2657system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 468390500 # number of overall miss cycles 2658system.cpu1.l2cache.overall_miss_latency::cpu1.inst 20167259000 # number of overall miss cycles 2659system.cpu1.l2cache.overall_miss_latency::cpu1.data 53374093477 # number of overall miss cycles 2660system.cpu1.l2cache.overall_miss_latency::total 74603902977 # number of overall miss cycles 2661system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 515565 # number of ReadReq accesses(hits+misses) 2662system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 179008 # number of ReadReq accesses(hits+misses) 2663system.cpu1.l2cache.ReadReq_accesses::total 694573 # number of ReadReq accesses(hits+misses) 2664system.cpu1.l2cache.Writeback_accesses::writebacks 3362558 # number of Writeback accesses(hits+misses) 2665system.cpu1.l2cache.Writeback_accesses::total 3362558 # number of Writeback accesses(hits+misses) 2666system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 216338 # number of UpgradeReq accesses(hits+misses) 2667system.cpu1.l2cache.UpgradeReq_accesses::total 216338 # number of UpgradeReq accesses(hits+misses) 2668system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 193898 # number of SCUpgradeReq accesses(hits+misses) 2669system.cpu1.l2cache.SCUpgradeReq_accesses::total 193898 # number of SCUpgradeReq accesses(hits+misses) 2670system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses) 2671system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) 2672system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1115869 # number of ReadExReq accesses(hits+misses) 2673system.cpu1.l2cache.ReadExReq_accesses::total 1115869 # number of ReadExReq accesses(hits+misses) 2674system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5203326 # number of ReadCleanReq accesses(hits+misses) 2675system.cpu1.l2cache.ReadCleanReq_accesses::total 5203326 # number of ReadCleanReq accesses(hits+misses) 2676system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3729830 # number of ReadSharedReq accesses(hits+misses) 2677system.cpu1.l2cache.ReadSharedReq_accesses::total 3729830 # number of ReadSharedReq accesses(hits+misses) 2678system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 401778 # number of InvalidateReq accesses(hits+misses) 2679system.cpu1.l2cache.InvalidateReq_accesses::total 401778 # number of InvalidateReq accesses(hits+misses) 2680system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 515565 # number of demand (read+write) accesses 2681system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 179008 # number of demand (read+write) accesses 2682system.cpu1.l2cache.demand_accesses::cpu1.inst 5203326 # number of demand (read+write) accesses 2683system.cpu1.l2cache.demand_accesses::cpu1.data 4845699 # number of demand (read+write) accesses 2684system.cpu1.l2cache.demand_accesses::total 10743598 # number of demand (read+write) accesses 2685system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 515565 # number of overall (read+write) accesses 2686system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 179008 # number of overall (read+write) accesses 2687system.cpu1.l2cache.overall_accesses::cpu1.inst 5203326 # number of overall (read+write) accesses 2688system.cpu1.l2cache.overall_accesses::cpu1.data 4845699 # number of overall (read+write) accesses 2689system.cpu1.l2cache.overall_accesses::total 10743598 # number of overall (read+write) accesses 2690system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022620 # miss rate for ReadReq accesses 2691system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.048048 # miss rate for ReadReq accesses 2692system.cpu1.l2cache.ReadReq_miss_rate::total 0.029173 # miss rate for ReadReq accesses 2693system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000004 # miss rate for Writeback accesses 2694system.cpu1.l2cache.Writeback_miss_rate::total 0.000004 # miss rate for Writeback accesses 2695system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.647921 # miss rate for UpgradeReq accesses 2696system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.647921 # miss rate for UpgradeReq accesses 2697system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.825645 # miss rate for SCUpgradeReq accesses 2698system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.825645 # miss rate for SCUpgradeReq accesses 2699system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2700system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2701system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.258751 # miss rate for ReadExReq accesses 2702system.cpu1.l2cache.ReadExReq_miss_rate::total 0.258751 # miss rate for ReadExReq accesses 2703system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.110574 # miss rate for ReadCleanReq accesses 2704system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.110574 # miss rate for ReadCleanReq accesses 2705system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.263919 # miss rate for ReadSharedReq accesses 2706system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.263919 # miss rate for ReadSharedReq accesses 2707system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.555737 # miss rate for InvalidateReq accesses 2708system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.555737 # miss rate for InvalidateReq accesses 2709system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022620 # miss rate for demand accesses 2710system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.048048 # miss rate for demand accesses 2711system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.110574 # miss rate for demand accesses 2712system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.262729 # miss rate for demand accesses 2713system.cpu1.l2cache.demand_miss_rate::total 0.173938 # miss rate for demand accesses 2714system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022620 # miss rate for overall accesses 2715system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.048048 # miss rate for overall accesses 2716system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.110574 # miss rate for overall accesses 2717system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.262729 # miss rate for overall accesses 2718system.cpu1.l2cache.overall_miss_rate::total 0.173938 # miss rate for overall accesses 2719system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 50948.379352 # average ReadReq miss latency 2720system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 54457.679340 # average ReadReq miss latency 2721system.cpu1.l2cache.ReadReq_avg_miss_latency::total 52437.965750 # average ReadReq miss latency 2722system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 30036.858807 # average UpgradeReq miss latency 2723system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 30036.858807 # average UpgradeReq miss latency 2724system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 23556.908258 # average SCUpgradeReq miss latency 2725system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 23556.908258 # average SCUpgradeReq miss latency 2726system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 864083 # average SCUpgradeFailReq miss latency 2727system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 864083 # average SCUpgradeFailReq miss latency 2728system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53802.630110 # average ReadExReq miss latency 2729system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53802.630110 # average ReadExReq miss latency 2730system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 35051.975048 # average ReadCleanReq miss latency 2731system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 35051.975048 # average ReadCleanReq miss latency 2732system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 38440.219348 # average ReadSharedReq miss latency 2733system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 38440.219348 # average ReadSharedReq miss latency 2734system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 60126.075424 # average InvalidateReq miss latency 2735system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 60126.075424 # average InvalidateReq miss latency 2736system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 50948.379352 # average overall miss latency 2737system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 54457.679340 # average overall miss latency 2738system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35051.975048 # average overall miss latency 2739system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 41924.312254 # average overall miss latency 2740system.cpu1.l2cache.demand_avg_miss_latency::total 39922.419160 # average overall miss latency 2741system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 50948.379352 # average overall miss latency 2742system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 54457.679340 # average overall miss latency 2743system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35051.975048 # average overall miss latency 2744system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 41924.312254 # average overall miss latency 2745system.cpu1.l2cache.overall_avg_miss_latency::total 39922.419160 # average overall miss latency 2746system.cpu1.l2cache.blocked_cycles::no_mshrs 689 # number of cycles access was blocked 2747system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2748system.cpu1.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked 2749system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2750system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 137.800000 # average number of cycles each access was blocked 2751system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2752system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2753system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2754system.cpu1.l2cache.writebacks::writebacks 1011189 # number of writebacks 2755system.cpu1.l2cache.writebacks::total 1011189 # number of writebacks 2756system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 3 # number of ReadReq MSHR hits 2757system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 149 # number of ReadReq MSHR hits 2758system.cpu1.l2cache.ReadReq_mshr_hits::total 152 # number of ReadReq MSHR hits 2759system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 48488 # number of ReadExReq MSHR hits 2760system.cpu1.l2cache.ReadExReq_mshr_hits::total 48488 # number of ReadExReq MSHR hits 2761system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 3759 # number of ReadSharedReq MSHR hits 2762system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 3759 # number of ReadSharedReq MSHR hits 2763system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 12 # number of InvalidateReq MSHR hits 2764system.cpu1.l2cache.InvalidateReq_mshr_hits::total 12 # number of InvalidateReq MSHR hits 2765system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 3 # number of demand (read+write) MSHR hits 2766system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 149 # number of demand (read+write) MSHR hits 2767system.cpu1.l2cache.demand_mshr_hits::cpu1.data 52247 # number of demand (read+write) MSHR hits 2768system.cpu1.l2cache.demand_mshr_hits::total 52399 # number of demand (read+write) MSHR hits 2769system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 3 # number of overall MSHR hits 2770system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 149 # number of overall MSHR hits 2771system.cpu1.l2cache.overall_mshr_hits::cpu1.data 52247 # number of overall MSHR hits 2772system.cpu1.l2cache.overall_mshr_hits::total 52399 # number of overall MSHR hits 2773system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 11659 # number of ReadReq MSHR misses 2774system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8452 # number of ReadReq MSHR misses 2775system.cpu1.l2cache.ReadReq_mshr_misses::total 20111 # number of ReadReq MSHR misses 2776system.cpu1.l2cache.Writeback_mshr_misses::writebacks 12 # number of Writeback MSHR misses 2777system.cpu1.l2cache.Writeback_mshr_misses::total 12 # number of Writeback MSHR misses 2778system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 102199 # number of CleanEvict MSHR misses 2779system.cpu1.l2cache.CleanEvict_mshr_misses::total 102199 # number of CleanEvict MSHR misses 2780system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 721665 # number of HardPFReq MSHR misses 2781system.cpu1.l2cache.HardPFReq_mshr_misses::total 721665 # number of HardPFReq MSHR misses 2782system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 140170 # number of UpgradeReq MSHR misses 2783system.cpu1.l2cache.UpgradeReq_mshr_misses::total 140170 # number of UpgradeReq MSHR misses 2784system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 160091 # number of SCUpgradeReq MSHR misses 2785system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 160091 # number of SCUpgradeReq MSHR misses 2786system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses 2787system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses 2788system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 240244 # number of ReadExReq MSHR misses 2789system.cpu1.l2cache.ReadExReq_mshr_misses::total 240244 # number of ReadExReq MSHR misses 2790system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 575353 # number of ReadCleanReq MSHR misses 2791system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 575353 # number of ReadCleanReq MSHR misses 2792system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 980615 # number of ReadSharedReq MSHR misses 2793system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 980615 # number of ReadSharedReq MSHR misses 2794system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 223271 # number of InvalidateReq MSHR misses 2795system.cpu1.l2cache.InvalidateReq_mshr_misses::total 223271 # number of InvalidateReq MSHR misses 2796system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 11659 # number of demand (read+write) MSHR misses 2797system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8452 # number of demand (read+write) MSHR misses 2798system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 575353 # number of demand (read+write) MSHR misses 2799system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1220859 # number of demand (read+write) MSHR misses 2800system.cpu1.l2cache.demand_mshr_misses::total 1816323 # number of demand (read+write) MSHR misses 2801system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 11659 # number of overall MSHR misses 2802system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8452 # number of overall MSHR misses 2803system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 575353 # number of overall MSHR misses 2804system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1220859 # number of overall MSHR misses 2805system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 721665 # number of overall MSHR misses 2806system.cpu1.l2cache.overall_mshr_misses::total 2537988 # number of overall MSHR misses 2807system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 2808system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5159 # number of ReadReq MSHR uncacheable 2809system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5226 # number of ReadReq MSHR uncacheable 2810system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 4882 # number of WriteReq MSHR uncacheable 2811system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 4882 # number of WriteReq MSHR uncacheable 2812system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 2813system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10041 # number of overall MSHR uncacheable misses 2814system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10108 # number of overall MSHR uncacheable misses 2815system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 524142000 # number of ReadReq MSHR miss cycles 2816system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 406910000 # number of ReadReq MSHR miss cycles 2817system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 931052000 # number of ReadReq MSHR miss cycles 2818system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 46701535932 # number of HardPFReq MSHR miss cycles 2819system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 46701535932 # number of HardPFReq MSHR miss cycles 2820system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4601332497 # number of UpgradeReq MSHR miss cycles 2821system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4601332497 # number of UpgradeReq MSHR miss cycles 2822system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2959393998 # number of SCUpgradeReq MSHR miss cycles 2823system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2959393998 # number of SCUpgradeReq MSHR miss cycles 2824system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 4812498 # number of SCUpgradeFailReq MSHR miss cycles 2825system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4812498 # number of SCUpgradeFailReq MSHR miss cycles 2826system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 11648353997 # number of ReadExReq MSHR miss cycles 2827system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 11648353997 # number of ReadExReq MSHR miss cycles 2828system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 16715141000 # number of ReadCleanReq MSHR miss cycles 2829system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 16715141000 # number of ReadCleanReq MSHR miss cycles 2830system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 31784270480 # number of ReadSharedReq MSHR miss cycles 2831system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 31784270480 # number of ReadSharedReq MSHR miss cycles 2832system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 12084897499 # number of InvalidateReq MSHR miss cycles 2833system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 12084897499 # number of InvalidateReq MSHR miss cycles 2834system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 524142000 # number of demand (read+write) MSHR miss cycles 2835system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 406910000 # number of demand (read+write) MSHR miss cycles 2836system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 16715141000 # number of demand (read+write) MSHR miss cycles 2837system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 43432624477 # number of demand (read+write) MSHR miss cycles 2838system.cpu1.l2cache.demand_mshr_miss_latency::total 61078817477 # number of demand (read+write) MSHR miss cycles 2839system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 524142000 # number of overall MSHR miss cycles 2840system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 406910000 # number of overall MSHR miss cycles 2841system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 16715141000 # number of overall MSHR miss cycles 2842system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 43432624477 # number of overall MSHR miss cycles 2843system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 46701535932 # number of overall MSHR miss cycles 2844system.cpu1.l2cache.overall_mshr_miss_latency::total 107780353409 # number of overall MSHR miss cycles 2845system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8404500 # number of ReadReq MSHR uncacheable cycles 2846system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 479244000 # number of ReadReq MSHR uncacheable cycles 2847system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 487648500 # number of ReadReq MSHR uncacheable cycles 2848system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 512985500 # number of WriteReq MSHR uncacheable cycles 2849system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 512985500 # number of WriteReq MSHR uncacheable cycles 2850system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8404500 # number of overall MSHR uncacheable cycles 2851system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 992229500 # number of overall MSHR uncacheable cycles 2852system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1000634000 # number of overall MSHR uncacheable cycles 2853system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022614 # mshr miss rate for ReadReq accesses 2854system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.047216 # mshr miss rate for ReadReq accesses 2855system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.028954 # mshr miss rate for ReadReq accesses 2856system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000004 # mshr miss rate for Writeback accesses 2857system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000004 # mshr miss rate for Writeback accesses 2858system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 2859system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 2860system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2861system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2862system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.647921 # mshr miss rate for UpgradeReq accesses 2863system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.647921 # mshr miss rate for UpgradeReq accesses 2864system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.825645 # mshr miss rate for SCUpgradeReq accesses 2865system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.825645 # mshr miss rate for SCUpgradeReq accesses 2866system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2867system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2868system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.215298 # mshr miss rate for ReadExReq accesses 2869system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.215298 # mshr miss rate for ReadExReq accesses 2870system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.110574 # mshr miss rate for ReadCleanReq accesses 2871system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.110574 # mshr miss rate for ReadCleanReq accesses 2872system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.262911 # mshr miss rate for ReadSharedReq accesses 2873system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.262911 # mshr miss rate for ReadSharedReq accesses 2874system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.555707 # mshr miss rate for InvalidateReq accesses 2875system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.555707 # mshr miss rate for InvalidateReq accesses 2876system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022614 # mshr miss rate for demand accesses 2877system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.047216 # mshr miss rate for demand accesses 2878system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.110574 # mshr miss rate for demand accesses 2879system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.251947 # mshr miss rate for demand accesses 2880system.cpu1.l2cache.demand_mshr_miss_rate::total 0.169061 # mshr miss rate for demand accesses 2881system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022614 # mshr miss rate for overall accesses 2882system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.047216 # mshr miss rate for overall accesses 2883system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.110574 # mshr miss rate for overall accesses 2884system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.251947 # mshr miss rate for overall accesses 2885system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2886system.cpu1.l2cache.overall_mshr_miss_rate::total 0.236233 # mshr miss rate for overall accesses 2887system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 44955.999657 # average ReadReq mshr miss latency 2888system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 48143.634643 # average ReadReq mshr miss latency 2889system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 46295.659092 # average ReadReq mshr miss latency 2890system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 64713.594163 # average HardPFReq mshr miss latency 2891system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 64713.594163 # average HardPFReq mshr miss latency 2892system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 32826.799579 # average UpgradeReq mshr miss latency 2893system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 32826.799579 # average UpgradeReq mshr miss latency 2894system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18485.698746 # average SCUpgradeReq mshr miss latency 2895system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18485.698746 # average SCUpgradeReq mshr miss latency 2896system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 802083 # average SCUpgradeFailReq mshr miss latency 2897system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 802083 # average SCUpgradeFailReq mshr miss latency 2898system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 48485.514714 # average ReadExReq mshr miss latency 2899system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 48485.514714 # average ReadExReq mshr miss latency 2900system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 29051.975048 # average ReadCleanReq mshr miss latency 2901system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 29051.975048 # average ReadCleanReq mshr miss latency 2902system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 32412.588508 # average ReadSharedReq mshr miss latency 2903system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32412.588508 # average ReadSharedReq mshr miss latency 2904system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 54126.588312 # average InvalidateReq mshr miss latency 2905system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 54126.588312 # average InvalidateReq mshr miss latency 2906system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 44955.999657 # average overall mshr miss latency 2907system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 48143.634643 # average overall mshr miss latency 2908system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29051.975048 # average overall mshr miss latency 2909system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 35575.463241 # average overall mshr miss latency 2910system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 33627.728921 # average overall mshr miss latency 2911system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 44955.999657 # average overall mshr miss latency 2912system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 48143.634643 # average overall mshr miss latency 2913system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29051.975048 # average overall mshr miss latency 2914system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 35575.463241 # average overall mshr miss latency 2915system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 64713.594163 # average overall mshr miss latency 2916system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42466.849098 # average overall mshr miss latency 2917system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 125440.298507 # average ReadReq mshr uncacheable latency 2918system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 92894.747044 # average ReadReq mshr uncacheable latency 2919system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 93311.997704 # average ReadReq mshr uncacheable latency 2920system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 105076.915199 # average WriteReq mshr uncacheable latency 2921system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 105076.915199 # average WriteReq mshr uncacheable latency 2922system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 125440.298507 # average overall mshr uncacheable latency 2923system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 98817.797032 # average overall mshr uncacheable latency 2924system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 98994.261971 # average overall mshr uncacheable latency 2925system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2926system.cpu1.toL2Bus.snoop_filter.tot_requests 21572446 # Total number of requests made to the snoop filter. 2927system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11121796 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2928system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1158 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2929system.cpu1.toL2Bus.snoop_filter.tot_snoops 524506 # Total number of snoops made to the snoop filter. 2930system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 524489 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2931system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 17 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2932system.cpu1.toL2Bus.trans_dist::ReadReq 847854 # Transaction distribution 2933system.cpu1.toL2Bus.trans_dist::ReadResp 9869269 # Transaction distribution 2934system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 2935system.cpu1.toL2Bus.trans_dist::WriteReq 4882 # Transaction distribution 2936system.cpu1.toL2Bus.trans_dist::WriteResp 4882 # Transaction distribution 2937system.cpu1.toL2Bus.trans_dist::Writeback 4416651 # Transaction distribution 2938system.cpu1.toL2Bus.trans_dist::CleanEvict 8880510 # Transaction distribution 2939system.cpu1.toL2Bus.trans_dist::HardPFReq 907695 # Transaction distribution 2940system.cpu1.toL2Bus.trans_dist::HardPFResp 13 # Transaction distribution 2941system.cpu1.toL2Bus.trans_dist::UpgradeReq 421769 # Transaction distribution 2942system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 350236 # Transaction distribution 2943system.cpu1.toL2Bus.trans_dist::UpgradeResp 471619 # Transaction distribution 2944system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 69 # Transaction distribution 2945system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution 2946system.cpu1.toL2Bus.trans_dist::ReadExReq 1189775 # Transaction distribution 2947system.cpu1.toL2Bus.trans_dist::ReadExResp 1122660 # Transaction distribution 2948system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5203338 # Transaction distribution 2949system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4763767 # Transaction distribution 2950system.cpu1.toL2Bus.trans_dist::InvalidateReq 409409 # Transaction distribution 2951system.cpu1.toL2Bus.trans_dist::InvalidateResp 401778 # Transaction distribution 2952system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 15609171 # Packet count per connected master and slave (bytes) 2953system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16649345 # Packet count per connected master and slave (bytes) 2954system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 393406 # Packet count per connected master and slave (bytes) 2955system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1143795 # Packet count per connected master and slave (bytes) 2956system.cpu1.toL2Bus.pkt_count::total 33795717 # Packet count per connected master and slave (bytes) 2957system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 333013936 # Cumulative packet size per connected master and slave (bytes) 2958system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 531452177 # Cumulative packet size per connected master and slave (bytes) 2959system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1432064 # Cumulative packet size per connected master and slave (bytes) 2960system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4124520 # Cumulative packet size per connected master and slave (bytes) 2961system.cpu1.toL2Bus.pkt_size::total 870022697 # Cumulative packet size per connected master and slave (bytes) 2962system.cpu1.toL2Bus.snoops 5627139 # Total snoops (count) 2963system.cpu1.toL2Bus.snoop_fanout::samples 27397107 # Request fanout histogram 2964system.cpu1.toL2Bus.snoop_fanout::mean 0.032027 # Request fanout histogram 2965system.cpu1.toL2Bus.snoop_fanout::stdev 0.176075 # Request fanout histogram 2966system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2967system.cpu1.toL2Bus.snoop_fanout::0 26519684 96.80% 96.80% # Request fanout histogram 2968system.cpu1.toL2Bus.snoop_fanout::1 877406 3.20% 100.00% # Request fanout histogram 2969system.cpu1.toL2Bus.snoop_fanout::2 17 0.00% 100.00% # Request fanout histogram 2970system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2971system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2972system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2973system.cpu1.toL2Bus.snoop_fanout::total 27397107 # Request fanout histogram 2974system.cpu1.toL2Bus.reqLayer0.occupancy 14402314458 # Layer occupancy (ticks) 2975system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2976system.cpu1.toL2Bus.snoopLayer0.occupancy 173479331 # Layer occupancy (ticks) 2977system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2978system.cpu1.toL2Bus.respLayer0.occupancy 7809268085 # Layer occupancy (ticks) 2979system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2980system.cpu1.toL2Bus.respLayer1.occupancy 7687735490 # Layer occupancy (ticks) 2981system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2982system.cpu1.toL2Bus.respLayer2.occupancy 214700392 # Layer occupancy (ticks) 2983system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2984system.cpu1.toL2Bus.respLayer3.occupancy 628828296 # Layer occupancy (ticks) 2985system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2986system.iobus.trans_dist::ReadReq 40404 # Transaction distribution 2987system.iobus.trans_dist::ReadResp 40404 # Transaction distribution 2988system.iobus.trans_dist::WriteReq 136681 # Transaction distribution 2989system.iobus.trans_dist::WriteResp 136681 # Transaction distribution 2990system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47892 # Packet count per connected master and slave (bytes) 2991system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2992system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2993system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2994system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2995system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2996system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2997system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2998system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2999system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 3000system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 3001system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 3002system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 3003system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 3004system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 3005system.iobus.pkt_count_system.bridge.master::total 122826 # Packet count per connected master and slave (bytes) 3006system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231264 # Packet count per connected master and slave (bytes) 3007system.iobus.pkt_count_system.realview.ide.dma::total 231264 # Packet count per connected master and slave (bytes) 3008system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 3009system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 3010system.iobus.pkt_count::total 354170 # Packet count per connected master and slave (bytes) 3011system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47912 # Cumulative packet size per connected master and slave (bytes) 3012system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 3013system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 3014system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 3015system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 3016system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3017system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3018system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3019system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 3020system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3021system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 3022system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 3023system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 3024system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 3025system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 3026system.iobus.pkt_size_system.bridge.master::total 155933 # Cumulative packet size per connected master and slave (bytes) 3027system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339072 # Cumulative packet size per connected master and slave (bytes) 3028system.iobus.pkt_size_system.realview.ide.dma::total 7339072 # Cumulative packet size per connected master and slave (bytes) 3029system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 3030system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 3031system.iobus.pkt_size::total 7497091 # Cumulative packet size per connected master and slave (bytes) 3032system.iobus.reqLayer0.occupancy 36369000 # Layer occupancy (ticks) 3033system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 3034system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 3035system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 3036system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 3037system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 3038system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 3039system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 3040system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 3041system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 3042system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 3043system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 3044system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 3045system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 3046system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 3047system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 3048system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 3049system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 3050system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 3051system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 3052system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) 3053system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 3054system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 3055system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 3056system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 3057system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 3058system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 3059system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 3060system.iobus.reqLayer27.occupancy 566086533 # Layer occupancy (ticks) 3061system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 3062system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 3063system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 3064system.iobus.respLayer0.occupancy 92876000 # Layer occupancy (ticks) 3065system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 3066system.iobus.respLayer3.occupancy 147960000 # Layer occupancy (ticks) 3067system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 3068system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 3069system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 3070system.iocache.tags.replacements 115614 # number of replacements 3071system.iocache.tags.tagsinuse 11.301705 # Cycle average of tags in use 3072system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 3073system.iocache.tags.sampled_refs 115630 # Sample count of references to valid blocks. 3074system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 3075system.iocache.tags.warmup_cycle 9126915715000 # Cycle when the warmup percentage was hit. 3076system.iocache.tags.occ_blocks::realview.ethernet 3.837722 # Average occupied blocks per requestor 3077system.iocache.tags.occ_blocks::realview.ide 7.463983 # Average occupied blocks per requestor 3078system.iocache.tags.occ_percent::realview.ethernet 0.239858 # Average percentage of cache occupancy 3079system.iocache.tags.occ_percent::realview.ide 0.466499 # Average percentage of cache occupancy 3080system.iocache.tags.occ_percent::total 0.706357 # Average percentage of cache occupancy 3081system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 3082system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 3083system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 3084system.iocache.tags.tag_accesses 1041045 # Number of tag accesses 3085system.iocache.tags.data_accesses 1041045 # Number of data accesses 3086system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 3087system.iocache.ReadReq_misses::realview.ide 8904 # number of ReadReq misses 3088system.iocache.ReadReq_misses::total 8941 # number of ReadReq misses 3089system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 3090system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 3091system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 3092system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 3093system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 3094system.iocache.demand_misses::realview.ide 8904 # number of demand (read+write) misses 3095system.iocache.demand_misses::total 8944 # number of demand (read+write) misses 3096system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 3097system.iocache.overall_misses::realview.ide 8904 # number of overall misses 3098system.iocache.overall_misses::total 8944 # number of overall misses 3099system.iocache.ReadReq_miss_latency::realview.ethernet 5199000 # number of ReadReq miss cycles 3100system.iocache.ReadReq_miss_latency::realview.ide 1751682968 # number of ReadReq miss cycles 3101system.iocache.ReadReq_miss_latency::total 1756881968 # number of ReadReq miss cycles 3102system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 3103system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 3104system.iocache.WriteLineReq_miss_latency::realview.ide 13928366565 # number of WriteLineReq miss cycles 3105system.iocache.WriteLineReq_miss_latency::total 13928366565 # number of WriteLineReq miss cycles 3106system.iocache.demand_miss_latency::realview.ethernet 5568000 # number of demand (read+write) miss cycles 3107system.iocache.demand_miss_latency::realview.ide 1751682968 # number of demand (read+write) miss cycles 3108system.iocache.demand_miss_latency::total 1757250968 # number of demand (read+write) miss cycles 3109system.iocache.overall_miss_latency::realview.ethernet 5568000 # number of overall miss cycles 3110system.iocache.overall_miss_latency::realview.ide 1751682968 # number of overall miss cycles 3111system.iocache.overall_miss_latency::total 1757250968 # number of overall miss cycles 3112system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 3113system.iocache.ReadReq_accesses::realview.ide 8904 # number of ReadReq accesses(hits+misses) 3114system.iocache.ReadReq_accesses::total 8941 # number of ReadReq accesses(hits+misses) 3115system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 3116system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 3117system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 3118system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 3119system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 3120system.iocache.demand_accesses::realview.ide 8904 # number of demand (read+write) accesses 3121system.iocache.demand_accesses::total 8944 # number of demand (read+write) accesses 3122system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 3123system.iocache.overall_accesses::realview.ide 8904 # number of overall (read+write) accesses 3124system.iocache.overall_accesses::total 8944 # number of overall (read+write) accesses 3125system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 3126system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 3127system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 3128system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 3129system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 3130system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 3131system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 3132system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 3133system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 3134system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 3135system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 3136system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 3137system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 3138system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140513.513514 # average ReadReq miss latency 3139system.iocache.ReadReq_avg_miss_latency::realview.ide 196729.893082 # average ReadReq miss latency 3140system.iocache.ReadReq_avg_miss_latency::total 196497.256235 # average ReadReq miss latency 3141system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 3142system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 3143system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130503.397094 # average WriteLineReq miss latency 3144system.iocache.WriteLineReq_avg_miss_latency::total 130503.397094 # average WriteLineReq miss latency 3145system.iocache.demand_avg_miss_latency::realview.ethernet 139200 # average overall miss latency 3146system.iocache.demand_avg_miss_latency::realview.ide 196729.893082 # average overall miss latency 3147system.iocache.demand_avg_miss_latency::total 196472.603757 # average overall miss latency 3148system.iocache.overall_avg_miss_latency::realview.ethernet 139200 # average overall miss latency 3149system.iocache.overall_avg_miss_latency::realview.ide 196729.893082 # average overall miss latency 3150system.iocache.overall_avg_miss_latency::total 196472.603757 # average overall miss latency 3151system.iocache.blocked_cycles::no_mshrs 36915 # number of cycles access was blocked 3152system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3153system.iocache.blocked::no_mshrs 3596 # number of cycles access was blocked 3154system.iocache.blocked::no_targets 0 # number of cycles access was blocked 3155system.iocache.avg_blocked_cycles::no_mshrs 10.265573 # average number of cycles each access was blocked 3156system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3157system.iocache.fast_writes 0 # number of fast writes performed 3158system.iocache.cache_copies 0 # number of cache copies performed 3159system.iocache.writebacks::writebacks 106695 # number of writebacks 3160system.iocache.writebacks::total 106695 # number of writebacks 3161system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 3162system.iocache.ReadReq_mshr_misses::realview.ide 8904 # number of ReadReq MSHR misses 3163system.iocache.ReadReq_mshr_misses::total 8941 # number of ReadReq MSHR misses 3164system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 3165system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 3166system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 3167system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 3168system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 3169system.iocache.demand_mshr_misses::realview.ide 8904 # number of demand (read+write) MSHR misses 3170system.iocache.demand_mshr_misses::total 8944 # number of demand (read+write) MSHR misses 3171system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 3172system.iocache.overall_mshr_misses::realview.ide 8904 # number of overall MSHR misses 3173system.iocache.overall_mshr_misses::total 8944 # number of overall MSHR misses 3174system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3349000 # number of ReadReq MSHR miss cycles 3175system.iocache.ReadReq_mshr_miss_latency::realview.ide 1306482968 # number of ReadReq MSHR miss cycles 3176system.iocache.ReadReq_mshr_miss_latency::total 1309831968 # number of ReadReq MSHR miss cycles 3177system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 3178system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 3179system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8591966565 # number of WriteLineReq MSHR miss cycles 3180system.iocache.WriteLineReq_mshr_miss_latency::total 8591966565 # number of WriteLineReq MSHR miss cycles 3181system.iocache.demand_mshr_miss_latency::realview.ethernet 3568000 # number of demand (read+write) MSHR miss cycles 3182system.iocache.demand_mshr_miss_latency::realview.ide 1306482968 # number of demand (read+write) MSHR miss cycles 3183system.iocache.demand_mshr_miss_latency::total 1310050968 # number of demand (read+write) MSHR miss cycles 3184system.iocache.overall_mshr_miss_latency::realview.ethernet 3568000 # number of overall MSHR miss cycles 3185system.iocache.overall_mshr_miss_latency::realview.ide 1306482968 # number of overall MSHR miss cycles 3186system.iocache.overall_mshr_miss_latency::total 1310050968 # number of overall MSHR miss cycles 3187system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 3188system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 3189system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 3190system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 3191system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 3192system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 3193system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 3194system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 3195system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 3196system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 3197system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 3198system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 3199system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 3200system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90513.513514 # average ReadReq mshr miss latency 3201system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 146729.893082 # average ReadReq mshr miss latency 3202system.iocache.ReadReq_avg_mshr_miss_latency::total 146497.256235 # average ReadReq mshr miss latency 3203system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 3204system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 3205system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80503.397094 # average WriteLineReq mshr miss latency 3206system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80503.397094 # average WriteLineReq mshr miss latency 3207system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89200 # average overall mshr miss latency 3208system.iocache.demand_avg_mshr_miss_latency::realview.ide 146729.893082 # average overall mshr miss latency 3209system.iocache.demand_avg_mshr_miss_latency::total 146472.603757 # average overall mshr miss latency 3210system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89200 # average overall mshr miss latency 3211system.iocache.overall_avg_mshr_miss_latency::realview.ide 146729.893082 # average overall mshr miss latency 3212system.iocache.overall_avg_mshr_miss_latency::total 146472.603757 # average overall mshr miss latency 3213system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 3214system.l2c.tags.replacements 1633941 # number of replacements 3215system.l2c.tags.tagsinuse 63813.673701 # Cycle average of tags in use 3216system.l2c.tags.total_refs 5902225 # Total number of references to valid blocks. 3217system.l2c.tags.sampled_refs 1694519 # Sample count of references to valid blocks. 3218system.l2c.tags.avg_refs 3.483127 # Average number of references to valid blocks. 3219system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 3220system.l2c.tags.occ_blocks::writebacks 18421.604397 # Average occupied blocks per requestor 3221system.l2c.tags.occ_blocks::cpu0.dtb.walker 145.885026 # Average occupied blocks per requestor 3222system.l2c.tags.occ_blocks::cpu0.itb.walker 177.213344 # Average occupied blocks per requestor 3223system.l2c.tags.occ_blocks::cpu0.inst 5018.050694 # Average occupied blocks per requestor 3224system.l2c.tags.occ_blocks::cpu0.data 11022.844294 # Average occupied blocks per requestor 3225system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9747.408023 # Average occupied blocks per requestor 3226system.l2c.tags.occ_blocks::cpu1.dtb.walker 214.913940 # Average occupied blocks per requestor 3227system.l2c.tags.occ_blocks::cpu1.itb.walker 271.296665 # Average occupied blocks per requestor 3228system.l2c.tags.occ_blocks::cpu1.inst 2354.078258 # Average occupied blocks per requestor 3229system.l2c.tags.occ_blocks::cpu1.data 5504.302098 # Average occupied blocks per requestor 3230system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 10936.076961 # Average occupied blocks per requestor 3231system.l2c.tags.occ_percent::writebacks 0.281091 # Average percentage of cache occupancy 3232system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002226 # Average percentage of cache occupancy 3233system.l2c.tags.occ_percent::cpu0.itb.walker 0.002704 # Average percentage of cache occupancy 3234system.l2c.tags.occ_percent::cpu0.inst 0.076569 # Average percentage of cache occupancy 3235system.l2c.tags.occ_percent::cpu0.data 0.168195 # Average percentage of cache occupancy 3236system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.148734 # Average percentage of cache occupancy 3237system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003279 # Average percentage of cache occupancy 3238system.l2c.tags.occ_percent::cpu1.itb.walker 0.004140 # Average percentage of cache occupancy 3239system.l2c.tags.occ_percent::cpu1.inst 0.035920 # Average percentage of cache occupancy 3240system.l2c.tags.occ_percent::cpu1.data 0.083989 # Average percentage of cache occupancy 3241system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.166871 # Average percentage of cache occupancy 3242system.l2c.tags.occ_percent::total 0.973719 # Average percentage of cache occupancy 3243system.l2c.tags.occ_task_id_blocks::1022 11165 # Occupied blocks per task id 3244system.l2c.tags.occ_task_id_blocks::1023 256 # Occupied blocks per task id 3245system.l2c.tags.occ_task_id_blocks::1024 49157 # Occupied blocks per task id 3246system.l2c.tags.age_task_id_blocks_1022::2 1008 # Occupied blocks per task id 3247system.l2c.tags.age_task_id_blocks_1022::3 549 # Occupied blocks per task id 3248system.l2c.tags.age_task_id_blocks_1022::4 9608 # Occupied blocks per task id 3249system.l2c.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id 3250system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 3251system.l2c.tags.age_task_id_blocks_1023::4 249 # Occupied blocks per task id 3252system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id 3253system.l2c.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id 3254system.l2c.tags.age_task_id_blocks_1024::2 2663 # Occupied blocks per task id 3255system.l2c.tags.age_task_id_blocks_1024::3 4864 # Occupied blocks per task id 3256system.l2c.tags.age_task_id_blocks_1024::4 41332 # Occupied blocks per task id 3257system.l2c.tags.occ_task_id_percent::1022 0.170364 # Percentage of cache occupancy per task id 3258system.l2c.tags.occ_task_id_percent::1023 0.003906 # Percentage of cache occupancy per task id 3259system.l2c.tags.occ_task_id_percent::1024 0.750076 # Percentage of cache occupancy per task id 3260system.l2c.tags.tag_accesses 73803894 # Number of tag accesses 3261system.l2c.tags.data_accesses 73803894 # Number of data accesses 3262system.l2c.Writeback_hits::writebacks 2578909 # number of Writeback hits 3263system.l2c.Writeback_hits::total 2578909 # number of Writeback hits 3264system.l2c.UpgradeReq_hits::cpu0.data 27661 # number of UpgradeReq hits 3265system.l2c.UpgradeReq_hits::cpu1.data 31933 # number of UpgradeReq hits 3266system.l2c.UpgradeReq_hits::total 59594 # number of UpgradeReq hits 3267system.l2c.SCUpgradeReq_hits::cpu0.data 6629 # number of SCUpgradeReq hits 3268system.l2c.SCUpgradeReq_hits::cpu1.data 5839 # number of SCUpgradeReq hits 3269system.l2c.SCUpgradeReq_hits::total 12468 # number of SCUpgradeReq hits 3270system.l2c.ReadExReq_hits::cpu0.data 166000 # number of ReadExReq hits 3271system.l2c.ReadExReq_hits::cpu1.data 160567 # number of ReadExReq hits 3272system.l2c.ReadExReq_hits::total 326567 # number of ReadExReq hits 3273system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 7163 # number of ReadSharedReq hits 3274system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4665 # number of ReadSharedReq hits 3275system.l2c.ReadSharedReq_hits::cpu0.inst 621325 # number of ReadSharedReq hits 3276system.l2c.ReadSharedReq_hits::cpu0.data 619304 # number of ReadSharedReq hits 3277system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 290117 # number of ReadSharedReq hits 3278system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6244 # number of ReadSharedReq hits 3279system.l2c.ReadSharedReq_hits::cpu1.itb.walker 4367 # number of ReadSharedReq hits 3280system.l2c.ReadSharedReq_hits::cpu1.inst 539807 # number of ReadSharedReq hits 3281system.l2c.ReadSharedReq_hits::cpu1.data 573735 # number of ReadSharedReq hits 3282system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 292658 # number of ReadSharedReq hits 3283system.l2c.ReadSharedReq_hits::total 2959385 # number of ReadSharedReq hits 3284system.l2c.demand_hits::cpu0.dtb.walker 7163 # number of demand (read+write) hits 3285system.l2c.demand_hits::cpu0.itb.walker 4665 # number of demand (read+write) hits 3286system.l2c.demand_hits::cpu0.inst 621325 # number of demand (read+write) hits 3287system.l2c.demand_hits::cpu0.data 785304 # number of demand (read+write) hits 3288system.l2c.demand_hits::cpu0.l2cache.prefetcher 290117 # number of demand (read+write) hits 3289system.l2c.demand_hits::cpu1.dtb.walker 6244 # number of demand (read+write) hits 3290system.l2c.demand_hits::cpu1.itb.walker 4367 # number of demand (read+write) hits 3291system.l2c.demand_hits::cpu1.inst 539807 # number of demand (read+write) hits 3292system.l2c.demand_hits::cpu1.data 734302 # number of demand (read+write) hits 3293system.l2c.demand_hits::cpu1.l2cache.prefetcher 292658 # number of demand (read+write) hits 3294system.l2c.demand_hits::total 3285952 # number of demand (read+write) hits 3295system.l2c.overall_hits::cpu0.dtb.walker 7163 # number of overall hits 3296system.l2c.overall_hits::cpu0.itb.walker 4665 # number of overall hits 3297system.l2c.overall_hits::cpu0.inst 621325 # number of overall hits 3298system.l2c.overall_hits::cpu0.data 785304 # number of overall hits 3299system.l2c.overall_hits::cpu0.l2cache.prefetcher 290117 # number of overall hits 3300system.l2c.overall_hits::cpu1.dtb.walker 6244 # number of overall hits 3301system.l2c.overall_hits::cpu1.itb.walker 4367 # number of overall hits 3302system.l2c.overall_hits::cpu1.inst 539807 # number of overall hits 3303system.l2c.overall_hits::cpu1.data 734302 # number of overall hits 3304system.l2c.overall_hits::cpu1.l2cache.prefetcher 292658 # number of overall hits 3305system.l2c.overall_hits::total 3285952 # number of overall hits 3306system.l2c.UpgradeReq_misses::cpu0.data 47272 # number of UpgradeReq misses 3307system.l2c.UpgradeReq_misses::cpu1.data 44187 # number of UpgradeReq misses 3308system.l2c.UpgradeReq_misses::total 91459 # number of UpgradeReq misses 3309system.l2c.SCUpgradeReq_misses::cpu0.data 10524 # number of SCUpgradeReq misses 3310system.l2c.SCUpgradeReq_misses::cpu1.data 8835 # number of SCUpgradeReq misses 3311system.l2c.SCUpgradeReq_misses::total 19359 # number of SCUpgradeReq misses 3312system.l2c.ReadExReq_misses::cpu0.data 557751 # number of ReadExReq misses 3313system.l2c.ReadExReq_misses::cpu1.data 109635 # number of ReadExReq misses 3314system.l2c.ReadExReq_misses::total 667386 # number of ReadExReq misses 3315system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2718 # number of ReadSharedReq misses 3316system.l2c.ReadSharedReq_misses::cpu0.itb.walker 2691 # number of ReadSharedReq misses 3317system.l2c.ReadSharedReq_misses::cpu0.inst 73804 # number of ReadSharedReq misses 3318system.l2c.ReadSharedReq_misses::cpu0.data 176754 # number of ReadSharedReq misses 3319system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 337074 # number of ReadSharedReq misses 3320system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2418 # number of ReadSharedReq misses 3321system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2009 # number of ReadSharedReq misses 3322system.l2c.ReadSharedReq_misses::cpu1.inst 35546 # number of ReadSharedReq misses 3323system.l2c.ReadSharedReq_misses::cpu1.data 108545 # number of ReadSharedReq misses 3324system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 227714 # number of ReadSharedReq misses 3325system.l2c.ReadSharedReq_misses::total 969273 # number of ReadSharedReq misses 3326system.l2c.demand_misses::cpu0.dtb.walker 2718 # number of demand (read+write) misses 3327system.l2c.demand_misses::cpu0.itb.walker 2691 # number of demand (read+write) misses 3328system.l2c.demand_misses::cpu0.inst 73804 # number of demand (read+write) misses 3329system.l2c.demand_misses::cpu0.data 734505 # number of demand (read+write) misses 3330system.l2c.demand_misses::cpu0.l2cache.prefetcher 337074 # number of demand (read+write) misses 3331system.l2c.demand_misses::cpu1.dtb.walker 2418 # number of demand (read+write) misses 3332system.l2c.demand_misses::cpu1.itb.walker 2009 # number of demand (read+write) misses 3333system.l2c.demand_misses::cpu1.inst 35546 # number of demand (read+write) misses 3334system.l2c.demand_misses::cpu1.data 218180 # number of demand (read+write) misses 3335system.l2c.demand_misses::cpu1.l2cache.prefetcher 227714 # number of demand (read+write) misses 3336system.l2c.demand_misses::total 1636659 # number of demand (read+write) misses 3337system.l2c.overall_misses::cpu0.dtb.walker 2718 # number of overall misses 3338system.l2c.overall_misses::cpu0.itb.walker 2691 # number of overall misses 3339system.l2c.overall_misses::cpu0.inst 73804 # number of overall misses 3340system.l2c.overall_misses::cpu0.data 734505 # number of overall misses 3341system.l2c.overall_misses::cpu0.l2cache.prefetcher 337074 # number of overall misses 3342system.l2c.overall_misses::cpu1.dtb.walker 2418 # number of overall misses 3343system.l2c.overall_misses::cpu1.itb.walker 2009 # number of overall misses 3344system.l2c.overall_misses::cpu1.inst 35546 # number of overall misses 3345system.l2c.overall_misses::cpu1.data 218180 # number of overall misses 3346system.l2c.overall_misses::cpu1.l2cache.prefetcher 227714 # number of overall misses 3347system.l2c.overall_misses::total 1636659 # number of overall misses 3348system.l2c.UpgradeReq_miss_latency::cpu0.data 726731000 # number of UpgradeReq miss cycles 3349system.l2c.UpgradeReq_miss_latency::cpu1.data 727663000 # number of UpgradeReq miss cycles 3350system.l2c.UpgradeReq_miss_latency::total 1454394000 # number of UpgradeReq miss cycles 3351system.l2c.SCUpgradeReq_miss_latency::cpu0.data 175002000 # number of SCUpgradeReq miss cycles 3352system.l2c.SCUpgradeReq_miss_latency::cpu1.data 129347000 # number of SCUpgradeReq miss cycles 3353system.l2c.SCUpgradeReq_miss_latency::total 304349000 # number of SCUpgradeReq miss cycles 3354system.l2c.ReadExReq_miss_latency::cpu0.data 99619806501 # number of ReadExReq miss cycles 3355system.l2c.ReadExReq_miss_latency::cpu1.data 16419004998 # number of ReadExReq miss cycles 3356system.l2c.ReadExReq_miss_latency::total 116038811499 # number of ReadExReq miss cycles 3357system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 387278500 # number of ReadSharedReq miss cycles 3358system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 381455000 # number of ReadSharedReq miss cycles 3359system.l2c.ReadSharedReq_miss_latency::cpu0.inst 10138420502 # number of ReadSharedReq miss cycles 3360system.l2c.ReadSharedReq_miss_latency::cpu0.data 26142956500 # number of ReadSharedReq miss cycles 3361system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 61823794743 # number of ReadSharedReq miss cycles 3362system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 346383500 # number of ReadSharedReq miss cycles 3363system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 287503000 # number of ReadSharedReq miss cycles 3364system.l2c.ReadSharedReq_miss_latency::cpu1.inst 4887103000 # number of ReadSharedReq miss cycles 3365system.l2c.ReadSharedReq_miss_latency::cpu1.data 15686030000 # number of ReadSharedReq miss cycles 3366system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 41333236319 # number of ReadSharedReq miss cycles 3367system.l2c.ReadSharedReq_miss_latency::total 161414161064 # number of ReadSharedReq miss cycles 3368system.l2c.demand_miss_latency::cpu0.dtb.walker 387278500 # number of demand (read+write) miss cycles 3369system.l2c.demand_miss_latency::cpu0.itb.walker 381455000 # number of demand (read+write) miss cycles 3370system.l2c.demand_miss_latency::cpu0.inst 10138420502 # number of demand (read+write) miss cycles 3371system.l2c.demand_miss_latency::cpu0.data 125762763001 # number of demand (read+write) miss cycles 3372system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 61823794743 # number of demand (read+write) miss cycles 3373system.l2c.demand_miss_latency::cpu1.dtb.walker 346383500 # number of demand (read+write) miss cycles 3374system.l2c.demand_miss_latency::cpu1.itb.walker 287503000 # number of demand (read+write) miss cycles 3375system.l2c.demand_miss_latency::cpu1.inst 4887103000 # number of demand (read+write) miss cycles 3376system.l2c.demand_miss_latency::cpu1.data 32105034998 # number of demand (read+write) miss cycles 3377system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 41333236319 # number of demand (read+write) miss cycles 3378system.l2c.demand_miss_latency::total 277452972563 # number of demand (read+write) miss cycles 3379system.l2c.overall_miss_latency::cpu0.dtb.walker 387278500 # number of overall miss cycles 3380system.l2c.overall_miss_latency::cpu0.itb.walker 381455000 # number of overall miss cycles 3381system.l2c.overall_miss_latency::cpu0.inst 10138420502 # number of overall miss cycles 3382system.l2c.overall_miss_latency::cpu0.data 125762763001 # number of overall miss cycles 3383system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 61823794743 # number of overall miss cycles 3384system.l2c.overall_miss_latency::cpu1.dtb.walker 346383500 # number of overall miss cycles 3385system.l2c.overall_miss_latency::cpu1.itb.walker 287503000 # number of overall miss cycles 3386system.l2c.overall_miss_latency::cpu1.inst 4887103000 # number of overall miss cycles 3387system.l2c.overall_miss_latency::cpu1.data 32105034998 # number of overall miss cycles 3388system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 41333236319 # number of overall miss cycles 3389system.l2c.overall_miss_latency::total 277452972563 # number of overall miss cycles 3390system.l2c.Writeback_accesses::writebacks 2578909 # number of Writeback accesses(hits+misses) 3391system.l2c.Writeback_accesses::total 2578909 # number of Writeback accesses(hits+misses) 3392system.l2c.UpgradeReq_accesses::cpu0.data 74933 # number of UpgradeReq accesses(hits+misses) 3393system.l2c.UpgradeReq_accesses::cpu1.data 76120 # number of UpgradeReq accesses(hits+misses) 3394system.l2c.UpgradeReq_accesses::total 151053 # number of UpgradeReq accesses(hits+misses) 3395system.l2c.SCUpgradeReq_accesses::cpu0.data 17153 # number of SCUpgradeReq accesses(hits+misses) 3396system.l2c.SCUpgradeReq_accesses::cpu1.data 14674 # number of SCUpgradeReq accesses(hits+misses) 3397system.l2c.SCUpgradeReq_accesses::total 31827 # number of SCUpgradeReq accesses(hits+misses) 3398system.l2c.ReadExReq_accesses::cpu0.data 723751 # number of ReadExReq accesses(hits+misses) 3399system.l2c.ReadExReq_accesses::cpu1.data 270202 # number of ReadExReq accesses(hits+misses) 3400system.l2c.ReadExReq_accesses::total 993953 # number of ReadExReq accesses(hits+misses) 3401system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 9881 # number of ReadSharedReq accesses(hits+misses) 3402system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7356 # number of ReadSharedReq accesses(hits+misses) 3403system.l2c.ReadSharedReq_accesses::cpu0.inst 695129 # number of ReadSharedReq accesses(hits+misses) 3404system.l2c.ReadSharedReq_accesses::cpu0.data 796058 # number of ReadSharedReq accesses(hits+misses) 3405system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 627191 # number of ReadSharedReq accesses(hits+misses) 3406system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 8662 # number of ReadSharedReq accesses(hits+misses) 3407system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6376 # number of ReadSharedReq accesses(hits+misses) 3408system.l2c.ReadSharedReq_accesses::cpu1.inst 575353 # number of ReadSharedReq accesses(hits+misses) 3409system.l2c.ReadSharedReq_accesses::cpu1.data 682280 # number of ReadSharedReq accesses(hits+misses) 3410system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 520372 # number of ReadSharedReq accesses(hits+misses) 3411system.l2c.ReadSharedReq_accesses::total 3928658 # number of ReadSharedReq accesses(hits+misses) 3412system.l2c.demand_accesses::cpu0.dtb.walker 9881 # number of demand (read+write) accesses 3413system.l2c.demand_accesses::cpu0.itb.walker 7356 # number of demand (read+write) accesses 3414system.l2c.demand_accesses::cpu0.inst 695129 # number of demand (read+write) accesses 3415system.l2c.demand_accesses::cpu0.data 1519809 # number of demand (read+write) accesses 3416system.l2c.demand_accesses::cpu0.l2cache.prefetcher 627191 # number of demand (read+write) accesses 3417system.l2c.demand_accesses::cpu1.dtb.walker 8662 # number of demand (read+write) accesses 3418system.l2c.demand_accesses::cpu1.itb.walker 6376 # number of demand (read+write) accesses 3419system.l2c.demand_accesses::cpu1.inst 575353 # number of demand (read+write) accesses 3420system.l2c.demand_accesses::cpu1.data 952482 # number of demand (read+write) accesses 3421system.l2c.demand_accesses::cpu1.l2cache.prefetcher 520372 # number of demand (read+write) accesses 3422system.l2c.demand_accesses::total 4922611 # number of demand (read+write) accesses 3423system.l2c.overall_accesses::cpu0.dtb.walker 9881 # number of overall (read+write) accesses 3424system.l2c.overall_accesses::cpu0.itb.walker 7356 # number of overall (read+write) accesses 3425system.l2c.overall_accesses::cpu0.inst 695129 # number of overall (read+write) accesses 3426system.l2c.overall_accesses::cpu0.data 1519809 # number of overall (read+write) accesses 3427system.l2c.overall_accesses::cpu0.l2cache.prefetcher 627191 # number of overall (read+write) accesses 3428system.l2c.overall_accesses::cpu1.dtb.walker 8662 # number of overall (read+write) accesses 3429system.l2c.overall_accesses::cpu1.itb.walker 6376 # number of overall (read+write) accesses 3430system.l2c.overall_accesses::cpu1.inst 575353 # number of overall (read+write) accesses 3431system.l2c.overall_accesses::cpu1.data 952482 # number of overall (read+write) accesses 3432system.l2c.overall_accesses::cpu1.l2cache.prefetcher 520372 # number of overall (read+write) accesses 3433system.l2c.overall_accesses::total 4922611 # number of overall (read+write) accesses 3434system.l2c.UpgradeReq_miss_rate::cpu0.data 0.630857 # miss rate for UpgradeReq accesses 3435system.l2c.UpgradeReq_miss_rate::cpu1.data 0.580491 # miss rate for UpgradeReq accesses 3436system.l2c.UpgradeReq_miss_rate::total 0.605476 # miss rate for UpgradeReq accesses 3437system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.613537 # miss rate for SCUpgradeReq accesses 3438system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.602085 # miss rate for SCUpgradeReq accesses 3439system.l2c.SCUpgradeReq_miss_rate::total 0.608257 # miss rate for SCUpgradeReq accesses 3440system.l2c.ReadExReq_miss_rate::cpu0.data 0.770639 # miss rate for ReadExReq accesses 3441system.l2c.ReadExReq_miss_rate::cpu1.data 0.405752 # miss rate for ReadExReq accesses 3442system.l2c.ReadExReq_miss_rate::total 0.671446 # miss rate for ReadExReq accesses 3443system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.275073 # miss rate for ReadSharedReq accesses 3444system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.365824 # miss rate for ReadSharedReq accesses 3445system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.106173 # miss rate for ReadSharedReq accesses 3446system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.222037 # miss rate for ReadSharedReq accesses 3447system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.537434 # miss rate for ReadSharedReq accesses 3448system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.279150 # miss rate for ReadSharedReq accesses 3449system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.315088 # miss rate for ReadSharedReq accesses 3450system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.061781 # miss rate for ReadSharedReq accesses 3451system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.159092 # miss rate for ReadSharedReq accesses 3452system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.437598 # miss rate for ReadSharedReq accesses 3453system.l2c.ReadSharedReq_miss_rate::total 0.246719 # miss rate for ReadSharedReq accesses 3454system.l2c.demand_miss_rate::cpu0.dtb.walker 0.275073 # miss rate for demand accesses 3455system.l2c.demand_miss_rate::cpu0.itb.walker 0.365824 # miss rate for demand accesses 3456system.l2c.demand_miss_rate::cpu0.inst 0.106173 # miss rate for demand accesses 3457system.l2c.demand_miss_rate::cpu0.data 0.483288 # miss rate for demand accesses 3458system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.537434 # miss rate for demand accesses 3459system.l2c.demand_miss_rate::cpu1.dtb.walker 0.279150 # miss rate for demand accesses 3460system.l2c.demand_miss_rate::cpu1.itb.walker 0.315088 # miss rate for demand accesses 3461system.l2c.demand_miss_rate::cpu1.inst 0.061781 # miss rate for demand accesses 3462system.l2c.demand_miss_rate::cpu1.data 0.229065 # miss rate for demand accesses 3463system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.437598 # miss rate for demand accesses 3464system.l2c.demand_miss_rate::total 0.332478 # miss rate for demand accesses 3465system.l2c.overall_miss_rate::cpu0.dtb.walker 0.275073 # miss rate for overall accesses 3466system.l2c.overall_miss_rate::cpu0.itb.walker 0.365824 # miss rate for overall accesses 3467system.l2c.overall_miss_rate::cpu0.inst 0.106173 # miss rate for overall accesses 3468system.l2c.overall_miss_rate::cpu0.data 0.483288 # miss rate for overall accesses 3469system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.537434 # miss rate for overall accesses 3470system.l2c.overall_miss_rate::cpu1.dtb.walker 0.279150 # miss rate for overall accesses 3471system.l2c.overall_miss_rate::cpu1.itb.walker 0.315088 # miss rate for overall accesses 3472system.l2c.overall_miss_rate::cpu1.inst 0.061781 # miss rate for overall accesses 3473system.l2c.overall_miss_rate::cpu1.data 0.229065 # miss rate for overall accesses 3474system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.437598 # miss rate for overall accesses 3475system.l2c.overall_miss_rate::total 0.332478 # miss rate for overall accesses 3476system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 15373.392283 # average UpgradeReq miss latency 3477system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 16467.807274 # average UpgradeReq miss latency 3478system.l2c.UpgradeReq_avg_miss_latency::total 15902.141943 # average UpgradeReq miss latency 3479system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 16628.848347 # average SCUpgradeReq miss latency 3480system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 14640.294284 # average SCUpgradeReq miss latency 3481system.l2c.SCUpgradeReq_avg_miss_latency::total 15721.318250 # average SCUpgradeReq miss latency 3482system.l2c.ReadExReq_avg_miss_latency::cpu0.data 178609.821410 # average ReadExReq miss latency 3483system.l2c.ReadExReq_avg_miss_latency::cpu1.data 149760.614749 # average ReadExReq miss latency 3484system.l2c.ReadExReq_avg_miss_latency::total 173870.610859 # average ReadExReq miss latency 3485system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 142486.571008 # average ReadSharedReq miss latency 3486system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 141752.136752 # average ReadSharedReq miss latency 3487system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 137369.526069 # average ReadSharedReq miss latency 3488system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 147905.883318 # average ReadSharedReq miss latency 3489system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 183413.122172 # average ReadSharedReq miss latency 3490system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 143252.067825 # average ReadSharedReq miss latency 3491system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 143107.516177 # average ReadSharedReq miss latency 3492system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 137486.721431 # average ReadSharedReq miss latency 3493system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 144511.769312 # average ReadSharedReq miss latency 3494system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 181513.812585 # average ReadSharedReq miss latency 3495system.l2c.ReadSharedReq_avg_miss_latency::total 166531.164145 # average ReadSharedReq miss latency 3496system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 142486.571008 # average overall miss latency 3497system.l2c.demand_avg_miss_latency::cpu0.itb.walker 141752.136752 # average overall miss latency 3498system.l2c.demand_avg_miss_latency::cpu0.inst 137369.526069 # average overall miss latency 3499system.l2c.demand_avg_miss_latency::cpu0.data 171221.112179 # average overall miss latency 3500system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 183413.122172 # average overall miss latency 3501system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 143252.067825 # average overall miss latency 3502system.l2c.demand_avg_miss_latency::cpu1.itb.walker 143107.516177 # average overall miss latency 3503system.l2c.demand_avg_miss_latency::cpu1.inst 137486.721431 # average overall miss latency 3504system.l2c.demand_avg_miss_latency::cpu1.data 147149.303318 # average overall miss latency 3505system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 181513.812585 # average overall miss latency 3506system.l2c.demand_avg_miss_latency::total 169523.995263 # average overall miss latency 3507system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 142486.571008 # average overall miss latency 3508system.l2c.overall_avg_miss_latency::cpu0.itb.walker 141752.136752 # average overall miss latency 3509system.l2c.overall_avg_miss_latency::cpu0.inst 137369.526069 # average overall miss latency 3510system.l2c.overall_avg_miss_latency::cpu0.data 171221.112179 # average overall miss latency 3511system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 183413.122172 # average overall miss latency 3512system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 143252.067825 # average overall miss latency 3513system.l2c.overall_avg_miss_latency::cpu1.itb.walker 143107.516177 # average overall miss latency 3514system.l2c.overall_avg_miss_latency::cpu1.inst 137486.721431 # average overall miss latency 3515system.l2c.overall_avg_miss_latency::cpu1.data 147149.303318 # average overall miss latency 3516system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 181513.812585 # average overall miss latency 3517system.l2c.overall_avg_miss_latency::total 169523.995263 # average overall miss latency 3518system.l2c.blocked_cycles::no_mshrs 5328 # number of cycles access was blocked 3519system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 3520system.l2c.blocked::no_mshrs 43 # number of cycles access was blocked 3521system.l2c.blocked::no_targets 0 # number of cycles access was blocked 3522system.l2c.avg_blocked_cycles::no_mshrs 123.906977 # average number of cycles each access was blocked 3523system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3524system.l2c.fast_writes 0 # number of fast writes performed 3525system.l2c.cache_copies 0 # number of cache copies performed 3526system.l2c.writebacks::writebacks 1264610 # number of writebacks 3527system.l2c.writebacks::total 1264610 # number of writebacks 3528system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 171 # number of ReadSharedReq MSHR hits 3529system.l2c.ReadSharedReq_mshr_hits::cpu0.data 23 # number of ReadSharedReq MSHR hits 3530system.l2c.ReadSharedReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadSharedReq MSHR hits 3531system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 152 # number of ReadSharedReq MSHR hits 3532system.l2c.ReadSharedReq_mshr_hits::cpu1.data 16 # number of ReadSharedReq MSHR hits 3533system.l2c.ReadSharedReq_mshr_hits::cpu1.l2cache.prefetcher 1 # number of ReadSharedReq MSHR hits 3534system.l2c.ReadSharedReq_mshr_hits::total 364 # number of ReadSharedReq MSHR hits 3535system.l2c.demand_mshr_hits::cpu0.inst 171 # number of demand (read+write) MSHR hits 3536system.l2c.demand_mshr_hits::cpu0.data 23 # number of demand (read+write) MSHR hits 3537system.l2c.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits 3538system.l2c.demand_mshr_hits::cpu1.inst 152 # number of demand (read+write) MSHR hits 3539system.l2c.demand_mshr_hits::cpu1.data 16 # number of demand (read+write) MSHR hits 3540system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits 3541system.l2c.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits 3542system.l2c.overall_mshr_hits::cpu0.inst 171 # number of overall MSHR hits 3543system.l2c.overall_mshr_hits::cpu0.data 23 # number of overall MSHR hits 3544system.l2c.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits 3545system.l2c.overall_mshr_hits::cpu1.inst 152 # number of overall MSHR hits 3546system.l2c.overall_mshr_hits::cpu1.data 16 # number of overall MSHR hits 3547system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 1 # number of overall MSHR hits 3548system.l2c.overall_mshr_hits::total 364 # number of overall MSHR hits 3549system.l2c.CleanEvict_mshr_misses::writebacks 56079 # number of CleanEvict MSHR misses 3550system.l2c.CleanEvict_mshr_misses::total 56079 # number of CleanEvict MSHR misses 3551system.l2c.UpgradeReq_mshr_misses::cpu0.data 47272 # number of UpgradeReq MSHR misses 3552system.l2c.UpgradeReq_mshr_misses::cpu1.data 44187 # number of UpgradeReq MSHR misses 3553system.l2c.UpgradeReq_mshr_misses::total 91459 # number of UpgradeReq MSHR misses 3554system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 10524 # number of SCUpgradeReq MSHR misses 3555system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 8835 # number of SCUpgradeReq MSHR misses 3556system.l2c.SCUpgradeReq_mshr_misses::total 19359 # number of SCUpgradeReq MSHR misses 3557system.l2c.ReadExReq_mshr_misses::cpu0.data 557751 # number of ReadExReq MSHR misses 3558system.l2c.ReadExReq_mshr_misses::cpu1.data 109635 # number of ReadExReq MSHR misses 3559system.l2c.ReadExReq_mshr_misses::total 667386 # number of ReadExReq MSHR misses 3560system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 2718 # number of ReadSharedReq MSHR misses 3561system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 2691 # number of ReadSharedReq MSHR misses 3562system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 73633 # number of ReadSharedReq MSHR misses 3563system.l2c.ReadSharedReq_mshr_misses::cpu0.data 176731 # number of ReadSharedReq MSHR misses 3564system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 337074 # number of ReadSharedReq MSHR misses 3565system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2417 # number of ReadSharedReq MSHR misses 3566system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2009 # number of ReadSharedReq MSHR misses 3567system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 35394 # number of ReadSharedReq MSHR misses 3568system.l2c.ReadSharedReq_mshr_misses::cpu1.data 108529 # number of ReadSharedReq MSHR misses 3569system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 227713 # number of ReadSharedReq MSHR misses 3570system.l2c.ReadSharedReq_mshr_misses::total 968909 # number of ReadSharedReq MSHR misses 3571system.l2c.demand_mshr_misses::cpu0.dtb.walker 2718 # number of demand (read+write) MSHR misses 3572system.l2c.demand_mshr_misses::cpu0.itb.walker 2691 # number of demand (read+write) MSHR misses 3573system.l2c.demand_mshr_misses::cpu0.inst 73633 # number of demand (read+write) MSHR misses 3574system.l2c.demand_mshr_misses::cpu0.data 734482 # number of demand (read+write) MSHR misses 3575system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 337074 # number of demand (read+write) MSHR misses 3576system.l2c.demand_mshr_misses::cpu1.dtb.walker 2417 # number of demand (read+write) MSHR misses 3577system.l2c.demand_mshr_misses::cpu1.itb.walker 2009 # number of demand (read+write) MSHR misses 3578system.l2c.demand_mshr_misses::cpu1.inst 35394 # number of demand (read+write) MSHR misses 3579system.l2c.demand_mshr_misses::cpu1.data 218164 # number of demand (read+write) MSHR misses 3580system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 227713 # number of demand (read+write) MSHR misses 3581system.l2c.demand_mshr_misses::total 1636295 # number of demand (read+write) MSHR misses 3582system.l2c.overall_mshr_misses::cpu0.dtb.walker 2718 # number of overall MSHR misses 3583system.l2c.overall_mshr_misses::cpu0.itb.walker 2691 # number of overall MSHR misses 3584system.l2c.overall_mshr_misses::cpu0.inst 73633 # number of overall MSHR misses 3585system.l2c.overall_mshr_misses::cpu0.data 734482 # number of overall MSHR misses 3586system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 337074 # number of overall MSHR misses 3587system.l2c.overall_mshr_misses::cpu1.dtb.walker 2417 # number of overall MSHR misses 3588system.l2c.overall_mshr_misses::cpu1.itb.walker 2009 # number of overall MSHR misses 3589system.l2c.overall_mshr_misses::cpu1.inst 35394 # number of overall MSHR misses 3590system.l2c.overall_mshr_misses::cpu1.data 218164 # number of overall MSHR misses 3591system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 227713 # number of overall MSHR misses 3592system.l2c.overall_mshr_misses::total 1636295 # number of overall MSHR misses 3593system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 21294 # number of ReadReq MSHR uncacheable 3594system.l2c.ReadReq_mshr_uncacheable::cpu0.data 33238 # number of ReadReq MSHR uncacheable 3595system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 3596system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5157 # number of ReadReq MSHR uncacheable 3597system.l2c.ReadReq_mshr_uncacheable::total 59756 # number of ReadReq MSHR uncacheable 3598system.l2c.WriteReq_mshr_uncacheable::cpu0.data 33405 # number of WriteReq MSHR uncacheable 3599system.l2c.WriteReq_mshr_uncacheable::cpu1.data 4882 # number of WriteReq MSHR uncacheable 3600system.l2c.WriteReq_mshr_uncacheable::total 38287 # number of WriteReq MSHR uncacheable 3601system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 21294 # number of overall MSHR uncacheable misses 3602system.l2c.overall_mshr_uncacheable_misses::cpu0.data 66643 # number of overall MSHR uncacheable misses 3603system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 3604system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10039 # number of overall MSHR uncacheable misses 3605system.l2c.overall_mshr_uncacheable_misses::total 98043 # number of overall MSHR uncacheable misses 3606system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 3479994002 # number of UpgradeReq MSHR miss cycles 3607system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3250114501 # number of UpgradeReq MSHR miss cycles 3608system.l2c.UpgradeReq_mshr_miss_latency::total 6730108503 # number of UpgradeReq MSHR miss cycles 3609system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 804681003 # number of SCUpgradeReq MSHR miss cycles 3610system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 675684001 # number of SCUpgradeReq MSHR miss cycles 3611system.l2c.SCUpgradeReq_mshr_miss_latency::total 1480365004 # number of SCUpgradeReq MSHR miss cycles 3612system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 94042296501 # number of ReadExReq MSHR miss cycles 3613system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 15322654998 # number of ReadExReq MSHR miss cycles 3614system.l2c.ReadExReq_mshr_miss_latency::total 109364951499 # number of ReadExReq MSHR miss cycles 3615system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 360098500 # number of ReadSharedReq MSHR miss cycles 3616system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 354545000 # number of ReadSharedReq MSHR miss cycles 3617system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 9382267002 # number of ReadSharedReq MSHR miss cycles 3618system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 24372813000 # number of ReadSharedReq MSHR miss cycles 3619system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 58453054743 # number of ReadSharedReq MSHR miss cycles 3620system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 321914500 # number of ReadSharedReq MSHR miss cycles 3621system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 267413000 # number of ReadSharedReq MSHR miss cycles 3622system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 4514510000 # number of ReadSharedReq MSHR miss cycles 3623system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 14598503500 # number of ReadSharedReq MSHR miss cycles 3624system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 39056095819 # number of ReadSharedReq MSHR miss cycles 3625system.l2c.ReadSharedReq_mshr_miss_latency::total 151681215064 # number of ReadSharedReq MSHR miss cycles 3626system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 360098500 # number of demand (read+write) MSHR miss cycles 3627system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 354545000 # number of demand (read+write) MSHR miss cycles 3628system.l2c.demand_mshr_miss_latency::cpu0.inst 9382267002 # number of demand (read+write) MSHR miss cycles 3629system.l2c.demand_mshr_miss_latency::cpu0.data 118415109501 # number of demand (read+write) MSHR miss cycles 3630system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 58453054743 # number of demand (read+write) MSHR miss cycles 3631system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 321914500 # number of demand (read+write) MSHR miss cycles 3632system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 267413000 # number of demand (read+write) MSHR miss cycles 3633system.l2c.demand_mshr_miss_latency::cpu1.inst 4514510000 # number of demand (read+write) MSHR miss cycles 3634system.l2c.demand_mshr_miss_latency::cpu1.data 29921158498 # number of demand (read+write) MSHR miss cycles 3635system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 39056095819 # number of demand (read+write) MSHR miss cycles 3636system.l2c.demand_mshr_miss_latency::total 261046166563 # number of demand (read+write) MSHR miss cycles 3637system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 360098500 # number of overall MSHR miss cycles 3638system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 354545000 # number of overall MSHR miss cycles 3639system.l2c.overall_mshr_miss_latency::cpu0.inst 9382267002 # number of overall MSHR miss cycles 3640system.l2c.overall_mshr_miss_latency::cpu0.data 118415109501 # number of overall MSHR miss cycles 3641system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 58453054743 # number of overall MSHR miss cycles 3642system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 321914500 # number of overall MSHR miss cycles 3643system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 267413000 # number of overall MSHR miss cycles 3644system.l2c.overall_mshr_miss_latency::cpu1.inst 4514510000 # number of overall MSHR miss cycles 3645system.l2c.overall_mshr_miss_latency::cpu1.data 29921158498 # number of overall MSHR miss cycles 3646system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 39056095819 # number of overall MSHR miss cycles 3647system.l2c.overall_mshr_miss_latency::total 261046166563 # number of overall MSHR miss cycles 3648system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2396727000 # number of ReadReq MSHR uncacheable cycles 3649system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5133320000 # number of ReadReq MSHR uncacheable cycles 3650system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7197500 # number of ReadReq MSHR uncacheable cycles 3651system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 386376500 # number of ReadReq MSHR uncacheable cycles 3652system.l2c.ReadReq_mshr_uncacheable_latency::total 7923621000 # number of ReadReq MSHR uncacheable cycles 3653system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 5120804533 # number of WriteReq MSHR uncacheable cycles 3654system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 429980000 # number of WriteReq MSHR uncacheable cycles 3655system.l2c.WriteReq_mshr_uncacheable_latency::total 5550784533 # number of WriteReq MSHR uncacheable cycles 3656system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2396727000 # number of overall MSHR uncacheable cycles 3657system.l2c.overall_mshr_uncacheable_latency::cpu0.data 10254124533 # number of overall MSHR uncacheable cycles 3658system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7197500 # number of overall MSHR uncacheable cycles 3659system.l2c.overall_mshr_uncacheable_latency::cpu1.data 816356500 # number of overall MSHR uncacheable cycles 3660system.l2c.overall_mshr_uncacheable_latency::total 13474405533 # number of overall MSHR uncacheable cycles 3661system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3662system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3663system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.630857 # mshr miss rate for UpgradeReq accesses 3664system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.580491 # mshr miss rate for UpgradeReq accesses 3665system.l2c.UpgradeReq_mshr_miss_rate::total 0.605476 # mshr miss rate for UpgradeReq accesses 3666system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.613537 # mshr miss rate for SCUpgradeReq accesses 3667system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.602085 # mshr miss rate for SCUpgradeReq accesses 3668system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.608257 # mshr miss rate for SCUpgradeReq accesses 3669system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.770639 # mshr miss rate for ReadExReq accesses 3670system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.405752 # mshr miss rate for ReadExReq accesses 3671system.l2c.ReadExReq_mshr_miss_rate::total 0.671446 # mshr miss rate for ReadExReq accesses 3672system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.275073 # mshr miss rate for ReadSharedReq accesses 3673system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.365824 # mshr miss rate for ReadSharedReq accesses 3674system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.105927 # mshr miss rate for ReadSharedReq accesses 3675system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.222008 # mshr miss rate for ReadSharedReq accesses 3676system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.537434 # mshr miss rate for ReadSharedReq accesses 3677system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.279035 # mshr miss rate for ReadSharedReq accesses 3678system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.315088 # mshr miss rate for ReadSharedReq accesses 3679system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.061517 # mshr miss rate for ReadSharedReq accesses 3680system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.159068 # mshr miss rate for ReadSharedReq accesses 3681system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.437597 # mshr miss rate for ReadSharedReq accesses 3682system.l2c.ReadSharedReq_mshr_miss_rate::total 0.246626 # mshr miss rate for ReadSharedReq accesses 3683system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.275073 # mshr miss rate for demand accesses 3684system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.365824 # mshr miss rate for demand accesses 3685system.l2c.demand_mshr_miss_rate::cpu0.inst 0.105927 # mshr miss rate for demand accesses 3686system.l2c.demand_mshr_miss_rate::cpu0.data 0.483273 # mshr miss rate for demand accesses 3687system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.537434 # mshr miss rate for demand accesses 3688system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.279035 # mshr miss rate for demand accesses 3689system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.315088 # mshr miss rate for demand accesses 3690system.l2c.demand_mshr_miss_rate::cpu1.inst 0.061517 # mshr miss rate for demand accesses 3691system.l2c.demand_mshr_miss_rate::cpu1.data 0.229048 # mshr miss rate for demand accesses 3692system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.437597 # mshr miss rate for demand accesses 3693system.l2c.demand_mshr_miss_rate::total 0.332404 # mshr miss rate for demand accesses 3694system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.275073 # mshr miss rate for overall accesses 3695system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.365824 # mshr miss rate for overall accesses 3696system.l2c.overall_mshr_miss_rate::cpu0.inst 0.105927 # mshr miss rate for overall accesses 3697system.l2c.overall_mshr_miss_rate::cpu0.data 0.483273 # mshr miss rate for overall accesses 3698system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.537434 # mshr miss rate for overall accesses 3699system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.279035 # mshr miss rate for overall accesses 3700system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.315088 # mshr miss rate for overall accesses 3701system.l2c.overall_mshr_miss_rate::cpu1.inst 0.061517 # mshr miss rate for overall accesses 3702system.l2c.overall_mshr_miss_rate::cpu1.data 0.229048 # mshr miss rate for overall accesses 3703system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.437597 # mshr miss rate for overall accesses 3704system.l2c.overall_mshr_miss_rate::total 0.332404 # mshr miss rate for overall accesses 3705system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73616.390294 # average UpgradeReq mshr miss latency 3706system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73553.635707 # average UpgradeReq mshr miss latency 3707system.l2c.UpgradeReq_avg_mshr_miss_latency::total 73586.071387 # average UpgradeReq mshr miss latency 3708system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76461.516819 # average SCUpgradeReq mshr miss latency 3709system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76478.098585 # average SCUpgradeReq mshr miss latency 3710system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76469.084354 # average SCUpgradeReq mshr miss latency 3711system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 168609.821410 # average ReadExReq mshr miss latency 3712system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 139760.614749 # average ReadExReq mshr miss latency 3713system.l2c.ReadExReq_avg_mshr_miss_latency::total 163870.610859 # average ReadExReq mshr miss latency 3714system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 132486.571008 # average ReadSharedReq mshr miss latency 3715system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 131752.136752 # average ReadSharedReq mshr miss latency 3716system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 127419.322885 # average ReadSharedReq mshr miss latency 3717system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 137909.099139 # average ReadSharedReq mshr miss latency 3718system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 173413.122172 # average ReadSharedReq mshr miss latency 3719system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 133187.629293 # average ReadSharedReq mshr miss latency 3720system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 133107.516177 # average ReadSharedReq mshr miss latency 3721system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127550.149743 # average ReadSharedReq mshr miss latency 3722system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 134512.466714 # average ReadSharedReq mshr miss latency 3723system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171514.563591 # average ReadSharedReq mshr miss latency 3724system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 156548.463338 # average ReadSharedReq mshr miss latency 3725system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 132486.571008 # average overall mshr miss latency 3726system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 131752.136752 # average overall mshr miss latency 3727system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 127419.322885 # average overall mshr miss latency 3728system.l2c.demand_avg_mshr_miss_latency::cpu0.data 161222.616076 # average overall mshr miss latency 3729system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 173413.122172 # average overall mshr miss latency 3730system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 133187.629293 # average overall mshr miss latency 3731system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 133107.516177 # average overall mshr miss latency 3732system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127550.149743 # average overall mshr miss latency 3733system.l2c.demand_avg_mshr_miss_latency::cpu1.data 137149.843686 # average overall mshr miss latency 3734system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171514.563591 # average overall mshr miss latency 3735system.l2c.demand_avg_mshr_miss_latency::total 159534.904503 # average overall mshr miss latency 3736system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 132486.571008 # average overall mshr miss latency 3737system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 131752.136752 # average overall mshr miss latency 3738system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 127419.322885 # average overall mshr miss latency 3739system.l2c.overall_avg_mshr_miss_latency::cpu0.data 161222.616076 # average overall mshr miss latency 3740system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 173413.122172 # average overall mshr miss latency 3741system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 133187.629293 # average overall mshr miss latency 3742system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 133107.516177 # average overall mshr miss latency 3743system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127550.149743 # average overall mshr miss latency 3744system.l2c.overall_avg_mshr_miss_latency::cpu1.data 137149.843686 # average overall mshr miss latency 3745system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171514.563591 # average overall mshr miss latency 3746system.l2c.overall_avg_mshr_miss_latency::total 159534.904503 # average overall mshr miss latency 3747system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112554.099746 # average ReadReq mshr uncacheable latency 3748system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154441.302124 # average ReadReq mshr uncacheable latency 3749system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 107425.373134 # average ReadReq mshr uncacheable latency 3750system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 74922.726391 # average ReadReq mshr uncacheable latency 3751system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 132599.588326 # average ReadReq mshr uncacheable latency 3752system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153294.552702 # average WriteReq mshr uncacheable latency 3753system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 88074.559607 # average WriteReq mshr uncacheable latency 3754system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 144978.309426 # average WriteReq mshr uncacheable latency 3755system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112554.099746 # average overall mshr uncacheable latency 3756system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 153866.490599 # average overall mshr uncacheable latency 3757system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 107425.373134 # average overall mshr uncacheable latency 3758system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81318.507820 # average overall mshr uncacheable latency 3759system.l2c.overall_avg_mshr_uncacheable_latency::total 137433.631498 # average overall mshr uncacheable latency 3760system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3761system.membus.trans_dist::ReadReq 59756 # Transaction distribution 3762system.membus.trans_dist::ReadResp 1037606 # Transaction distribution 3763system.membus.trans_dist::WriteReq 38287 # Transaction distribution 3764system.membus.trans_dist::WriteResp 38287 # Transaction distribution 3765system.membus.trans_dist::Writeback 1371305 # Transaction distribution 3766system.membus.trans_dist::CleanEvict 262648 # Transaction distribution 3767system.membus.trans_dist::UpgradeReq 440849 # Transaction distribution 3768system.membus.trans_dist::SCUpgradeReq 306045 # Transaction distribution 3769system.membus.trans_dist::UpgradeResp 117782 # Transaction distribution 3770system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution 3771system.membus.trans_dist::ReadExReq 681386 # Transaction distribution 3772system.membus.trans_dist::ReadExResp 660425 # Transaction distribution 3773system.membus.trans_dist::ReadSharedReq 977850 # Transaction distribution 3774system.membus.trans_dist::InvalidateReq 106728 # Transaction distribution 3775system.membus.trans_dist::InvalidateResp 106728 # Transaction distribution 3776system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122826 # Packet count per connected master and slave (bytes) 3777system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) 3778system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25318 # Packet count per connected master and slave (bytes) 3779system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5711814 # Packet count per connected master and slave (bytes) 3780system.membus.pkt_count_system.l2c.mem_side::total 5860036 # Packet count per connected master and slave (bytes) 3781system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 343033 # Packet count per connected master and slave (bytes) 3782system.membus.pkt_count_system.iocache.mem_side::total 343033 # Packet count per connected master and slave (bytes) 3783system.membus.pkt_count::total 6203069 # Packet count per connected master and slave (bytes) 3784system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155933 # Cumulative packet size per connected master and slave (bytes) 3785system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes) 3786system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50636 # Cumulative packet size per connected master and slave (bytes) 3787system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 185527680 # Cumulative packet size per connected master and slave (bytes) 3788system.membus.pkt_size_system.l2c.mem_side::total 185734821 # Cumulative packet size per connected master and slave (bytes) 3789system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7281536 # Cumulative packet size per connected master and slave (bytes) 3790system.membus.pkt_size_system.iocache.mem_side::total 7281536 # Cumulative packet size per connected master and slave (bytes) 3791system.membus.pkt_size::total 193016357 # Cumulative packet size per connected master and slave (bytes) 3792system.membus.snoops 652692 # Total snoops (count) 3793system.membus.snoop_fanout::samples 4246933 # Request fanout histogram 3794system.membus.snoop_fanout::mean 1 # Request fanout histogram 3795system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3796system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3797system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3798system.membus.snoop_fanout::1 4246933 100.00% 100.00% # Request fanout histogram 3799system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3800system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3801system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3802system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3803system.membus.snoop_fanout::total 4246933 # Request fanout histogram 3804system.membus.reqLayer0.occupancy 98658999 # Layer occupancy (ticks) 3805system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3806system.membus.reqLayer1.occupancy 54500 # Layer occupancy (ticks) 3807system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3808system.membus.reqLayer2.occupancy 21380469 # Layer occupancy (ticks) 3809system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3810system.membus.reqLayer5.occupancy 9518454911 # Layer occupancy (ticks) 3811system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3812system.membus.respLayer2.occupancy 8904498116 # Layer occupancy (ticks) 3813system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3814system.membus.respLayer3.occupancy 230513312 # Layer occupancy (ticks) 3815system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3816system.realview.ethernet.txBytes 966 # Bytes Transmitted 3817system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3818system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3819system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3820system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3821system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3822system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3823system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3824system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3825system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3826system.realview.ethernet.totPackets 3 # Total Packets 3827system.realview.ethernet.totBytes 966 # Total Bytes 3828system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3829system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3830system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3831system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3832system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3833system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3834system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3835system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3836system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3837system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3838system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3839system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3840system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3841system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3842system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3843system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3844system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3845system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3846system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3847system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3848system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3849system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3850system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3851system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3852system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3853system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3854system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3855system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3856system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3857system.realview.ethernet.droppedPackets 0 # number of packets dropped 3858system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks 3859system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks 3860system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks 3861system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks 3862system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks 3863system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks 3864system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks 3865system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks 3866system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks 3867system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks 3868system.toL2Bus.snoop_filter.tot_requests 11772030 # Total number of requests made to the snoop filter. 3869system.toL2Bus.snoop_filter.hit_single_requests 5986527 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3870system.toL2Bus.snoop_filter.hit_multi_requests 2060183 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3871system.toL2Bus.snoop_filter.tot_snoops 193514 # Total number of snoops made to the snoop filter. 3872system.toL2Bus.snoop_filter.hit_single_snoops 180675 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3873system.toL2Bus.snoop_filter.hit_multi_snoops 12839 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3874system.toL2Bus.trans_dist::ReadReq 59758 # Transaction distribution 3875system.toL2Bus.trans_dist::ReadResp 4863251 # Transaction distribution 3876system.toL2Bus.trans_dist::WriteReq 38287 # Transaction distribution 3877system.toL2Bus.trans_dist::WriteResp 38287 # Transaction distribution 3878system.toL2Bus.trans_dist::Writeback 3950228 # Transaction distribution 3879system.toL2Bus.trans_dist::CleanEvict 1568757 # Transaction distribution 3880system.toL2Bus.trans_dist::UpgradeReq 493482 # Transaction distribution 3881system.toL2Bus.trans_dist::SCUpgradeReq 318513 # Transaction distribution 3882system.toL2Bus.trans_dist::UpgradeResp 811995 # Transaction distribution 3883system.toL2Bus.trans_dist::SCUpgradeFailReq 125 # Transaction distribution 3884system.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution 3885system.toL2Bus.trans_dist::ReadExReq 1145198 # Transaction distribution 3886system.toL2Bus.trans_dist::ReadExResp 1145198 # Transaction distribution 3887system.toL2Bus.trans_dist::ReadSharedReq 4810734 # Transaction distribution 3888system.toL2Bus.trans_dist::InvalidateReq 106728 # Transaction distribution 3889system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9122705 # Packet count per connected master and slave (bytes) 3890system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6709100 # Packet count per connected master and slave (bytes) 3891system.toL2Bus.pkt_count::total 15831805 # Packet count per connected master and slave (bytes) 3892system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 283955252 # Cumulative packet size per connected master and slave (bytes) 3893system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 196820081 # Cumulative packet size per connected master and slave (bytes) 3894system.toL2Bus.pkt_size::total 480775333 # Cumulative packet size per connected master and slave (bytes) 3895system.toL2Bus.snoops 3520564 # Total snoops (count) 3896system.toL2Bus.snoop_fanout::samples 13735314 # Request fanout histogram 3897system.toL2Bus.snoop_fanout::mean 0.326662 # Request fanout histogram 3898system.toL2Bus.snoop_fanout::stdev 0.470981 # Request fanout histogram 3899system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3900system.toL2Bus.snoop_fanout::0 9261350 67.43% 67.43% # Request fanout histogram 3901system.toL2Bus.snoop_fanout::1 4461125 32.48% 99.91% # Request fanout histogram 3902system.toL2Bus.snoop_fanout::2 12839 0.09% 100.00% # Request fanout histogram 3903system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3904system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3905system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3906system.toL2Bus.snoop_fanout::total 13735314 # Request fanout histogram 3907system.toL2Bus.reqLayer0.occupancy 9000721880 # Layer occupancy (ticks) 3908system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3909system.toL2Bus.snoopLayer0.occupancy 2650288 # Layer occupancy (ticks) 3910system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3911system.toL2Bus.respLayer0.occupancy 5320683808 # Layer occupancy (ticks) 3912system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3913system.toL2Bus.respLayer1.occupancy 4098533956 # Layer occupancy (ticks) 3914system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3915system.cpu0.kern.inst.arm 0 # number of arm instructions executed 3916system.cpu0.kern.inst.quiesce 13032 # number of quiesce instructions executed 3917system.cpu1.kern.inst.arm 0 # number of arm instructions executed 3918system.cpu1.kern.inst.quiesce 5368 # number of quiesce instructions executed 3919 3920---------- End Simulation Statistics ---------- 3921