stats.txt revision 11201
110515SAli.Saidi@ARM.com 210515SAli.Saidi@ARM.com---------- Begin Simulation Statistics ---------- 311201Sandreas.hansson@arm.comsim_seconds 47.314506 # Number of seconds simulated 411201Sandreas.hansson@arm.comsim_ticks 47314506373000 # Number of ticks simulated 511201Sandreas.hansson@arm.comfinal_tick 47314506373000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SAli.Saidi@ARM.comsim_freq 1000000000000 # Frequency of simulated ticks 711201Sandreas.hansson@arm.comhost_inst_rate 99848 # Simulator instruction rate (inst/s) 811201Sandreas.hansson@arm.comhost_op_rate 117399 # Simulator op (including micro ops) rate (op/s) 911201Sandreas.hansson@arm.comhost_tick_rate 5125940674 # Simulator tick rate (ticks/s) 1011201Sandreas.hansson@arm.comhost_mem_usage 814164 # Number of bytes of host memory used 1111201Sandreas.hansson@arm.comhost_seconds 9230.40 # Real time elapsed on the host 1211201Sandreas.hansson@arm.comsim_insts 921635123 # Number of instructions simulated 1311201Sandreas.hansson@arm.comsim_ops 1083644532 # Number of ops (including micro ops) simulated 1410515SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 141824 # Number of bytes read from this memory 1711201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 130048 # Number of bytes read from this memory 1811201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 4236960 # Number of bytes read from this memory 1911201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 43669256 # Number of bytes read from this memory 2011201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.l2cache.prefetcher 19384064 # Number of bytes read from this memory 2111201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 193856 # Number of bytes read from this memory 2211201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 178880 # Number of bytes read from this memory 2311201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 3171232 # Number of bytes read from this memory 2411201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 16700240 # Number of bytes read from this memory 2511201Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.l2cache.prefetcher 15629760 # Number of bytes read from this memory 2611201Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 443968 # Number of bytes read from this memory 2711201Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 103880088 # Number of bytes read from this memory 2811201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 4236960 # Number of instructions bytes read from this memory 2911201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 3171232 # Number of instructions bytes read from this memory 3011201Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 7408192 # Number of instructions bytes read from this memory 3111201Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 86326016 # Number of bytes written to this memory 3210827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3310585Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3411201Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 86346600 # Number of bytes written to this memory 3511201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 2216 # Number of read requests responded to by this memory 3611201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 2032 # Number of read requests responded to by this memory 3711201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 82155 # Number of read requests responded to by this memory 3811201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 682345 # Number of read requests responded to by this memory 3911201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.l2cache.prefetcher 302876 # Number of read requests responded to by this memory 4011201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 3029 # Number of read requests responded to by this memory 4111201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.itb.walker 2795 # Number of read requests responded to by this memory 4211201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 49594 # Number of read requests responded to by this memory 4311201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 260954 # Number of read requests responded to by this memory 4411201Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.l2cache.prefetcher 244215 # Number of read requests responded to by this memory 4511201Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6937 # Number of read requests responded to by this memory 4611201Sandreas.hansson@arm.comsystem.physmem.num_reads::total 1639148 # Number of read requests responded to by this memory 4711201Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1348844 # Number of write requests responded to by this memory 4810827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 4910585Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 5011201Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1351418 # Number of write requests responded to by this memory 5111201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 2997 # Total read bandwidth from this memory (bytes/s) 5211201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.itb.walker 2749 # Total read bandwidth from this memory (bytes/s) 5311201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 89549 # Total read bandwidth from this memory (bytes/s) 5411201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 922957 # Total read bandwidth from this memory (bytes/s) 5511201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.l2cache.prefetcher 409685 # Total read bandwidth from this memory (bytes/s) 5611201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 4097 # Total read bandwidth from this memory (bytes/s) 5711201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.itb.walker 3781 # Total read bandwidth from this memory (bytes/s) 5811201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 67025 # Total read bandwidth from this memory (bytes/s) 5911201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 352962 # Total read bandwidth from this memory (bytes/s) 6011201Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.l2cache.prefetcher 330338 # Total read bandwidth from this memory (bytes/s) 6111201Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 9383 # Total read bandwidth from this memory (bytes/s) 6211201Sandreas.hansson@arm.comsystem.physmem.bw_read::total 2195523 # Total read bandwidth from this memory (bytes/s) 6311201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 89549 # Instruction read bandwidth from this memory (bytes/s) 6411201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 67025 # Instruction read bandwidth from this memory (bytes/s) 6511201Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 156573 # Instruction read bandwidth from this memory (bytes/s) 6611201Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 1824515 # Write bandwidth from this memory (bytes/s) 6711201Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) 6810585Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 6911201Sandreas.hansson@arm.comsystem.physmem.bw_write::total 1824950 # Write bandwidth from this memory (bytes/s) 7011201Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 1824515 # Total bandwidth to/from this memory (bytes/s) 7111201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 2997 # Total bandwidth to/from this memory (bytes/s) 7211201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.itb.walker 2749 # Total bandwidth to/from this memory (bytes/s) 7311201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 89549 # Total bandwidth to/from this memory (bytes/s) 7411201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 923392 # Total bandwidth to/from this memory (bytes/s) 7511201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.l2cache.prefetcher 409685 # Total bandwidth to/from this memory (bytes/s) 7611201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 4097 # Total bandwidth to/from this memory (bytes/s) 7711201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.itb.walker 3781 # Total bandwidth to/from this memory (bytes/s) 7811201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 67025 # Total bandwidth to/from this memory (bytes/s) 7911201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 352962 # Total bandwidth to/from this memory (bytes/s) 8011201Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.l2cache.prefetcher 330338 # Total bandwidth to/from this memory (bytes/s) 8111201Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 9383 # Total bandwidth to/from this memory (bytes/s) 8211201Sandreas.hansson@arm.comsystem.physmem.bw_total::total 4020473 # Total bandwidth to/from this memory (bytes/s) 8311201Sandreas.hansson@arm.comsystem.physmem.readReqs 1639148 # Number of read requests accepted 8411201Sandreas.hansson@arm.comsystem.physmem.writeReqs 1351418 # Number of write requests accepted 8511201Sandreas.hansson@arm.comsystem.physmem.readBursts 1639148 # Number of DRAM read bursts, including those serviced by the write queue 8611201Sandreas.hansson@arm.comsystem.physmem.writeBursts 1351418 # Number of DRAM write bursts, including those merged in the write queue 8711201Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 104871744 # Total number of bytes read from DRAM 8811201Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 33728 # Total number of bytes read from write queue 8911201Sandreas.hansson@arm.comsystem.physmem.bytesWritten 86344960 # Total number of bytes written to DRAM 9011201Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 103880088 # Total read bytes from the system interface side 9111201Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 86346600 # Total written bytes from the system interface side 9211201Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 527 # Number of DRAM read bursts serviced by the write queue 9310892Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 2246 # Number of DRAM write bursts merged with an existing one 9411201Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 532498 # Number of requests that are neither read nor write 9511201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 106578 # Per bank write bursts 9611201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 104344 # Per bank write bursts 9711201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 100892 # Per bank write bursts 9811201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 102125 # Per bank write bursts 9911201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 100013 # Per bank write bursts 10011201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 109287 # Per bank write bursts 10111201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 101103 # Per bank write bursts 10211201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 99682 # Per bank write bursts 10311201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 97394 # Per bank write bursts 10411201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 128253 # Per bank write bursts 10511201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 98226 # Per bank write bursts 10611201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 99141 # Per bank write bursts 10711201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 97088 # Per bank write bursts 10811201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 102696 # Per bank write bursts 10911201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 95500 # Per bank write bursts 11011201Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 96299 # Per bank write bursts 11111201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 86551 # Per bank write bursts 11211201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 88756 # Per bank write bursts 11311201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 83871 # Per bank write bursts 11411201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 85066 # Per bank write bursts 11511201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 83226 # Per bank write bursts 11611201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 90269 # Per bank write bursts 11711201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 84251 # Per bank write bursts 11811201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 84163 # Per bank write bursts 11911201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 81439 # Per bank write bursts 12011201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 87752 # Per bank write bursts 12111201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 80936 # Per bank write bursts 12211201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 83767 # Per bank write bursts 12311201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 81736 # Per bank write bursts 12411201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 86099 # Per bank write bursts 12511201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 79882 # Per bank write bursts 12611201Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 81376 # Per bank write bursts 12710515SAli.Saidi@ARM.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 12811201Sandreas.hansson@arm.comsystem.physmem.numWrRetry 31 # Number of times write queue was full causing retry 12911201Sandreas.hansson@arm.comsystem.physmem.totGap 47314504873500 # Total gap between requests 13010515SAli.Saidi@ARM.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 13110515SAli.Saidi@ARM.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 13210515SAli.Saidi@ARM.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 13310827Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 25 # Read request sizes (log2) 13410726Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 21333 # Read request sizes (log2) 13510515SAli.Saidi@ARM.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 13611201Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 1617790 # Read request sizes (log2) 13710515SAli.Saidi@ARM.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 13810515SAli.Saidi@ARM.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 13910515SAli.Saidi@ARM.comsystem.physmem.writePktSize::2 2 # Write request sizes (log2) 14010827Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 14110515SAli.Saidi@ARM.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 14210515SAli.Saidi@ARM.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 14311201Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 1348844 # Write request sizes (log2) 14411201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 620628 # What read queue length does an incoming req see 14511201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 413232 # What read queue length does an incoming req see 14611201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 168696 # What read queue length does an incoming req see 14711201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 160410 # What read queue length does an incoming req see 14811201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 100263 # What read queue length does an incoming req see 14911201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 61902 # What read queue length does an incoming req see 15011201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 33280 # What read queue length does an incoming req see 15111201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 31024 # What read queue length does an incoming req see 15211201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 27376 # What read queue length does an incoming req see 15311201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 8356 # What read queue length does an incoming req see 15411201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 4589 # What read queue length does an incoming req see 15511201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 2828 # What read queue length does an incoming req see 15611201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 1806 # What read queue length does an incoming req see 15711201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 1455 # What read queue length does an incoming req see 15811201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 943 # What read queue length does an incoming req see 15911201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 634 # What read queue length does an incoming req see 16011201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 519 # What read queue length does an incoming req see 16111201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 410 # What read queue length does an incoming req see 16211201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 142 # What read queue length does an incoming req see 16311201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 99 # What read queue length does an incoming req see 16411201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see 16511201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 8 # What read queue length does an incoming req see 16611201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see 16711201Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 3 # What read queue length does an incoming req see 16811103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see 16911103Snilay@cs.wisc.edusystem.physmem.rdQLenPdf::25 1 # What read queue length does an incoming req see 17010628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 17110628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 17210628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 17310628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 17410628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 17510628Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 17610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 17710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 17810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 17910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 18010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 18110515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 18210515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 18310515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 18410515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 18510515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 18610515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 18710515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 18810515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 18910515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 19010515SAli.Saidi@ARM.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 19111201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 21855 # What write queue length does an incoming req see 19211201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 24510 # What write queue length does an incoming req see 19311201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 36669 # What write queue length does an incoming req see 19411201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 44426 # What write queue length does an incoming req see 19511201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 54078 # What write queue length does an incoming req see 19611201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 62537 # What write queue length does an incoming req see 19711201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 72022 # What write queue length does an incoming req see 19811201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 78343 # What write queue length does an incoming req see 19911201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 84949 # What write queue length does an incoming req see 20011201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 88390 # What write queue length does an incoming req see 20111201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 91151 # What write queue length does an incoming req see 20211201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 97634 # What write queue length does an incoming req see 20311201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 95478 # What write queue length does an incoming req see 20411201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 99505 # What write queue length does an incoming req see 20511201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 110959 # What write queue length does an incoming req see 20611201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 99115 # What write queue length does an incoming req see 20711201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 88325 # What write queue length does an incoming req see 20811201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 81966 # What write queue length does an incoming req see 20911201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 3988 # What write queue length does an incoming req see 21011201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 2451 # What write queue length does an incoming req see 21111201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 1670 # What write queue length does an incoming req see 21211201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 1309 # What write queue length does an incoming req see 21311201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 925 # What write queue length does an incoming req see 21411201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 730 # What write queue length does an incoming req see 21511201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 590 # What write queue length does an incoming req see 21611201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 476 # What write queue length does an incoming req see 21711201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 482 # What write queue length does an incoming req see 21811201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 436 # What write queue length does an incoming req see 21911201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 354 # What write queue length does an incoming req see 22011201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 335 # What write queue length does an incoming req see 22111201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 328 # What write queue length does an incoming req see 22211201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 276 # What write queue length does an incoming req see 22311201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 327 # What write queue length does an incoming req see 22411201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 365 # What write queue length does an incoming req see 22511201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 308 # What write queue length does an incoming req see 22611201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 230 # What write queue length does an incoming req see 22711201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 211 # What write queue length does an incoming req see 22811201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 237 # What write queue length does an incoming req see 22911201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 191 # What write queue length does an incoming req see 23011201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 194 # What write queue length does an incoming req see 23111201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 154 # What write queue length does an incoming req see 23211201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 116 # What write queue length does an incoming req see 23311201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 103 # What write queue length does an incoming req see 23411201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 104 # What write queue length does an incoming req see 23511201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 88 # What write queue length does an incoming req see 23611201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 66 # What write queue length does an incoming req see 23711201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 85 # What write queue length does an incoming req see 23811201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 53 # What write queue length does an incoming req see 23911201Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 63 # What write queue length does an incoming req see 24011201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 1061449 # Bytes accessed per row activation 24111201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 180.146498 # Bytes accessed per row activation 24211201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 111.187522 # Bytes accessed per row activation 24311201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 239.320652 # Bytes accessed per row activation 24411201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 660214 62.20% 62.20% # Bytes accessed per row activation 24511201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 197053 18.56% 80.76% # Bytes accessed per row activation 24611201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 62946 5.93% 86.69% # Bytes accessed per row activation 24711201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 34930 3.29% 89.98% # Bytes accessed per row activation 24811201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 24785 2.34% 92.32% # Bytes accessed per row activation 24911201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 13743 1.29% 93.61% # Bytes accessed per row activation 25011201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 13849 1.30% 94.92% # Bytes accessed per row activation 25111201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 7639 0.72% 95.64% # Bytes accessed per row activation 25211201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 46290 4.36% 100.00% # Bytes accessed per row activation 25311201Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 1061449 # Bytes accessed per row activation 25411201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 76381 # Reads before turning the bus around for writes 25511201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 21.453032 # Reads before turning the bus around for writes 25611201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 249.608933 # Reads before turning the bus around for writes 25711201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-4095 76378 100.00% 100.00% # Reads before turning the bus around for writes 25811138Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes 25910892Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::8192-12287 1 0.00% 100.00% # Reads before turning the bus around for writes 26011138Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::65536-69631 1 0.00% 100.00% # Reads before turning the bus around for writes 26111201Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 76381 # Reads before turning the bus around for writes 26211201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 76381 # Writes before turning the bus around for reads 26311201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 17.663293 # Writes before turning the bus around for reads 26411201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 17.185244 # Writes before turning the bus around for reads 26511201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 6.515109 # Writes before turning the bus around for reads 26611201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-19 70865 92.78% 92.78% # Writes before turning the bus around for reads 26711201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::20-23 3094 4.05% 96.83% # Writes before turning the bus around for reads 26811201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::24-27 460 0.60% 97.43% # Writes before turning the bus around for reads 26911201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::28-31 346 0.45% 97.88% # Writes before turning the bus around for reads 27011201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-35 86 0.11% 98.00% # Writes before turning the bus around for reads 27111201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::36-39 303 0.40% 98.39% # Writes before turning the bus around for reads 27211201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::40-43 170 0.22% 98.62% # Writes before turning the bus around for reads 27311201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::44-47 108 0.14% 98.76% # Writes before turning the bus around for reads 27411201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-51 111 0.15% 98.90% # Writes before turning the bus around for reads 27511201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::52-55 84 0.11% 99.01% # Writes before turning the bus around for reads 27611201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::56-59 42 0.05% 99.07% # Writes before turning the bus around for reads 27711201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::60-63 72 0.09% 99.16% # Writes before turning the bus around for reads 27811201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-67 382 0.50% 99.66% # Writes before turning the bus around for reads 27911201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::68-71 49 0.06% 99.73% # Writes before turning the bus around for reads 28011201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::72-75 51 0.07% 99.79% # Writes before turning the bus around for reads 28111201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::76-79 81 0.11% 99.90% # Writes before turning the bus around for reads 28211201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-83 17 0.02% 99.92% # Writes before turning the bus around for reads 28311201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::84-87 3 0.00% 99.93% # Writes before turning the bus around for reads 28411201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::88-91 1 0.00% 99.93% # Writes before turning the bus around for reads 28511201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::92-95 3 0.00% 99.93% # Writes before turning the bus around for reads 28611201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::96-99 1 0.00% 99.93% # Writes before turning the bus around for reads 28711201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::100-103 3 0.00% 99.94% # Writes before turning the bus around for reads 28811201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads 28911201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::108-111 1 0.00% 99.94% # Writes before turning the bus around for reads 29011201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-115 2 0.00% 99.94% # Writes before turning the bus around for reads 29111201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::124-127 4 0.01% 99.95% # Writes before turning the bus around for reads 29211201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-131 25 0.03% 99.98% # Writes before turning the bus around for reads 29311201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads 29411201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads 29511201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::140-143 1 0.00% 99.98% # Writes before turning the bus around for reads 29611201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-147 1 0.00% 99.98% # Writes before turning the bus around for reads 29711201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::148-151 1 0.00% 99.99% # Writes before turning the bus around for reads 29811201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::152-155 3 0.00% 99.99% # Writes before turning the bus around for reads 29911201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads 30011201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::164-167 3 0.00% 99.99% # Writes before turning the bus around for reads 30111201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::168-171 2 0.00% 100.00% # Writes before turning the bus around for reads 30211201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::172-175 1 0.00% 100.00% # Writes before turning the bus around for reads 30311201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads 30411201Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 76381 # Writes before turning the bus around for reads 30511201Sandreas.hansson@arm.comsystem.physmem.totQLat 70826288095 # Total ticks spent queuing 30611201Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 101550431845 # Total ticks spent from burst creation until serviced by the DRAM 30711201Sandreas.hansson@arm.comsystem.physmem.totBusLat 8193105000 # Total ticks spent in databus transfers 30811201Sandreas.hansson@arm.comsystem.physmem.avgQLat 43223.11 # Average queueing delay per DRAM burst 30910515SAli.Saidi@ARM.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 31011201Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 61973.11 # Average memory access latency per DRAM burst 31111201Sandreas.hansson@arm.comsystem.physmem.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s 31211201Sandreas.hansson@arm.comsystem.physmem.avgWrBW 1.82 # Average achieved write bandwidth in MiByte/s 31311201Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 2.20 # Average system read bandwidth in MiByte/s 31411201Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 1.82 # Average system write bandwidth in MiByte/s 31510515SAli.Saidi@ARM.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 31610628Sandreas.hansson@arm.comsystem.physmem.busUtil 0.03 # Data bus utilization in percentage 31710892Sandreas.hansson@arm.comsystem.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 31811103Snilay@cs.wisc.edusystem.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 31911201Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.33 # Average read queue length when enqueuing 32011201Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 26.65 # Average write queue length when enqueuing 32111201Sandreas.hansson@arm.comsystem.physmem.readRowHits 1314681 # Number of row buffer hits during reads 32211201Sandreas.hansson@arm.comsystem.physmem.writeRowHits 611629 # Number of row buffer hits during writes 32311201Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 80.23 # Row buffer hit rate for reads 32411201Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 45.33 # Row buffer hit rate for writes 32511201Sandreas.hansson@arm.comsystem.physmem.avgGap 15821254.20 # Average gap between requests 32611201Sandreas.hansson@arm.comsystem.physmem.pageHitRate 64.47 # Row buffer hit rate, read and write combined 32711201Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 4090980600 # Energy for activate commands per rank (pJ) 32811201Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 2232181875 # Energy for precharge commands per rank (pJ) 32911201Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 6427387200 # Energy for read commands per rank (pJ) 33011201Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 4446271440 # Energy for write commands per rank (pJ) 33111201Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 3090353329440 # Energy for refresh commands per rank (pJ) 33211201Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 1181376195975 # Energy for active background per rank (pJ) 33311201Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 27352407006750 # Energy for precharge background per rank (pJ) 33411201Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 31641333353280 # Total energy per rank (pJ) 33511201Sandreas.hansson@arm.comsystem.physmem_0.averagePower 668.744914 # Core power per rank (mW) 33611201Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 45502947755010 # Time in different power states 33711201Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 1579935240000 # Time in different power states 33810628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 33911201Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 231620211240 # Time in different power states 34010628Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 34111201Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 3933573840 # Energy for activate commands per rank (pJ) 34211201Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 2146295250 # Energy for precharge commands per rank (pJ) 34311201Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 6353809800 # Energy for read commands per rank (pJ) 34411201Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 4296155760 # Energy for write commands per rank (pJ) 34511201Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 3090353329440 # Energy for refresh commands per rank (pJ) 34611201Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 1178540083170 # Energy for active background per rank (pJ) 34711201Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 27354894825000 # Energy for precharge background per rank (pJ) 34811201Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 31640518072260 # Total energy per rank (pJ) 34911201Sandreas.hansson@arm.comsystem.physmem_1.averagePower 668.727683 # Core power per rank (mW) 35011201Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 45507092069935 # Time in different power states 35111201Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 1579935240000 # Time in different power states 35210628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 35311201Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 227478372065 # Time in different power states 35410628Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 35511201Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory 35610576Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 35710576Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory 35810576Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 35911201Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_read::total 556 # Number of bytes read from this memory 36011201Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_inst_read::cpu0.inst 368 # Number of instructions bytes read from this memory 36110576Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory 36211201Sandreas.hansson@arm.comsystem.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory 36311201Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::cpu0.inst 23 # Number of read requests responded to by this memory 36410576Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 36510576Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory 36610576Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 36711201Sandreas.hansson@arm.comsystem.realview.nvmem.num_reads::total 38 # Number of read requests responded to by this memory 36810576Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) 36910576Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 37010576Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::cpu1.inst 3 # Total read bandwidth from this memory (bytes/s) 37110576Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 37210576Sandreas.hansson@arm.comsystem.realview.nvmem.bw_read::total 12 # Total read bandwidth from this memory (bytes/s) 37310576Sandreas.hansson@arm.comsystem.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) 37410576Sandreas.hansson@arm.comsystem.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s) 37510576Sandreas.hansson@arm.comsystem.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s) 37610576Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) 37710576Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 37810576Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) 37910576Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 38010576Sandreas.hansson@arm.comsystem.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) 38110576Sandreas.hansson@arm.comsystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 38210576Sandreas.hansson@arm.comsystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 38310576Sandreas.hansson@arm.comsystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 38410576Sandreas.hansson@arm.comsystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 38510576Sandreas.hansson@arm.comsystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 38610576Sandreas.hansson@arm.comsystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 38711201Sandreas.hansson@arm.comsystem.cpu0.branchPred.lookups 132773230 # Number of BP lookups 38811201Sandreas.hansson@arm.comsystem.cpu0.branchPred.condPredicted 87983669 # Number of conditional branches predicted 38911201Sandreas.hansson@arm.comsystem.cpu0.branchPred.condIncorrect 6601963 # Number of conditional branches incorrect 39011201Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBLookups 93351299 # Number of BTB lookups 39111201Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBHits 61553732 # Number of BTB hits 39210576Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 39311201Sandreas.hansson@arm.comsystem.cpu0.branchPred.BTBHitPct 65.937735 # BTB Hit Percentage 39411201Sandreas.hansson@arm.comsystem.cpu0.branchPred.usedRAS 18245658 # Number of times the RAS was used to get a target. 39511201Sandreas.hansson@arm.comsystem.cpu0.branchPred.RASInCorrect 197691 # Number of incorrect RAS predictions. 39610515SAli.Saidi@ARM.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 39710628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 39810628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 39910628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 40010628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 40110628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 40210628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 40310628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 40410628Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 40510576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 40610576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 40710576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 40810576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 40910576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 41010576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 41110576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 41210576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 41310576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 41410576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 41510576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 41610576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 41710576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 41810576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 41910576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 42010576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 42110576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 42210576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 42310576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 42410576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 42510576Sandreas.hansson@arm.comsystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 42611201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walks 574649 # Table walker walks requested 42711201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLong 574649 # Table walker walks initiated with long descriptors 42811201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level2 12370 # Level at which table walker walks with long descriptors terminate 42911201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level3 88781 # Level at which table walker walks with long descriptors terminate 43011201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksSquashedBefore 269295 # Table walks squashed before starting 43111201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 305354 # Table walker wait (enqueue to first request) latency 43211201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::mean 2428.535405 # Table walker wait (enqueue to first request) latency 43311201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::stdev 14847.246962 # Table walker wait (enqueue to first request) latency 43411201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0-65535 302828 99.17% 99.17% # Table walker wait (enqueue to first request) latency 43511201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::65536-131071 1395 0.46% 99.63% # Table walker wait (enqueue to first request) latency 43611201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::131072-196607 849 0.28% 99.91% # Table walker wait (enqueue to first request) latency 43711201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::196608-262143 146 0.05% 99.96% # Table walker wait (enqueue to first request) latency 43811201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::262144-327679 44 0.01% 99.97% # Table walker wait (enqueue to first request) latency 43911201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::327680-393215 73 0.02% 99.99% # Table walker wait (enqueue to first request) latency 44011201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::393216-458751 14 0.00% 100.00% # Table walker wait (enqueue to first request) latency 44111167Sjthestness@gmail.comsystem.cpu0.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 44211201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 44311167Sjthestness@gmail.comsystem.cpu0.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 44411201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 305354 # Table walker wait (enqueue to first request) latency 44511201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::samples 295785 # Table walker service (enqueue to completion) latency 44611201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::mean 20483.935967 # Table walker service (enqueue to completion) latency 44711201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::gmean 17662.897721 # Table walker service (enqueue to completion) latency 44811201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::stdev 19270.228379 # Table walker service (enqueue to completion) latency 44911201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::0-65535 292925 99.03% 99.03% # Table walker service (enqueue to completion) latency 45011201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::65536-131071 638 0.22% 99.25% # Table walker service (enqueue to completion) latency 45111201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::131072-196607 1609 0.54% 99.79% # Table walker service (enqueue to completion) latency 45211201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::196608-262143 142 0.05% 99.84% # Table walker service (enqueue to completion) latency 45311201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::262144-327679 290 0.10% 99.94% # Table walker service (enqueue to completion) latency 45411201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::327680-393215 80 0.03% 99.97% # Table walker service (enqueue to completion) latency 45511201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::393216-458751 60 0.02% 99.99% # Table walker service (enqueue to completion) latency 45611201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::458752-524287 29 0.01% 100.00% # Table walker service (enqueue to completion) latency 45711201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::524288-589823 11 0.00% 100.00% # Table walker service (enqueue to completion) latency 45811201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 45911201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::total 295785 # Table walker service (enqueue to completion) latency 46011201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::samples 533721818468 # Table walker pending requests distribution 46111201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::mean 0.601728 # Table walker pending requests distribution 46211201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::stdev 0.544409 # Table walker pending requests distribution 46311201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::0-1 532429522968 99.76% 99.76% # Table walker pending requests distribution 46411201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::2-3 722596500 0.14% 99.89% # Table walker pending requests distribution 46511201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::4-5 256398500 0.05% 99.94% # Table walker pending requests distribution 46611201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::6-7 121663500 0.02% 99.96% # Table walker pending requests distribution 46711201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::8-9 95265000 0.02% 99.98% # Table walker pending requests distribution 46811201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::10-11 53651000 0.01% 99.99% # Table walker pending requests distribution 46911201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::12-13 19676500 0.00% 100.00% # Table walker pending requests distribution 47011201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::14-15 22307000 0.00% 100.00% # Table walker pending requests distribution 47111201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::16-17 728500 0.00% 100.00% # Table walker pending requests distribution 47211201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::18-19 9000 0.00% 100.00% # Table walker pending requests distribution 47311201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::total 533721818468 # Table walker pending requests distribution 47411201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 88781 87.77% 87.77% # Table walker page sizes translated 47511201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 12370 12.23% 100.00% # Table walker page sizes translated 47611201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 101151 # Table walker page sizes translated 47711201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 574649 # Table walker requests started/completed, data/inst 47810628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 47911201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 574649 # Table walker requests started/completed, data/inst 48011201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 101151 # Table walker requests started/completed, data/inst 48110628Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 48211201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 101151 # Table walker requests started/completed, data/inst 48311201Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 675800 # Table walker requests started/completed, data/inst 48410576Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_hits 0 # ITB inst hits 48510576Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_misses 0 # ITB inst misses 48611201Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 96498807 # DTB read hits 48711201Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 413728 # DTB read misses 48811201Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 78559139 # DTB write hits 48911201Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 160921 # DTB write misses 49011103Snilay@cs.wisc.edusystem.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 49110576Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 49211201Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 44695 # Number of times TLB was flushed by MVA & ASID 49311201Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID 49411201Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_entries 38359 # Number of entries that have been flushed from TLB 49511201Sandreas.hansson@arm.comsystem.cpu0.dtb.align_faults 510 # Number of TLB faults due to alignment restrictions 49611201Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 7352 # Number of TLB faults due to prefetch 49710576Sandreas.hansson@arm.comsystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 49811201Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 37571 # Number of TLB faults due to permissions restrictions 49911201Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 96912535 # DTB read accesses 50011201Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 78720060 # DTB write accesses 50110576Sandreas.hansson@arm.comsystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 50211201Sandreas.hansson@arm.comsystem.cpu0.dtb.hits 175057946 # DTB hits 50311201Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 574649 # DTB misses 50411201Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 175632595 # DTB accesses 50510628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 50610628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 50710628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 50810628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 50910628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 51010628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 51110628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 51210628Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 51310576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 51410576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 51510576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 51610576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 51710576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 51810576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 51910576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 52010576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 52110576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 52210576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 52310576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 52410576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 52510576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 52610576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 52710576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 52810576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 52910576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 53010576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 53110576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 53210576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 53310576Sandreas.hansson@arm.comsystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 53411201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walks 78486 # Table walker walks requested 53511201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLong 78486 # Table walker walks initiated with long descriptors 53611201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level2 887 # Level at which table walker walks with long descriptors terminate 53711201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level3 55688 # Level at which table walker walks with long descriptors terminate 53811201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksSquashedBefore 9272 # Table walks squashed before starting 53911201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 69214 # Table walker wait (enqueue to first request) latency 54011201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::mean 1487.228017 # Table walker wait (enqueue to first request) latency 54111201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::stdev 11268.156243 # Table walker wait (enqueue to first request) latency 54211201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::0-32767 68484 98.95% 98.95% # Table walker wait (enqueue to first request) latency 54311201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::32768-65535 441 0.64% 99.58% # Table walker wait (enqueue to first request) latency 54411201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::65536-98303 31 0.04% 99.63% # Table walker wait (enqueue to first request) latency 54511201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::98304-131071 33 0.05% 99.67% # Table walker wait (enqueue to first request) latency 54611201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::131072-163839 145 0.21% 99.88% # Table walker wait (enqueue to first request) latency 54711201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::163840-196607 56 0.08% 99.97% # Table walker wait (enqueue to first request) latency 54811201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.97% # Table walker wait (enqueue to first request) latency 54911201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.98% # Table walker wait (enqueue to first request) latency 55011201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::262144-294911 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency 55111201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::294912-327679 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency 55211201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 55311167Sjthestness@gmail.comsystem.cpu0.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 55411201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 69214 # Table walker wait (enqueue to first request) latency 55511201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::samples 65847 # Table walker service (enqueue to completion) latency 55611201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::mean 26575.804517 # Table walker service (enqueue to completion) latency 55711201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::gmean 22865.862438 # Table walker service (enqueue to completion) latency 55811201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::stdev 26620.164914 # Table walker service (enqueue to completion) latency 55911201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::0-65535 64258 97.59% 97.59% # Table walker service (enqueue to completion) latency 56011201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::65536-131071 112 0.17% 97.76% # Table walker service (enqueue to completion) latency 56111201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::131072-196607 1232 1.87% 99.63% # Table walker service (enqueue to completion) latency 56211201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::196608-262143 99 0.15% 99.78% # Table walker service (enqueue to completion) latency 56311201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::262144-327679 79 0.12% 99.90% # Table walker service (enqueue to completion) latency 56411201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::327680-393215 35 0.05% 99.95% # Table walker service (enqueue to completion) latency 56511201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::393216-458751 19 0.03% 99.98% # Table walker service (enqueue to completion) latency 56611201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::458752-524287 11 0.02% 100.00% # Table walker service (enqueue to completion) latency 56711201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 56811201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 56911201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::total 65847 # Table walker service (enqueue to completion) latency 57011201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::samples 404869617088 # Table walker pending requests distribution 57111201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::mean 0.839049 # Table walker pending requests distribution 57211201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::stdev 0.367685 # Table walker pending requests distribution 57311201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::0 65190904252 16.10% 16.10% # Table walker pending requests distribution 57411201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::1 339654890336 83.89% 99.99% # Table walker pending requests distribution 57511201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::2 21211000 0.01% 100.00% # Table walker pending requests distribution 57611201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::3 2423500 0.00% 100.00% # Table walker pending requests distribution 57711167Sjthestness@gmail.comsystem.cpu0.itb.walker.walksPending::4 188000 0.00% 100.00% # Table walker pending requests distribution 57811201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksPending::total 404869617088 # Table walker pending requests distribution 57911201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 55688 98.43% 98.43% # Table walker page sizes translated 58011201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::2M 887 1.57% 100.00% # Table walker page sizes translated 58111201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 56575 # Table walker page sizes translated 58210628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 58311201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 78486 # Table walker requests started/completed, data/inst 58411201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 78486 # Table walker requests started/completed, data/inst 58510628Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 58611201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56575 # Table walker requests started/completed, data/inst 58711201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 56575 # Table walker requests started/completed, data/inst 58811201Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 135061 # Table walker requests started/completed, data/inst 58911201Sandreas.hansson@arm.comsystem.cpu0.itb.inst_hits 209228100 # ITB inst hits 59011201Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 78486 # ITB inst misses 59110576Sandreas.hansson@arm.comsystem.cpu0.itb.read_hits 0 # DTB read hits 59210576Sandreas.hansson@arm.comsystem.cpu0.itb.read_misses 0 # DTB read misses 59310576Sandreas.hansson@arm.comsystem.cpu0.itb.write_hits 0 # DTB write hits 59410576Sandreas.hansson@arm.comsystem.cpu0.itb.write_misses 0 # DTB write misses 59511103Snilay@cs.wisc.edusystem.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 59610576Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 59711201Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 44695 # Number of times TLB was flushed by MVA & ASID 59811201Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID 59911201Sandreas.hansson@arm.comsystem.cpu0.itb.flush_entries 27529 # Number of entries that have been flushed from TLB 60010576Sandreas.hansson@arm.comsystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 60110576Sandreas.hansson@arm.comsystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 60210576Sandreas.hansson@arm.comsystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 60311201Sandreas.hansson@arm.comsystem.cpu0.itb.perms_faults 202656 # Number of TLB faults due to permissions restrictions 60410576Sandreas.hansson@arm.comsystem.cpu0.itb.read_accesses 0 # DTB read accesses 60510576Sandreas.hansson@arm.comsystem.cpu0.itb.write_accesses 0 # DTB write accesses 60611201Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 209306586 # ITB inst accesses 60711201Sandreas.hansson@arm.comsystem.cpu0.itb.hits 209228100 # DTB hits 60811201Sandreas.hansson@arm.comsystem.cpu0.itb.misses 78486 # DTB misses 60911201Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 209306586 # DTB accesses 61011201Sandreas.hansson@arm.comsystem.cpu0.numCycles 789288757 # number of cpu cycles simulated 61110576Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 61210576Sandreas.hansson@arm.comsystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 61311201Sandreas.hansson@arm.comsystem.cpu0.fetch.icacheStallCycles 88186567 # Number of cycles fetch is stalled on an Icache miss 61411201Sandreas.hansson@arm.comsystem.cpu0.fetch.Insts 587222731 # Number of instructions fetch has processed 61511201Sandreas.hansson@arm.comsystem.cpu0.fetch.Branches 132773230 # Number of branches that fetch encountered 61611201Sandreas.hansson@arm.comsystem.cpu0.fetch.predictedBranches 79799390 # Number of branches that fetch has predicted taken 61711201Sandreas.hansson@arm.comsystem.cpu0.fetch.Cycles 653950437 # Number of cycles fetch has run and was not squashing or blocked 61811201Sandreas.hansson@arm.comsystem.cpu0.fetch.SquashCycles 14236776 # Number of cycles fetch has spent squashing 61911201Sandreas.hansson@arm.comsystem.cpu0.fetch.TlbCycles 1849931 # Number of cycles fetch has spent waiting for tlb 62011201Sandreas.hansson@arm.comsystem.cpu0.fetch.MiscStallCycles 326899 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 62111201Sandreas.hansson@arm.comsystem.cpu0.fetch.PendingTrapStallCycles 5945958 # Number of stall cycles due to pending traps 62211201Sandreas.hansson@arm.comsystem.cpu0.fetch.PendingQuiesceStallCycles 775108 # Number of stall cycles due to pending quiesce instructions 62311201Sandreas.hansson@arm.comsystem.cpu0.fetch.IcacheWaitRetryStallCycles 835772 # Number of stall cycles due to full MSHR 62411201Sandreas.hansson@arm.comsystem.cpu0.fetch.CacheLines 209027134 # Number of cache lines fetched 62511201Sandreas.hansson@arm.comsystem.cpu0.fetch.IcacheSquashes 1689441 # Number of outstanding Icache misses that were squashed 62611201Sandreas.hansson@arm.comsystem.cpu0.fetch.ItlbSquashes 26384 # Number of outstanding ITLB misses that were squashed 62711201Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::samples 758989060 # Number of instructions fetched each cycle (Total) 62811201Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::mean 0.905560 # Number of instructions fetched each cycle (Total) 62911201Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::stdev 1.200949 # Number of instructions fetched each cycle (Total) 63010576Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 63111201Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::0 429796828 56.63% 56.63% # Number of instructions fetched each cycle (Total) 63211201Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::1 127839256 16.84% 73.47% # Number of instructions fetched each cycle (Total) 63311201Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::2 44588296 5.87% 79.35% # Number of instructions fetched each cycle (Total) 63411201Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::3 156764680 20.65% 100.00% # Number of instructions fetched each cycle (Total) 63510576Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 63610576Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 63710576Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 63811201Sandreas.hansson@arm.comsystem.cpu0.fetch.rateDist::total 758989060 # Number of instructions fetched each cycle (Total) 63911201Sandreas.hansson@arm.comsystem.cpu0.fetch.branchRate 0.168219 # Number of branch fetches per cycle 64011201Sandreas.hansson@arm.comsystem.cpu0.fetch.rate 0.743990 # Number of inst fetches per cycle 64111201Sandreas.hansson@arm.comsystem.cpu0.decode.IdleCycles 104466806 # Number of cycles decode is idle 64211201Sandreas.hansson@arm.comsystem.cpu0.decode.BlockedCycles 394260374 # Number of cycles decode is blocked 64311201Sandreas.hansson@arm.comsystem.cpu0.decode.RunCycles 219139619 # Number of cycles decode is running 64411201Sandreas.hansson@arm.comsystem.cpu0.decode.UnblockCycles 36084867 # Number of cycles decode is unblocking 64511201Sandreas.hansson@arm.comsystem.cpu0.decode.SquashCycles 5037394 # Number of cycles decode is squashing 64611201Sandreas.hansson@arm.comsystem.cpu0.decode.BranchResolved 19164568 # Number of times decode resolved a branch 64711201Sandreas.hansson@arm.comsystem.cpu0.decode.BranchMispred 2120604 # Number of times decode detected a branch misprediction 64811201Sandreas.hansson@arm.comsystem.cpu0.decode.DecodedInsts 606612799 # Number of instructions handled by decode 64911201Sandreas.hansson@arm.comsystem.cpu0.decode.SquashedInsts 22830363 # Number of squashed instructions handled by decode 65011201Sandreas.hansson@arm.comsystem.cpu0.rename.SquashCycles 5037394 # Number of cycles rename is squashing 65111201Sandreas.hansson@arm.comsystem.cpu0.rename.IdleCycles 138662412 # Number of cycles rename is idle 65211201Sandreas.hansson@arm.comsystem.cpu0.rename.BlockCycles 63104555 # Number of cycles rename is blocking 65311201Sandreas.hansson@arm.comsystem.cpu0.rename.serializeStallCycles 247113571 # count of cycles rename stalled for serializing inst 65411201Sandreas.hansson@arm.comsystem.cpu0.rename.RunCycles 220473798 # Number of cycles rename is running 65511201Sandreas.hansson@arm.comsystem.cpu0.rename.UnblockCycles 84597330 # Number of cycles rename is unblocking 65611201Sandreas.hansson@arm.comsystem.cpu0.rename.RenamedInsts 589875332 # Number of instructions processed by rename 65711201Sandreas.hansson@arm.comsystem.cpu0.rename.SquashedInsts 5798642 # Number of squashed instructions processed by rename 65811201Sandreas.hansson@arm.comsystem.cpu0.rename.ROBFullEvents 10641909 # Number of times rename has blocked due to ROB full 65911201Sandreas.hansson@arm.comsystem.cpu0.rename.IQFullEvents 381250 # Number of times rename has blocked due to IQ full 66011201Sandreas.hansson@arm.comsystem.cpu0.rename.LQFullEvents 853231 # Number of times rename has blocked due to LQ full 66111201Sandreas.hansson@arm.comsystem.cpu0.rename.SQFullEvents 50687884 # Number of times rename has blocked due to SQ full 66211201Sandreas.hansson@arm.comsystem.cpu0.rename.FullRegisterEvents 10092 # Number of times there has been no free registers 66311201Sandreas.hansson@arm.comsystem.cpu0.rename.RenamedOperands 564041119 # Number of destination operands rename has renamed 66411201Sandreas.hansson@arm.comsystem.cpu0.rename.RenameLookups 911558490 # Number of register rename lookups that rename has made 66511201Sandreas.hansson@arm.comsystem.cpu0.rename.int_rename_lookups 696481853 # Number of integer rename lookups 66611201Sandreas.hansson@arm.comsystem.cpu0.rename.fp_rename_lookups 699850 # Number of floating rename lookups 66711201Sandreas.hansson@arm.comsystem.cpu0.rename.CommittedMaps 508008632 # Number of HB maps that are committed 66811201Sandreas.hansson@arm.comsystem.cpu0.rename.UndoneMaps 56032481 # Number of HB maps that are undone due to squashing 66911201Sandreas.hansson@arm.comsystem.cpu0.rename.serializingInsts 14857922 # count of serializing insts renamed 67011201Sandreas.hansson@arm.comsystem.cpu0.rename.tempSerializingInsts 12905611 # count of temporary serializing insts renamed 67111201Sandreas.hansson@arm.comsystem.cpu0.rename.skidInsts 72985645 # count of insts added to the skid buffer 67211201Sandreas.hansson@arm.comsystem.cpu0.memDep0.insertedLoads 96647129 # Number of loads inserted to the mem dependence unit. 67311201Sandreas.hansson@arm.comsystem.cpu0.memDep0.insertedStores 81788442 # Number of stores inserted to the mem dependence unit. 67411201Sandreas.hansson@arm.comsystem.cpu0.memDep0.conflictingLoads 8697028 # Number of conflicting loads. 67511201Sandreas.hansson@arm.comsystem.cpu0.memDep0.conflictingStores 7422933 # Number of conflicting stores. 67611201Sandreas.hansson@arm.comsystem.cpu0.iq.iqInstsAdded 568689811 # Number of instructions added to the IQ (excludes non-spec) 67711201Sandreas.hansson@arm.comsystem.cpu0.iq.iqNonSpecInstsAdded 14912069 # Number of non-speculative instructions added to the IQ 67811201Sandreas.hansson@arm.comsystem.cpu0.iq.iqInstsIssued 572654206 # Number of instructions issued 67911201Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedInstsIssued 2621739 # Number of squashed instructions issued 68011201Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedInstsExamined 52458189 # Number of squashed instructions iterated over during squash; mainly for profiling 68111201Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedOperandsExamined 34404562 # Number of squashed operands that are examined and possibly removed from graph 68211201Sandreas.hansson@arm.comsystem.cpu0.iq.iqSquashedNonSpecRemoved 258659 # Number of squashed non-spec instructions that were removed 68311201Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::samples 758989060 # Number of insts issued each cycle 68411201Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::mean 0.754496 # Number of insts issued each cycle 68511201Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::stdev 1.046900 # Number of insts issued each cycle 68610576Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 68711201Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::0 446419238 58.82% 58.82% # Number of insts issued each cycle 68811201Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::1 130584028 17.20% 76.02% # Number of insts issued each cycle 68911201Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::2 111330924 14.67% 90.69% # Number of insts issued each cycle 69011201Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::3 63215854 8.33% 99.02% # Number of insts issued each cycle 69111201Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::4 7434312 0.98% 100.00% # Number of insts issued each cycle 69211201Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::5 4704 0.00% 100.00% # Number of insts issued each cycle 69310726Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 69410576Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 69510576Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 69610576Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 69710576Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 69810726Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 69911201Sandreas.hansson@arm.comsystem.cpu0.iq.issued_per_cycle::total 758989060 # Number of insts issued each cycle 70010576Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 70111201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::IntAlu 59334745 45.62% 45.62% # attempts to use FU when none available 70211201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::IntMult 61701 0.05% 45.67% # attempts to use FU when none available 70311201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::IntDiv 15638 0.01% 45.68% # attempts to use FU when none available 70411201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.68% # attempts to use FU when none available 70511201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.68% # attempts to use FU when none available 70611201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.68% # attempts to use FU when none available 70711201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatMult 0 0.00% 45.68% # attempts to use FU when none available 70811201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.68% # attempts to use FU when none available 70911201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.68% # attempts to use FU when none available 71011201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.68% # attempts to use FU when none available 71111201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.68% # attempts to use FU when none available 71211201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.68% # attempts to use FU when none available 71311201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.68% # attempts to use FU when none available 71411201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.68% # attempts to use FU when none available 71511201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.68% # attempts to use FU when none available 71611201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdMult 0 0.00% 45.68% # attempts to use FU when none available 71711201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.68% # attempts to use FU when none available 71811201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdShift 0 0.00% 45.68% # attempts to use FU when none available 71911201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.68% # attempts to use FU when none available 72011201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.68% # attempts to use FU when none available 72111201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.68% # attempts to use FU when none available 72211201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.68% # attempts to use FU when none available 72311201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.68% # attempts to use FU when none available 72411201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.68% # attempts to use FU when none available 72511201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.68% # attempts to use FU when none available 72611201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatMisc 17 0.00% 45.68% # attempts to use FU when none available 72711201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.68% # attempts to use FU when none available 72811201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.68% # attempts to use FU when none available 72911201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.68% # attempts to use FU when none available 73011201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::MemRead 34211739 26.30% 71.98% # attempts to use FU when none available 73111201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::MemWrite 36440950 28.02% 100.00% # attempts to use FU when none available 73210576Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 73310576Sandreas.hansson@arm.comsystem.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 73411201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued 73511201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IntAlu 391815865 68.42% 68.42% # Type of FU issued 73611201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IntMult 1438003 0.25% 68.67% # Type of FU issued 73711201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IntDiv 75602 0.01% 68.69% # Type of FU issued 73811201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.69% # Type of FU issued 73911201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.69% # Type of FU issued 74011201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.69% # Type of FU issued 74111201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.69% # Type of FU issued 74211201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.69% # Type of FU issued 74311201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.69% # Type of FU issued 74411201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.69% # Type of FU issued 74511201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.69% # Type of FU issued 74611201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.69% # Type of FU issued 74711201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.69% # Type of FU issued 74811201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.69% # Type of FU issued 74911201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.69% # Type of FU issued 75011201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.69% # Type of FU issued 75111201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.69% # Type of FU issued 75211201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.69% # Type of FU issued 75311201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.69% # Type of FU issued 75411201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.69% # Type of FU issued 75511201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.69% # Type of FU issued 75611201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.69% # Type of FU issued 75711201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.69% # Type of FU issued 75811201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.69% # Type of FU issued 75911201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.69% # Type of FU issued 76011201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMisc 42288 0.01% 68.69% # Type of FU issued 76111201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.69% # Type of FU issued 76211201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.69% # Type of FU issued 76311201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.69% # Type of FU issued 76411201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::MemRead 99488891 17.37% 86.07% # Type of FU issued 76511201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::MemWrite 79793556 13.93% 100.00% # Type of FU issued 76610576Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 76710576Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 76811201Sandreas.hansson@arm.comsystem.cpu0.iq.FU_type_0::total 572654206 # Type of FU issued 76911201Sandreas.hansson@arm.comsystem.cpu0.iq.rate 0.725532 # Inst issue rate 77011201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_busy_cnt 130064790 # FU busy when requested 77111201Sandreas.hansson@arm.comsystem.cpu0.iq.fu_busy_rate 0.227126 # FU busy rate (busy events/executed inst) 77211201Sandreas.hansson@arm.comsystem.cpu0.iq.int_inst_queue_reads 2035873022 # Number of integer instruction queue reads 77311201Sandreas.hansson@arm.comsystem.cpu0.iq.int_inst_queue_writes 635743875 # Number of integer instruction queue writes 77411201Sandreas.hansson@arm.comsystem.cpu0.iq.int_inst_queue_wakeup_accesses 556160378 # Number of integer instruction queue wakeup accesses 77511201Sandreas.hansson@arm.comsystem.cpu0.iq.fp_inst_queue_reads 1110977 # Number of floating instruction queue reads 77611201Sandreas.hansson@arm.comsystem.cpu0.iq.fp_inst_queue_writes 443650 # Number of floating instruction queue writes 77711201Sandreas.hansson@arm.comsystem.cpu0.iq.fp_inst_queue_wakeup_accesses 409772 # Number of floating instruction queue wakeup accesses 77811201Sandreas.hansson@arm.comsystem.cpu0.iq.int_alu_accesses 702028683 # Number of integer alu accesses 77911201Sandreas.hansson@arm.comsystem.cpu0.iq.fp_alu_accesses 690312 # Number of floating point alu accesses 78011201Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.forwLoads 2617659 # Number of loads that had data forwarded from stores 78110576Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 78211201Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.squashedLoads 11976787 # Number of loads squashed 78311201Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.ignoredResponses 15696 # Number of memory responses ignored because the instruction is squashed 78411201Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.memOrderViolation 128509 # Number of memory ordering violations 78511201Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.squashedStores 5549515 # Number of stores squashed 78610576Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 78710576Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 78811201Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.rescheduledLoads 2485031 # Number of loads that were rescheduled 78911201Sandreas.hansson@arm.comsystem.cpu0.iew.lsq.thread0.cacheBlocked 4622903 # Number of times an access to memory failed due to the cache being blocked 79010576Sandreas.hansson@arm.comsystem.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 79111201Sandreas.hansson@arm.comsystem.cpu0.iew.iewSquashCycles 5037394 # Number of cycles IEW is squashing 79211201Sandreas.hansson@arm.comsystem.cpu0.iew.iewBlockCycles 7963594 # Number of cycles IEW is blocking 79311201Sandreas.hansson@arm.comsystem.cpu0.iew.iewUnblockCycles 7170717 # Number of cycles IEW is unblocking 79411201Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispatchedInsts 583715188 # Number of instructions dispatched to IQ 79510576Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 79611201Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispLoadInsts 96647129 # Number of dispatched load instructions 79711201Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispStoreInsts 81788442 # Number of dispatched store instructions 79811201Sandreas.hansson@arm.comsystem.cpu0.iew.iewDispNonSpecInsts 12627210 # Number of dispatched non-speculative instructions 79911201Sandreas.hansson@arm.comsystem.cpu0.iew.iewIQFullEvents 54569 # Number of times the IQ has become full, causing a stall 80011201Sandreas.hansson@arm.comsystem.cpu0.iew.iewLSQFullEvents 7047111 # Number of times the LSQ has become full, causing a stall 80111201Sandreas.hansson@arm.comsystem.cpu0.iew.memOrderViolationEvents 128509 # Number of memory order violations 80211201Sandreas.hansson@arm.comsystem.cpu0.iew.predictedTakenIncorrect 1976888 # Number of branches that were predicted taken incorrectly 80311201Sandreas.hansson@arm.comsystem.cpu0.iew.predictedNotTakenIncorrect 2838838 # Number of branches that were predicted not taken incorrectly 80411201Sandreas.hansson@arm.comsystem.cpu0.iew.branchMispredicts 4815726 # Number of branch mispredicts detected at execute 80511201Sandreas.hansson@arm.comsystem.cpu0.iew.iewExecutedInsts 565090405 # Number of executed instructions 80611201Sandreas.hansson@arm.comsystem.cpu0.iew.iewExecLoadInsts 96493854 # Number of load instructions executed 80711201Sandreas.hansson@arm.comsystem.cpu0.iew.iewExecSquashedInsts 6996299 # Number of squashed instructions skipped in execute 80810576Sandreas.hansson@arm.comsystem.cpu0.iew.exec_swp 0 # number of swp insts executed 80911201Sandreas.hansson@arm.comsystem.cpu0.iew.exec_nop 113308 # number of nop insts executed 81011201Sandreas.hansson@arm.comsystem.cpu0.iew.exec_refs 175051410 # number of memory reference insts executed 81111201Sandreas.hansson@arm.comsystem.cpu0.iew.exec_branches 106737211 # Number of branches executed 81211201Sandreas.hansson@arm.comsystem.cpu0.iew.exec_stores 78557556 # Number of stores executed 81311201Sandreas.hansson@arm.comsystem.cpu0.iew.exec_rate 0.715949 # Inst execution rate 81411201Sandreas.hansson@arm.comsystem.cpu0.iew.wb_sent 557331942 # cumulative count of insts sent to commit 81511201Sandreas.hansson@arm.comsystem.cpu0.iew.wb_count 556570150 # cumulative count of insts written-back 81611201Sandreas.hansson@arm.comsystem.cpu0.iew.wb_producers 270940614 # num instructions producing a value 81711201Sandreas.hansson@arm.comsystem.cpu0.iew.wb_consumers 444738310 # num instructions consuming a value 81810576Sandreas.hansson@arm.comsystem.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 81911201Sandreas.hansson@arm.comsystem.cpu0.iew.wb_rate 0.705154 # insts written-back per cycle 82011201Sandreas.hansson@arm.comsystem.cpu0.iew.wb_fanout 0.609214 # average fanout of values written-back 82110576Sandreas.hansson@arm.comsystem.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 82211201Sandreas.hansson@arm.comsystem.cpu0.commit.commitSquashedInsts 45776609 # The number of squashed insts skipped by commit 82311201Sandreas.hansson@arm.comsystem.cpu0.commit.commitNonSpecStalls 14653410 # The number of times commit has been forced to stall to communicate backwards 82411201Sandreas.hansson@arm.comsystem.cpu0.commit.branchMispredicts 4520969 # The number of times a branch was mispredicted 82511201Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::samples 750266004 # Number of insts commited each cycle 82611201Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::mean 0.707940 # Number of insts commited each cycle 82711201Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::stdev 1.517135 # Number of insts commited each cycle 82810576Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 82911201Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::0 517711139 69.00% 69.00% # Number of insts commited each cycle 83011201Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::1 119807975 15.97% 84.97% # Number of insts commited each cycle 83111201Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::2 52242096 6.96% 91.94% # Number of insts commited each cycle 83211201Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::3 17345693 2.31% 94.25% # Number of insts commited each cycle 83311201Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::4 12502849 1.67% 95.91% # Number of insts commited each cycle 83411201Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::5 8569717 1.14% 97.06% # Number of insts commited each cycle 83511201Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::6 5628818 0.75% 97.81% # Number of insts commited each cycle 83611201Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::7 3480187 0.46% 98.27% # Number of insts commited each cycle 83711201Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::8 12977530 1.73% 100.00% # Number of insts commited each cycle 83810576Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 83910576Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 84010576Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 84111201Sandreas.hansson@arm.comsystem.cpu0.commit.committed_per_cycle::total 750266004 # Number of insts commited each cycle 84211201Sandreas.hansson@arm.comsystem.cpu0.commit.committedInsts 452897446 # Number of instructions committed 84311201Sandreas.hansson@arm.comsystem.cpu0.commit.committedOps 531143684 # Number of ops (including micro ops) committed 84410576Sandreas.hansson@arm.comsystem.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 84511201Sandreas.hansson@arm.comsystem.cpu0.commit.refs 160909268 # Number of memory references committed 84611201Sandreas.hansson@arm.comsystem.cpu0.commit.loads 84670341 # Number of loads committed 84711201Sandreas.hansson@arm.comsystem.cpu0.commit.membars 3612111 # Number of memory barriers committed 84811201Sandreas.hansson@arm.comsystem.cpu0.commit.branches 101352463 # Number of branches committed 84911201Sandreas.hansson@arm.comsystem.cpu0.commit.fp_insts 401266 # Number of committed floating point instructions. 85011201Sandreas.hansson@arm.comsystem.cpu0.commit.int_insts 487082373 # Number of committed integer instructions. 85111201Sandreas.hansson@arm.comsystem.cpu0.commit.function_calls 13540419 # Number of function calls committed. 85210576Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 85311201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::IntAlu 368934944 69.46% 69.46% # Class of committed instruction 85411201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::IntMult 1203387 0.23% 69.69% # Class of committed instruction 85511201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::IntDiv 59505 0.01% 69.70% # Class of committed instruction 85611201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.70% # Class of committed instruction 85711201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.70% # Class of committed instruction 85811201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.70% # Class of committed instruction 85911201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.70% # Class of committed instruction 86011201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.70% # Class of committed instruction 86111201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.70% # Class of committed instruction 86211201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.70% # Class of committed instruction 86311201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.70% # Class of committed instruction 86411201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.70% # Class of committed instruction 86511201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.70% # Class of committed instruction 86611201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.70% # Class of committed instruction 86711201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.70% # Class of committed instruction 86811201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.70% # Class of committed instruction 86911201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.70% # Class of committed instruction 87011201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.70% # Class of committed instruction 87111201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.70% # Class of committed instruction 87211201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.70% # Class of committed instruction 87311201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.70% # Class of committed instruction 87411201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.70% # Class of committed instruction 87511201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.70% # Class of committed instruction 87611201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.70% # Class of committed instruction 87711201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.70% # Class of committed instruction 87811201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatMisc 36580 0.01% 69.71% # Class of committed instruction 87911201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.71% # Class of committed instruction 88011201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.71% # Class of committed instruction 88111201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.71% # Class of committed instruction 88211201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::MemRead 84670341 15.94% 85.65% # Class of committed instruction 88311201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::MemWrite 76238927 14.35% 100.00% # Class of committed instruction 88410576Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 88510576Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 88611201Sandreas.hansson@arm.comsystem.cpu0.commit.op_class_0::total 531143684 # Class of committed instruction 88711201Sandreas.hansson@arm.comsystem.cpu0.commit.bw_lim_events 12977530 # number cycles where commit BW limit reached 88811201Sandreas.hansson@arm.comsystem.cpu0.rob.rob_reads 1309875410 # The number of ROB reads 88911201Sandreas.hansson@arm.comsystem.cpu0.rob.rob_writes 1162529912 # The number of ROB writes 89011201Sandreas.hansson@arm.comsystem.cpu0.timesIdled 987855 # Number of times that the entire CPU went into an idle state and unscheduled itself 89111201Sandreas.hansson@arm.comsystem.cpu0.idleCycles 30299697 # Total number of cycles that the CPU has spent unscheduled due to idling 89211201Sandreas.hansson@arm.comsystem.cpu0.quiesceCycles 93839724027 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 89311201Sandreas.hansson@arm.comsystem.cpu0.committedInsts 452897446 # Number of Instructions Simulated 89411201Sandreas.hansson@arm.comsystem.cpu0.committedOps 531143684 # Number of Ops (including micro ops) Simulated 89511201Sandreas.hansson@arm.comsystem.cpu0.cpi 1.742754 # CPI: Cycles Per Instruction 89611201Sandreas.hansson@arm.comsystem.cpu0.cpi_total 1.742754 # CPI: Total CPI of All Threads 89711201Sandreas.hansson@arm.comsystem.cpu0.ipc 0.573805 # IPC: Instructions Per Cycle 89811201Sandreas.hansson@arm.comsystem.cpu0.ipc_total 0.573805 # IPC: Total IPC of All Threads 89911201Sandreas.hansson@arm.comsystem.cpu0.int_regfile_reads 666947650 # number of integer regfile reads 90011201Sandreas.hansson@arm.comsystem.cpu0.int_regfile_writes 396615179 # number of integer regfile writes 90111201Sandreas.hansson@arm.comsystem.cpu0.fp_regfile_reads 682678 # number of floating regfile reads 90211201Sandreas.hansson@arm.comsystem.cpu0.fp_regfile_writes 298828 # number of floating regfile writes 90311201Sandreas.hansson@arm.comsystem.cpu0.cc_regfile_reads 124079442 # number of cc regfile reads 90411201Sandreas.hansson@arm.comsystem.cpu0.cc_regfile_writes 124706529 # number of cc regfile writes 90511201Sandreas.hansson@arm.comsystem.cpu0.misc_regfile_reads 1318525921 # number of misc regfile reads 90611201Sandreas.hansson@arm.comsystem.cpu0.misc_regfile_writes 14734262 # number of misc regfile writes 90711201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 5881965 # number of replacements 90811201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 478.956800 # Cycle average of tags in use 90911201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 149156359 # Total number of references to valid blocks. 91011201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 5882471 # Sample count of references to valid blocks. 91111201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 25.356072 # Average number of references to valid blocks. 91211201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 2962390000 # Cycle when the warmup percentage was hit. 91311201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 478.956800 # Average occupied blocks per requestor 91411201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.935463 # Average percentage of cache occupancy 91511201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.935463 # Average percentage of cache occupancy 91611201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 506 # Occupied blocks per task id 91711201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id 91811201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 370 # Occupied blocks per task id 91911201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id 92011201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 0.988281 # Percentage of cache occupancy per task id 92111201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 334047120 # Number of tag accesses 92211201Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 334047120 # Number of data accesses 92311201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 78452229 # number of ReadReq hits 92411201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 78452229 # number of ReadReq hits 92511201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 65886147 # number of WriteReq hits 92611201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 65886147 # number of WriteReq hits 92711201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 209885 # number of SoftPFReq hits 92811201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 209885 # number of SoftPFReq hits 92911201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::cpu0.data 258671 # number of WriteLineReq hits 93011201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_hits::total 258671 # number of WriteLineReq hits 93111201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1757048 # number of LoadLockedReq hits 93211201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 1757048 # number of LoadLockedReq hits 93311201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 1773588 # number of StoreCondReq hits 93411201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 1773588 # number of StoreCondReq hits 93511201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 144338376 # number of demand (read+write) hits 93611201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 144338376 # number of demand (read+write) hits 93711201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 144548261 # number of overall hits 93811201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 144548261 # number of overall hits 93911201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 6459284 # number of ReadReq misses 94011201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 6459284 # number of ReadReq misses 94111201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 7288144 # number of WriteReq misses 94211201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 7288144 # number of WriteReq misses 94311201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 689122 # number of SoftPFReq misses 94411201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 689122 # number of SoftPFReq misses 94511201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::cpu0.data 817042 # number of WriteLineReq misses 94611201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_misses::total 817042 # number of WriteLineReq misses 94711201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 245228 # number of LoadLockedReq misses 94811201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 245228 # number of LoadLockedReq misses 94911201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 193470 # number of StoreCondReq misses 95011201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 193470 # number of StoreCondReq misses 95111201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 13747428 # number of demand (read+write) misses 95211201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 13747428 # number of demand (read+write) misses 95311201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 14436550 # number of overall misses 95411201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 14436550 # number of overall misses 95511201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 110052955500 # number of ReadReq miss cycles 95611201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 110052955500 # number of ReadReq miss cycles 95711201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 170225463786 # number of WriteReq miss cycles 95811201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 170225463786 # number of WriteReq miss cycles 95911201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 91498155223 # number of WriteLineReq miss cycles 96011201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_latency::total 91498155223 # number of WriteLineReq miss cycles 96111201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3890581500 # number of LoadLockedReq miss cycles 96211201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 3890581500 # number of LoadLockedReq miss cycles 96311201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 5535454500 # number of StoreCondReq miss cycles 96411201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 5535454500 # number of StoreCondReq miss cycles 96511201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 8571500 # number of StoreCondFailReq miss cycles 96611201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::total 8571500 # number of StoreCondFailReq miss cycles 96711201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 280278419286 # number of demand (read+write) miss cycles 96811201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::total 280278419286 # number of demand (read+write) miss cycles 96911201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 280278419286 # number of overall miss cycles 97011201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::total 280278419286 # number of overall miss cycles 97111201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 84911513 # number of ReadReq accesses(hits+misses) 97211201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 84911513 # number of ReadReq accesses(hits+misses) 97311201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 73174291 # number of WriteReq accesses(hits+misses) 97411201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 73174291 # number of WriteReq accesses(hits+misses) 97511201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 899007 # number of SoftPFReq accesses(hits+misses) 97611201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 899007 # number of SoftPFReq accesses(hits+misses) 97711201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::cpu0.data 1075713 # number of WriteLineReq accesses(hits+misses) 97811201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_accesses::total 1075713 # number of WriteLineReq accesses(hits+misses) 97911201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2002276 # number of LoadLockedReq accesses(hits+misses) 98011201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 2002276 # number of LoadLockedReq accesses(hits+misses) 98111201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1967058 # number of StoreCondReq accesses(hits+misses) 98211201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 1967058 # number of StoreCondReq accesses(hits+misses) 98311201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 158085804 # number of demand (read+write) accesses 98411201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 158085804 # number of demand (read+write) accesses 98511201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 158984811 # number of overall (read+write) accesses 98611201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 158984811 # number of overall (read+write) accesses 98711201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.076071 # miss rate for ReadReq accesses 98811201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.076071 # miss rate for ReadReq accesses 98911201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.099600 # miss rate for WriteReq accesses 99011201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.099600 # miss rate for WriteReq accesses 99111201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.766537 # miss rate for SoftPFReq accesses 99211201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.766537 # miss rate for SoftPFReq accesses 99311201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.759535 # miss rate for WriteLineReq accesses 99411201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_miss_rate::total 0.759535 # miss rate for WriteLineReq accesses 99511201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.122475 # miss rate for LoadLockedReq accesses 99611201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.122475 # miss rate for LoadLockedReq accesses 99711201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098355 # miss rate for StoreCondReq accesses 99811201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.098355 # miss rate for StoreCondReq accesses 99911201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.086962 # miss rate for demand accesses 100011201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.086962 # miss rate for demand accesses 100111201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.090805 # miss rate for overall accesses 100211201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.090805 # miss rate for overall accesses 100311201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17037.949640 # average ReadReq miss latency 100411201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 17037.949640 # average ReadReq miss latency 100511201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 23356.490183 # average WriteReq miss latency 100611201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 23356.490183 # average WriteReq miss latency 100711201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 111987.089064 # average WriteLineReq miss latency 100811201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_miss_latency::total 111987.089064 # average WriteLineReq miss latency 100911201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15865.160177 # average LoadLockedReq miss latency 101011201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15865.160177 # average LoadLockedReq miss latency 101111201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 28611.435882 # average StoreCondReq miss latency 101211201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28611.435882 # average StoreCondReq miss latency 101310576Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 101410576Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 101511201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 20387.698651 # average overall miss latency 101611201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 20387.698651 # average overall miss latency 101711201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19414.501338 # average overall miss latency 101811201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 19414.501338 # average overall miss latency 101911201Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_mshrs 28857818 # number of cycles access was blocked 102011201Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked_cycles::no_targets 25701299 # number of cycles access was blocked 102111201Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_mshrs 757026 # number of cycles access was blocked 102211201Sandreas.hansson@arm.comsystem.cpu0.dcache.blocked::no_targets 713337 # number of cycles access was blocked 102311201Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_mshrs 38.119983 # average number of cycles each access was blocked 102411201Sandreas.hansson@arm.comsystem.cpu0.dcache.avg_blocked_cycles::no_targets 36.029673 # average number of cycles each access was blocked 102510585Sandreas.hansson@arm.comsystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 102610576Sandreas.hansson@arm.comsystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 102711201Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 5882015 # number of writebacks 102811201Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 5882015 # number of writebacks 102911201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3286907 # number of ReadReq MSHR hits 103011201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 3286907 # number of ReadReq MSHR hits 103111201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5842010 # number of WriteReq MSHR hits 103211201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 5842010 # number of WriteReq MSHR hits 103311201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4476 # number of WriteLineReq MSHR hits 103411201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_hits::total 4476 # number of WriteLineReq MSHR hits 103511201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 122858 # number of LoadLockedReq MSHR hits 103611201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 122858 # number of LoadLockedReq MSHR hits 103711201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 9128917 # number of demand (read+write) MSHR hits 103811201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 9128917 # number of demand (read+write) MSHR hits 103911201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 9128917 # number of overall MSHR hits 104011201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 9128917 # number of overall MSHR hits 104111201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3172377 # number of ReadReq MSHR misses 104211201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 3172377 # number of ReadReq MSHR misses 104311201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1446134 # number of WriteReq MSHR misses 104411201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 1446134 # number of WriteReq MSHR misses 104511201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 682277 # number of SoftPFReq MSHR misses 104611201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::total 682277 # number of SoftPFReq MSHR misses 104711201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 812566 # number of WriteLineReq MSHR misses 104811201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_misses::total 812566 # number of WriteLineReq MSHR misses 104911201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 122370 # number of LoadLockedReq MSHR misses 105011201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 122370 # number of LoadLockedReq MSHR misses 105111201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 193461 # number of StoreCondReq MSHR misses 105211201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 193461 # number of StoreCondReq MSHR misses 105311201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 4618511 # number of demand (read+write) MSHR misses 105411201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 4618511 # number of demand (read+write) MSHR misses 105511201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 5300788 # number of overall MSHR misses 105611201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 5300788 # number of overall MSHR misses 105711201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32879 # number of ReadReq MSHR uncacheable 105811201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::total 32879 # number of ReadReq MSHR uncacheable 105911201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 32981 # number of WriteReq MSHR uncacheable 106011201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::total 32981 # number of WriteReq MSHR uncacheable 106111201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 65860 # number of overall MSHR uncacheable misses 106211201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::total 65860 # number of overall MSHR uncacheable misses 106311201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 49995905500 # number of ReadReq MSHR miss cycles 106411201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 49995905500 # number of ReadReq MSHR miss cycles 106511201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 39710234771 # number of WriteReq MSHR miss cycles 106611201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 39710234771 # number of WriteReq MSHR miss cycles 106711201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 17655223500 # number of SoftPFReq MSHR miss cycles 106811201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 17655223500 # number of SoftPFReq MSHR miss cycles 106911201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 90433652723 # number of WriteLineReq MSHR miss cycles 107011201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 90433652723 # number of WriteLineReq MSHR miss cycles 107111201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1780369000 # number of LoadLockedReq MSHR miss cycles 107211201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1780369000 # number of LoadLockedReq MSHR miss cycles 107311201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 5342108500 # number of StoreCondReq MSHR miss cycles 107411201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 5342108500 # number of StoreCondReq MSHR miss cycles 107511201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 8456500 # number of StoreCondFailReq MSHR miss cycles 107611201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 8456500 # number of StoreCondFailReq MSHR miss cycles 107711201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 89706140271 # number of demand (read+write) MSHR miss cycles 107811201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 89706140271 # number of demand (read+write) MSHR miss cycles 107911201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 107361363771 # number of overall MSHR miss cycles 108011201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 107361363771 # number of overall MSHR miss cycles 108111201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6303225000 # number of ReadReq MSHR uncacheable cycles 108211201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6303225000 # number of ReadReq MSHR uncacheable cycles 108311201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 6238855500 # number of WriteReq MSHR uncacheable cycles 108411201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 6238855500 # number of WriteReq MSHR uncacheable cycles 108511201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12542080500 # number of overall MSHR uncacheable cycles 108611201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 12542080500 # number of overall MSHR uncacheable cycles 108711201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037361 # mshr miss rate for ReadReq accesses 108811201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037361 # mshr miss rate for ReadReq accesses 108911201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019763 # mshr miss rate for WriteReq accesses 109011201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019763 # mshr miss rate for WriteReq accesses 109111201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.758923 # mshr miss rate for SoftPFReq accesses 109211201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.758923 # mshr miss rate for SoftPFReq accesses 109311201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.755374 # mshr miss rate for WriteLineReq accesses 109411201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.755374 # mshr miss rate for WriteLineReq accesses 109511201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.061115 # mshr miss rate for LoadLockedReq accesses 109611201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.061115 # mshr miss rate for LoadLockedReq accesses 109711201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098350 # mshr miss rate for StoreCondReq accesses 109811201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098350 # mshr miss rate for StoreCondReq accesses 109911201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029215 # mshr miss rate for demand accesses 110011201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.029215 # mshr miss rate for demand accesses 110111201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.033341 # mshr miss rate for overall accesses 110211201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.033341 # mshr miss rate for overall accesses 110311201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15759.761687 # average ReadReq mshr miss latency 110411201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15759.761687 # average ReadReq mshr miss latency 110511201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27459.581734 # average WriteReq mshr miss latency 110611201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27459.581734 # average WriteReq mshr miss latency 110711201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 25876.914362 # average SoftPFReq mshr miss latency 110811201Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 25876.914362 # average SoftPFReq mshr miss latency 110911201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 111293.916707 # average WriteLineReq mshr miss latency 111011201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 111293.916707 # average WriteLineReq mshr miss latency 111111201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14549.064313 # average LoadLockedReq mshr miss latency 111211201Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14549.064313 # average LoadLockedReq mshr miss latency 111311201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 27613.361349 # average StoreCondReq mshr miss latency 111411201Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27613.361349 # average StoreCondReq mshr miss latency 111510576Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 111610576Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 111711201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19423.173458 # average overall mshr miss latency 111811201Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 19423.173458 # average overall mshr miss latency 111911201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20253.849762 # average overall mshr miss latency 112011201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 20253.849762 # average overall mshr miss latency 112111201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191709.753946 # average ReadReq mshr uncacheable latency 112211201Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191709.753946 # average ReadReq mshr uncacheable latency 112311201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189165.140535 # average WriteReq mshr uncacheable latency 112411201Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189165.140535 # average WriteReq mshr uncacheable latency 112511201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 190435.476769 # average overall mshr uncacheable latency 112611201Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190435.476769 # average overall mshr uncacheable latency 112710576Sandreas.hansson@arm.comsystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 112811201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 6005225 # number of replacements 112911201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.936915 # Cycle average of tags in use 113011201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 202641946 # Total number of references to valid blocks. 113111201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 6005737 # Sample count of references to valid blocks. 113211201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 33.741395 # Average number of references to valid blocks. 113311201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 21603135000 # Cycle when the warmup percentage was hit. 113411201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.936915 # Average occupied blocks per requestor 113511201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999877 # Average percentage of cache occupancy 113611201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_percent::total 0.999877 # Average percentage of cache occupancy 113710576Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 113811201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id 113911201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 333 # Occupied blocks per task id 114011201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id 114110576Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 114211201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 424004104 # Number of tag accesses 114311201Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 424004104 # Number of data accesses 114411201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 202641946 # number of ReadReq hits 114511201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 202641946 # number of ReadReq hits 114611201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 202641946 # number of demand (read+write) hits 114711201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 202641946 # number of demand (read+write) hits 114811201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 202641946 # number of overall hits 114911201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 202641946 # number of overall hits 115011201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 6357218 # number of ReadReq misses 115111201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 6357218 # number of ReadReq misses 115211201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 6357218 # number of demand (read+write) misses 115311201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 6357218 # number of demand (read+write) misses 115411201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 6357218 # number of overall misses 115511201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 6357218 # number of overall misses 115611201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 72002088632 # number of ReadReq miss cycles 115711201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 72002088632 # number of ReadReq miss cycles 115811201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 72002088632 # number of demand (read+write) miss cycles 115911201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::total 72002088632 # number of demand (read+write) miss cycles 116011201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 72002088632 # number of overall miss cycles 116111201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::total 72002088632 # number of overall miss cycles 116211201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 208999164 # number of ReadReq accesses(hits+misses) 116311201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 208999164 # number of ReadReq accesses(hits+misses) 116411201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 208999164 # number of demand (read+write) accesses 116511201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 208999164 # number of demand (read+write) accesses 116611201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 208999164 # number of overall (read+write) accesses 116711201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 208999164 # number of overall (read+write) accesses 116811201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.030417 # miss rate for ReadReq accesses 116911201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.030417 # miss rate for ReadReq accesses 117011201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.030417 # miss rate for demand accesses 117111201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.030417 # miss rate for demand accesses 117211201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.030417 # miss rate for overall accesses 117311201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.030417 # miss rate for overall accesses 117411201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11326.037369 # average ReadReq miss latency 117511201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 11326.037369 # average ReadReq miss latency 117611201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11326.037369 # average overall miss latency 117711201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 11326.037369 # average overall miss latency 117811201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11326.037369 # average overall miss latency 117911201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 11326.037369 # average overall miss latency 118011201Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_mshrs 11168048 # number of cycles access was blocked 118111201Sandreas.hansson@arm.comsystem.cpu0.icache.blocked_cycles::no_targets 1595 # number of cycles access was blocked 118211201Sandreas.hansson@arm.comsystem.cpu0.icache.blocked::no_mshrs 759109 # number of cycles access was blocked 118311167Sjthestness@gmail.comsystem.cpu0.icache.blocked::no_targets 14 # number of cycles access was blocked 118411201Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_mshrs 14.712048 # average number of cycles each access was blocked 118511201Sandreas.hansson@arm.comsystem.cpu0.icache.avg_blocked_cycles::no_targets 113.928571 # average number of cycles each access was blocked 118610576Sandreas.hansson@arm.comsystem.cpu0.icache.fast_writes 0 # number of fast writes performed 118710576Sandreas.hansson@arm.comsystem.cpu0.icache.cache_copies 0 # number of cache copies performed 118811201Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::writebacks 6005225 # number of writebacks 118911201Sandreas.hansson@arm.comsystem.cpu0.icache.writebacks::total 6005225 # number of writebacks 119011201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 351442 # number of ReadReq MSHR hits 119111201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_hits::total 351442 # number of ReadReq MSHR hits 119211201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_hits::cpu0.inst 351442 # number of demand (read+write) MSHR hits 119311201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_hits::total 351442 # number of demand (read+write) MSHR hits 119411201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_hits::cpu0.inst 351442 # number of overall MSHR hits 119511201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_hits::total 351442 # number of overall MSHR hits 119611201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6005776 # number of ReadReq MSHR misses 119711201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 6005776 # number of ReadReq MSHR misses 119811201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 6005776 # number of demand (read+write) MSHR misses 119911201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::total 6005776 # number of demand (read+write) MSHR misses 120011201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 6005776 # number of overall MSHR misses 120111201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::total 6005776 # number of overall MSHR misses 120211201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable 120311201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable 120411201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses 120511201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses 120611201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 64732998531 # number of ReadReq MSHR miss cycles 120711201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 64732998531 # number of ReadReq MSHR miss cycles 120811201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 64732998531 # number of demand (read+write) MSHR miss cycles 120911201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 64732998531 # number of demand (read+write) MSHR miss cycles 121011201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 64732998531 # number of overall MSHR miss cycles 121111201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 64732998531 # number of overall MSHR miss cycles 121211201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2939780998 # number of ReadReq MSHR uncacheable cycles 121311201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2939780998 # number of ReadReq MSHR uncacheable cycles 121411201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2939780998 # number of overall MSHR uncacheable cycles 121511201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_latency::total 2939780998 # number of overall MSHR uncacheable cycles 121611201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028736 # mshr miss rate for ReadReq accesses 121711201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028736 # mshr miss rate for ReadReq accesses 121811201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028736 # mshr miss rate for demand accesses 121911201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.028736 # mshr miss rate for demand accesses 122011201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028736 # mshr miss rate for overall accesses 122111201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.028736 # mshr miss rate for overall accesses 122211201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10778.457027 # average ReadReq mshr miss latency 122311201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10778.457027 # average ReadReq mshr miss latency 122411201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10778.457027 # average overall mshr miss latency 122511201Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 10778.457027 # average overall mshr miss latency 122611201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10778.457027 # average overall mshr miss latency 122711201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 10778.457027 # average overall mshr miss latency 122811201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 138063.260132 # average ReadReq mshr uncacheable latency 122911201Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 138063.260132 # average ReadReq mshr uncacheable latency 123011201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 138063.260132 # average overall mshr uncacheable latency 123111201Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 138063.260132 # average overall mshr uncacheable latency 123210576Sandreas.hansson@arm.comsystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 123311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 7993443 # number of hwpf issued 123411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 8002831 # number of prefetch candidates identified 123511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 8432 # number of redundant prefetches already in prefetch queue 123610628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 123710628Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 123811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 1016241 # number of prefetches not generated due to page crossing 123911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 2612055 # number of replacements 124011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 15872.009303 # Cycle average of tags in use 124111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 17309640 # Total number of references to valid blocks. 124211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2628171 # Sample count of references to valid blocks. 124311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 6.586192 # Average number of references to valid blocks. 124411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 3536776000 # Cycle when the warmup percentage was hit. 124511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 14904.546668 # Average occupied blocks per requestor 124611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 64.900343 # Average occupied blocks per requestor 124711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 63.931766 # Average occupied blocks per requestor 124811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 838.630526 # Average occupied blocks per requestor 124911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.909701 # Average percentage of cache occupancy 125011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003961 # Average percentage of cache occupancy 125111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003902 # Average percentage of cache occupancy 125211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.051186 # Average percentage of cache occupancy 125311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.968751 # Average percentage of cache occupancy 125411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1022 1148 # Occupied blocks per task id 125511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 72 # Occupied blocks per task id 125611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 14896 # Occupied blocks per task id 125711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::1 19 # Occupied blocks per task id 125811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::2 168 # Occupied blocks per task id 125911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::3 583 # Occupied blocks per task id 126011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::4 378 # Occupied blocks per task id 126111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 126211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 39 # Occupied blocks per task id 126311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id 126411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id 126511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 126611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1338 # Occupied blocks per task id 126711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5968 # Occupied blocks per task id 126811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4418 # Occupied blocks per task id 126911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3068 # Occupied blocks per task id 127011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1022 0.070068 # Percentage of cache occupancy per task id 127111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004395 # Percentage of cache occupancy per task id 127211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.909180 # Percentage of cache occupancy per task id 127311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 407586755 # Number of tag accesses 127411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 407586755 # Number of data accesses 127511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 586295 # number of ReadReq hits 127611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 178487 # number of ReadReq hits 127711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 764782 # number of ReadReq hits 127811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::writebacks 3871957 # number of WritebackDirty hits 127911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_hits::total 3871957 # number of WritebackDirty hits 128011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::writebacks 8013001 # number of WritebackClean hits 128111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_hits::total 8013001 # number of WritebackClean hits 128211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 532 # number of UpgradeReq hits 128311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 532 # number of UpgradeReq hits 128411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1 # number of SCUpgradeReq hits 128511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits 128611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 876856 # number of ReadExReq hits 128711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 876856 # number of ReadExReq hits 128811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5449817 # number of ReadCleanReq hits 128911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_hits::total 5449817 # number of ReadCleanReq hits 129011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2990512 # number of ReadSharedReq hits 129111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_hits::total 2990512 # number of ReadSharedReq hits 129211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::cpu0.data 195363 # number of InvalidateReq hits 129311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_hits::total 195363 # number of InvalidateReq hits 129411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 586295 # number of demand (read+write) hits 129511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 178487 # number of demand (read+write) hits 129611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 5449817 # number of demand (read+write) hits 129711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 3867368 # number of demand (read+write) hits 129811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 10081967 # number of demand (read+write) hits 129911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 586295 # number of overall hits 130011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 178487 # number of overall hits 130111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 5449817 # number of overall hits 130211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3867368 # number of overall hits 130311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 10081967 # number of overall hits 130411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11719 # number of ReadReq misses 130511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8497 # number of ReadReq misses 130611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 20216 # number of ReadReq misses 130711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_misses::writebacks 2 # number of WritebackDirty misses 130811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_misses::total 2 # number of WritebackDirty misses 130911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_misses::writebacks 2 # number of WritebackClean misses 131011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_misses::total 2 # number of WritebackClean misses 131111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 253056 # number of UpgradeReq misses 131211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 253056 # number of UpgradeReq misses 131311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 193456 # number of SCUpgradeReq misses 131411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 193456 # number of SCUpgradeReq misses 131511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 4 # number of SCUpgradeFailReq misses 131611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses 131711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 324941 # number of ReadExReq misses 131811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 324941 # number of ReadExReq misses 131911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 555934 # number of ReadCleanReq misses 132011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_misses::total 555934 # number of ReadCleanReq misses 132111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 984475 # number of ReadSharedReq misses 132211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_misses::total 984475 # number of ReadSharedReq misses 132311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::cpu0.data 615167 # number of InvalidateReq misses 132411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_misses::total 615167 # number of InvalidateReq misses 132511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11719 # number of demand (read+write) misses 132611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 8497 # number of demand (read+write) misses 132711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 555934 # number of demand (read+write) misses 132811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1309416 # number of demand (read+write) misses 132911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 1885566 # number of demand (read+write) misses 133011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11719 # number of overall misses 133111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 8497 # number of overall misses 133211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 555934 # number of overall misses 133311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1309416 # number of overall misses 133411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 1885566 # number of overall misses 133511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 564728500 # number of ReadReq miss cycles 133611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 467676000 # number of ReadReq miss cycles 133711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::total 1032404500 # number of ReadReq miss cycles 133811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 3400771000 # number of UpgradeReq miss cycles 133911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::total 3400771000 # number of UpgradeReq miss cycles 134011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2092190000 # number of SCUpgradeReq miss cycles 134111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2092190000 # number of SCUpgradeReq miss cycles 134211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 8283499 # number of SCUpgradeFailReq miss cycles 134311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 8283499 # number of SCUpgradeFailReq miss cycles 134411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 22038897500 # number of ReadExReq miss cycles 134511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::total 22038897500 # number of ReadExReq miss cycles 134611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 22689432998 # number of ReadCleanReq miss cycles 134711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_latency::total 22689432998 # number of ReadCleanReq miss cycles 134811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 43523481971 # number of ReadSharedReq miss cycles 134911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_latency::total 43523481971 # number of ReadSharedReq miss cycles 135011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 86915383999 # number of InvalidateReq miss cycles 135111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_latency::total 86915383999 # number of InvalidateReq miss cycles 135211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 564728500 # number of demand (read+write) miss cycles 135311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 467676000 # number of demand (read+write) miss cycles 135411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.inst 22689432998 # number of demand (read+write) miss cycles 135511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.data 65562379471 # number of demand (read+write) miss cycles 135611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::total 89284216969 # number of demand (read+write) miss cycles 135711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 564728500 # number of overall miss cycles 135811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 467676000 # number of overall miss cycles 135911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.inst 22689432998 # number of overall miss cycles 136011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.data 65562379471 # number of overall miss cycles 136111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::total 89284216969 # number of overall miss cycles 136211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 598014 # number of ReadReq accesses(hits+misses) 136311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 186984 # number of ReadReq accesses(hits+misses) 136411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 784998 # number of ReadReq accesses(hits+misses) 136511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::writebacks 3871959 # number of WritebackDirty accesses(hits+misses) 136611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_accesses::total 3871959 # number of WritebackDirty accesses(hits+misses) 136711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::writebacks 8013003 # number of WritebackClean accesses(hits+misses) 136811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_accesses::total 8013003 # number of WritebackClean accesses(hits+misses) 136911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 253588 # number of UpgradeReq accesses(hits+misses) 137011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 253588 # number of UpgradeReq accesses(hits+misses) 137111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 193457 # number of SCUpgradeReq accesses(hits+misses) 137211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 193457 # number of SCUpgradeReq accesses(hits+misses) 137311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 4 # number of SCUpgradeFailReq accesses(hits+misses) 137411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) 137511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1201797 # number of ReadExReq accesses(hits+misses) 137611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1201797 # number of ReadExReq accesses(hits+misses) 137711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6005751 # number of ReadCleanReq accesses(hits+misses) 137811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_accesses::total 6005751 # number of ReadCleanReq accesses(hits+misses) 137911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3974987 # number of ReadSharedReq accesses(hits+misses) 138011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_accesses::total 3974987 # number of ReadSharedReq accesses(hits+misses) 138111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 810530 # number of InvalidateReq accesses(hits+misses) 138211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_accesses::total 810530 # number of InvalidateReq accesses(hits+misses) 138311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 598014 # number of demand (read+write) accesses 138411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 186984 # number of demand (read+write) accesses 138511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 6005751 # number of demand (read+write) accesses 138611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 5176784 # number of demand (read+write) accesses 138711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::total 11967533 # number of demand (read+write) accesses 138811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 598014 # number of overall (read+write) accesses 138911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.itb.walker 186984 # number of overall (read+write) accesses 139011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.inst 6005751 # number of overall (read+write) accesses 139111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::cpu0.data 5176784 # number of overall (read+write) accesses 139211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_accesses::total 11967533 # number of overall (read+write) accesses 139311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.019597 # miss rate for ReadReq accesses 139411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.045442 # miss rate for ReadReq accesses 139511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.025753 # miss rate for ReadReq accesses 139611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses 139711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses 139811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses 139911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses 140011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.997902 # miss rate for UpgradeReq accesses 140111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.997902 # miss rate for UpgradeReq accesses 140211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999995 # miss rate for SCUpgradeReq accesses 140311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999995 # miss rate for SCUpgradeReq accesses 140410576Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 140510576Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 140611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.270379 # miss rate for ReadExReq accesses 140711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.270379 # miss rate for ReadExReq accesses 140811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.092567 # miss rate for ReadCleanReq accesses 140911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.092567 # miss rate for ReadCleanReq accesses 141011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.247667 # miss rate for ReadSharedReq accesses 141111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.247667 # miss rate for ReadSharedReq accesses 141211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.758969 # miss rate for InvalidateReq accesses 141311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_miss_rate::total 0.758969 # miss rate for InvalidateReq accesses 141411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.019597 # miss rate for demand accesses 141511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.045442 # miss rate for demand accesses 141611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.092567 # miss rate for demand accesses 141711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.252940 # miss rate for demand accesses 141811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.157557 # miss rate for demand accesses 141911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.019597 # miss rate for overall accesses 142011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.045442 # miss rate for overall accesses 142111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.092567 # miss rate for overall accesses 142211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.252940 # miss rate for overall accesses 142311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.157557 # miss rate for overall accesses 142411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 48189.137298 # average ReadReq miss latency 142511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 55040.131811 # average ReadReq miss latency 142611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::total 51068.683221 # average ReadReq miss latency 142711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 13438.808011 # average UpgradeReq miss latency 142811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 13438.808011 # average UpgradeReq miss latency 142911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 10814.810603 # average SCUpgradeReq miss latency 143011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 10814.810603 # average SCUpgradeReq miss latency 143111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 2070874.750000 # average SCUpgradeFailReq miss latency 143211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 2070874.750000 # average SCUpgradeFailReq miss latency 143311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 67824.305028 # average ReadExReq miss latency 143411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_miss_latency::total 67824.305028 # average ReadExReq miss latency 143511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 40813.177460 # average ReadCleanReq miss latency 143611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 40813.177460 # average ReadCleanReq miss latency 143711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 44209.839733 # average ReadSharedReq miss latency 143811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 44209.839733 # average ReadSharedReq miss latency 143911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 141287.461777 # average InvalidateReq miss latency 144011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 141287.461777 # average InvalidateReq miss latency 144111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 48189.137298 # average overall miss latency 144211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 55040.131811 # average overall miss latency 144311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 40813.177460 # average overall miss latency 144411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 50069.939172 # average overall miss latency 144511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::total 47351.414360 # average overall miss latency 144611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 48189.137298 # average overall miss latency 144711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 55040.131811 # average overall miss latency 144811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 40813.177460 # average overall miss latency 144911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 50069.939172 # average overall miss latency 145011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::total 47351.414360 # average overall miss latency 145111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_mshrs 3549 # number of cycles access was blocked 145210576Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 145311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_mshrs 15 # number of cycles access was blocked 145410576Sandreas.hansson@arm.comsystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 145511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs 236.600000 # average number of cycles each access was blocked 145610576Sandreas.hansson@arm.comsystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 145710576Sandreas.hansson@arm.comsystem.cpu0.l2cache.fast_writes 0 # number of fast writes performed 145810576Sandreas.hansson@arm.comsystem.cpu0.l2cache.cache_copies 0 # number of cache copies performed 145911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1633377 # number of writebacks 146011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 1633377 # number of writebacks 146111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 5 # number of ReadReq MSHR hits 146211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 190 # number of ReadReq MSHR hits 146311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::total 195 # number of ReadReq MSHR hits 146411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 59160 # number of ReadExReq MSHR hits 146511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_hits::total 59160 # number of ReadExReq MSHR hits 146611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 2 # number of ReadCleanReq MSHR hits 146711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits 146811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 6628 # number of ReadSharedReq MSHR hits 146911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_hits::total 6628 # number of ReadSharedReq MSHR hits 147011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 15 # number of InvalidateReq MSHR hits 147111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_hits::total 15 # number of InvalidateReq MSHR hits 147211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 5 # number of demand (read+write) MSHR hits 147311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 190 # number of demand (read+write) MSHR hits 147411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits 147511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::cpu0.data 65788 # number of demand (read+write) MSHR hits 147611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_hits::total 65985 # number of demand (read+write) MSHR hits 147711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 5 # number of overall MSHR hits 147811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 190 # number of overall MSHR hits 147911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits 148011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::cpu0.data 65788 # number of overall MSHR hits 148111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_hits::total 65985 # number of overall MSHR hits 148211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 11714 # number of ReadReq MSHR misses 148311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8307 # number of ReadReq MSHR misses 148411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_misses::total 20021 # number of ReadReq MSHR misses 148511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_mshr_misses::writebacks 2 # number of WritebackDirty MSHR misses 148611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_mshr_misses::total 2 # number of WritebackDirty MSHR misses 148711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 2 # number of WritebackClean MSHR misses 148811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_mshr_misses::total 2 # number of WritebackClean MSHR misses 148911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 825638 # number of HardPFReq MSHR misses 149011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_misses::total 825638 # number of HardPFReq MSHR misses 149111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 253056 # number of UpgradeReq MSHR misses 149211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_misses::total 253056 # number of UpgradeReq MSHR misses 149311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 193456 # number of SCUpgradeReq MSHR misses 149411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 193456 # number of SCUpgradeReq MSHR misses 149511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 4 # number of SCUpgradeFailReq MSHR misses 149611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses 149711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 265781 # number of ReadExReq MSHR misses 149811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_misses::total 265781 # number of ReadExReq MSHR misses 149911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 555932 # number of ReadCleanReq MSHR misses 150011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_misses::total 555932 # number of ReadCleanReq MSHR misses 150111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 977847 # number of ReadSharedReq MSHR misses 150211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_misses::total 977847 # number of ReadSharedReq MSHR misses 150311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 615152 # number of InvalidateReq MSHR misses 150411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_misses::total 615152 # number of InvalidateReq MSHR misses 150511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 11714 # number of demand (read+write) MSHR misses 150611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8307 # number of demand (read+write) MSHR misses 150711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.inst 555932 # number of demand (read+write) MSHR misses 150811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::cpu0.data 1243628 # number of demand (read+write) MSHR misses 150911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_misses::total 1819581 # number of demand (read+write) MSHR misses 151011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 11714 # number of overall MSHR misses 151111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8307 # number of overall MSHR misses 151211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.inst 555932 # number of overall MSHR misses 151311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.data 1243628 # number of overall MSHR misses 151411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 825638 # number of overall MSHR misses 151511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_misses::total 2645219 # number of overall MSHR misses 151611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable 151711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 32879 # number of ReadReq MSHR uncacheable 151811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable::total 54172 # number of ReadReq MSHR uncacheable 151911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 32981 # number of WriteReq MSHR uncacheable 152011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable::total 32981 # number of WriteReq MSHR uncacheable 152111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses 152211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 65860 # number of overall MSHR uncacheable misses 152311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_misses::total 87153 # number of overall MSHR uncacheable misses 152411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 494096500 # number of ReadReq MSHR miss cycles 152511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 408146000 # number of ReadReq MSHR miss cycles 152611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_latency::total 902242500 # number of ReadReq MSHR miss cycles 152711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 60235996440 # number of HardPFReq MSHR miss cycles 152811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 60235996440 # number of HardPFReq MSHR miss cycles 152911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 7625664494 # number of UpgradeReq MSHR miss cycles 153011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 7625664494 # number of UpgradeReq MSHR miss cycles 153111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3888505997 # number of SCUpgradeReq MSHR miss cycles 153211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3888505997 # number of SCUpgradeReq MSHR miss cycles 153311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 7593499 # number of SCUpgradeFailReq MSHR miss cycles 153411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 7593499 # number of SCUpgradeFailReq MSHR miss cycles 153511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 16722004500 # number of ReadExReq MSHR miss cycles 153611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 16722004500 # number of ReadExReq MSHR miss cycles 153711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 19353809498 # number of ReadCleanReq MSHR miss cycles 153811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 19353809498 # number of ReadCleanReq MSHR miss cycles 153911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 37185118471 # number of ReadSharedReq MSHR miss cycles 154011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 37185118471 # number of ReadSharedReq MSHR miss cycles 154111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 83223435999 # number of InvalidateReq MSHR miss cycles 154211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 83223435999 # number of InvalidateReq MSHR miss cycles 154311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 494096500 # number of demand (read+write) MSHR miss cycles 154411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 408146000 # number of demand (read+write) MSHR miss cycles 154511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 19353809498 # number of demand (read+write) MSHR miss cycles 154611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 53907122971 # number of demand (read+write) MSHR miss cycles 154711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::total 74163174969 # number of demand (read+write) MSHR miss cycles 154811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 494096500 # number of overall MSHR miss cycles 154911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 408146000 # number of overall MSHR miss cycles 155011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 19353809498 # number of overall MSHR miss cycles 155111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 53907122971 # number of overall MSHR miss cycles 155211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 60235996440 # number of overall MSHR miss cycles 155311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::total 134399171409 # number of overall MSHR miss cycles 155411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2780082500 # number of ReadReq MSHR uncacheable cycles 155511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6040017000 # number of ReadReq MSHR uncacheable cycles 155611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 8820099500 # number of ReadReq MSHR uncacheable cycles 155711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5985704467 # number of WriteReq MSHR uncacheable cycles 155811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5985704467 # number of WriteReq MSHR uncacheable cycles 155911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 2780082500 # number of overall MSHR uncacheable cycles 156011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 12025721467 # number of overall MSHR uncacheable cycles 156111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::total 14805803967 # number of overall MSHR uncacheable cycles 156211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.019588 # mshr miss rate for ReadReq accesses 156311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.044426 # mshr miss rate for ReadReq accesses 156411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.025505 # mshr miss rate for ReadReq accesses 156511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses 156611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses 156711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses 156811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses 156910576Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 157010576Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 157111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.997902 # mshr miss rate for UpgradeReq accesses 157211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.997902 # mshr miss rate for UpgradeReq accesses 157311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999995 # mshr miss rate for SCUpgradeReq accesses 157411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for SCUpgradeReq accesses 157510576Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 157610576Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 157711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.221153 # mshr miss rate for ReadExReq accesses 157811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.221153 # mshr miss rate for ReadExReq accesses 157911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.092567 # mshr miss rate for ReadCleanReq accesses 158011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.092567 # mshr miss rate for ReadCleanReq accesses 158111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.246000 # mshr miss rate for ReadSharedReq accesses 158211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.246000 # mshr miss rate for ReadSharedReq accesses 158311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.758950 # mshr miss rate for InvalidateReq accesses 158411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.758950 # mshr miss rate for InvalidateReq accesses 158511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.019588 # mshr miss rate for demand accesses 158611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.044426 # mshr miss rate for demand accesses 158711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.092567 # mshr miss rate for demand accesses 158811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.240232 # mshr miss rate for demand accesses 158911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::total 0.152043 # mshr miss rate for demand accesses 159011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.019588 # mshr miss rate for overall accesses 159111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.044426 # mshr miss rate for overall accesses 159211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.092567 # mshr miss rate for overall accesses 159311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.240232 # mshr miss rate for overall accesses 159410576Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 159511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::total 0.221033 # mshr miss rate for overall accesses 159611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 42179.998293 # average ReadReq mshr miss latency 159711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 49132.779583 # average ReadReq mshr miss latency 159811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 45064.806953 # average ReadReq mshr miss latency 159911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 72956.909009 # average HardPFReq mshr miss latency 160011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 72956.909009 # average HardPFReq mshr miss latency 160111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 30134.296338 # average UpgradeReq mshr miss latency 160211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 30134.296338 # average UpgradeReq mshr miss latency 160311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20100.208818 # average SCUpgradeReq mshr miss latency 160411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 20100.208818 # average SCUpgradeReq mshr miss latency 160511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 1898374.750000 # average SCUpgradeFailReq mshr miss latency 160611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1898374.750000 # average SCUpgradeFailReq mshr miss latency 160711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 62916.478228 # average ReadExReq mshr miss latency 160811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 62916.478228 # average ReadExReq mshr miss latency 160911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 34813.267626 # average ReadCleanReq mshr miss latency 161011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34813.267626 # average ReadCleanReq mshr miss latency 161111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 38027.542623 # average ReadSharedReq mshr miss latency 161211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 38027.542623 # average ReadSharedReq mshr miss latency 161311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 135289.222825 # average InvalidateReq mshr miss latency 161411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 135289.222825 # average InvalidateReq mshr miss latency 161511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 42179.998293 # average overall mshr miss latency 161611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 49132.779583 # average overall mshr miss latency 161711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34813.267626 # average overall mshr miss latency 161811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 43346.662323 # average overall mshr miss latency 161911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::total 40758.380621 # average overall mshr miss latency 162011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 42179.998293 # average overall mshr miss latency 162111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 49132.779583 # average overall mshr miss latency 162211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34813.267626 # average overall mshr miss latency 162311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 43346.662323 # average overall mshr miss latency 162411201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 72956.909009 # average overall mshr miss latency 162511201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50808.334361 # average overall mshr miss latency 162611201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263 # average ReadReq mshr uncacheable latency 162711201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183704.400985 # average ReadReq mshr uncacheable latency 162811201Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 162816.574983 # average ReadReq mshr uncacheable latency 162911201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181489.477790 # average WriteReq mshr uncacheable latency 163011201Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181489.477790 # average WriteReq mshr uncacheable latency 163111201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 130563.213263 # average overall mshr uncacheable latency 163211201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 182595.224218 # average overall mshr uncacheable latency 163311201Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 169882.895219 # average overall mshr uncacheable latency 163410576Sandreas.hansson@arm.comsystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 163511201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_requests 24664078 # Total number of requests made to the snoop filter. 163611201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_requests 12671171 # Number of requests hitting in the snoop filter with a single holder of the requested data. 163711201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_requests 2283 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 163811201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.tot_snoops 2001831 # Total number of snoops made to the snoop filter. 163911201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_single_snoops 2001348 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 164011201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 483 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 164111201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 921539 # Transaction distribution 164211201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 11008242 # Transaction distribution 164311201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution 164411201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 32982 # Transaction distribution 164511201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 32981 # Transaction distribution 164611201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackDirty 5510686 # Transaction distribution 164711201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WritebackClean 8013020 # Transaction distribution 164811201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::CleanEvict 2592060 # Transaction distribution 164911201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFReq 1056695 # Transaction distribution 165011201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution 165111201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 478539 # Transaction distribution 165211201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 354281 # Transaction distribution 165311201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 520874 # Transaction distribution 165411201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 100 # Transaction distribution 165511201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeFailResp 211 # Transaction distribution 165611201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1281558 # Transaction distribution 165711201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1212477 # Transaction distribution 165811201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadCleanReq 6005776 # Transaction distribution 165911201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadSharedReq 4986753 # Transaction distribution 166011201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateReq 818816 # Transaction distribution 166111201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::InvalidateResp 810530 # Transaction distribution 166211201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18057865 # Packet count per connected master and slave (bytes) 166311201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 19072336 # Packet count per connected master and slave (bytes) 166411201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 391759 # Packet count per connected master and slave (bytes) 166511201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1260604 # Packet count per connected master and slave (bytes) 166611201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 38782564 # Packet count per connected master and slave (bytes) 166711201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 768948880 # Cumulative packet size per connected master and slave (bytes) 166811201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 715383853 # Cumulative packet size per connected master and slave (bytes) 166911201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1495872 # Cumulative packet size per connected master and slave (bytes) 167011201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4784112 # Cumulative packet size per connected master and slave (bytes) 167111201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 1490612717 # Cumulative packet size per connected master and slave (bytes) 167211201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 7046224 # Total snoops (count) 167311201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 20167865 # Request fanout histogram 167411201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 0.116092 # Request fanout histogram 167511201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.320411 # Request fanout histogram 167610576Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 167711201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::0 17827011 88.39% 88.39% # Request fanout histogram 167811201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 2340371 11.60% 100.00% # Request fanout histogram 167911201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 483 0.00% 100.00% # Request fanout histogram 168010576Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 168111138Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 168210827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 168311201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 20167865 # Request fanout histogram 168411201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.occupancy 24544733928 # Layer occupancy (ticks) 168511201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 168611201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.occupancy 212322671 # Layer occupancy (ticks) 168710576Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 168811201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.occupancy 9035902540 # Layer occupancy (ticks) 168910576Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 169011201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.occupancy 8451585698 # Layer occupancy (ticks) 169110576Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 169211201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.occupancy 205222100 # Layer occupancy (ticks) 169310576Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 169411201Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.occupancy 663162345 # Layer occupancy (ticks) 169510576Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 169611201Sandreas.hansson@arm.comsystem.cpu1.branchPred.lookups 136771271 # Number of BP lookups 169711201Sandreas.hansson@arm.comsystem.cpu1.branchPred.condPredicted 91615454 # Number of conditional branches predicted 169811201Sandreas.hansson@arm.comsystem.cpu1.branchPred.condIncorrect 6699408 # Number of conditional branches incorrect 169911201Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBLookups 96252672 # Number of BTB lookups 170011201Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBHits 62838118 # Number of BTB hits 170110576Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 170211201Sandreas.hansson@arm.comsystem.cpu1.branchPred.BTBHitPct 65.284544 # BTB Hit Percentage 170311201Sandreas.hansson@arm.comsystem.cpu1.branchPred.usedRAS 18248077 # Number of times the RAS was used to get a target. 170411201Sandreas.hansson@arm.comsystem.cpu1.branchPred.RASInCorrect 178326 # Number of incorrect RAS predictions. 170510628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 170610628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 170710628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 170810628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 170910628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 171010628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 171110628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 171210628Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 171310576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 171410576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 171510576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 171610576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 171710576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 171810576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 171910576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 172010576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 172110576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 172210576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 172310576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 172410576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 172510576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 172610576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 172710576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 172810576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 172910576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 173010576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 173110576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 173210576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 173310576Sandreas.hansson@arm.comsystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 173411201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walks 587464 # Table walker walks requested 173511201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLong 587464 # Table walker walks initiated with long descriptors 173611201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level2 12287 # Level at which table walker walks with long descriptors terminate 173711201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level3 93954 # Level at which table walker walks with long descriptors terminate 173811201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksSquashedBefore 273243 # Table walks squashed before starting 173911201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 314221 # Table walker wait (enqueue to first request) latency 174011201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::mean 2460.273184 # Table walker wait (enqueue to first request) latency 174111201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::stdev 14941.067276 # Table walker wait (enqueue to first request) latency 174211201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0-65535 311748 99.21% 99.21% # Table walker wait (enqueue to first request) latency 174311201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::65536-131071 1254 0.40% 99.61% # Table walker wait (enqueue to first request) latency 174411201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::131072-196607 917 0.29% 99.90% # Table walker wait (enqueue to first request) latency 174511201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::196608-262143 161 0.05% 99.96% # Table walker wait (enqueue to first request) latency 174611201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::262144-327679 52 0.02% 99.97% # Table walker wait (enqueue to first request) latency 174711167Sjthestness@gmail.comsystem.cpu1.dtb.walker.walkWaitTime::327680-393215 63 0.02% 99.99% # Table walker wait (enqueue to first request) latency 174811201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::393216-458751 18 0.01% 100.00% # Table walker wait (enqueue to first request) latency 174911167Sjthestness@gmail.comsystem.cpu1.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 175011201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 175111201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 175211201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 175311201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 314221 # Table walker wait (enqueue to first request) latency 175411201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::samples 302969 # Table walker service (enqueue to completion) latency 175511201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::mean 20764.791117 # Table walker service (enqueue to completion) latency 175611201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::gmean 17394.458301 # Table walker service (enqueue to completion) latency 175711201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::stdev 22544.227052 # Table walker service (enqueue to completion) latency 175811201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::0-65535 299168 98.75% 98.75% # Table walker service (enqueue to completion) latency 175911201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::65536-131071 939 0.31% 99.06% # Table walker service (enqueue to completion) latency 176011201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::131072-196607 1914 0.63% 99.69% # Table walker service (enqueue to completion) latency 176111201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::196608-262143 156 0.05% 99.74% # Table walker service (enqueue to completion) latency 176211201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::262144-327679 510 0.17% 99.91% # Table walker service (enqueue to completion) latency 176311201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::327680-393215 121 0.04% 99.95% # Table walker service (enqueue to completion) latency 176411201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::393216-458751 110 0.04% 99.98% # Table walker service (enqueue to completion) latency 176511201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::458752-524287 28 0.01% 99.99% # Table walker service (enqueue to completion) latency 176611201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::524288-589823 7 0.00% 99.99% # Table walker service (enqueue to completion) latency 176711201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::589824-655359 9 0.00% 100.00% # Table walker service (enqueue to completion) latency 176811201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::655360-720895 7 0.00% 100.00% # Table walker service (enqueue to completion) latency 176911201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::total 302969 # Table walker service (enqueue to completion) latency 177011201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::samples 477883045620 # Table walker pending requests distribution 177111201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::mean 0.598615 # Table walker pending requests distribution 177211201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::stdev 0.553378 # Table walker pending requests distribution 177311201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::0-1 476579478620 99.73% 99.73% # Table walker pending requests distribution 177411201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::2-3 689019500 0.14% 99.87% # Table walker pending requests distribution 177511201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::4-5 279828500 0.06% 99.93% # Table walker pending requests distribution 177611201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::6-7 139297000 0.03% 99.96% # Table walker pending requests distribution 177711201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::8-9 94668000 0.02% 99.98% # Table walker pending requests distribution 177811201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::10-11 55014500 0.01% 99.99% # Table walker pending requests distribution 177911201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::12-13 17997000 0.00% 99.99% # Table walker pending requests distribution 178011201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::14-15 27375000 0.01% 100.00% # Table walker pending requests distribution 178111201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::16-17 352000 0.00% 100.00% # Table walker pending requests distribution 178211201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::18-19 15500 0.00% 100.00% # Table walker pending requests distribution 178311201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::total 477883045620 # Table walker pending requests distribution 178411201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 93955 88.43% 88.43% # Table walker page sizes translated 178511201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::2M 12287 11.57% 100.00% # Table walker page sizes translated 178611201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 106242 # Table walker page sizes translated 178711201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 587464 # Table walker requests started/completed, data/inst 178810628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 178911201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 587464 # Table walker requests started/completed, data/inst 179011201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 106242 # Table walker requests started/completed, data/inst 179110628Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 179211201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 106242 # Table walker requests started/completed, data/inst 179311201Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 693706 # Table walker requests started/completed, data/inst 179410576Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_hits 0 # ITB inst hits 179510576Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_misses 0 # ITB inst misses 179611201Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 101377575 # DTB read hits 179711201Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 401827 # DTB read misses 179811201Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 83690670 # DTB write hits 179911201Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 185637 # DTB write misses 180011103Snilay@cs.wisc.edusystem.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 180110576Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 180211201Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 44695 # Number of times TLB was flushed by MVA & ASID 180311201Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID 180411201Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 39959 # Number of entries that have been flushed from TLB 180511201Sandreas.hansson@arm.comsystem.cpu1.dtb.align_faults 225 # Number of TLB faults due to alignment restrictions 180611201Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 6406 # Number of TLB faults due to prefetch 180710576Sandreas.hansson@arm.comsystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 180811201Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 43965 # Number of TLB faults due to permissions restrictions 180911201Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 101779402 # DTB read accesses 181011201Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 83876307 # DTB write accesses 181110576Sandreas.hansson@arm.comsystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 181211201Sandreas.hansson@arm.comsystem.cpu1.dtb.hits 185068245 # DTB hits 181311201Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 587464 # DTB misses 181411201Sandreas.hansson@arm.comsystem.cpu1.dtb.accesses 185655709 # DTB accesses 181510628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 181610628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 181710628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 181810628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 181910628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 182010628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 182110628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 182210628Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 182310576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 182410576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 182510576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 182610576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 182710576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 182810576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 182910576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 183010576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 183110576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 183210576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 183310576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 183410576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 183510576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 183610576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 183710576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 183810576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 183910576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 184010576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 184110576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 184210576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 184310576Sandreas.hansson@arm.comsystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 184411201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walks 92227 # Table walker walks requested 184511201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLong 92227 # Table walker walks initiated with long descriptors 184611201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level2 973 # Level at which table walker walks with long descriptors terminate 184711201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level3 66704 # Level at which table walker walks with long descriptors terminate 184811201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksSquashedBefore 11080 # Table walks squashed before starting 184911201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 81147 # Table walker wait (enqueue to first request) latency 185011201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::mean 1613.670253 # Table walker wait (enqueue to first request) latency 185111201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::stdev 12323.334174 # Table walker wait (enqueue to first request) latency 185211201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::0-32767 80305 98.96% 98.96% # Table walker wait (enqueue to first request) latency 185311201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::32768-65535 403 0.50% 99.46% # Table walker wait (enqueue to first request) latency 185411201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::65536-98303 31 0.04% 99.50% # Table walker wait (enqueue to first request) latency 185511201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::98304-131071 81 0.10% 99.60% # Table walker wait (enqueue to first request) latency 185611201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::131072-163839 234 0.29% 99.89% # Table walker wait (enqueue to first request) latency 185711201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::163840-196607 59 0.07% 99.96% # Table walker wait (enqueue to first request) latency 185811201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::196608-229375 7 0.01% 99.97% # Table walker wait (enqueue to first request) latency 185911201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::229376-262143 8 0.01% 99.98% # Table walker wait (enqueue to first request) latency 186011201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::262144-294911 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency 186111201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::294912-327679 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency 186211201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 186311201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 186411201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 186511201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 81147 # Table walker wait (enqueue to first request) latency 186611201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::samples 78757 # Table walker service (enqueue to completion) latency 186711201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::mean 26873.185876 # Table walker service (enqueue to completion) latency 186811201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::gmean 22946.544582 # Table walker service (enqueue to completion) latency 186911201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::stdev 27397.779974 # Table walker service (enqueue to completion) latency 187011201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::0-65535 76775 97.48% 97.48% # Table walker service (enqueue to completion) latency 187111201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::65536-131071 153 0.19% 97.68% # Table walker service (enqueue to completion) latency 187211201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::131072-196607 1519 1.93% 99.61% # Table walker service (enqueue to completion) latency 187311201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::196608-262143 117 0.15% 99.75% # Table walker service (enqueue to completion) latency 187411201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::262144-327679 110 0.14% 99.89% # Table walker service (enqueue to completion) latency 187511201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::327680-393215 35 0.04% 99.94% # Table walker service (enqueue to completion) latency 187611201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::393216-458751 36 0.05% 99.98% # Table walker service (enqueue to completion) latency 187711201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::458752-524287 6 0.01% 99.99% # Table walker service (enqueue to completion) latency 187811201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::524288-589823 4 0.01% 100.00% # Table walker service (enqueue to completion) latency 187911201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 188011201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::786432-851967 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 188111201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::total 78757 # Table walker service (enqueue to completion) latency 188211201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::samples 434901307160 # Table walker pending requests distribution 188311201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::mean 0.857521 # Table walker pending requests distribution 188411201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::stdev 0.349757 # Table walker pending requests distribution 188511201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::0 61992873300 14.25% 14.25% # Table walker pending requests distribution 188611201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::1 372883353360 85.74% 99.99% # Table walker pending requests distribution 188711201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::2 22166000 0.01% 100.00% # Table walker pending requests distribution 188811201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::3 2474500 0.00% 100.00% # Table walker pending requests distribution 188911201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::4 253500 0.00% 100.00% # Table walker pending requests distribution 189011201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::5 186500 0.00% 100.00% # Table walker pending requests distribution 189111201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::total 434901307160 # Table walker pending requests distribution 189211201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 66704 98.56% 98.56% # Table walker page sizes translated 189311201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::2M 973 1.44% 100.00% # Table walker page sizes translated 189411201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 67677 # Table walker page sizes translated 189510628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 189611201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 92227 # Table walker requests started/completed, data/inst 189711201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 92227 # Table walker requests started/completed, data/inst 189810628Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 189911201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 67677 # Table walker requests started/completed, data/inst 190011201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 67677 # Table walker requests started/completed, data/inst 190111201Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 159904 # Table walker requests started/completed, data/inst 190211201Sandreas.hansson@arm.comsystem.cpu1.itb.inst_hits 215454990 # ITB inst hits 190311201Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 92227 # ITB inst misses 190410576Sandreas.hansson@arm.comsystem.cpu1.itb.read_hits 0 # DTB read hits 190510576Sandreas.hansson@arm.comsystem.cpu1.itb.read_misses 0 # DTB read misses 190610576Sandreas.hansson@arm.comsystem.cpu1.itb.write_hits 0 # DTB write hits 190710576Sandreas.hansson@arm.comsystem.cpu1.itb.write_misses 0 # DTB write misses 190811103Snilay@cs.wisc.edusystem.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 190910576Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 191011201Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 44695 # Number of times TLB was flushed by MVA & ASID 191111201Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID 191211201Sandreas.hansson@arm.comsystem.cpu1.itb.flush_entries 28858 # Number of entries that have been flushed from TLB 191310576Sandreas.hansson@arm.comsystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 191410576Sandreas.hansson@arm.comsystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 191510576Sandreas.hansson@arm.comsystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 191611201Sandreas.hansson@arm.comsystem.cpu1.itb.perms_faults 231246 # Number of TLB faults due to permissions restrictions 191710576Sandreas.hansson@arm.comsystem.cpu1.itb.read_accesses 0 # DTB read accesses 191810576Sandreas.hansson@arm.comsystem.cpu1.itb.write_accesses 0 # DTB write accesses 191911201Sandreas.hansson@arm.comsystem.cpu1.itb.inst_accesses 215547217 # ITB inst accesses 192011201Sandreas.hansson@arm.comsystem.cpu1.itb.hits 215454990 # DTB hits 192111201Sandreas.hansson@arm.comsystem.cpu1.itb.misses 92227 # DTB misses 192211201Sandreas.hansson@arm.comsystem.cpu1.itb.accesses 215547217 # DTB accesses 192311201Sandreas.hansson@arm.comsystem.cpu1.numCycles 759155378 # number of cpu cycles simulated 192410576Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 192510576Sandreas.hansson@arm.comsystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 192611201Sandreas.hansson@arm.comsystem.cpu1.fetch.icacheStallCycles 87128814 # Number of cycles fetch is stalled on an Icache miss 192711201Sandreas.hansson@arm.comsystem.cpu1.fetch.Insts 606063748 # Number of instructions fetch has processed 192811201Sandreas.hansson@arm.comsystem.cpu1.fetch.Branches 136771271 # Number of branches that fetch encountered 192911201Sandreas.hansson@arm.comsystem.cpu1.fetch.predictedBranches 81086195 # Number of branches that fetch has predicted taken 193011201Sandreas.hansson@arm.comsystem.cpu1.fetch.Cycles 630037393 # Number of cycles fetch has run and was not squashing or blocked 193111201Sandreas.hansson@arm.comsystem.cpu1.fetch.SquashCycles 14425462 # Number of cycles fetch has spent squashing 193211201Sandreas.hansson@arm.comsystem.cpu1.fetch.TlbCycles 2172177 # Number of cycles fetch has spent waiting for tlb 193311201Sandreas.hansson@arm.comsystem.cpu1.fetch.MiscStallCycles 325931 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 193411201Sandreas.hansson@arm.comsystem.cpu1.fetch.PendingTrapStallCycles 6736887 # Number of stall cycles due to pending traps 193511201Sandreas.hansson@arm.comsystem.cpu1.fetch.PendingQuiesceStallCycles 827556 # Number of stall cycles due to pending quiesce instructions 193611201Sandreas.hansson@arm.comsystem.cpu1.fetch.IcacheWaitRetryStallCycles 851702 # Number of stall cycles due to full MSHR 193711201Sandreas.hansson@arm.comsystem.cpu1.fetch.CacheLines 215200214 # Number of cache lines fetched 193811201Sandreas.hansson@arm.comsystem.cpu1.fetch.IcacheSquashes 1679756 # Number of outstanding Icache misses that were squashed 193911201Sandreas.hansson@arm.comsystem.cpu1.fetch.ItlbSquashes 31517 # Number of outstanding ITLB misses that were squashed 194011201Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::samples 735293191 # Number of instructions fetched each cycle (Total) 194111201Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::mean 0.969104 # Number of instructions fetched each cycle (Total) 194211201Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::stdev 1.218230 # Number of instructions fetched each cycle (Total) 194310576Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 194411201Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::0 394185812 53.61% 53.61% # Number of instructions fetched each cycle (Total) 194511201Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::1 132782093 18.06% 71.67% # Number of instructions fetched each cycle (Total) 194611201Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::2 45182528 6.14% 77.81% # Number of instructions fetched each cycle (Total) 194711201Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::3 163142758 22.19% 100.00% # Number of instructions fetched each cycle (Total) 194810576Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 194910576Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 195010576Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 195111201Sandreas.hansson@arm.comsystem.cpu1.fetch.rateDist::total 735293191 # Number of instructions fetched each cycle (Total) 195211201Sandreas.hansson@arm.comsystem.cpu1.fetch.branchRate 0.180162 # Number of branch fetches per cycle 195311201Sandreas.hansson@arm.comsystem.cpu1.fetch.rate 0.798340 # Number of inst fetches per cycle 195411201Sandreas.hansson@arm.comsystem.cpu1.decode.IdleCycles 105275670 # Number of cycles decode is idle 195511201Sandreas.hansson@arm.comsystem.cpu1.decode.BlockedCycles 361149345 # Number of cycles decode is blocked 195611201Sandreas.hansson@arm.comsystem.cpu1.decode.RunCycles 225652352 # Number of cycles decode is running 195711201Sandreas.hansson@arm.comsystem.cpu1.decode.UnblockCycles 38094367 # Number of cycles decode is unblocking 195811201Sandreas.hansson@arm.comsystem.cpu1.decode.SquashCycles 5121457 # Number of cycles decode is squashing 195911201Sandreas.hansson@arm.comsystem.cpu1.decode.BranchResolved 19322389 # Number of times decode resolved a branch 196011201Sandreas.hansson@arm.comsystem.cpu1.decode.BranchMispred 2132865 # Number of times decode detected a branch misprediction 196111201Sandreas.hansson@arm.comsystem.cpu1.decode.DecodedInsts 630175710 # Number of instructions handled by decode 196211201Sandreas.hansson@arm.comsystem.cpu1.decode.SquashedInsts 23074598 # Number of squashed instructions handled by decode 196311201Sandreas.hansson@arm.comsystem.cpu1.rename.SquashCycles 5121457 # Number of cycles rename is squashing 196411201Sandreas.hansson@arm.comsystem.cpu1.rename.IdleCycles 140790232 # Number of cycles rename is idle 196511201Sandreas.hansson@arm.comsystem.cpu1.rename.BlockCycles 54705867 # Number of cycles rename is blocking 196611201Sandreas.hansson@arm.comsystem.cpu1.rename.serializeStallCycles 237824642 # count of cycles rename stalled for serializing inst 196711201Sandreas.hansson@arm.comsystem.cpu1.rename.RunCycles 227778492 # Number of cycles rename is running 196811201Sandreas.hansson@arm.comsystem.cpu1.rename.UnblockCycles 69072501 # Number of cycles rename is unblocking 196911201Sandreas.hansson@arm.comsystem.cpu1.rename.RenamedInsts 613335461 # Number of instructions processed by rename 197011201Sandreas.hansson@arm.comsystem.cpu1.rename.SquashedInsts 5878562 # Number of squashed instructions processed by rename 197111201Sandreas.hansson@arm.comsystem.cpu1.rename.ROBFullEvents 11068691 # Number of times rename has blocked due to ROB full 197211201Sandreas.hansson@arm.comsystem.cpu1.rename.IQFullEvents 265258 # Number of times rename has blocked due to IQ full 197311201Sandreas.hansson@arm.comsystem.cpu1.rename.LQFullEvents 344448 # Number of times rename has blocked due to LQ full 197411201Sandreas.hansson@arm.comsystem.cpu1.rename.SQFullEvents 33464644 # Number of times rename has blocked due to SQ full 197511201Sandreas.hansson@arm.comsystem.cpu1.rename.FullRegisterEvents 12708 # Number of times there has been no free registers 197611201Sandreas.hansson@arm.comsystem.cpu1.rename.RenamedOperands 582683755 # Number of destination operands rename has renamed 197711201Sandreas.hansson@arm.comsystem.cpu1.rename.RenameLookups 946463821 # Number of register rename lookups that rename has made 197811201Sandreas.hansson@arm.comsystem.cpu1.rename.int_rename_lookups 725287459 # Number of integer rename lookups 197911201Sandreas.hansson@arm.comsystem.cpu1.rename.fp_rename_lookups 802163 # Number of floating rename lookups 198011201Sandreas.hansson@arm.comsystem.cpu1.rename.CommittedMaps 525337621 # Number of HB maps that are committed 198111201Sandreas.hansson@arm.comsystem.cpu1.rename.UndoneMaps 57346134 # Number of HB maps that are undone due to squashing 198211201Sandreas.hansson@arm.comsystem.cpu1.rename.serializingInsts 16349116 # count of serializing insts renamed 198311201Sandreas.hansson@arm.comsystem.cpu1.rename.tempSerializingInsts 14383675 # count of temporary serializing insts renamed 198411201Sandreas.hansson@arm.comsystem.cpu1.rename.skidInsts 76724538 # count of insts added to the skid buffer 198511201Sandreas.hansson@arm.comsystem.cpu1.memDep0.insertedLoads 101292205 # Number of loads inserted to the mem dependence unit. 198611201Sandreas.hansson@arm.comsystem.cpu1.memDep0.insertedStores 87094038 # Number of stores inserted to the mem dependence unit. 198711201Sandreas.hansson@arm.comsystem.cpu1.memDep0.conflictingLoads 9603338 # Number of conflicting loads. 198811201Sandreas.hansson@arm.comsystem.cpu1.memDep0.conflictingStores 8276902 # Number of conflicting stores. 198911201Sandreas.hansson@arm.comsystem.cpu1.iq.iqInstsAdded 590341476 # Number of instructions added to the IQ (excludes non-spec) 199011201Sandreas.hansson@arm.comsystem.cpu1.iq.iqNonSpecInstsAdded 16600780 # Number of non-speculative instructions added to the IQ 199111201Sandreas.hansson@arm.comsystem.cpu1.iq.iqInstsIssued 596033149 # Number of instructions issued 199211201Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedInstsIssued 2703684 # Number of squashed instructions issued 199311201Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedInstsExamined 54441407 # Number of squashed instructions iterated over during squash; mainly for profiling 199411201Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedOperandsExamined 34942140 # Number of squashed operands that are examined and possibly removed from graph 199511201Sandreas.hansson@arm.comsystem.cpu1.iq.iqSquashedNonSpecRemoved 296921 # Number of squashed non-spec instructions that were removed 199611201Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::samples 735293191 # Number of insts issued each cycle 199711201Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::mean 0.810606 # Number of insts issued each cycle 199811201Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::stdev 1.063717 # Number of insts issued each cycle 199910576Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 200011201Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::0 408888874 55.61% 55.61% # Number of insts issued each cycle 200111201Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::1 138685440 18.86% 74.47% # Number of insts issued each cycle 200211201Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::2 113812160 15.48% 89.95% # Number of insts issued each cycle 200311201Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::3 65908523 8.96% 98.91% # Number of insts issued each cycle 200411201Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::4 7993150 1.09% 100.00% # Number of insts issued each cycle 200511201Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::5 5044 0.00% 100.00% # Number of insts issued each cycle 200610628Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 200710576Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 200810576Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 200910576Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 201010576Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 201110628Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 201211201Sandreas.hansson@arm.comsystem.cpu1.iq.issued_per_cycle::total 735293191 # Number of insts issued each cycle 201310576Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 201411201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::IntAlu 59894815 43.89% 43.89% # attempts to use FU when none available 201511201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::IntMult 54223 0.04% 43.93% # attempts to use FU when none available 201611201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::IntDiv 19415 0.01% 43.94% # attempts to use FU when none available 201711201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.94% # attempts to use FU when none available 201811201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.94% # attempts to use FU when none available 201911201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.94% # attempts to use FU when none available 202011201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatMult 0 0.00% 43.94% # attempts to use FU when none available 202111201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.94% # attempts to use FU when none available 202211201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.94% # attempts to use FU when none available 202311201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.94% # attempts to use FU when none available 202411201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.94% # attempts to use FU when none available 202511201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.94% # attempts to use FU when none available 202611201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.94% # attempts to use FU when none available 202711201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.94% # attempts to use FU when none available 202811201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.94% # attempts to use FU when none available 202911201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdMult 0 0.00% 43.94% # attempts to use FU when none available 203011201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.94% # attempts to use FU when none available 203111201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdShift 0 0.00% 43.94% # attempts to use FU when none available 203211201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.94% # attempts to use FU when none available 203311201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.94% # attempts to use FU when none available 203411201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.94% # attempts to use FU when none available 203511201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.94% # attempts to use FU when none available 203611201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.94% # attempts to use FU when none available 203711201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.94% # attempts to use FU when none available 203811201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.94% # attempts to use FU when none available 203911201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatMisc 13 0.00% 43.94% # attempts to use FU when none available 204011201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.94% # attempts to use FU when none available 204111201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.94% # attempts to use FU when none available 204211201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.94% # attempts to use FU when none available 204311201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::MemRead 36698954 26.89% 70.83% # attempts to use FU when none available 204411201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::MemWrite 39811710 29.17% 100.00% # attempts to use FU when none available 204510576Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 204610576Sandreas.hansson@arm.comsystem.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 204711201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::No_OpClass 40 0.00% 0.00% # Type of FU issued 204811201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IntAlu 405160238 67.98% 67.98% # Type of FU issued 204911201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IntMult 1323587 0.22% 68.20% # Type of FU issued 205011201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IntDiv 73165 0.01% 68.21% # Type of FU issued 205111201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatAdd 6 0.00% 68.21% # Type of FU issued 205211201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.21% # Type of FU issued 205311201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.21% # Type of FU issued 205411201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.21% # Type of FU issued 205511201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.21% # Type of FU issued 205611201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.21% # Type of FU issued 205711201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.21% # Type of FU issued 205811201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.21% # Type of FU issued 205911201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.21% # Type of FU issued 206011201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.21% # Type of FU issued 206111201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.21% # Type of FU issued 206211201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.21% # Type of FU issued 206311201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.21% # Type of FU issued 206411201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.21% # Type of FU issued 206511201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.21% # Type of FU issued 206611201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.21% # Type of FU issued 206711201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.21% # Type of FU issued 206811201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.21% # Type of FU issued 206911201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.21% # Type of FU issued 207011201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.21% # Type of FU issued 207111201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.21% # Type of FU issued 207211201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.21% # Type of FU issued 207311201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMisc 83635 0.01% 68.22% # Type of FU issued 207411201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.22% # Type of FU issued 207511201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.22% # Type of FU issued 207611201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.22% # Type of FU issued 207711201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::MemRead 104404803 17.52% 85.74% # Type of FU issued 207811201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::MemWrite 84987627 14.26% 100.00% # Type of FU issued 207910576Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 208010576Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 208111201Sandreas.hansson@arm.comsystem.cpu1.iq.FU_type_0::total 596033149 # Type of FU issued 208211201Sandreas.hansson@arm.comsystem.cpu1.iq.rate 0.785127 # Inst issue rate 208311201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_busy_cnt 136479130 # FU busy when requested 208411201Sandreas.hansson@arm.comsystem.cpu1.iq.fu_busy_rate 0.228979 # FU busy rate (busy events/executed inst) 208511201Sandreas.hansson@arm.comsystem.cpu1.iq.int_inst_queue_reads 2065187396 # Number of integer instruction queue reads 208611201Sandreas.hansson@arm.comsystem.cpu1.iq.int_inst_queue_writes 660997777 # Number of integer instruction queue writes 208711201Sandreas.hansson@arm.comsystem.cpu1.iq.int_inst_queue_wakeup_accesses 578833453 # Number of integer instruction queue wakeup accesses 208811201Sandreas.hansson@arm.comsystem.cpu1.iq.fp_inst_queue_reads 1354907 # Number of floating instruction queue reads 208911201Sandreas.hansson@arm.comsystem.cpu1.iq.fp_inst_queue_writes 550149 # Number of floating instruction queue writes 209011201Sandreas.hansson@arm.comsystem.cpu1.iq.fp_inst_queue_wakeup_accesses 503649 # Number of floating instruction queue wakeup accesses 209111201Sandreas.hansson@arm.comsystem.cpu1.iq.int_alu_accesses 731674033 # Number of integer alu accesses 209211201Sandreas.hansson@arm.comsystem.cpu1.iq.fp_alu_accesses 838206 # Number of floating point alu accesses 209311201Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.forwLoads 2717332 # Number of loads that had data forwarded from stores 209410576Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 209511201Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.squashedLoads 12501770 # Number of loads squashed 209611201Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.ignoredResponses 16793 # Number of memory responses ignored because the instruction is squashed 209711201Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.memOrderViolation 165759 # Number of memory ordering violations 209811201Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.squashedStores 5982611 # Number of stores squashed 209910576Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 210010576Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 210111201Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.rescheduledLoads 2801463 # Number of loads that were rescheduled 210211201Sandreas.hansson@arm.comsystem.cpu1.iew.lsq.thread0.cacheBlocked 4362378 # Number of times an access to memory failed due to the cache being blocked 210310576Sandreas.hansson@arm.comsystem.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 210411201Sandreas.hansson@arm.comsystem.cpu1.iew.iewSquashCycles 5121457 # Number of cycles IEW is squashing 210511201Sandreas.hansson@arm.comsystem.cpu1.iew.iewBlockCycles 6701200 # Number of cycles IEW is blocking 210611201Sandreas.hansson@arm.comsystem.cpu1.iew.iewUnblockCycles 2456436 # Number of cycles IEW is unblocking 210711201Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispatchedInsts 607072203 # Number of instructions dispatched to IQ 210810576Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 210911201Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispLoadInsts 101292205 # Number of dispatched load instructions 211011201Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispStoreInsts 87094038 # Number of dispatched store instructions 211111201Sandreas.hansson@arm.comsystem.cpu1.iew.iewDispNonSpecInsts 14166456 # Number of dispatched non-speculative instructions 211211201Sandreas.hansson@arm.comsystem.cpu1.iew.iewIQFullEvents 66987 # Number of times the IQ has become full, causing a stall 211311201Sandreas.hansson@arm.comsystem.cpu1.iew.iewLSQFullEvents 2327340 # Number of times the LSQ has become full, causing a stall 211411201Sandreas.hansson@arm.comsystem.cpu1.iew.memOrderViolationEvents 165759 # Number of memory order violations 211511201Sandreas.hansson@arm.comsystem.cpu1.iew.predictedTakenIncorrect 2053658 # Number of branches that were predicted taken incorrectly 211611201Sandreas.hansson@arm.comsystem.cpu1.iew.predictedNotTakenIncorrect 2840126 # Number of branches that were predicted not taken incorrectly 211711201Sandreas.hansson@arm.comsystem.cpu1.iew.branchMispredicts 4893784 # Number of branch mispredicts detected at execute 211811201Sandreas.hansson@arm.comsystem.cpu1.iew.iewExecutedInsts 588333719 # Number of executed instructions 211911201Sandreas.hansson@arm.comsystem.cpu1.iew.iewExecLoadInsts 101371104 # Number of load instructions executed 212011201Sandreas.hansson@arm.comsystem.cpu1.iew.iewExecSquashedInsts 7124424 # Number of squashed instructions skipped in execute 212110576Sandreas.hansson@arm.comsystem.cpu1.iew.exec_swp 0 # number of swp insts executed 212211201Sandreas.hansson@arm.comsystem.cpu1.iew.exec_nop 129947 # number of nop insts executed 212311201Sandreas.hansson@arm.comsystem.cpu1.iew.exec_refs 185062017 # number of memory reference insts executed 212411201Sandreas.hansson@arm.comsystem.cpu1.iew.exec_branches 110209905 # Number of branches executed 212511201Sandreas.hansson@arm.comsystem.cpu1.iew.exec_stores 83690913 # Number of stores executed 212611201Sandreas.hansson@arm.comsystem.cpu1.iew.exec_rate 0.774985 # Inst execution rate 212711201Sandreas.hansson@arm.comsystem.cpu1.iew.wb_sent 580075402 # cumulative count of insts sent to commit 212811201Sandreas.hansson@arm.comsystem.cpu1.iew.wb_count 579337102 # cumulative count of insts written-back 212911201Sandreas.hansson@arm.comsystem.cpu1.iew.wb_producers 280158358 # num instructions producing a value 213011201Sandreas.hansson@arm.comsystem.cpu1.iew.wb_consumers 458852190 # num instructions consuming a value 213110576Sandreas.hansson@arm.comsystem.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 213211201Sandreas.hansson@arm.comsystem.cpu1.iew.wb_rate 0.763134 # insts written-back per cycle 213311201Sandreas.hansson@arm.comsystem.cpu1.iew.wb_fanout 0.610563 # average fanout of values written-back 213410576Sandreas.hansson@arm.comsystem.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 213511201Sandreas.hansson@arm.comsystem.cpu1.commit.commitSquashedInsts 47675638 # The number of squashed insts skipped by commit 213611201Sandreas.hansson@arm.comsystem.cpu1.commit.commitNonSpecStalls 16303859 # The number of times commit has been forced to stall to communicate backwards 213711201Sandreas.hansson@arm.comsystem.cpu1.commit.branchMispredicts 4608134 # The number of times a branch was mispredicted 213811201Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::samples 726275789 # Number of insts commited each cycle 213911201Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::mean 0.760731 # Number of insts commited each cycle 214011201Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::stdev 1.562013 # Number of insts commited each cycle 214110576Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 214211201Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::0 483439526 66.56% 66.56% # Number of insts commited each cycle 214311201Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::1 126884990 17.47% 84.03% # Number of insts commited each cycle 214411201Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::2 53284484 7.34% 91.37% # Number of insts commited each cycle 214511201Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::3 17968651 2.47% 93.85% # Number of insts commited each cycle 214611201Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::4 12727519 1.75% 95.60% # Number of insts commited each cycle 214711201Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::5 8624800 1.19% 96.79% # Number of insts commited each cycle 214811201Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::6 6048440 0.83% 97.62% # Number of insts commited each cycle 214911201Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::7 3562811 0.49% 98.11% # Number of insts commited each cycle 215011201Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::8 13734568 1.89% 100.00% # Number of insts commited each cycle 215110576Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 215210576Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 215310576Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 215411201Sandreas.hansson@arm.comsystem.cpu1.commit.committed_per_cycle::total 726275789 # Number of insts commited each cycle 215511201Sandreas.hansson@arm.comsystem.cpu1.commit.committedInsts 468737677 # Number of instructions committed 215611201Sandreas.hansson@arm.comsystem.cpu1.commit.committedOps 552500848 # Number of ops (including micro ops) committed 215710576Sandreas.hansson@arm.comsystem.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 215811201Sandreas.hansson@arm.comsystem.cpu1.commit.refs 169901862 # Number of memory references committed 215911201Sandreas.hansson@arm.comsystem.cpu1.commit.loads 88790435 # Number of loads committed 216011201Sandreas.hansson@arm.comsystem.cpu1.commit.membars 3923548 # Number of memory barriers committed 216111201Sandreas.hansson@arm.comsystem.cpu1.commit.branches 104577420 # Number of branches committed 216211201Sandreas.hansson@arm.comsystem.cpu1.commit.fp_insts 490317 # Number of committed floating point instructions. 216311201Sandreas.hansson@arm.comsystem.cpu1.commit.int_insts 507351840 # Number of committed integer instructions. 216411201Sandreas.hansson@arm.comsystem.cpu1.commit.function_calls 13608772 # Number of function calls committed. 216510576Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 216611201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::IntAlu 381394130 69.03% 69.03% # Class of committed instruction 216711201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::IntMult 1072293 0.19% 69.22% # Class of committed instruction 216811201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::IntDiv 58068 0.01% 69.24% # Class of committed instruction 216911201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.24% # Class of committed instruction 217011201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.24% # Class of committed instruction 217111201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.24% # Class of committed instruction 217211201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.24% # Class of committed instruction 217311201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.24% # Class of committed instruction 217411201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.24% # Class of committed instruction 217511201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.24% # Class of committed instruction 217611201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.24% # Class of committed instruction 217711201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.24% # Class of committed instruction 217811201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.24% # Class of committed instruction 217911201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.24% # Class of committed instruction 218011201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.24% # Class of committed instruction 218111201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.24% # Class of committed instruction 218211201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.24% # Class of committed instruction 218311201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.24% # Class of committed instruction 218411201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.24% # Class of committed instruction 218511201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.24% # Class of committed instruction 218611201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.24% # Class of committed instruction 218711201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.24% # Class of committed instruction 218811201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.24% # Class of committed instruction 218911201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.24% # Class of committed instruction 219011201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.24% # Class of committed instruction 219111201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatMisc 74453 0.01% 69.25% # Class of committed instruction 219211201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.25% # Class of committed instruction 219311201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.25% # Class of committed instruction 219411201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.25% # Class of committed instruction 219511201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::MemRead 88790435 16.07% 85.32% # Class of committed instruction 219611201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::MemWrite 81111427 14.68% 100.00% # Class of committed instruction 219710576Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 219810576Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 219911201Sandreas.hansson@arm.comsystem.cpu1.commit.op_class_0::total 552500848 # Class of committed instruction 220011201Sandreas.hansson@arm.comsystem.cpu1.commit.bw_lim_events 13734568 # number cycles where commit BW limit reached 220111201Sandreas.hansson@arm.comsystem.cpu1.rob.rob_reads 1308834452 # The number of ROB reads 220211201Sandreas.hansson@arm.comsystem.cpu1.rob.rob_writes 1209328543 # The number of ROB writes 220311201Sandreas.hansson@arm.comsystem.cpu1.timesIdled 978867 # Number of times that the entire CPU went into an idle state and unscheduled itself 220411201Sandreas.hansson@arm.comsystem.cpu1.idleCycles 23862187 # Total number of cycles that the CPU has spent unscheduled due to idling 220511201Sandreas.hansson@arm.comsystem.cpu1.quiesceCycles 93869849108 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 220611201Sandreas.hansson@arm.comsystem.cpu1.committedInsts 468737677 # Number of Instructions Simulated 220711201Sandreas.hansson@arm.comsystem.cpu1.committedOps 552500848 # Number of Ops (including micro ops) Simulated 220811201Sandreas.hansson@arm.comsystem.cpu1.cpi 1.619574 # CPI: Cycles Per Instruction 220911201Sandreas.hansson@arm.comsystem.cpu1.cpi_total 1.619574 # CPI: Total CPI of All Threads 221011201Sandreas.hansson@arm.comsystem.cpu1.ipc 0.617446 # IPC: Instructions Per Cycle 221111201Sandreas.hansson@arm.comsystem.cpu1.ipc_total 0.617446 # IPC: Total IPC of All Threads 221211201Sandreas.hansson@arm.comsystem.cpu1.int_regfile_reads 695521161 # number of integer regfile reads 221311201Sandreas.hansson@arm.comsystem.cpu1.int_regfile_writes 411377637 # number of integer regfile writes 221411201Sandreas.hansson@arm.comsystem.cpu1.fp_regfile_reads 787723 # number of floating regfile reads 221511201Sandreas.hansson@arm.comsystem.cpu1.fp_regfile_writes 479172 # number of floating regfile writes 221611201Sandreas.hansson@arm.comsystem.cpu1.cc_regfile_reads 125942514 # number of cc regfile reads 221711201Sandreas.hansson@arm.comsystem.cpu1.cc_regfile_writes 126793051 # number of cc regfile writes 221811201Sandreas.hansson@arm.comsystem.cpu1.misc_regfile_reads 1299771916 # number of misc regfile reads 221911201Sandreas.hansson@arm.comsystem.cpu1.misc_regfile_writes 16418490 # number of misc regfile writes 222011201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 5616176 # number of replacements 222111201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 458.902978 # Cycle average of tags in use 222211201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 158371031 # Total number of references to valid blocks. 222311201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 5616685 # Sample count of references to valid blocks. 222411201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 28.196531 # Average number of references to valid blocks. 222511201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 8486277940000 # Cycle when the warmup percentage was hit. 222611201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 458.902978 # Average occupied blocks per requestor 222711201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.896295 # Average percentage of cache occupancy 222811201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.896295 # Average percentage of cache occupancy 222911201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id 223011201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id 223111201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 363 # Occupied blocks per task id 223211201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id 223311201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id 223411201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 352316395 # Number of tag accesses 223511201Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 352316395 # Number of data accesses 223611201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 82533449 # number of ReadReq hits 223711201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 82533449 # number of ReadReq hits 223811201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 71018677 # number of WriteReq hits 223911201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 71018677 # number of WriteReq hits 224011201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 182219 # number of SoftPFReq hits 224111201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 182219 # number of SoftPFReq hits 224211201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::cpu1.data 55748 # number of WriteLineReq hits 224311201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_hits::total 55748 # number of WriteLineReq hits 224411201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1865594 # number of LoadLockedReq hits 224511201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 1865594 # number of LoadLockedReq hits 224611201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 1903770 # number of StoreCondReq hits 224711201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 1903770 # number of StoreCondReq hits 224811201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 153552126 # number of demand (read+write) hits 224911201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 153552126 # number of demand (read+write) hits 225011201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 153734345 # number of overall hits 225111201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 153734345 # number of overall hits 225211201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 6611698 # number of ReadReq misses 225311201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 6611698 # number of ReadReq misses 225411201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 7495595 # number of WriteReq misses 225511201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 7495595 # number of WriteReq misses 225611201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 706613 # number of SoftPFReq misses 225711201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 706613 # number of SoftPFReq misses 225811201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::cpu1.data 438931 # number of WriteLineReq misses 225911201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_misses::total 438931 # number of WriteLineReq misses 226011201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 288457 # number of LoadLockedReq misses 226111201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 288457 # number of LoadLockedReq misses 226211201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 203515 # number of StoreCondReq misses 226311201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 203515 # number of StoreCondReq misses 226411201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 14107293 # number of demand (read+write) misses 226511201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 14107293 # number of demand (read+write) misses 226611201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 14813906 # number of overall misses 226711201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 14813906 # number of overall misses 226811201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 112950117500 # number of ReadReq miss cycles 226911201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 112950117500 # number of ReadReq miss cycles 227011201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 162063724604 # number of WriteReq miss cycles 227111201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 162063724604 # number of WriteReq miss cycles 227211201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 18729695563 # number of WriteLineReq miss cycles 227311201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_latency::total 18729695563 # number of WriteLineReq miss cycles 227411201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 4597585500 # number of LoadLockedReq miss cycles 227511201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 4597585500 # number of LoadLockedReq miss cycles 227611201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 5657651000 # number of StoreCondReq miss cycles 227711201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 5657651000 # number of StoreCondReq miss cycles 227811201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 7414500 # number of StoreCondFailReq miss cycles 227911201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::total 7414500 # number of StoreCondFailReq miss cycles 228011201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 275013842104 # number of demand (read+write) miss cycles 228111201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::total 275013842104 # number of demand (read+write) miss cycles 228211201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 275013842104 # number of overall miss cycles 228311201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::total 275013842104 # number of overall miss cycles 228411201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 89145147 # number of ReadReq accesses(hits+misses) 228511201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 89145147 # number of ReadReq accesses(hits+misses) 228611201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 78514272 # number of WriteReq accesses(hits+misses) 228711201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 78514272 # number of WriteReq accesses(hits+misses) 228811201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 888832 # number of SoftPFReq accesses(hits+misses) 228911201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 888832 # number of SoftPFReq accesses(hits+misses) 229011201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::cpu1.data 494679 # number of WriteLineReq accesses(hits+misses) 229111201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_accesses::total 494679 # number of WriteLineReq accesses(hits+misses) 229211201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2154051 # number of LoadLockedReq accesses(hits+misses) 229311201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 2154051 # number of LoadLockedReq accesses(hits+misses) 229411201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2107285 # number of StoreCondReq accesses(hits+misses) 229511201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 2107285 # number of StoreCondReq accesses(hits+misses) 229611201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 167659419 # number of demand (read+write) accesses 229711201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 167659419 # number of demand (read+write) accesses 229811201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 168548251 # number of overall (read+write) accesses 229911201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 168548251 # number of overall (read+write) accesses 230011201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074168 # miss rate for ReadReq accesses 230111201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.074168 # miss rate for ReadReq accesses 230211201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.095468 # miss rate for WriteReq accesses 230311201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.095468 # miss rate for WriteReq accesses 230411201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.794991 # miss rate for SoftPFReq accesses 230511201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.794991 # miss rate for SoftPFReq accesses 230611201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.887305 # miss rate for WriteLineReq accesses 230711201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_miss_rate::total 0.887305 # miss rate for WriteLineReq accesses 230811201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.133914 # miss rate for LoadLockedReq accesses 230911201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.133914 # miss rate for LoadLockedReq accesses 231011201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.096577 # miss rate for StoreCondReq accesses 231111201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.096577 # miss rate for StoreCondReq accesses 231211201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.084143 # miss rate for demand accesses 231311201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.084143 # miss rate for demand accesses 231411201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.087891 # miss rate for overall accesses 231511201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.087891 # miss rate for overall accesses 231611201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17083.375178 # average ReadReq miss latency 231711201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 17083.375178 # average ReadReq miss latency 231811201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21621.195463 # average WriteReq miss latency 231911201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 21621.195463 # average WriteReq miss latency 232011201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 42671.161442 # average WriteLineReq miss latency 232111201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_miss_latency::total 42671.161442 # average WriteLineReq miss latency 232211201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15938.547166 # average LoadLockedReq miss latency 232311201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15938.547166 # average LoadLockedReq miss latency 232411201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27799.675700 # average StoreCondReq miss latency 232511201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27799.675700 # average StoreCondReq miss latency 232610576Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 232710576Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 232811201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19494.444618 # average overall miss latency 232911201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 19494.444618 # average overall miss latency 233011201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18564.573186 # average overall miss latency 233111201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 18564.573186 # average overall miss latency 233211201Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_mshrs 4974164 # number of cycles access was blocked 233311201Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked_cycles::no_targets 25867147 # number of cycles access was blocked 233411201Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_mshrs 359446 # number of cycles access was blocked 233511201Sandreas.hansson@arm.comsystem.cpu1.dcache.blocked::no_targets 756404 # number of cycles access was blocked 233611201Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_mshrs 13.838418 # average number of cycles each access was blocked 233711201Sandreas.hansson@arm.comsystem.cpu1.dcache.avg_blocked_cycles::no_targets 34.197528 # average number of cycles each access was blocked 233810585Sandreas.hansson@arm.comsystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 233910576Sandreas.hansson@arm.comsystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 234011201Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 5616192 # number of writebacks 234111201Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 5616192 # number of writebacks 234211201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3382349 # number of ReadReq MSHR hits 234311201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 3382349 # number of ReadReq MSHR hits 234411201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 6057293 # number of WriteReq MSHR hits 234511201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 6057293 # number of WriteReq MSHR hits 234611201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3337 # number of WriteLineReq MSHR hits 234711201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_hits::total 3337 # number of WriteLineReq MSHR hits 234811201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 147189 # number of LoadLockedReq MSHR hits 234911201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 147189 # number of LoadLockedReq MSHR hits 235011201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 9439642 # number of demand (read+write) MSHR hits 235111201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 9439642 # number of demand (read+write) MSHR hits 235211201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 9439642 # number of overall MSHR hits 235311201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 9439642 # number of overall MSHR hits 235411201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3229349 # number of ReadReq MSHR misses 235511201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 3229349 # number of ReadReq MSHR misses 235611201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1438302 # number of WriteReq MSHR misses 235711201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 1438302 # number of WriteReq MSHR misses 235811201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 706535 # number of SoftPFReq MSHR misses 235911201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::total 706535 # number of SoftPFReq MSHR misses 236011201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 435594 # number of WriteLineReq MSHR misses 236111201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_misses::total 435594 # number of WriteLineReq MSHR misses 236211201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 141268 # number of LoadLockedReq MSHR misses 236311201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 141268 # number of LoadLockedReq MSHR misses 236411201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 203504 # number of StoreCondReq MSHR misses 236511201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 203504 # number of StoreCondReq MSHR misses 236611201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 4667651 # number of demand (read+write) MSHR misses 236711201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 4667651 # number of demand (read+write) MSHR misses 236811201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 5374186 # number of overall MSHR misses 236911201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 5374186 # number of overall MSHR misses 237011201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5460 # number of ReadReq MSHR uncacheable 237111201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::total 5460 # number of ReadReq MSHR uncacheable 237211201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 5292 # number of WriteReq MSHR uncacheable 237311201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::total 5292 # number of WriteReq MSHR uncacheable 237411201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10752 # number of overall MSHR uncacheable misses 237511201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::total 10752 # number of overall MSHR uncacheable misses 237611201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 50929568500 # number of ReadReq MSHR miss cycles 237711201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 50929568500 # number of ReadReq MSHR miss cycles 237811201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 34490212579 # number of WriteReq MSHR miss cycles 237911201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 34490212579 # number of WriteReq MSHR miss cycles 238011201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 16980659000 # number of SoftPFReq MSHR miss cycles 238111201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 16980659000 # number of SoftPFReq MSHR miss cycles 238211201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 18123603563 # number of WriteLineReq MSHR miss cycles 238311201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 18123603563 # number of WriteLineReq MSHR miss cycles 238411201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 2072685000 # number of LoadLockedReq MSHR miss cycles 238511201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 2072685000 # number of LoadLockedReq MSHR miss cycles 238611201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 5454243000 # number of StoreCondReq MSHR miss cycles 238711201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 5454243000 # number of StoreCondReq MSHR miss cycles 238811201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 7318500 # number of StoreCondFailReq MSHR miss cycles 238911201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 7318500 # number of StoreCondFailReq MSHR miss cycles 239011201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 85419781079 # number of demand (read+write) MSHR miss cycles 239111201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 85419781079 # number of demand (read+write) MSHR miss cycles 239211201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 102400440079 # number of overall MSHR miss cycles 239311201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 102400440079 # number of overall MSHR miss cycles 239411201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 594704500 # number of ReadReq MSHR uncacheable cycles 239511201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 594704500 # number of ReadReq MSHR uncacheable cycles 239611201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 661334500 # number of WriteReq MSHR uncacheable cycles 239711201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 661334500 # number of WriteReq MSHR uncacheable cycles 239811201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1256039000 # number of overall MSHR uncacheable cycles 239911201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 1256039000 # number of overall MSHR uncacheable cycles 240011201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036226 # mshr miss rate for ReadReq accesses 240111201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036226 # mshr miss rate for ReadReq accesses 240211201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018319 # mshr miss rate for WriteReq accesses 240311201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018319 # mshr miss rate for WriteReq accesses 240411201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.794903 # mshr miss rate for SoftPFReq accesses 240511201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.794903 # mshr miss rate for SoftPFReq accesses 240611201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.880559 # mshr miss rate for WriteLineReq accesses 240711201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.880559 # mshr miss rate for WriteLineReq accesses 240811201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.065582 # mshr miss rate for LoadLockedReq accesses 240911201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.065582 # mshr miss rate for LoadLockedReq accesses 241011201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.096572 # mshr miss rate for StoreCondReq accesses 241111201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.096572 # mshr miss rate for StoreCondReq accesses 241211201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027840 # mshr miss rate for demand accesses 241311201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.027840 # mshr miss rate for demand accesses 241411201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.031885 # mshr miss rate for overall accesses 241511201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.031885 # mshr miss rate for overall accesses 241611201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15770.846849 # average ReadReq mshr miss latency 241711201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15770.846849 # average ReadReq mshr miss latency 241811201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23979.812709 # average WriteReq mshr miss latency 241911201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23979.812709 # average WriteReq mshr miss latency 242011201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24033.712413 # average SoftPFReq mshr miss latency 242111201Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24033.712413 # average SoftPFReq mshr miss latency 242211201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 41606.641880 # average WriteLineReq mshr miss latency 242311201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 41606.641880 # average WriteLineReq mshr miss latency 242411201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 14672.006399 # average LoadLockedReq mshr miss latency 242511201Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14672.006399 # average LoadLockedReq mshr miss latency 242611201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26801.650090 # average StoreCondReq mshr miss latency 242711201Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26801.650090 # average StoreCondReq mshr miss latency 242810576Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 242910576Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 243011201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18300.378730 # average overall mshr miss latency 243111201Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 18300.378730 # average overall mshr miss latency 243211201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19054.130259 # average overall mshr miss latency 243311201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 19054.130259 # average overall mshr miss latency 243411201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 108920.238095 # average ReadReq mshr uncacheable latency 243511201Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 108920.238095 # average ReadReq mshr uncacheable latency 243611201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 124968.726379 # average WriteReq mshr uncacheable latency 243711201Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 124968.726379 # average WriteReq mshr uncacheable latency 243811201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 116819.103423 # average overall mshr uncacheable latency 243911201Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 116819.103423 # average overall mshr uncacheable latency 244010576Sandreas.hansson@arm.comsystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 244111201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 5955939 # number of replacements 244211201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 501.596349 # Cycle average of tags in use 244311201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 208888584 # Total number of references to valid blocks. 244411201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 5956451 # Sample count of references to valid blocks. 244511201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 35.069303 # Average number of references to valid blocks. 244611201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 8525956583000 # Cycle when the warmup percentage was hit. 244711201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 501.596349 # Average occupied blocks per requestor 244811201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.979680 # Average percentage of cache occupancy 244911201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.979680 # Average percentage of cache occupancy 245010576Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 245111201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id 245211201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id 245311201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 97 # Occupied blocks per task id 245410576Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 245511201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 436342012 # Number of tag accesses 245611201Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 436342012 # Number of data accesses 245711201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 208888584 # number of ReadReq hits 245811201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 208888584 # number of ReadReq hits 245911201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 208888584 # number of demand (read+write) hits 246011201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 208888584 # number of demand (read+write) hits 246111201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 208888584 # number of overall hits 246211201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 208888584 # number of overall hits 246311201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 6304191 # number of ReadReq misses 246411201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 6304191 # number of ReadReq misses 246511201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 6304191 # number of demand (read+write) misses 246611201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 6304191 # number of demand (read+write) misses 246711201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 6304191 # number of overall misses 246811201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 6304191 # number of overall misses 246911201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 70452471315 # number of ReadReq miss cycles 247011201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 70452471315 # number of ReadReq miss cycles 247111201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 70452471315 # number of demand (read+write) miss cycles 247211201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::total 70452471315 # number of demand (read+write) miss cycles 247311201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 70452471315 # number of overall miss cycles 247411201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::total 70452471315 # number of overall miss cycles 247511201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 215192775 # number of ReadReq accesses(hits+misses) 247611201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 215192775 # number of ReadReq accesses(hits+misses) 247711201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 215192775 # number of demand (read+write) accesses 247811201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 215192775 # number of demand (read+write) accesses 247911201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 215192775 # number of overall (read+write) accesses 248011201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 215192775 # number of overall (read+write) accesses 248111201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029296 # miss rate for ReadReq accesses 248211201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.029296 # miss rate for ReadReq accesses 248311201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.029296 # miss rate for demand accesses 248411201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.029296 # miss rate for demand accesses 248511201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.029296 # miss rate for overall accesses 248611201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.029296 # miss rate for overall accesses 248711201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 11175.497588 # average ReadReq miss latency 248811201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 11175.497588 # average ReadReq miss latency 248911201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 11175.497588 # average overall miss latency 249011201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 11175.497588 # average overall miss latency 249111201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 11175.497588 # average overall miss latency 249211201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 11175.497588 # average overall miss latency 249311201Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_mshrs 10802796 # number of cycles access was blocked 249411201Sandreas.hansson@arm.comsystem.cpu1.icache.blocked_cycles::no_targets 573 # number of cycles access was blocked 249511201Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_mshrs 747541 # number of cycles access was blocked 249611201Sandreas.hansson@arm.comsystem.cpu1.icache.blocked::no_targets 5 # number of cycles access was blocked 249711201Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_mshrs 14.451108 # average number of cycles each access was blocked 249811201Sandreas.hansson@arm.comsystem.cpu1.icache.avg_blocked_cycles::no_targets 114.600000 # average number of cycles each access was blocked 249910576Sandreas.hansson@arm.comsystem.cpu1.icache.fast_writes 0 # number of fast writes performed 250010576Sandreas.hansson@arm.comsystem.cpu1.icache.cache_copies 0 # number of cache copies performed 250111201Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::writebacks 5955939 # number of writebacks 250211201Sandreas.hansson@arm.comsystem.cpu1.icache.writebacks::total 5955939 # number of writebacks 250311201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 347729 # number of ReadReq MSHR hits 250411201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_hits::total 347729 # number of ReadReq MSHR hits 250511201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_hits::cpu1.inst 347729 # number of demand (read+write) MSHR hits 250611201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_hits::total 347729 # number of demand (read+write) MSHR hits 250711201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_hits::cpu1.inst 347729 # number of overall MSHR hits 250811201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_hits::total 347729 # number of overall MSHR hits 250911201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5956462 # number of ReadReq MSHR misses 251011201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 5956462 # number of ReadReq MSHR misses 251111201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 5956462 # number of demand (read+write) MSHR misses 251211201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::total 5956462 # number of demand (read+write) MSHR misses 251311201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 5956462 # number of overall MSHR misses 251411201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::total 5956462 # number of overall MSHR misses 251510827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 251610827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable 251710827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 251810827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses 251911201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 63484136905 # number of ReadReq MSHR miss cycles 252011201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 63484136905 # number of ReadReq MSHR miss cycles 252111201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 63484136905 # number of demand (read+write) MSHR miss cycles 252211201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 63484136905 # number of demand (read+write) MSHR miss cycles 252311201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 63484136905 # number of overall MSHR miss cycles 252411201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 63484136905 # number of overall MSHR miss cycles 252511201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8835998 # number of ReadReq MSHR uncacheable cycles 252611201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8835998 # number of ReadReq MSHR uncacheable cycles 252711201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8835998 # number of overall MSHR uncacheable cycles 252811201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::total 8835998 # number of overall MSHR uncacheable cycles 252911201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027680 # mshr miss rate for ReadReq accesses 253011201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027680 # mshr miss rate for ReadReq accesses 253111201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027680 # mshr miss rate for demand accesses 253211201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.027680 # mshr miss rate for demand accesses 253311201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027680 # mshr miss rate for overall accesses 253411201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.027680 # mshr miss rate for overall accesses 253511201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10658.027686 # average ReadReq mshr miss latency 253611201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10658.027686 # average ReadReq mshr miss latency 253711201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10658.027686 # average overall mshr miss latency 253811201Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 10658.027686 # average overall mshr miss latency 253911201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10658.027686 # average overall mshr miss latency 254011201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 10658.027686 # average overall mshr miss latency 254111201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 131880.567164 # average ReadReq mshr uncacheable latency 254211201Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 131880.567164 # average ReadReq mshr uncacheable latency 254311201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 131880.567164 # average overall mshr uncacheable latency 254411201Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 131880.567164 # average overall mshr uncacheable latency 254510576Sandreas.hansson@arm.comsystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 254611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 7807580 # number of hwpf issued 254711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 7812689 # number of prefetch candidates identified 254811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 4721 # number of redundant prefetches already in prefetch queue 254910628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 255010628Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 255111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 919623 # number of prefetches not generated due to page crossing 255211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 2337918 # number of replacements 255311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13374.571842 # Cycle average of tags in use 255411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 17269379 # Total number of references to valid blocks. 255511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 2353639 # Sample count of references to valid blocks. 255611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 7.337310 # Average number of references to valid blocks. 255711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 10121843878000 # Cycle when the warmup percentage was hit. 255811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 12566.070038 # Average occupied blocks per requestor 255911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 56.667232 # Average occupied blocks per requestor 256011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 65.366082 # Average occupied blocks per requestor 256111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.data 0.000003 # Average occupied blocks per requestor 256211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 686.468486 # Average occupied blocks per requestor 256311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.766972 # Average percentage of cache occupancy 256411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003459 # Average percentage of cache occupancy 256511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.003990 # Average percentage of cache occupancy 256611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.data 0.000000 # Average percentage of cache occupancy 256711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.041899 # Average percentage of cache occupancy 256811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.816319 # Average percentage of cache occupancy 256911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1022 1203 # Occupied blocks per task id 257011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 84 # Occupied blocks per task id 257111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 14434 # Occupied blocks per task id 257211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::1 80 # Occupied blocks per task id 257311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::2 187 # Occupied blocks per task id 257411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::3 549 # Occupied blocks per task id 257511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::4 387 # Occupied blocks per task id 257611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id 257711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::2 65 # Occupied blocks per task id 257811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id 257911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id 258011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id 258111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 840 # Occupied blocks per task id 258211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4705 # Occupied blocks per task id 258311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4934 # Occupied blocks per task id 258411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3842 # Occupied blocks per task id 258511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1022 0.073425 # Percentage of cache occupancy per task id 258611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005127 # Percentage of cache occupancy per task id 258711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.880981 # Percentage of cache occupancy per task id 258811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tag_accesses 397810098 # Number of tag accesses 258911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 397810098 # Number of data accesses 259011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 597256 # number of ReadReq hits 259111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 208532 # number of ReadReq hits 259211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 805788 # number of ReadReq hits 259311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::writebacks 3539726 # number of WritebackDirty hits 259411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_hits::total 3539726 # number of WritebackDirty hits 259511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::writebacks 8031138 # number of WritebackClean hits 259611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_hits::total 8031138 # number of WritebackClean hits 259711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 945 # number of UpgradeReq hits 259811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 945 # number of UpgradeReq hits 259911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 4 # number of SCUpgradeReq hits 260011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits 260111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 889943 # number of ReadExReq hits 260211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 889943 # number of ReadExReq hits 260311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5374664 # number of ReadCleanReq hits 260411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_hits::total 5374664 # number of ReadCleanReq hits 260511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 3032294 # number of ReadSharedReq hits 260611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_hits::total 3032294 # number of ReadSharedReq hits 260711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::cpu1.data 189660 # number of InvalidateReq hits 260811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_hits::total 189660 # number of InvalidateReq hits 260911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 597256 # number of demand (read+write) hits 261011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 208532 # number of demand (read+write) hits 261111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 5374664 # number of demand (read+write) hits 261211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3922237 # number of demand (read+write) hits 261311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 10102689 # number of demand (read+write) hits 261411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 597256 # number of overall hits 261511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 208532 # number of overall hits 261611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 5374664 # number of overall hits 261711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3922237 # number of overall hits 261811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::total 10102689 # number of overall hits 261911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12883 # number of ReadReq misses 262011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10252 # number of ReadReq misses 262111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 23135 # number of ReadReq misses 262211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_misses::writebacks 5 # number of WritebackDirty misses 262311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_misses::total 5 # number of WritebackDirty misses 262411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 246019 # number of UpgradeReq misses 262511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 246019 # number of UpgradeReq misses 262611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 203494 # number of SCUpgradeReq misses 262711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 203494 # number of SCUpgradeReq misses 262811167Sjthestness@gmail.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses 262911167Sjthestness@gmail.comsystem.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses 263011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 311077 # number of ReadExReq misses 263111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 311077 # number of ReadExReq misses 263211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 581787 # number of ReadCleanReq misses 263311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_misses::total 581787 # number of ReadCleanReq misses 263411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1040673 # number of ReadSharedReq misses 263511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_misses::total 1040673 # number of ReadSharedReq misses 263611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::cpu1.data 244105 # number of InvalidateReq misses 263711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_misses::total 244105 # number of InvalidateReq misses 263811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12883 # number of demand (read+write) misses 263911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 10252 # number of demand (read+write) misses 264011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 581787 # number of demand (read+write) misses 264111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1351750 # number of demand (read+write) misses 264211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::total 1956672 # number of demand (read+write) misses 264311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12883 # number of overall misses 264411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 10252 # number of overall misses 264511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 581787 # number of overall misses 264611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1351750 # number of overall misses 264711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 1956672 # number of overall misses 264811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 705237000 # number of ReadReq miss cycles 264911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 609311000 # number of ReadReq miss cycles 265011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::total 1314548000 # number of ReadReq miss cycles 265111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3694717000 # number of UpgradeReq miss cycles 265211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::total 3694717000 # number of UpgradeReq miss cycles 265311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 1939092500 # number of SCUpgradeReq miss cycles 265411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::total 1939092500 # number of SCUpgradeReq miss cycles 265511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 7171998 # number of SCUpgradeFailReq miss cycles 265611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 7171998 # number of SCUpgradeFailReq miss cycles 265711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 16701418499 # number of ReadExReq miss cycles 265811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::total 16701418499 # number of ReadExReq miss cycles 265911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 22000590000 # number of ReadCleanReq miss cycles 266011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_latency::total 22000590000 # number of ReadCleanReq miss cycles 266111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 43617133977 # number of ReadSharedReq miss cycles 266211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_latency::total 43617133977 # number of ReadSharedReq miss cycles 266311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 15757180999 # number of InvalidateReq miss cycles 266411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_latency::total 15757180999 # number of InvalidateReq miss cycles 266511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 705237000 # number of demand (read+write) miss cycles 266611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 609311000 # number of demand (read+write) miss cycles 266711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.inst 22000590000 # number of demand (read+write) miss cycles 266811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.data 60318552476 # number of demand (read+write) miss cycles 266911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::total 83633690476 # number of demand (read+write) miss cycles 267011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 705237000 # number of overall miss cycles 267111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 609311000 # number of overall miss cycles 267211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.inst 22000590000 # number of overall miss cycles 267311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.data 60318552476 # number of overall miss cycles 267411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::total 83633690476 # number of overall miss cycles 267511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 610139 # number of ReadReq accesses(hits+misses) 267611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 218784 # number of ReadReq accesses(hits+misses) 267711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 828923 # number of ReadReq accesses(hits+misses) 267811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::writebacks 3539731 # number of WritebackDirty accesses(hits+misses) 267911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_accesses::total 3539731 # number of WritebackDirty accesses(hits+misses) 268011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::writebacks 8031138 # number of WritebackClean accesses(hits+misses) 268111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackClean_accesses::total 8031138 # number of WritebackClean accesses(hits+misses) 268211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 246964 # number of UpgradeReq accesses(hits+misses) 268311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 246964 # number of UpgradeReq accesses(hits+misses) 268411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 203498 # number of SCUpgradeReq accesses(hits+misses) 268511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 203498 # number of SCUpgradeReq accesses(hits+misses) 268611167Sjthestness@gmail.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses) 268711167Sjthestness@gmail.comsystem.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) 268811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1201020 # number of ReadExReq accesses(hits+misses) 268911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1201020 # number of ReadExReq accesses(hits+misses) 269011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5956451 # number of ReadCleanReq accesses(hits+misses) 269111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_accesses::total 5956451 # number of ReadCleanReq accesses(hits+misses) 269211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 4072967 # number of ReadSharedReq accesses(hits+misses) 269311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_accesses::total 4072967 # number of ReadSharedReq accesses(hits+misses) 269411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 433765 # number of InvalidateReq accesses(hits+misses) 269511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_accesses::total 433765 # number of InvalidateReq accesses(hits+misses) 269611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 610139 # number of demand (read+write) accesses 269711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 218784 # number of demand (read+write) accesses 269811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 5956451 # number of demand (read+write) accesses 269911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 5273987 # number of demand (read+write) accesses 270011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 12059361 # number of demand (read+write) accesses 270111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 610139 # number of overall (read+write) accesses 270211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 218784 # number of overall (read+write) accesses 270311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 5956451 # number of overall (read+write) accesses 270411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 5273987 # number of overall (read+write) accesses 270511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 12059361 # number of overall (read+write) accesses 270611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021115 # miss rate for ReadReq accesses 270711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.046859 # miss rate for ReadReq accesses 270811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_rate::total 0.027910 # miss rate for ReadReq accesses 270911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_miss_rate::writebacks 0.000001 # miss rate for WritebackDirty accesses 271011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_miss_rate::total 0.000001 # miss rate for WritebackDirty accesses 271111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.996174 # miss rate for UpgradeReq accesses 271211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_rate::total 0.996174 # miss rate for UpgradeReq accesses 271311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.999980 # miss rate for SCUpgradeReq accesses 271411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.999980 # miss rate for SCUpgradeReq accesses 271510576Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 271610576Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 271711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.259011 # miss rate for ReadExReq accesses 271811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_rate::total 0.259011 # miss rate for ReadExReq accesses 271911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.097673 # miss rate for ReadCleanReq accesses 272011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.097673 # miss rate for ReadCleanReq accesses 272111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.255507 # miss rate for ReadSharedReq accesses 272211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.255507 # miss rate for ReadSharedReq accesses 272311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.562759 # miss rate for InvalidateReq accesses 272411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_miss_rate::total 0.562759 # miss rate for InvalidateReq accesses 272511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021115 # miss rate for demand accesses 272611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.046859 # miss rate for demand accesses 272711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.097673 # miss rate for demand accesses 272811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::cpu1.data 0.256305 # miss rate for demand accesses 272911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_rate::total 0.162253 # miss rate for demand accesses 273011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021115 # miss rate for overall accesses 273111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.046859 # miss rate for overall accesses 273211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.097673 # miss rate for overall accesses 273311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.256305 # miss rate for overall accesses 273411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.162253 # miss rate for overall accesses 273511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 54741.675076 # average ReadReq miss latency 273611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 59433.378853 # average ReadReq miss latency 273711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::total 56820.747785 # average ReadReq miss latency 273811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 15018.014869 # average UpgradeReq miss latency 273911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 15018.014869 # average UpgradeReq miss latency 274011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 9528.991027 # average SCUpgradeReq miss latency 274111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 9528.991027 # average SCUpgradeReq miss latency 274211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1195333 # average SCUpgradeFailReq miss latency 274311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1195333 # average SCUpgradeFailReq miss latency 274411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 53689.017507 # average ReadExReq miss latency 274511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_miss_latency::total 53689.017507 # average ReadExReq miss latency 274611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37815.540739 # average ReadCleanReq miss latency 274711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37815.540739 # average ReadCleanReq miss latency 274811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 41912.429723 # average ReadSharedReq miss latency 274911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 41912.429723 # average ReadSharedReq miss latency 275011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 64550.832629 # average InvalidateReq miss latency 275111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 64550.832629 # average InvalidateReq miss latency 275211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 54741.675076 # average overall miss latency 275311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 59433.378853 # average overall miss latency 275411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37815.540739 # average overall miss latency 275511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 44622.565176 # average overall miss latency 275611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_miss_latency::total 42742.825816 # average overall miss latency 275711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 54741.675076 # average overall miss latency 275811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 59433.378853 # average overall miss latency 275911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37815.540739 # average overall miss latency 276011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 44622.565176 # average overall miss latency 276111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_miss_latency::total 42742.825816 # average overall miss latency 276211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_mshrs 758 # number of cycles access was blocked 276310576Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 276411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked 276510576Sandreas.hansson@arm.comsystem.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 276611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_mshrs 126.333333 # average number of cycles each access was blocked 276710576Sandreas.hansson@arm.comsystem.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 276810576Sandreas.hansson@arm.comsystem.cpu1.l2cache.fast_writes 0 # number of fast writes performed 276910576Sandreas.hansson@arm.comsystem.cpu1.l2cache.cache_copies 0 # number of cache copies performed 277011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::writebacks 1264789 # number of writebacks 277111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.writebacks::total 1264789 # number of writebacks 277211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 4 # number of ReadReq MSHR hits 277311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 169 # number of ReadReq MSHR hits 277411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_hits::total 173 # number of ReadReq MSHR hits 277511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 44408 # number of ReadExReq MSHR hits 277611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_hits::total 44408 # number of ReadExReq MSHR hits 277711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 5726 # number of ReadSharedReq MSHR hits 277811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_hits::total 5726 # number of ReadSharedReq MSHR hits 277911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 6 # number of InvalidateReq MSHR hits 278011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_hits::total 6 # number of InvalidateReq MSHR hits 278111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 4 # number of demand (read+write) MSHR hits 278211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 169 # number of demand (read+write) MSHR hits 278311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::cpu1.data 50134 # number of demand (read+write) MSHR hits 278411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_hits::total 50307 # number of demand (read+write) MSHR hits 278511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 4 # number of overall MSHR hits 278611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 169 # number of overall MSHR hits 278711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::cpu1.data 50134 # number of overall MSHR hits 278811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_hits::total 50307 # number of overall MSHR hits 278911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12879 # number of ReadReq MSHR misses 279011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10083 # number of ReadReq MSHR misses 279111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_misses::total 22962 # number of ReadReq MSHR misses 279211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_mshr_misses::writebacks 5 # number of WritebackDirty MSHR misses 279311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_mshr_misses::total 5 # number of WritebackDirty MSHR misses 279411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 820594 # number of HardPFReq MSHR misses 279511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_misses::total 820594 # number of HardPFReq MSHR misses 279611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 246019 # number of UpgradeReq MSHR misses 279711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_misses::total 246019 # number of UpgradeReq MSHR misses 279811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 203494 # number of SCUpgradeReq MSHR misses 279911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 203494 # number of SCUpgradeReq MSHR misses 280011167Sjthestness@gmail.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses 280111167Sjthestness@gmail.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses 280211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 266669 # number of ReadExReq MSHR misses 280311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_misses::total 266669 # number of ReadExReq MSHR misses 280411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 581787 # number of ReadCleanReq MSHR misses 280511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_misses::total 581787 # number of ReadCleanReq MSHR misses 280611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 1034947 # number of ReadSharedReq MSHR misses 280711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_misses::total 1034947 # number of ReadSharedReq MSHR misses 280811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 244099 # number of InvalidateReq MSHR misses 280911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_misses::total 244099 # number of InvalidateReq MSHR misses 281011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12879 # number of demand (read+write) MSHR misses 281111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10083 # number of demand (read+write) MSHR misses 281211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.inst 581787 # number of demand (read+write) MSHR misses 281311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.data 1301616 # number of demand (read+write) MSHR misses 281411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::total 1906365 # number of demand (read+write) MSHR misses 281511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12879 # number of overall MSHR misses 281611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10083 # number of overall MSHR misses 281711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.inst 581787 # number of overall MSHR misses 281811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.data 1301616 # number of overall MSHR misses 281911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 820594 # number of overall MSHR misses 282011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::total 2726959 # number of overall MSHR misses 282110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 282211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5460 # number of ReadReq MSHR uncacheable 282311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5527 # number of ReadReq MSHR uncacheable 282411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 5292 # number of WriteReq MSHR uncacheable 282511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::total 5292 # number of WriteReq MSHR uncacheable 282610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 282711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10752 # number of overall MSHR uncacheable misses 282811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10819 # number of overall MSHR uncacheable misses 282911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 627888000 # number of ReadReq MSHR miss cycles 283011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 537691500 # number of ReadReq MSHR miss cycles 283111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1165579500 # number of ReadReq MSHR miss cycles 283211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 49091164625 # number of HardPFReq MSHR miss cycles 283311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 49091164625 # number of HardPFReq MSHR miss cycles 283411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 7718588995 # number of UpgradeReq MSHR miss cycles 283511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 7718588995 # number of UpgradeReq MSHR miss cycles 283611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3925065997 # number of SCUpgradeReq MSHR miss cycles 283711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3925065997 # number of SCUpgradeReq MSHR miss cycles 283811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 6595998 # number of SCUpgradeFailReq MSHR miss cycles 283911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 6595998 # number of SCUpgradeFailReq MSHR miss cycles 284011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 12865032499 # number of ReadExReq MSHR miss cycles 284111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 12865032499 # number of ReadExReq MSHR miss cycles 284211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 18509868000 # number of ReadCleanReq MSHR miss cycles 284311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 18509868000 # number of ReadCleanReq MSHR miss cycles 284411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 37054911477 # number of ReadSharedReq MSHR miss cycles 284511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 37054911477 # number of ReadSharedReq MSHR miss cycles 284611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 14292006999 # number of InvalidateReq MSHR miss cycles 284711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 14292006999 # number of InvalidateReq MSHR miss cycles 284811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 627888000 # number of demand (read+write) MSHR miss cycles 284911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 537691500 # number of demand (read+write) MSHR miss cycles 285011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 18509868000 # number of demand (read+write) MSHR miss cycles 285111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 49919943976 # number of demand (read+write) MSHR miss cycles 285211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::total 69595391476 # number of demand (read+write) MSHR miss cycles 285311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 627888000 # number of overall MSHR miss cycles 285411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 537691500 # number of overall MSHR miss cycles 285511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 18509868000 # number of overall MSHR miss cycles 285611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 49919943976 # number of overall MSHR miss cycles 285711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 49091164625 # number of overall MSHR miss cycles 285811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::total 118686556101 # number of overall MSHR miss cycles 285911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8332500 # number of ReadReq MSHR uncacheable cycles 286011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 550904000 # number of ReadReq MSHR uncacheable cycles 286111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 559236500 # number of ReadReq MSHR uncacheable cycles 286211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 621567000 # number of WriteReq MSHR uncacheable cycles 286311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 621567000 # number of WriteReq MSHR uncacheable cycles 286411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8332500 # number of overall MSHR uncacheable cycles 286511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1172471000 # number of overall MSHR uncacheable cycles 286611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1180803500 # number of overall MSHR uncacheable cycles 286711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021108 # mshr miss rate for ReadReq accesses 286811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.046087 # mshr miss rate for ReadReq accesses 286911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.027701 # mshr miss rate for ReadReq accesses 287011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for WritebackDirty accesses 287111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WritebackDirty_mshr_miss_rate::total 0.000001 # mshr miss rate for WritebackDirty accesses 287210576Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 287310576Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 287411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.996174 # mshr miss rate for UpgradeReq accesses 287511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.996174 # mshr miss rate for UpgradeReq accesses 287611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999980 # mshr miss rate for SCUpgradeReq accesses 287711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999980 # mshr miss rate for SCUpgradeReq accesses 287810576Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 287910576Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 288011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.222035 # mshr miss rate for ReadExReq accesses 288111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.222035 # mshr miss rate for ReadExReq accesses 288211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.097673 # mshr miss rate for ReadCleanReq accesses 288311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.097673 # mshr miss rate for ReadCleanReq accesses 288411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.254101 # mshr miss rate for ReadSharedReq accesses 288511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.254101 # mshr miss rate for ReadSharedReq accesses 288611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.562745 # mshr miss rate for InvalidateReq accesses 288711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.562745 # mshr miss rate for InvalidateReq accesses 288811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021108 # mshr miss rate for demand accesses 288911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.046087 # mshr miss rate for demand accesses 289011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.097673 # mshr miss rate for demand accesses 289111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.246799 # mshr miss rate for demand accesses 289211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::total 0.158082 # mshr miss rate for demand accesses 289311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021108 # mshr miss rate for overall accesses 289411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.046087 # mshr miss rate for overall accesses 289511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.097673 # mshr miss rate for overall accesses 289611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.246799 # mshr miss rate for overall accesses 289710576Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 289811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::total 0.226128 # mshr miss rate for overall accesses 289911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 48752.853482 # average ReadReq mshr miss latency 290011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 53326.539720 # average ReadReq mshr miss latency 290111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 50761.235955 # average ReadReq mshr miss latency 290211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 59823.938056 # average HardPFReq mshr miss latency 290311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 59823.938056 # average HardPFReq mshr miss latency 290411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 31373.954837 # average UpgradeReq mshr miss latency 290511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31373.954837 # average UpgradeReq mshr miss latency 290611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 19288.362296 # average SCUpgradeReq mshr miss latency 290711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 19288.362296 # average SCUpgradeReq mshr miss latency 290811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1099333 # average SCUpgradeFailReq mshr miss latency 290911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1099333 # average SCUpgradeFailReq mshr miss latency 291011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 48243.449741 # average ReadExReq mshr miss latency 291111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 48243.449741 # average ReadExReq mshr miss latency 291211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31815.540739 # average ReadCleanReq mshr miss latency 291311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31815.540739 # average ReadCleanReq mshr miss latency 291411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 35803.680263 # average ReadSharedReq mshr miss latency 291511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35803.680263 # average ReadSharedReq mshr miss latency 291611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 58550.043216 # average InvalidateReq mshr miss latency 291711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 58550.043216 # average InvalidateReq mshr miss latency 291811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 48752.853482 # average overall mshr miss latency 291911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 53326.539720 # average overall mshr miss latency 292011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31815.540739 # average overall mshr miss latency 292111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 38352.282068 # average overall mshr miss latency 292211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::total 36506.855443 # average overall mshr miss latency 292311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 48752.853482 # average overall mshr miss latency 292411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 53326.539720 # average overall mshr miss latency 292511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31815.540739 # average overall mshr miss latency 292611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 38352.282068 # average overall mshr miss latency 292711201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 59823.938056 # average overall mshr miss latency 292811201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::total 43523.410547 # average overall mshr miss latency 292911201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 124365.671642 # average ReadReq mshr uncacheable latency 293011201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 100898.168498 # average ReadReq mshr uncacheable latency 293111201Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 101182.648815 # average ReadReq mshr uncacheable latency 293211201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117454.081633 # average WriteReq mshr uncacheable latency 293311201Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117454.081633 # average WriteReq mshr uncacheable latency 293411201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 124365.671642 # average overall mshr uncacheable latency 293511201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 109046.781994 # average overall mshr uncacheable latency 293611201Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 109141.648951 # average overall mshr uncacheable latency 293710576Sandreas.hansson@arm.comsystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 293811201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_requests 24065952 # Total number of requests made to the snoop filter. 293911201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_requests 12401926 # Number of requests hitting in the snoop filter with a single holder of the requested data. 294011201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1256 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 294111201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.tot_snoops 2060689 # Total number of snoops made to the snoop filter. 294211201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_single_snoops 2060329 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 294311201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 360 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 294411201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 934376 # Transaction distribution 294511201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 11053796 # Transaction distribution 294611201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution 294711201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 5292 # Transaction distribution 294811201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 5292 # Transaction distribution 294911201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackDirty 4812576 # Transaction distribution 295011201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WritebackClean 8031153 # Transaction distribution 295111201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::CleanEvict 2767424 # Transaction distribution 295211201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFReq 1034593 # Transaction distribution 295311201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution 295411201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 454030 # Transaction distribution 295511201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 361772 # Transaction distribution 295611201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 513435 # Transaction distribution 295711201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 121 # Transaction distribution 295811201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeFailResp 211 # Transaction distribution 295911201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1276992 # Transaction distribution 296011201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1207288 # Transaction distribution 296111201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadCleanReq 5956462 # Transaction distribution 296211201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadSharedReq 5025648 # Transaction distribution 296311201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateReq 440267 # Transaction distribution 296411201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::InvalidateResp 433765 # Transaction distribution 296511201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17868522 # Packet count per connected master and slave (bytes) 296611201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 18112795 # Packet count per connected master and slave (bytes) 296711201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 459206 # Packet count per connected master and slave (bytes) 296811201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1298566 # Packet count per connected master and slave (bytes) 296911201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 37739089 # Packet count per connected master and slave (bytes) 297011201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 762364336 # Cumulative packet size per connected master and slave (bytes) 297111201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 703129592 # Cumulative packet size per connected master and slave (bytes) 297211201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1750272 # Cumulative packet size per connected master and slave (bytes) 297311201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4881112 # Cumulative packet size per connected master and slave (bytes) 297411201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 1472125312 # Cumulative packet size per connected master and slave (bytes) 297511201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 6734851 # Total snoops (count) 297611201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 19529823 # Request fanout histogram 297711201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 0.125012 # Request fanout histogram 297811201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.330788 # Request fanout histogram 297910576Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 298011201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::0 17088727 87.50% 87.50% # Request fanout histogram 298111201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 2440736 12.50% 100.00% # Request fanout histogram 298211201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 360 0.00% 100.00% # Request fanout histogram 298310576Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 298411138Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 298510827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 298611201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 19529823 # Request fanout histogram 298711201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.occupancy 23888032965 # Layer occupancy (ticks) 298811201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 298911201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.occupancy 176197847 # Layer occupancy (ticks) 299010576Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 299111201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.occupancy 8940771887 # Layer occupancy (ticks) 299210576Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 299311201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.occupancy 8370756543 # Layer occupancy (ticks) 299410576Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 299511201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.occupancy 240887058 # Layer occupancy (ticks) 299610576Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 299711201Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.occupancy 689185473 # Layer occupancy (ticks) 299810576Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 299911201Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 40298 # Transaction distribution 300011201Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 40298 # Transaction distribution 300111201Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136623 # Transaction distribution 300211201Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 136623 # Transaction distribution 300311201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47620 # Packet count per connected master and slave (bytes) 300410576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 300510576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 300610576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 300710576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 300810576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 300910576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 301010576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 301110576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 301210576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 301311138Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 301410576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 301510576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 301610576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 301710576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 301811201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122554 # Packet count per connected master and slave (bytes) 301911201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231208 # Packet count per connected master and slave (bytes) 302011201Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231208 # Packet count per connected master and slave (bytes) 302110576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 302210576Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 302311201Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 353842 # Packet count per connected master and slave (bytes) 302411201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47640 # Cumulative packet size per connected master and slave (bytes) 302510576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 302610576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 302710576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 302810576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 302910576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 303010576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 303110576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 303210576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 303310576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 303411138Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 303510576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 303610576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 303710576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 303810576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 303911201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155661 # Cumulative packet size per connected master and slave (bytes) 304011201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338848 # Cumulative packet size per connected master and slave (bytes) 304111201Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7338848 # Cumulative packet size per connected master and slave (bytes) 304210576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 304310576Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 304411201Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 7496595 # Cumulative packet size per connected master and slave (bytes) 304511201Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 36904500 # Layer occupancy (ticks) 304610576Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 304711201Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) 304810576Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 304911201Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 305010576Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 305111201Sandreas.hansson@arm.comsystem.iobus.reqLayer3.occupancy 9000 # Layer occupancy (ticks) 305210576Sandreas.hansson@arm.comsystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 305311201Sandreas.hansson@arm.comsystem.iobus.reqLayer10.occupancy 9500 # Layer occupancy (ticks) 305410576Sandreas.hansson@arm.comsystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 305511201Sandreas.hansson@arm.comsystem.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) 305610576Sandreas.hansson@arm.comsystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 305711201Sandreas.hansson@arm.comsystem.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) 305810576Sandreas.hansson@arm.comsystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 305911201Sandreas.hansson@arm.comsystem.iobus.reqLayer15.occupancy 9500 # Layer occupancy (ticks) 306010576Sandreas.hansson@arm.comsystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 306111201Sandreas.hansson@arm.comsystem.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) 306210576Sandreas.hansson@arm.comsystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 306311201Sandreas.hansson@arm.comsystem.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) 306410576Sandreas.hansson@arm.comsystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 306511201Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 24719501 # Layer occupancy (ticks) 306610576Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 306711201Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 169000 # Layer occupancy (ticks) 306810576Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 306911201Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 36445000 # Layer occupancy (ticks) 307010576Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 307111201Sandreas.hansson@arm.comsystem.iobus.reqLayer26.occupancy 115000 # Layer occupancy (ticks) 307210576Sandreas.hansson@arm.comsystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 307311201Sandreas.hansson@arm.comsystem.iobus.reqLayer27.occupancy 565389979 # Layer occupancy (ticks) 307410576Sandreas.hansson@arm.comsystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 307511201Sandreas.hansson@arm.comsystem.iobus.reqLayer28.occupancy 44500 # Layer occupancy (ticks) 307610576Sandreas.hansson@arm.comsystem.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 307711201Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 92662000 # Layer occupancy (ticks) 307810576Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 307911201Sandreas.hansson@arm.comsystem.iobus.respLayer3.occupancy 147904000 # Layer occupancy (ticks) 308010576Sandreas.hansson@arm.comsystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 308110892Sandreas.hansson@arm.comsystem.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 308210576Sandreas.hansson@arm.comsystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 308311201Sandreas.hansson@arm.comsystem.iocache.tags.replacements 115596 # number of replacements 308411201Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 11.294963 # Cycle average of tags in use 308511201Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 4 # Total number of references to valid blocks. 308611201Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 115612 # Sample count of references to valid blocks. 308711201Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0.000035 # Average number of references to valid blocks. 308811201Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 9125681000000 # Cycle when the warmup percentage was hit. 308911201Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 7.424342 # Average occupied blocks per requestor 309011201Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 3.870620 # Average occupied blocks per requestor 309111201Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.464021 # Average percentage of cache occupancy 309211201Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.241914 # Average percentage of cache occupancy 309311201Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.705935 # Average percentage of cache occupancy 309410576Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 309510576Sandreas.hansson@arm.comsystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 309610576Sandreas.hansson@arm.comsystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 309711201Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 1040789 # Number of tag accesses 309811201Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 1040789 # Number of data accesses 309910576Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 310011201Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 8876 # number of ReadReq misses 310111201Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 8913 # number of ReadReq misses 310210576Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 310310576Sandreas.hansson@arm.comsystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 310410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 310510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 310610576Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 310711201Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 8876 # number of demand (read+write) misses 310811201Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 8916 # number of demand (read+write) misses 310910576Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 311011201Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 8876 # number of overall misses 311111201Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 8916 # number of overall misses 311211201Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ethernet 5200000 # number of ReadReq miss cycles 311311201Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1711011512 # number of ReadReq miss cycles 311411201Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 1716211512 # number of ReadReq miss cycles 311510944Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 311610944Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 311711201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::realview.ide 13978863467 # number of WriteLineReq miss cycles 311811201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_latency::total 13978863467 # number of WriteLineReq miss cycles 311911201Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ethernet 5569000 # number of demand (read+write) miss cycles 312011201Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ide 1711011512 # number of demand (read+write) miss cycles 312111201Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 1716580512 # number of demand (read+write) miss cycles 312211201Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ethernet 5569000 # number of overall miss cycles 312311201Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ide 1711011512 # number of overall miss cycles 312411201Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 1716580512 # number of overall miss cycles 312510576Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 312611201Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8876 # number of ReadReq accesses(hits+misses) 312711201Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 8913 # number of ReadReq accesses(hits+misses) 312810576Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 312910576Sandreas.hansson@arm.comsystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 313010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 313110892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 313210576Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 313311201Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 8876 # number of demand (read+write) accesses 313411201Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 8916 # number of demand (read+write) accesses 313510576Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 313611201Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 8876 # number of overall (read+write) accesses 313711201Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 8916 # number of overall (read+write) accesses 313810576Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 313910576Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 314010576Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 314110576Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 314210576Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 314310892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 314410892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 314510576Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 314610576Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 314710576Sandreas.hansson@arm.comsystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 314810576Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 314910576Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 315010576Sandreas.hansson@arm.comsystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 315111201Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 140540.540541 # average ReadReq miss latency 315211201Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 192768.309148 # average ReadReq miss latency 315311201Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 192551.499159 # average ReadReq miss latency 315410944Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 315510944Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 315611201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::realview.ide 130976.533496 # average WriteLineReq miss latency 315711201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_miss_latency::total 130976.533496 # average WriteLineReq miss latency 315811201Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ethernet 139225 # average overall miss latency 315911201Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 192768.309148 # average overall miss latency 316011201Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 192528.096904 # average overall miss latency 316111201Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ethernet 139225 # average overall miss latency 316211201Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 192768.309148 # average overall miss latency 316311201Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 192528.096904 # average overall miss latency 316411201Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 36708 # number of cycles access was blocked 316510576Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 316611201Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 3726 # number of cycles access was blocked 316710576Sandreas.hansson@arm.comsystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 316811201Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 9.851852 # average number of cycles each access was blocked 316910576Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 317010585Sandreas.hansson@arm.comsystem.iocache.fast_writes 0 # number of fast writes performed 317110576Sandreas.hansson@arm.comsystem.iocache.cache_copies 0 # number of cache copies performed 317211201Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 106693 # number of writebacks 317311201Sandreas.hansson@arm.comsystem.iocache.writebacks::total 106693 # number of writebacks 317410576Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 317511201Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8876 # number of ReadReq MSHR misses 317611201Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 8913 # number of ReadReq MSHR misses 317710576Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 317810576Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 317910892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 318010892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 318110576Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 318211201Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ide 8876 # number of demand (read+write) MSHR misses 318311201Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 8916 # number of demand (read+write) MSHR misses 318410576Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 318511201Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ide 8876 # number of overall MSHR misses 318611201Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 8916 # number of overall MSHR misses 318711201Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3350000 # number of ReadReq MSHR miss cycles 318811201Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1267211512 # number of ReadReq MSHR miss cycles 318911201Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1270561512 # number of ReadReq MSHR miss cycles 319010944Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 319110944Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 319211201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8642463467 # number of WriteLineReq MSHR miss cycles 319311201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_latency::total 8642463467 # number of WriteLineReq MSHR miss cycles 319411201Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ethernet 3569000 # number of demand (read+write) MSHR miss cycles 319511201Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 1267211512 # number of demand (read+write) MSHR miss cycles 319611201Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 1270780512 # number of demand (read+write) MSHR miss cycles 319711201Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ethernet 3569000 # number of overall MSHR miss cycles 319811201Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 1267211512 # number of overall MSHR miss cycles 319911201Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 1270780512 # number of overall MSHR miss cycles 320010576Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 320110576Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 320210576Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 320310576Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 320410576Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 320510892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 320610892Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 320710576Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 320810576Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 320910576Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 321010576Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 321110576Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 321210576Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 321311201Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90540.540541 # average ReadReq mshr miss latency 321411201Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 142768.309148 # average ReadReq mshr miss latency 321511201Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 142551.499159 # average ReadReq mshr miss latency 321610944Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 321710944Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 321811201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80976.533496 # average WriteLineReq mshr miss latency 321911201Sandreas.hansson@arm.comsystem.iocache.WriteLineReq_avg_mshr_miss_latency::total 80976.533496 # average WriteLineReq mshr miss latency 322011201Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89225 # average overall mshr miss latency 322111201Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 142768.309148 # average overall mshr miss latency 322211201Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 142528.096904 # average overall mshr miss latency 322311201Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89225 # average overall mshr miss latency 322411201Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 142768.309148 # average overall mshr miss latency 322511201Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 142528.096904 # average overall mshr miss latency 322610576Sandreas.hansson@arm.comsystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 322711201Sandreas.hansson@arm.comsystem.l2c.tags.replacements 1583129 # number of replacements 322811201Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 63158.639853 # Cycle average of tags in use 322911201Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 6207421 # Total number of references to valid blocks. 323011201Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 1642739 # Sample count of references to valid blocks. 323111201Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 3.778702 # Average number of references to valid blocks. 323210892Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 323311201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 20395.624897 # Average occupied blocks per requestor 323411201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 35.797068 # Average occupied blocks per requestor 323511201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 37.096794 # Average occupied blocks per requestor 323611201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 3244.022805 # Average occupied blocks per requestor 323711201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 4223.269206 # Average occupied blocks per requestor 323811201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 3404.413573 # Average occupied blocks per requestor 323911201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 297.158145 # Average occupied blocks per requestor 324011201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 465.494648 # Average occupied blocks per requestor 324111201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 3968.740099 # Average occupied blocks per requestor 324211201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 9359.576527 # Average occupied blocks per requestor 324311201Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17727.446091 # Average occupied blocks per requestor 324411201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.311213 # Average percentage of cache occupancy 324511201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.000546 # Average percentage of cache occupancy 324611201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.000566 # Average percentage of cache occupancy 324711201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.049500 # Average percentage of cache occupancy 324811201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.064442 # Average percentage of cache occupancy 324911201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.051947 # Average percentage of cache occupancy 325011201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.004534 # Average percentage of cache occupancy 325111201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.007103 # Average percentage of cache occupancy 325211201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.060558 # Average percentage of cache occupancy 325311201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.142816 # Average percentage of cache occupancy 325411201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.270499 # Average percentage of cache occupancy 325511201Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.963724 # Average percentage of cache occupancy 325611201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1022 10142 # Occupied blocks per task id 325711201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 206 # Occupied blocks per task id 325811201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 49262 # Occupied blocks per task id 325911201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::2 1206 # Occupied blocks per task id 326011201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::3 394 # Occupied blocks per task id 326111201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::4 8542 # Occupied blocks per task id 326211201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 326311201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 205 # Occupied blocks per task id 326411201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 326511201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 375 # Occupied blocks per task id 326611201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 3055 # Occupied blocks per task id 326711201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 5795 # Occupied blocks per task id 326811201Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 39993 # Occupied blocks per task id 326911201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1022 0.154755 # Percentage of cache occupancy per task id 327011201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.003143 # Percentage of cache occupancy per task id 327111201Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.751678 # Percentage of cache occupancy per task id 327211201Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 79196544 # Number of tag accesses 327311201Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 79196544 # Number of data accesses 327411201Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::writebacks 2898173 # number of WritebackDirty hits 327511201Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_hits::total 2898173 # number of WritebackDirty hits 327611201Sandreas.hansson@arm.comsystem.l2c.WritebackClean_hits::writebacks 1 # number of WritebackClean hits 327711201Sandreas.hansson@arm.comsystem.l2c.WritebackClean_hits::total 1 # number of WritebackClean hits 327811201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 160488 # number of UpgradeReq hits 327911201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 150342 # number of UpgradeReq hits 328011201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 310830 # number of UpgradeReq hits 328111201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 37186 # number of SCUpgradeReq hits 328211201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 44723 # number of SCUpgradeReq hits 328311201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 81909 # number of SCUpgradeReq hits 328411201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 154261 # number of ReadExReq hits 328511201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 179531 # number of ReadExReq hits 328611201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 333792 # number of ReadExReq hits 328711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.dtb.walker 5731 # number of ReadSharedReq hits 328811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.itb.walker 3658 # number of ReadSharedReq hits 328911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.inst 494823 # number of ReadSharedReq hits 329011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.data 574885 # number of ReadSharedReq hits 329111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 276090 # number of ReadSharedReq hits 329211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.dtb.walker 6999 # number of ReadSharedReq hits 329311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.itb.walker 5287 # number of ReadSharedReq hits 329411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.inst 532007 # number of ReadSharedReq hits 329511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.data 626878 # number of ReadSharedReq hits 329611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 326161 # number of ReadSharedReq hits 329711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_hits::total 2852519 # number of ReadSharedReq hits 329811201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 5731 # number of demand (read+write) hits 329911201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 3658 # number of demand (read+write) hits 330011201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 494823 # number of demand (read+write) hits 330111201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 729146 # number of demand (read+write) hits 330211201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.l2cache.prefetcher 276090 # number of demand (read+write) hits 330311201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 6999 # number of demand (read+write) hits 330411201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 5287 # number of demand (read+write) hits 330511201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 532007 # number of demand (read+write) hits 330611201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 806409 # number of demand (read+write) hits 330711201Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.l2cache.prefetcher 326161 # number of demand (read+write) hits 330811201Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 3186311 # number of demand (read+write) hits 330911201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 5731 # number of overall hits 331011201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 3658 # number of overall hits 331111201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 494823 # number of overall hits 331211201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 729146 # number of overall hits 331311201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.l2cache.prefetcher 276090 # number of overall hits 331411201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 6999 # number of overall hits 331511201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 5287 # number of overall hits 331611201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 532007 # number of overall hits 331711201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 806409 # number of overall hits 331811201Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.l2cache.prefetcher 326161 # number of overall hits 331911201Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 3186311 # number of overall hits 332011201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 60003 # number of UpgradeReq misses 332111201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 64185 # number of UpgradeReq misses 332211201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 124188 # number of UpgradeReq misses 332311201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 13364 # number of SCUpgradeReq misses 332411201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 11770 # number of SCUpgradeReq misses 332511201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 25134 # number of SCUpgradeReq misses 332611201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 540709 # number of ReadExReq misses 332711201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 127504 # number of ReadExReq misses 332811201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 668213 # number of ReadExReq misses 332911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.dtb.walker 2216 # number of ReadSharedReq misses 333011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.itb.walker 2032 # number of ReadSharedReq misses 333111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.inst 61109 # number of ReadSharedReq misses 333211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.data 146627 # number of ReadSharedReq misses 333311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 303108 # number of ReadSharedReq misses 333411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.dtb.walker 3029 # number of ReadSharedReq misses 333511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.itb.walker 2795 # number of ReadSharedReq misses 333611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.inst 49780 # number of ReadSharedReq misses 333711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.data 138724 # number of ReadSharedReq misses 333811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 244242 # number of ReadSharedReq misses 333911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_misses::total 953662 # number of ReadSharedReq misses 334011201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 2216 # number of demand (read+write) misses 334111201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 2032 # number of demand (read+write) misses 334211201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 61109 # number of demand (read+write) misses 334311201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 687336 # number of demand (read+write) misses 334411201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.l2cache.prefetcher 303108 # number of demand (read+write) misses 334511201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 3029 # number of demand (read+write) misses 334611201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 2795 # number of demand (read+write) misses 334711201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 49780 # number of demand (read+write) misses 334811201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 266228 # number of demand (read+write) misses 334911201Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.l2cache.prefetcher 244242 # number of demand (read+write) misses 335011201Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 1621875 # number of demand (read+write) misses 335111201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 2216 # number of overall misses 335211201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 2032 # number of overall misses 335311201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 61109 # number of overall misses 335411201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 687336 # number of overall misses 335511201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.l2cache.prefetcher 303108 # number of overall misses 335611201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 3029 # number of overall misses 335711201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 2795 # number of overall misses 335811201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 49780 # number of overall misses 335911201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 266228 # number of overall misses 336011201Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.l2cache.prefetcher 244242 # number of overall misses 336111201Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 1621875 # number of overall misses 336211201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 974602500 # number of UpgradeReq miss cycles 336311201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 1153364500 # number of UpgradeReq miss cycles 336411201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::total 2127967000 # number of UpgradeReq miss cycles 336511201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.data 208392500 # number of SCUpgradeReq miss cycles 336611201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.data 213995000 # number of SCUpgradeReq miss cycles 336711201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::total 422387500 # number of SCUpgradeReq miss cycles 336811201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 89500490493 # number of ReadExReq miss cycles 336911201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 18793488998 # number of ReadExReq miss cycles 337011201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::total 108293979491 # number of ReadExReq miss cycles 337111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 316188000 # number of ReadSharedReq miss cycles 337211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 293419000 # number of ReadSharedReq miss cycles 337311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.inst 8381886002 # number of ReadSharedReq miss cycles 337411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.data 21271080498 # number of ReadSharedReq miss cycles 337511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 54991951248 # number of ReadSharedReq miss cycles 337611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 433939500 # number of ReadSharedReq miss cycles 337711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 397141000 # number of ReadSharedReq miss cycles 337811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.inst 6825711500 # number of ReadSharedReq miss cycles 337911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.data 19972888998 # number of ReadSharedReq miss cycles 338011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 43219182868 # number of ReadSharedReq miss cycles 338111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_latency::total 156103388614 # number of ReadSharedReq miss cycles 338211201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.dtb.walker 316188000 # number of demand (read+write) miss cycles 338311201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.itb.walker 293419000 # number of demand (read+write) miss cycles 338411201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 8381886002 # number of demand (read+write) miss cycles 338511201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.data 110771570991 # number of demand (read+write) miss cycles 338611201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 54991951248 # number of demand (read+write) miss cycles 338711201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.dtb.walker 433939500 # number of demand (read+write) miss cycles 338811201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.itb.walker 397141000 # number of demand (read+write) miss cycles 338911201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 6825711500 # number of demand (read+write) miss cycles 339011201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.data 38766377996 # number of demand (read+write) miss cycles 339111201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 43219182868 # number of demand (read+write) miss cycles 339211201Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::total 264397368105 # number of demand (read+write) miss cycles 339311201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.dtb.walker 316188000 # number of overall miss cycles 339411201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.itb.walker 293419000 # number of overall miss cycles 339511201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 8381886002 # number of overall miss cycles 339611201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.data 110771570991 # number of overall miss cycles 339711201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 54991951248 # number of overall miss cycles 339811201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.dtb.walker 433939500 # number of overall miss cycles 339911201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.itb.walker 397141000 # number of overall miss cycles 340011201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 6825711500 # number of overall miss cycles 340111201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.data 38766377996 # number of overall miss cycles 340211201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 43219182868 # number of overall miss cycles 340311201Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::total 264397368105 # number of overall miss cycles 340411201Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::writebacks 2898173 # number of WritebackDirty accesses(hits+misses) 340511201Sandreas.hansson@arm.comsystem.l2c.WritebackDirty_accesses::total 2898173 # number of WritebackDirty accesses(hits+misses) 340611201Sandreas.hansson@arm.comsystem.l2c.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) 340711201Sandreas.hansson@arm.comsystem.l2c.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) 340811201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 220491 # number of UpgradeReq accesses(hits+misses) 340911201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 214527 # number of UpgradeReq accesses(hits+misses) 341011201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 435018 # number of UpgradeReq accesses(hits+misses) 341111201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 50550 # number of SCUpgradeReq accesses(hits+misses) 341211201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 56493 # number of SCUpgradeReq accesses(hits+misses) 341311201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 107043 # number of SCUpgradeReq accesses(hits+misses) 341411201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 694970 # number of ReadExReq accesses(hits+misses) 341511201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 307035 # number of ReadExReq accesses(hits+misses) 341611201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 1002005 # number of ReadExReq accesses(hits+misses) 341711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 7947 # number of ReadSharedReq accesses(hits+misses) 341811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.itb.walker 5690 # number of ReadSharedReq accesses(hits+misses) 341911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.inst 555932 # number of ReadSharedReq accesses(hits+misses) 342011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.data 721512 # number of ReadSharedReq accesses(hits+misses) 342111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 579198 # number of ReadSharedReq accesses(hits+misses) 342211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 10028 # number of ReadSharedReq accesses(hits+misses) 342311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.itb.walker 8082 # number of ReadSharedReq accesses(hits+misses) 342411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.inst 581787 # number of ReadSharedReq accesses(hits+misses) 342511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.data 765602 # number of ReadSharedReq accesses(hits+misses) 342611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 570403 # number of ReadSharedReq accesses(hits+misses) 342711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_accesses::total 3806181 # number of ReadSharedReq accesses(hits+misses) 342811201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 7947 # number of demand (read+write) accesses 342911201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 5690 # number of demand (read+write) accesses 343011201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 555932 # number of demand (read+write) accesses 343111201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 1416482 # number of demand (read+write) accesses 343211201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.l2cache.prefetcher 579198 # number of demand (read+write) accesses 343311201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 10028 # number of demand (read+write) accesses 343411201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 8082 # number of demand (read+write) accesses 343511201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 581787 # number of demand (read+write) accesses 343611201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 1072637 # number of demand (read+write) accesses 343711201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.l2cache.prefetcher 570403 # number of demand (read+write) accesses 343811201Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 4808186 # number of demand (read+write) accesses 343911201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 7947 # number of overall (read+write) accesses 344011201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 5690 # number of overall (read+write) accesses 344111201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 555932 # number of overall (read+write) accesses 344211201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 1416482 # number of overall (read+write) accesses 344311201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.l2cache.prefetcher 579198 # number of overall (read+write) accesses 344411201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 10028 # number of overall (read+write) accesses 344511201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 8082 # number of overall (read+write) accesses 344611201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 581787 # number of overall (read+write) accesses 344711201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 1072637 # number of overall (read+write) accesses 344811201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.l2cache.prefetcher 570403 # number of overall (read+write) accesses 344911201Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 4808186 # number of overall (read+write) accesses 345011201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.272134 # miss rate for UpgradeReq accesses 345111201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.299193 # miss rate for UpgradeReq accesses 345211201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.285478 # miss rate for UpgradeReq accesses 345311201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.264372 # miss rate for SCUpgradeReq accesses 345411201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.208344 # miss rate for SCUpgradeReq accesses 345511201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.234803 # miss rate for SCUpgradeReq accesses 345611201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.778032 # miss rate for ReadExReq accesses 345711201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.415275 # miss rate for ReadExReq accesses 345811201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.666876 # miss rate for ReadExReq accesses 345911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.278847 # miss rate for ReadSharedReq accesses 346011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.357118 # miss rate for ReadSharedReq accesses 346111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.109922 # miss rate for ReadSharedReq accesses 346211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.data 0.203222 # miss rate for ReadSharedReq accesses 346311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.523324 # miss rate for ReadSharedReq accesses 346411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.302054 # miss rate for ReadSharedReq accesses 346511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.345830 # miss rate for ReadSharedReq accesses 346611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.085564 # miss rate for ReadSharedReq accesses 346711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.data 0.181196 # miss rate for ReadSharedReq accesses 346811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.428192 # miss rate for ReadSharedReq accesses 346911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_miss_rate::total 0.250556 # miss rate for ReadSharedReq accesses 347011201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.278847 # miss rate for demand accesses 347111201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.357118 # miss rate for demand accesses 347211201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.109922 # miss rate for demand accesses 347311201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.485242 # miss rate for demand accesses 347411201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.523324 # miss rate for demand accesses 347511201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.302054 # miss rate for demand accesses 347611201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.345830 # miss rate for demand accesses 347711201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.085564 # miss rate for demand accesses 347811201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.248200 # miss rate for demand accesses 347911201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.428192 # miss rate for demand accesses 348011201Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.337315 # miss rate for demand accesses 348111201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.278847 # miss rate for overall accesses 348211201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.357118 # miss rate for overall accesses 348311201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.109922 # miss rate for overall accesses 348411201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.485242 # miss rate for overall accesses 348511201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.523324 # miss rate for overall accesses 348611201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.302054 # miss rate for overall accesses 348711201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.345830 # miss rate for overall accesses 348811201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.085564 # miss rate for overall accesses 348911201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.248200 # miss rate for overall accesses 349011201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.428192 # miss rate for overall accesses 349111201Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.337315 # miss rate for overall accesses 349211201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 16242.562872 # average UpgradeReq miss latency 349311201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 17969.377580 # average UpgradeReq miss latency 349411201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::total 17135.045254 # average UpgradeReq miss latency 349511201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 15593.572284 # average SCUpgradeReq miss latency 349611201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 18181.393373 # average SCUpgradeReq miss latency 349711201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::total 16805.422933 # average SCUpgradeReq miss latency 349811201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 165524.321757 # average ReadExReq miss latency 349911201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 147395.289544 # average ReadExReq miss latency 350011201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 162065.059331 # average ReadExReq miss latency 350111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 142684.115523 # average ReadSharedReq miss latency 350211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 144399.114173 # average ReadSharedReq miss latency 350311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 137162.872932 # average ReadSharedReq miss latency 350411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 145069.328964 # average ReadSharedReq miss latency 350511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 181426.921256 # average ReadSharedReq miss latency 350611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 143261.637504 # average ReadSharedReq miss latency 350711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 142089.803220 # average ReadSharedReq miss latency 350811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 137117.547208 # average ReadSharedReq miss latency 350911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 143975.728771 # average ReadSharedReq miss latency 351011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 176952.296771 # average ReadSharedReq miss latency 351111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_miss_latency::total 163688.380804 # average ReadSharedReq miss latency 351211201Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.dtb.walker 142684.115523 # average overall miss latency 351311201Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.itb.walker 144399.114173 # average overall miss latency 351411201Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 137162.872932 # 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number of overall MSHR miss cycles 366411201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 40776701375 # number of overall MSHR miss cycles 366511201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_latency::total 248017540622 # number of overall MSHR miss cycles 366611201Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2396808000 # number of ReadReq MSHR uncacheable cycles 366711201Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5447961500 # number of ReadReq MSHR uncacheable cycles 366811201Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7124500 # number of ReadReq MSHR uncacheable cycles 366911201Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 452516500 # number of ReadReq MSHR uncacheable cycles 367011201Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable_latency::total 8304410500 # number of ReadReq MSHR uncacheable cycles 367111201Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 5424521033 # number of WriteReq MSHR uncacheable cycles 367211201Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 531333000 # number of WriteReq MSHR uncacheable cycles 367311201Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable_latency::total 5955854033 # number of WriteReq MSHR uncacheable cycles 367411201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2396808000 # number of overall MSHR uncacheable cycles 367511201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.data 10872482533 # number of overall MSHR uncacheable cycles 367611201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7124500 # number of overall MSHR uncacheable cycles 367711201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.data 983849500 # number of overall MSHR uncacheable cycles 367811201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::total 14260264533 # number of overall MSHR uncacheable cycles 367910892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 368010892Sandreas.hansson@arm.comsystem.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 368111201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.272134 # mshr miss rate for UpgradeReq accesses 368211201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.299193 # mshr miss rate for UpgradeReq accesses 368311201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.285478 # mshr miss rate for UpgradeReq accesses 368411201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.264372 # mshr miss rate for SCUpgradeReq accesses 368511201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.208344 # mshr miss rate for SCUpgradeReq accesses 368611201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.234803 # mshr miss rate for SCUpgradeReq accesses 368711201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.778031 # mshr miss rate for ReadExReq accesses 368811201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.415275 # mshr miss rate for ReadExReq accesses 368911201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.666875 # mshr miss rate for ReadExReq accesses 369011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.278847 # mshr miss rate for ReadSharedReq accesses 369111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.357118 # mshr miss rate for ReadSharedReq accesses 369211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.109544 # mshr miss rate for ReadSharedReq accesses 369311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.202317 # mshr miss rate for ReadSharedReq accesses 369411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.523301 # mshr miss rate for ReadSharedReq accesses 369511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.302054 # mshr miss rate for ReadSharedReq accesses 369611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.345830 # mshr miss rate for ReadSharedReq accesses 369711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.085145 # mshr miss rate for ReadSharedReq accesses 369811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.180852 # mshr miss rate for ReadSharedReq accesses 369911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.428190 # mshr miss rate for ReadSharedReq accesses 370011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_mshr_miss_rate::total 0.250193 # mshr miss rate for ReadSharedReq accesses 370111201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.278847 # mshr miss rate for demand accesses 370211201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.357118 # mshr miss rate for demand accesses 370311201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.109544 # mshr miss rate for demand accesses 370411201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.484780 # mshr miss rate for demand accesses 370511201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.523301 # mshr miss rate for demand accesses 370611201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.302054 # mshr miss rate for demand accesses 370711201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.345830 # mshr miss rate for demand accesses 370811201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.085145 # mshr miss rate for demand accesses 370911201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.247954 # mshr miss rate for demand accesses 371011201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.428190 # mshr miss rate for demand accesses 371111201Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.337027 # mshr miss rate for demand accesses 371211201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.278847 # mshr miss rate for overall accesses 371311201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.357118 # mshr miss rate for overall accesses 371411201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.109544 # mshr miss rate for overall accesses 371511201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.484780 # mshr miss rate for overall accesses 371611201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.523301 # mshr miss rate for overall accesses 371711201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.302054 # mshr miss rate for overall accesses 371811201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.345830 # mshr miss rate for overall accesses 371911201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.085145 # mshr miss rate for overall accesses 372011201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.247954 # mshr miss rate for overall accesses 372111201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.428190 # mshr miss rate for overall accesses 372211201Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.337027 # mshr miss rate for overall accesses 372311201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 73513.974368 # average UpgradeReq mshr miss latency 372411201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 73520.246226 # average UpgradeReq mshr miss latency 372511201Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 73517.215898 # average UpgradeReq mshr miss latency 372611201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 76539.471865 # average SCUpgradeReq mshr miss latency 372711201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76458.666015 # average SCUpgradeReq mshr miss latency 372811201Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 76501.631296 # average SCUpgradeReq mshr miss latency 372911201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 155524.478079 # average ReadExReq mshr miss latency 373011201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 137395.289544 # average ReadExReq mshr miss latency 373111201Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 152065.180648 # average ReadExReq mshr miss latency 373211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 132684.115523 # average ReadSharedReq mshr miss latency 373311201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 134399.114173 # average ReadSharedReq mshr miss latency 373411201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 127229.273092 # average ReadSharedReq mshr miss latency 373511201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 135142.172565 # average ReadSharedReq mshr miss latency 373611201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 171429.963404 # average ReadSharedReq mshr miss latency 373711201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 133261.637504 # average ReadSharedReq mshr miss latency 373811201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 132089.803220 # average ReadSharedReq mshr miss latency 373911201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 127189.983043 # average ReadSharedReq mshr miss latency 374011201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 133999.223594 # average ReadSharedReq mshr miss latency 374111201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166952.728555 # average ReadSharedReq mshr miss latency 374211201Sandreas.hansson@arm.comsystem.l2c.ReadSharedReq_avg_mshr_miss_latency::total 153742.669820 # average ReadSharedReq mshr miss latency 374311201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 132684.115523 # average overall mshr miss latency 374411201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 134399.114173 # average overall mshr miss latency 374511201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 127229.273092 # average overall mshr miss latency 374611201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 151191.633086 # average overall mshr miss latency 374711201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 171429.963404 # average overall mshr miss latency 374811201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 133261.637504 # average overall mshr miss latency 374911201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 132089.803220 # average overall mshr miss latency 375011201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 127189.983043 # average overall mshr miss latency 375111201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 135627.302450 # average overall mshr miss latency 375211201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166952.728555 # average overall mshr miss latency 375311201Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 153050.954108 # average overall mshr miss latency 375411201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 132684.115523 # average overall mshr miss latency 375511201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 134399.114173 # average overall mshr miss latency 375611201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 127229.273092 # average overall mshr miss latency 375711201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 151191.633086 # average overall mshr miss latency 375811201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 171429.963404 # average overall mshr miss latency 375911201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 133261.637504 # average overall mshr miss latency 376011201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 132089.803220 # average overall mshr miss latency 376111201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 127189.983043 # average overall mshr miss latency 376211201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 135627.302450 # average overall mshr miss latency 376311201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 166952.728555 # average overall mshr miss latency 376411201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 153050.954108 # average overall mshr miss latency 376511201Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781 # average ReadReq mshr uncacheable latency 376611201Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 165697.299188 # average ReadReq mshr uncacheable latency 376711201Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 106335.820896 # average ReadReq mshr uncacheable latency 376811201Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 82908.849395 # average ReadReq mshr uncacheable latency 376911201Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total 139109.343853 # average ReadReq mshr uncacheable latency 377011201Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164474.122464 # average WriteReq mshr uncacheable latency 377111201Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100403.061224 # average WriteReq mshr uncacheable latency 377211201Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::total 155615.029734 # average WriteReq mshr uncacheable latency 377311201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 112563.189781 # average overall mshr uncacheable latency 377411201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 165084.763635 # average overall mshr uncacheable latency 377511201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 106335.820896 # average overall mshr uncacheable latency 377611201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 91520.883721 # average overall mshr uncacheable latency 377711201Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total 145557.461805 # average overall mshr uncacheable latency 377810515SAli.Saidi@ARM.comsystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 377911201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 59697 # Transaction distribution 378011201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 1020888 # Transaction distribution 378111201Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 38273 # Transaction distribution 378211201Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 38273 # Transaction distribution 378311201Sandreas.hansson@arm.comsystem.membus.trans_dist::WritebackDirty 1348844 # Transaction distribution 378411201Sandreas.hansson@arm.comsystem.membus.trans_dist::CleanEvict 267564 # Transaction distribution 378511201Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 448101 # Transaction distribution 378611201Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 314840 # Transaction distribution 378711201Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 158230 # Transaction distribution 378811138Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution 378911201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 678893 # Transaction distribution 379011201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 659308 # Transaction distribution 379111201Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 961191 # Transaction distribution 379211201Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateReq 106727 # Transaction distribution 379311201Sandreas.hansson@arm.comsystem.membus.trans_dist::InvalidateResp 106727 # Transaction distribution 379411201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122554 # Packet count per connected master and slave (bytes) 379511201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) 379611201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25446 # Packet count per connected master and slave (bytes) 379711201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5713992 # Packet count per connected master and slave (bytes) 379811201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 5862068 # Packet count per connected master and slave (bytes) 379911201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 342759 # Packet count per connected master and slave (bytes) 380011201Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 342759 # Packet count per connected master and slave (bytes) 380111201Sandreas.hansson@arm.comsystem.membus.pkt_count::total 6204827 # Packet count per connected master and slave (bytes) 380211201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155661 # Cumulative packet size per connected master and slave (bytes) 380311201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes) 380411201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50892 # Cumulative packet size per connected master and slave (bytes) 380511201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 182954368 # Cumulative packet size per connected master and slave (bytes) 380611201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 183161477 # Cumulative packet size per connected master and slave (bytes) 380711201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7272320 # Cumulative packet size per connected master and slave (bytes) 380811201Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 7272320 # Cumulative packet size per connected master and slave (bytes) 380911201Sandreas.hansson@arm.comsystem.membus.pkt_size::total 190433797 # Cumulative packet size per connected master and slave (bytes) 381011201Sandreas.hansson@arm.comsystem.membus.snoops 627031 # Total snoops (count) 381111201Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 4226315 # Request fanout histogram 381210576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 1 # Request fanout histogram 381310576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 381410576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 381510576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 381611201Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 4226315 100.00% 100.00% # Request fanout histogram 381710576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 381810576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 381910576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 382010576Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 382111201Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 4226315 # Request fanout histogram 382211201Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 98488499 # Layer occupancy (ticks) 382310576Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 382411201Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 53000 # Layer occupancy (ticks) 382510576Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 382611201Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 21525971 # Layer occupancy (ticks) 382710576Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 382811201Sandreas.hansson@arm.comsystem.membus.reqLayer5.occupancy 9456985184 # Layer occupancy (ticks) 382910585Sandreas.hansson@arm.comsystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 383011201Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 8888143010 # Layer occupancy (ticks) 383110576Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 383211201Sandreas.hansson@arm.comsystem.membus.respLayer3.occupancy 228798971 # Layer occupancy (ticks) 383310576Sandreas.hansson@arm.comsystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 383410515SAli.Saidi@ARM.comsystem.realview.ethernet.txBytes 966 # Bytes Transmitted 383510515SAli.Saidi@ARM.comsystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 383610515SAli.Saidi@ARM.comsystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 383710515SAli.Saidi@ARM.comsystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 383810515SAli.Saidi@ARM.comsystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 383910515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 384010515SAli.Saidi@ARM.comsystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 384110515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 384210515SAli.Saidi@ARM.comsystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 384310515SAli.Saidi@ARM.comsystem.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 384410515SAli.Saidi@ARM.comsystem.realview.ethernet.totPackets 3 # Total Packets 384510515SAli.Saidi@ARM.comsystem.realview.ethernet.totBytes 966 # Total Bytes 384610515SAli.Saidi@ARM.comsystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 384710515SAli.Saidi@ARM.comsystem.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 384810515SAli.Saidi@ARM.comsystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 384910515SAli.Saidi@ARM.comsystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 385010515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 385110515SAli.Saidi@ARM.comsystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 385210515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 385310515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 385410515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 385510515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 385610515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 385710515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 385810515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 385910515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 386010515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 386110515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 386210515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 386310515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 386410515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 386510515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 386610515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 386710515SAli.Saidi@ARM.comsystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 386810515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 386910515SAli.Saidi@ARM.comsystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 387010515SAli.Saidi@ARM.comsystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 387110515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 387210515SAli.Saidi@ARM.comsystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 387310515SAli.Saidi@ARM.comsystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 387410515SAli.Saidi@ARM.comsystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 387510515SAli.Saidi@ARM.comsystem.realview.ethernet.droppedPackets 0 # number of packets dropped 387611103Snilay@cs.wisc.edusystem.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks 387711014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks 387811014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks 387911014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks 388011014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks 388111014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks 388211014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks 388311014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks 388411014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks 388511014Sandreas.sandberg@arm.comsystem.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks 388611201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_requests 12205155 # Total number of requests made to the snoop filter. 388711201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_requests 6621083 # Number of requests hitting in the snoop filter with a single holder of the requested data. 388811201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_requests 1960564 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 388911201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.tot_snoops 171525 # Total number of snoops made to the snoop filter. 389011201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_single_snoops 155955 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 389111201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_filter.hit_multi_snoops 15570 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 389211201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 59699 # Transaction distribution 389311201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 4664873 # Transaction distribution 389411201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 38273 # Transaction distribution 389511201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 38273 # Transaction distribution 389611201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WritebackDirty 4247047 # Transaction distribution 389711201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution 389811201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::CleanEvict 1614803 # Transaction distribution 389911201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 750027 # Transaction distribution 390011201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 396749 # Transaction distribution 390111201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 1146775 # Transaction distribution 390211201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeFailReq 211 # Transaction distribution 390311201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeFailResp 211 # Transaction distribution 390411201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 1140836 # Transaction distribution 390511201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 1140836 # Transaction distribution 390611201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadSharedReq 4612412 # Transaction distribution 390711201Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::InvalidateReq 106727 # Transaction distribution 390811201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8853195 # Packet count per connected master and slave (bytes) 390911201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7749082 # Packet count per connected master and slave (bytes) 391011201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 16602277 # Packet count per connected master and slave (bytes) 391111201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 269317869 # Cumulative packet size per connected master and slave (bytes) 391211201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 224565592 # Cumulative packet size per connected master and slave (bytes) 391311201Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 493883461 # Cumulative packet size per connected master and slave (bytes) 391411201Sandreas.hansson@arm.comsystem.toL2Bus.snoops 3357154 # Total snoops (count) 391511201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 8803755 # Request fanout histogram 391611201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 0.347401 # Request fanout histogram 391711201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.479844 # Request fanout histogram 391810515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 391911201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::0 5760896 65.44% 65.44% # Request fanout histogram 392011201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 3027289 34.39% 99.82% # Request fanout histogram 392111201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 15570 0.18% 100.00% # Request fanout histogram 392210515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 392311138Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 392410515SAli.Saidi@ARM.comsystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 392511201Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 8803755 # Request fanout histogram 392611201Sandreas.hansson@arm.comsystem.toL2Bus.reqLayer0.occupancy 9517655622 # Layer occupancy (ticks) 392710515SAli.Saidi@ARM.comsystem.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 392811201Sandreas.hansson@arm.comsystem.toL2Bus.snoopLayer0.occupancy 2614297 # Layer occupancy (ticks) 392910515SAli.Saidi@ARM.comsystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 393011201Sandreas.hansson@arm.comsystem.toL2Bus.respLayer0.occupancy 4898920623 # Layer occupancy (ticks) 393110515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 393211201Sandreas.hansson@arm.comsystem.toL2Bus.respLayer1.occupancy 4389147401 # Layer occupancy (ticks) 393310515SAli.Saidi@ARM.comsystem.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 393410515SAli.Saidi@ARM.comsystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 393511201Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 12586 # number of quiesce instructions executed 393610515SAli.Saidi@ARM.comsystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 393711201Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 5763 # number of quiesce instructions executed 393810515SAli.Saidi@ARM.com 393910515SAli.Saidi@ARM.com---------- End Simulation Statistics ---------- 3940