stats.txt revision 11167:207d6f2f1d53
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.667490 # Number of seconds simulated 4sim_ticks 51667489826000 # Number of ticks simulated 5final_tick 51667489826000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 98445 # Simulator instruction rate (inst/s) 8host_op_rate 115675 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5518412939 # Simulator tick rate (ticks/s) 10host_mem_usage 676348 # Number of bytes of host memory used 11host_seconds 9362.74 # Real time elapsed on the host 12sim_insts 921716010 # Number of instructions simulated 13sim_ops 1083032845 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.dtb.walker 356224 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.itb.walker 294592 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.inst 10211648 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.data 93641864 # Number of bytes read from this memory 20system.physmem.bytes_read::realview.ide 394368 # Number of bytes read from this memory 21system.physmem.bytes_read::total 104898696 # Number of bytes read from this memory 22system.physmem.bytes_inst_read::cpu.inst 10211648 # Number of instructions bytes read from this memory 23system.physmem.bytes_inst_read::total 10211648 # Number of instructions bytes read from this memory 24system.physmem.bytes_written::writebacks 87439552 # Number of bytes written to this memory 25system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 26system.physmem.bytes_written::total 87460132 # Number of bytes written to this memory 27system.physmem.num_reads::cpu.dtb.walker 5566 # Number of read requests responded to by this memory 28system.physmem.num_reads::cpu.itb.walker 4603 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.inst 159557 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.data 1463167 # Number of read requests responded to by this memory 31system.physmem.num_reads::realview.ide 6162 # Number of read requests responded to by this memory 32system.physmem.num_reads::total 1639055 # Number of read requests responded to by this memory 33system.physmem.num_writes::writebacks 1366243 # Number of write requests responded to by this memory 34system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 35system.physmem.num_writes::total 1368816 # Number of write requests responded to by this memory 36system.physmem.bw_read::cpu.dtb.walker 6895 # Total read bandwidth from this memory (bytes/s) 37system.physmem.bw_read::cpu.itb.walker 5702 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.inst 197642 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.data 1812394 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::realview.ide 7633 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::total 2030265 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_inst_read::cpu.inst 197642 # Instruction read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::total 197642 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_write::writebacks 1692351 # Write bandwidth from this memory (bytes/s) 45system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::total 1692750 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_total::writebacks 1692351 # Total bandwidth to/from this memory (bytes/s) 48system.physmem.bw_total::cpu.dtb.walker 6895 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.itb.walker 5702 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.inst 197642 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.data 1812793 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::realview.ide 7633 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::total 3723015 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.readReqs 1639055 # Number of read requests accepted 55system.physmem.writeReqs 1368816 # Number of write requests accepted 56system.physmem.readBursts 1639055 # Number of DRAM read bursts, including those serviced by the write queue 57system.physmem.writeBursts 1368816 # Number of DRAM write bursts, including those merged in the write queue 58system.physmem.bytesReadDRAM 104838592 # Total number of bytes read from DRAM 59system.physmem.bytesReadWrQ 60928 # Total number of bytes read from write queue 60system.physmem.bytesWritten 87458560 # Total number of bytes written to DRAM 61system.physmem.bytesReadSys 104898696 # Total read bytes from the system interface side 62system.physmem.bytesWrittenSys 87460132 # Total written bytes from the system interface side 63system.physmem.servicedByWrQ 952 # Number of DRAM read bursts serviced by the write queue 64system.physmem.mergedWrBursts 2245 # Number of DRAM write bursts merged with an existing one 65system.physmem.neitherReadNorWriteReqs 145140 # Number of requests that are neither read nor write 66system.physmem.perBankRdBursts::0 96907 # Per bank write bursts 67system.physmem.perBankRdBursts::1 103074 # Per bank write bursts 68system.physmem.perBankRdBursts::2 99514 # Per bank write bursts 69system.physmem.perBankRdBursts::3 96513 # Per bank write bursts 70system.physmem.perBankRdBursts::4 97689 # Per bank write bursts 71system.physmem.perBankRdBursts::5 108359 # Per bank write bursts 72system.physmem.perBankRdBursts::6 97886 # Per bank write bursts 73system.physmem.perBankRdBursts::7 97902 # Per bank write bursts 74system.physmem.perBankRdBursts::8 96810 # Per bank write bursts 75system.physmem.perBankRdBursts::9 157961 # Per bank write bursts 76system.physmem.perBankRdBursts::10 100161 # Per bank write bursts 77system.physmem.perBankRdBursts::11 104541 # Per bank write bursts 78system.physmem.perBankRdBursts::12 94779 # Per bank write bursts 79system.physmem.perBankRdBursts::13 97199 # Per bank write bursts 80system.physmem.perBankRdBursts::14 94176 # Per bank write bursts 81system.physmem.perBankRdBursts::15 94632 # Per bank write bursts 82system.physmem.perBankWrBursts::0 82268 # Per bank write bursts 83system.physmem.perBankWrBursts::1 85491 # Per bank write bursts 84system.physmem.perBankWrBursts::2 84713 # Per bank write bursts 85system.physmem.perBankWrBursts::3 83877 # Per bank write bursts 86system.physmem.perBankWrBursts::4 85039 # Per bank write bursts 87system.physmem.perBankWrBursts::5 91961 # Per bank write bursts 88system.physmem.perBankWrBursts::6 84027 # Per bank write bursts 89system.physmem.perBankWrBursts::7 85348 # Per bank write bursts 90system.physmem.perBankWrBursts::8 84923 # Per bank write bursts 91system.physmem.perBankWrBursts::9 91534 # Per bank write bursts 92system.physmem.perBankWrBursts::10 85936 # Per bank write bursts 93system.physmem.perBankWrBursts::11 89456 # Per bank write bursts 94system.physmem.perBankWrBursts::12 82822 # Per bank write bursts 95system.physmem.perBankWrBursts::13 84269 # Per bank write bursts 96system.physmem.perBankWrBursts::14 82271 # Per bank write bursts 97system.physmem.perBankWrBursts::15 82605 # Per bank write bursts 98system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 99system.physmem.numWrRetry 26 # Number of times write queue was full causing retry 100system.physmem.totGap 51667488071000 # Total gap between requests 101system.physmem.readPktSize::0 0 # Read request sizes (log2) 102system.physmem.readPktSize::1 0 # Read request sizes (log2) 103system.physmem.readPktSize::2 0 # Read request sizes (log2) 104system.physmem.readPktSize::3 13 # Read request sizes (log2) 105system.physmem.readPktSize::4 2 # Read request sizes (log2) 106system.physmem.readPktSize::5 0 # Read request sizes (log2) 107system.physmem.readPktSize::6 1639040 # Read request sizes (log2) 108system.physmem.writePktSize::0 0 # Write request sizes (log2) 109system.physmem.writePktSize::1 0 # Write request sizes (log2) 110system.physmem.writePktSize::2 1 # Write request sizes (log2) 111system.physmem.writePktSize::3 2572 # Write request sizes (log2) 112system.physmem.writePktSize::4 0 # Write request sizes (log2) 113system.physmem.writePktSize::5 0 # Write request sizes (log2) 114system.physmem.writePktSize::6 1366243 # Write request sizes (log2) 115system.physmem.rdQLenPdf::0 1313990 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::1 317969 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::2 940 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::3 332 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::4 443 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::5 534 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::6 495 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::7 1094 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::8 660 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::9 341 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::10 336 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::11 159 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::12 164 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::13 118 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::14 109 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::15 103 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::16 95 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::17 91 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::18 73 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::19 54 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 147system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::15 14883 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::16 17196 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::17 65910 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::18 80385 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::19 82507 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::20 82508 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::21 83232 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::22 83418 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::23 85151 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::24 84166 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::25 84814 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::26 89146 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::27 84019 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::28 82787 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::29 91825 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::30 82010 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::31 83266 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::32 79973 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::33 1221 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::34 663 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::35 487 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::36 510 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::37 476 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::38 421 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::39 348 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::40 389 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::41 302 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::42 399 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::43 340 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::44 412 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::45 268 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::46 306 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::47 328 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::48 306 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::49 350 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::50 244 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::51 174 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::52 164 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::53 184 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::54 172 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::55 177 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::56 135 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::57 114 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::58 95 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::59 109 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::60 91 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::61 76 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::62 45 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::63 54 # What write queue length does an incoming req see 211system.physmem.bytesPerActivate::samples 648381 # Bytes accessed per row activation 212system.physmem.bytesPerActivate::mean 296.579894 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::gmean 173.167741 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::stdev 323.754919 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::0-127 255622 39.42% 39.42% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::128-255 156386 24.12% 63.54% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::256-383 60110 9.27% 72.81% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::384-511 34859 5.38% 78.19% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::512-639 25315 3.90% 82.10% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::640-767 18876 2.91% 85.01% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::768-895 13882 2.14% 87.15% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::896-1023 12930 1.99% 89.14% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::1024-1151 70401 10.86% 100.00% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::total 648381 # Bytes accessed per row activation 225system.physmem.rdPerTurnAround::samples 79285 # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::mean 20.660314 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::stdev 283.326654 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::0-4095 79282 100.00% 100.00% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::4096-8191 1 0.00% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::24576-28671 1 0.00% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::73728-77823 1 0.00% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::total 79285 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 79285 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 17.235795 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 16.792425 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 6.378813 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16-19 77022 97.15% 97.15% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::20-23 299 0.38% 97.52% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::24-27 59 0.07% 97.60% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::28-31 299 0.38% 97.97% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::32-35 54 0.07% 98.04% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::36-39 317 0.40% 98.44% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::40-43 225 0.28% 98.73% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::44-47 23 0.03% 98.76% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::48-51 58 0.07% 98.83% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::52-55 133 0.17% 99.00% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::56-59 25 0.03% 99.03% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::60-63 40 0.05% 99.08% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::64-67 480 0.61% 99.68% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::68-71 36 0.05% 99.73% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::72-75 17 0.02% 99.75% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::76-79 132 0.17% 99.92% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::80-83 8 0.01% 99.93% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::84-87 2 0.00% 99.93% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::92-95 3 0.00% 99.93% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::96-99 2 0.00% 99.94% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::100-103 5 0.01% 99.94% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::104-107 1 0.00% 99.94% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::124-127 2 0.00% 99.95% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::128-131 28 0.04% 99.98% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::132-135 1 0.00% 99.98% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::136-139 1 0.00% 99.98% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::140-143 3 0.00% 99.99% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::144-147 1 0.00% 99.99% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::152-155 4 0.01% 99.99% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::156-159 3 0.00% 100.00% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::164-167 1 0.00% 100.00% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::176-179 1 0.00% 100.00% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::total 79285 # Writes before turning the bus around for reads 270system.physmem.totQLat 26536419219 # Total ticks spent queuing 271system.physmem.totMemAccLat 57250850469 # Total ticks spent from burst creation until serviced by the DRAM 272system.physmem.totBusLat 8190515000 # Total ticks spent in databus transfers 273system.physmem.avgQLat 16199.48 # Average queueing delay per DRAM burst 274system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 275system.physmem.avgMemAccLat 34949.48 # Average memory access latency per DRAM burst 276system.physmem.avgRdBW 2.03 # Average DRAM read bandwidth in MiByte/s 277system.physmem.avgWrBW 1.69 # Average achieved write bandwidth in MiByte/s 278system.physmem.avgRdBWSys 2.03 # Average system read bandwidth in MiByte/s 279system.physmem.avgWrBWSys 1.69 # Average system write bandwidth in MiByte/s 280system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 281system.physmem.busUtil 0.03 # Data bus utilization in percentage 282system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads 283system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 284system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 285system.physmem.avgWrQLen 24.18 # Average write queue length when enqueuing 286system.physmem.readRowHits 1330988 # Number of row buffer hits during reads 287system.physmem.writeRowHits 1025273 # Number of row buffer hits during writes 288system.physmem.readRowHitRate 81.25 # Row buffer hit rate for reads 289system.physmem.writeRowHitRate 75.03 # Row buffer hit rate for writes 290system.physmem.avgGap 17177428.18 # Average gap between requests 291system.physmem.pageHitRate 78.42 # Row buffer hit rate, read and write combined 292system.physmem_0.actEnergy 2459736720 # Energy for activate commands per rank (pJ) 293system.physmem_0.preEnergy 1342118250 # Energy for precharge commands per rank (pJ) 294system.physmem_0.readEnergy 6223136400 # Energy for read commands per rank (pJ) 295system.physmem_0.writeEnergy 4424051520 # Energy for write commands per rank (pJ) 296system.physmem_0.refreshEnergy 3374668883040 # Energy for refresh commands per rank (pJ) 297system.physmem_0.actBackEnergy 1319911106400 # Energy for active background per rank (pJ) 298system.physmem_0.preBackEnergy 29842673702250 # Energy for precharge background per rank (pJ) 299system.physmem_0.totalEnergy 34551702734580 # Total energy per rank (pJ) 300system.physmem_0.averagePower 668.732053 # Core power per rank (mW) 301system.physmem_0.memoryStateTime::IDLE 49645039210452 # Time in different power states 302system.physmem_0.memoryStateTime::REF 1725290840000 # Time in different power states 303system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 304system.physmem_0.memoryStateTime::ACT 297159003548 # Time in different power states 305system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 306system.physmem_1.actEnergy 2442023640 # Energy for activate commands per rank (pJ) 307system.physmem_1.preEnergy 1332453375 # Energy for precharge commands per rank (pJ) 308system.physmem_1.readEnergy 6554020200 # Energy for read commands per rank (pJ) 309system.physmem_1.writeEnergy 4431127680 # Energy for write commands per rank (pJ) 310system.physmem_1.refreshEnergy 3374668883040 # Energy for refresh commands per rank (pJ) 311system.physmem_1.actBackEnergy 1320412056885 # Energy for active background per rank (pJ) 312system.physmem_1.preBackEnergy 29842234272000 # Energy for precharge background per rank (pJ) 313system.physmem_1.totalEnergy 34552074836820 # Total energy per rank (pJ) 314system.physmem_1.averagePower 668.739255 # Core power per rank (mW) 315system.physmem_1.memoryStateTime::IDLE 49644231851772 # Time in different power states 316system.physmem_1.memoryStateTime::REF 1725290840000 # Time in different power states 317system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 318system.physmem_1.memoryStateTime::ACT 297961425728 # Time in different power states 319system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 320system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory 321system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 322system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory 323system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory 324system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory 325system.realview.nvmem.num_reads::cpu.inst 11 # Number of read requests responded to by this memory 326system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 327system.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory 328system.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s) 329system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 330system.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s) 331system.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s) 332system.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s) 333system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) 334system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 335system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) 336system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 337system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 338system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 339system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 340system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 341system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 342system.cpu.branchPred.lookups 252436095 # Number of BP lookups 343system.cpu.branchPred.condPredicted 176405196 # Number of conditional branches predicted 344system.cpu.branchPred.condIncorrect 11951074 # Number of conditional branches incorrect 345system.cpu.branchPred.BTBLookups 185535740 # Number of BTB lookups 346system.cpu.branchPred.BTBHits 131467669 # Number of BTB hits 347system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 348system.cpu.branchPred.BTBHitPct 70.858407 # BTB Hit Percentage 349system.cpu.branchPred.usedRAS 30937069 # Number of times the RAS was used to get a target. 350system.cpu.branchPred.RASInCorrect 2133020 # Number of incorrect RAS predictions. 351system.cpu_clk_domain.clock 500 # Clock period in ticks 352system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 353system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 354system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 355system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 356system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 357system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 358system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 359system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 360system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 361system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 362system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 363system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 364system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 365system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 366system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 367system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 368system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 369system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 370system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 371system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 372system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 373system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 374system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 375system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 376system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 377system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 378system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 379system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 380system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 381system.cpu.dtb.walker.walks 560363 # Table walker walks requested 382system.cpu.dtb.walker.walksLong 560363 # Table walker walks initiated with long descriptors 383system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20601 # Level at which table walker walks with long descriptors terminate 384system.cpu.dtb.walker.walksLongTerminationLevel::Level3 178609 # Level at which table walker walks with long descriptors terminate 385system.cpu.dtb.walker.walkWaitTime::samples 560363 # Table walker wait (enqueue to first request) latency 386system.cpu.dtb.walker.walkWaitTime::0 560363 100.00% 100.00% # Table walker wait (enqueue to first request) latency 387system.cpu.dtb.walker.walkWaitTime::total 560363 # Table walker wait (enqueue to first request) latency 388system.cpu.dtb.walker.walkCompletionTime::samples 199210 # Table walker service (enqueue to completion) latency 389system.cpu.dtb.walker.walkCompletionTime::mean 27145.243713 # Table walker service (enqueue to completion) latency 390system.cpu.dtb.walker.walkCompletionTime::gmean 23005.972162 # Table walker service (enqueue to completion) latency 391system.cpu.dtb.walker.walkCompletionTime::stdev 20907.221064 # Table walker service (enqueue to completion) latency 392system.cpu.dtb.walker.walkCompletionTime::0-65535 196938 98.86% 98.86% # Table walker service (enqueue to completion) latency 393system.cpu.dtb.walker.walkCompletionTime::65536-131071 1 0.00% 98.86% # Table walker service (enqueue to completion) latency 394system.cpu.dtb.walker.walkCompletionTime::131072-196607 1933 0.97% 99.83% # Table walker service (enqueue to completion) latency 395system.cpu.dtb.walker.walkCompletionTime::196608-262143 52 0.03% 99.86% # Table walker service (enqueue to completion) latency 396system.cpu.dtb.walker.walkCompletionTime::262144-327679 120 0.06% 99.92% # Table walker service (enqueue to completion) latency 397system.cpu.dtb.walker.walkCompletionTime::327680-393215 58 0.03% 99.95% # Table walker service (enqueue to completion) latency 398system.cpu.dtb.walker.walkCompletionTime::393216-458751 84 0.04% 99.99% # Table walker service (enqueue to completion) latency 399system.cpu.dtb.walker.walkCompletionTime::458752-524287 11 0.01% 99.99% # Table walker service (enqueue to completion) latency 400system.cpu.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency 401system.cpu.dtb.walker.walkCompletionTime::589824-655359 6 0.00% 100.00% # Table walker service (enqueue to completion) latency 402system.cpu.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 403system.cpu.dtb.walker.walkCompletionTime::total 199210 # Table walker service (enqueue to completion) latency 404system.cpu.dtb.walker.walksPending::samples -1571833592 # Table walker pending requests distribution 405system.cpu.dtb.walker.walksPending::0 -1571833592 100.00% 100.00% # Table walker pending requests distribution 406system.cpu.dtb.walker.walksPending::total -1571833592 # Table walker pending requests distribution 407system.cpu.dtb.walker.walkPageSizes::4K 178610 89.66% 89.66% # Table walker page sizes translated 408system.cpu.dtb.walker.walkPageSizes::2M 20601 10.34% 100.00% # Table walker page sizes translated 409system.cpu.dtb.walker.walkPageSizes::total 199211 # Table walker page sizes translated 410system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 560363 # Table walker requests started/completed, data/inst 411system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 412system.cpu.dtb.walker.walkRequestOrigin_Requested::total 560363 # Table walker requests started/completed, data/inst 413system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 199211 # Table walker requests started/completed, data/inst 414system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 415system.cpu.dtb.walker.walkRequestOrigin_Completed::total 199211 # Table walker requests started/completed, data/inst 416system.cpu.dtb.walker.walkRequestOrigin::total 759574 # Table walker requests started/completed, data/inst 417system.cpu.dtb.inst_hits 0 # ITB inst hits 418system.cpu.dtb.inst_misses 0 # ITB inst misses 419system.cpu.dtb.read_hits 178192284 # DTB read hits 420system.cpu.dtb.read_misses 462603 # DTB read misses 421system.cpu.dtb.write_hits 157870024 # DTB write hits 422system.cpu.dtb.write_misses 97760 # DTB write misses 423system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 424system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 425system.cpu.dtb.flush_tlb_mva_asid 45300 # Number of times TLB was flushed by MVA & ASID 426system.cpu.dtb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID 427system.cpu.dtb.flush_entries 78455 # Number of entries that have been flushed from TLB 428system.cpu.dtb.align_faults 1375 # Number of TLB faults due to alignment restrictions 429system.cpu.dtb.prefetch_faults 14585 # Number of TLB faults due to prefetch 430system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 431system.cpu.dtb.perms_faults 23059 # Number of TLB faults due to permissions restrictions 432system.cpu.dtb.read_accesses 178654887 # DTB read accesses 433system.cpu.dtb.write_accesses 157967784 # DTB write accesses 434system.cpu.dtb.inst_accesses 0 # ITB inst accesses 435system.cpu.dtb.hits 336062308 # DTB hits 436system.cpu.dtb.misses 560363 # DTB misses 437system.cpu.dtb.accesses 336622671 # DTB accesses 438system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 439system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 440system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 441system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 442system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 443system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 444system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 445system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 446system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 447system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 448system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 449system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 450system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 451system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 452system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 453system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 454system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 455system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 456system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 457system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 458system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 459system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 460system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 461system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 462system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 463system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 464system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 465system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 466system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 467system.cpu.itb.walker.walks 134893 # Table walker walks requested 468system.cpu.itb.walker.walksLong 134893 # Table walker walks initiated with long descriptors 469system.cpu.itb.walker.walksLongTerminationLevel::Level2 1070 # Level at which table walker walks with long descriptors terminate 470system.cpu.itb.walker.walksLongTerminationLevel::Level3 117642 # Level at which table walker walks with long descriptors terminate 471system.cpu.itb.walker.walkWaitTime::samples 134893 # Table walker wait (enqueue to first request) latency 472system.cpu.itb.walker.walkWaitTime::0 134893 100.00% 100.00% # Table walker wait (enqueue to first request) latency 473system.cpu.itb.walker.walkWaitTime::total 134893 # Table walker wait (enqueue to first request) latency 474system.cpu.itb.walker.walkCompletionTime::samples 118712 # Table walker service (enqueue to completion) latency 475system.cpu.itb.walker.walkCompletionTime::mean 30207.312656 # Table walker service (enqueue to completion) latency 476system.cpu.itb.walker.walkCompletionTime::gmean 25802.029077 # Table walker service (enqueue to completion) latency 477system.cpu.itb.walker.walkCompletionTime::stdev 23121.543530 # Table walker service (enqueue to completion) latency 478system.cpu.itb.walker.walkCompletionTime::0-65535 116190 97.88% 97.88% # Table walker service (enqueue to completion) latency 479system.cpu.itb.walker.walkCompletionTime::65536-131071 6 0.01% 97.88% # Table walker service (enqueue to completion) latency 480system.cpu.itb.walker.walkCompletionTime::131072-196607 2295 1.93% 99.81% # Table walker service (enqueue to completion) latency 481system.cpu.itb.walker.walkCompletionTime::196608-262143 67 0.06% 99.87% # Table walker service (enqueue to completion) latency 482system.cpu.itb.walker.walkCompletionTime::262144-327679 109 0.09% 99.96% # Table walker service (enqueue to completion) latency 483system.cpu.itb.walker.walkCompletionTime::327680-393215 28 0.02% 99.99% # Table walker service (enqueue to completion) latency 484system.cpu.itb.walker.walkCompletionTime::393216-458751 11 0.01% 99.99% # Table walker service (enqueue to completion) latency 485system.cpu.itb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency 486system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 487system.cpu.itb.walker.walkCompletionTime::total 118712 # Table walker service (enqueue to completion) latency 488system.cpu.itb.walker.walksPending::samples -1572850092 # Table walker pending requests distribution 489system.cpu.itb.walker.walksPending::0 -1572850092 100.00% 100.00% # Table walker pending requests distribution 490system.cpu.itb.walker.walksPending::total -1572850092 # Table walker pending requests distribution 491system.cpu.itb.walker.walkPageSizes::4K 117642 99.10% 99.10% # Table walker page sizes translated 492system.cpu.itb.walker.walkPageSizes::2M 1070 0.90% 100.00% # Table walker page sizes translated 493system.cpu.itb.walker.walkPageSizes::total 118712 # Table walker page sizes translated 494system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 495system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 134893 # Table walker requests started/completed, data/inst 496system.cpu.itb.walker.walkRequestOrigin_Requested::total 134893 # Table walker requests started/completed, data/inst 497system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 498system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 118712 # Table walker requests started/completed, data/inst 499system.cpu.itb.walker.walkRequestOrigin_Completed::total 118712 # Table walker requests started/completed, data/inst 500system.cpu.itb.walker.walkRequestOrigin::total 253605 # Table walker requests started/completed, data/inst 501system.cpu.itb.inst_hits 438788360 # ITB inst hits 502system.cpu.itb.inst_misses 134893 # ITB inst misses 503system.cpu.itb.read_hits 0 # DTB read hits 504system.cpu.itb.read_misses 0 # DTB read misses 505system.cpu.itb.write_hits 0 # DTB write hits 506system.cpu.itb.write_misses 0 # DTB write misses 507system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 508system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 509system.cpu.itb.flush_tlb_mva_asid 45300 # Number of times TLB was flushed by MVA & ASID 510system.cpu.itb.flush_tlb_asid 1089 # Number of times TLB was flushed by ASID 511system.cpu.itb.flush_entries 56501 # Number of entries that have been flushed from TLB 512system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 513system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 514system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 515system.cpu.itb.perms_faults 359579 # Number of TLB faults due to permissions restrictions 516system.cpu.itb.read_accesses 0 # DTB read accesses 517system.cpu.itb.write_accesses 0 # DTB write accesses 518system.cpu.itb.inst_accesses 438923253 # ITB inst accesses 519system.cpu.itb.hits 438788360 # DTB hits 520system.cpu.itb.misses 134893 # DTB misses 521system.cpu.itb.accesses 438923253 # DTB accesses 522system.cpu.numCycles 2560804207 # number of cpu cycles simulated 523system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 524system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 525system.cpu.committedInsts 921716010 # Number of instructions committed 526system.cpu.committedOps 1083032845 # Number of ops (including micro ops) committed 527system.cpu.discardedOps 92871017 # Number of ops (including micro ops) which were discarded before commit 528system.cpu.numFetchSuspends 7624 # Number of times Execute suspended instruction fetching 529system.cpu.quiesceCycles 100775316475 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 530system.cpu.cpi 2.778301 # CPI: cycles per instruction 531system.cpu.ipc 0.359932 # IPC: instructions per cycle 532system.cpu.kern.inst.arm 0 # number of arm instructions executed 533system.cpu.kern.inst.quiesce 16484 # number of quiesce instructions executed 534system.cpu.tickCycles 1740208465 # Number of cycles that the object actually ticked 535system.cpu.idleCycles 820595742 # Total number of cycles that the object has spent stopped 536system.cpu.dcache.tags.replacements 10718531 # number of replacements 537system.cpu.dcache.tags.tagsinuse 511.930101 # Cycle average of tags in use 538system.cpu.dcache.tags.total_refs 320228714 # Total number of references to valid blocks. 539system.cpu.dcache.tags.sampled_refs 10719043 # Sample count of references to valid blocks. 540system.cpu.dcache.tags.avg_refs 29.874749 # Average number of references to valid blocks. 541system.cpu.dcache.tags.warmup_cycle 7085883500 # Cycle when the warmup percentage was hit. 542system.cpu.dcache.tags.occ_blocks::cpu.data 511.930101 # Average occupied blocks per requestor 543system.cpu.dcache.tags.occ_percent::cpu.data 0.999863 # Average percentage of cache occupancy 544system.cpu.dcache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy 545system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 546system.cpu.dcache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id 547system.cpu.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id 548system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id 549system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 550system.cpu.dcache.tags.tag_accesses 1345217745 # Number of tag accesses 551system.cpu.dcache.tags.data_accesses 1345217745 # Number of data accesses 552system.cpu.dcache.ReadReq_hits::cpu.data 163909013 # number of ReadReq hits 553system.cpu.dcache.ReadReq_hits::total 163909013 # number of ReadReq hits 554system.cpu.dcache.WriteReq_hits::cpu.data 147410694 # number of WriteReq hits 555system.cpu.dcache.WriteReq_hits::total 147410694 # number of WriteReq hits 556system.cpu.dcache.SoftPFReq_hits::cpu.data 512357 # number of SoftPFReq hits 557system.cpu.dcache.SoftPFReq_hits::total 512357 # number of SoftPFReq hits 558system.cpu.dcache.WriteLineReq_hits::cpu.data 335795 # number of WriteLineReq hits 559system.cpu.dcache.WriteLineReq_hits::total 335795 # number of WriteLineReq hits 560system.cpu.dcache.LoadLockedReq_hits::cpu.data 3851860 # number of LoadLockedReq hits 561system.cpu.dcache.LoadLockedReq_hits::total 3851860 # number of LoadLockedReq hits 562system.cpu.dcache.StoreCondReq_hits::cpu.data 4160801 # number of StoreCondReq hits 563system.cpu.dcache.StoreCondReq_hits::total 4160801 # number of StoreCondReq hits 564system.cpu.dcache.demand_hits::cpu.data 311319707 # number of demand (read+write) hits 565system.cpu.dcache.demand_hits::total 311319707 # number of demand (read+write) hits 566system.cpu.dcache.overall_hits::cpu.data 311832064 # number of overall hits 567system.cpu.dcache.overall_hits::total 311832064 # number of overall hits 568system.cpu.dcache.ReadReq_misses::cpu.data 6365428 # number of ReadReq misses 569system.cpu.dcache.ReadReq_misses::total 6365428 # number of ReadReq misses 570system.cpu.dcache.WriteReq_misses::cpu.data 4129661 # number of WriteReq misses 571system.cpu.dcache.WriteReq_misses::total 4129661 # number of WriteReq misses 572system.cpu.dcache.SoftPFReq_misses::cpu.data 1399457 # number of SoftPFReq misses 573system.cpu.dcache.SoftPFReq_misses::total 1399457 # number of SoftPFReq misses 574system.cpu.dcache.WriteLineReq_misses::cpu.data 1238951 # number of WriteLineReq misses 575system.cpu.dcache.WriteLineReq_misses::total 1238951 # number of WriteLineReq misses 576system.cpu.dcache.LoadLockedReq_misses::cpu.data 310648 # number of LoadLockedReq misses 577system.cpu.dcache.LoadLockedReq_misses::total 310648 # number of LoadLockedReq misses 578system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 579system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses 580system.cpu.dcache.demand_misses::cpu.data 10495089 # number of demand (read+write) misses 581system.cpu.dcache.demand_misses::total 10495089 # number of demand (read+write) misses 582system.cpu.dcache.overall_misses::cpu.data 11894546 # number of overall misses 583system.cpu.dcache.overall_misses::total 11894546 # number of overall misses 584system.cpu.dcache.ReadReq_miss_latency::cpu.data 117272085000 # number of ReadReq miss cycles 585system.cpu.dcache.ReadReq_miss_latency::total 117272085000 # number of ReadReq miss cycles 586system.cpu.dcache.WriteReq_miss_latency::cpu.data 200088691000 # number of WriteReq miss cycles 587system.cpu.dcache.WriteReq_miss_latency::total 200088691000 # number of WriteReq miss cycles 588system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 84456521500 # number of WriteLineReq miss cycles 589system.cpu.dcache.WriteLineReq_miss_latency::total 84456521500 # number of WriteLineReq miss cycles 590system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5138880500 # number of LoadLockedReq miss cycles 591system.cpu.dcache.LoadLockedReq_miss_latency::total 5138880500 # number of LoadLockedReq miss cycles 592system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles 593system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles 594system.cpu.dcache.demand_miss_latency::cpu.data 317360776000 # number of demand (read+write) miss cycles 595system.cpu.dcache.demand_miss_latency::total 317360776000 # number of demand (read+write) miss cycles 596system.cpu.dcache.overall_miss_latency::cpu.data 317360776000 # number of overall miss cycles 597system.cpu.dcache.overall_miss_latency::total 317360776000 # number of overall miss cycles 598system.cpu.dcache.ReadReq_accesses::cpu.data 170274441 # number of ReadReq accesses(hits+misses) 599system.cpu.dcache.ReadReq_accesses::total 170274441 # number of ReadReq accesses(hits+misses) 600system.cpu.dcache.WriteReq_accesses::cpu.data 151540355 # number of WriteReq accesses(hits+misses) 601system.cpu.dcache.WriteReq_accesses::total 151540355 # number of WriteReq accesses(hits+misses) 602system.cpu.dcache.SoftPFReq_accesses::cpu.data 1911814 # number of SoftPFReq accesses(hits+misses) 603system.cpu.dcache.SoftPFReq_accesses::total 1911814 # number of SoftPFReq accesses(hits+misses) 604system.cpu.dcache.WriteLineReq_accesses::cpu.data 1574746 # number of WriteLineReq accesses(hits+misses) 605system.cpu.dcache.WriteLineReq_accesses::total 1574746 # number of WriteLineReq accesses(hits+misses) 606system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4162508 # number of LoadLockedReq accesses(hits+misses) 607system.cpu.dcache.LoadLockedReq_accesses::total 4162508 # number of LoadLockedReq accesses(hits+misses) 608system.cpu.dcache.StoreCondReq_accesses::cpu.data 4160802 # number of StoreCondReq accesses(hits+misses) 609system.cpu.dcache.StoreCondReq_accesses::total 4160802 # number of StoreCondReq accesses(hits+misses) 610system.cpu.dcache.demand_accesses::cpu.data 321814796 # number of demand (read+write) accesses 611system.cpu.dcache.demand_accesses::total 321814796 # number of demand (read+write) accesses 612system.cpu.dcache.overall_accesses::cpu.data 323726610 # number of overall (read+write) accesses 613system.cpu.dcache.overall_accesses::total 323726610 # number of overall (read+write) accesses 614system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037383 # miss rate for ReadReq accesses 615system.cpu.dcache.ReadReq_miss_rate::total 0.037383 # miss rate for ReadReq accesses 616system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027251 # miss rate for WriteReq accesses 617system.cpu.dcache.WriteReq_miss_rate::total 0.027251 # miss rate for WriteReq accesses 618system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.732005 # miss rate for SoftPFReq accesses 619system.cpu.dcache.SoftPFReq_miss_rate::total 0.732005 # miss rate for SoftPFReq accesses 620system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.786762 # miss rate for WriteLineReq accesses 621system.cpu.dcache.WriteLineReq_miss_rate::total 0.786762 # miss rate for WriteLineReq accesses 622system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.074630 # miss rate for LoadLockedReq accesses 623system.cpu.dcache.LoadLockedReq_miss_rate::total 0.074630 # miss rate for LoadLockedReq accesses 624system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 625system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses 626system.cpu.dcache.demand_miss_rate::cpu.data 0.032612 # miss rate for demand accesses 627system.cpu.dcache.demand_miss_rate::total 0.032612 # miss rate for demand accesses 628system.cpu.dcache.overall_miss_rate::cpu.data 0.036743 # miss rate for overall accesses 629system.cpu.dcache.overall_miss_rate::total 0.036743 # miss rate for overall accesses 630system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18423.283556 # average ReadReq miss latency 631system.cpu.dcache.ReadReq_avg_miss_latency::total 18423.283556 # average ReadReq miss latency 632system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48451.601960 # average WriteReq miss latency 633system.cpu.dcache.WriteReq_avg_miss_latency::total 48451.601960 # average WriteReq miss latency 634system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 68167.765715 # average WriteLineReq miss latency 635system.cpu.dcache.WriteLineReq_avg_miss_latency::total 68167.765715 # average WriteLineReq miss latency 636system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16542.454804 # average LoadLockedReq miss latency 637system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16542.454804 # average LoadLockedReq miss latency 638system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency 639system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency 640system.cpu.dcache.demand_avg_miss_latency::cpu.data 30238.979012 # average overall miss latency 641system.cpu.dcache.demand_avg_miss_latency::total 30238.979012 # average overall miss latency 642system.cpu.dcache.overall_avg_miss_latency::cpu.data 26681.201283 # average overall miss latency 643system.cpu.dcache.overall_avg_miss_latency::total 26681.201283 # average overall miss latency 644system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 645system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 646system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 647system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 648system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 649system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 650system.cpu.dcache.fast_writes 0 # number of fast writes performed 651system.cpu.dcache.cache_copies 0 # number of cache copies performed 652system.cpu.dcache.writebacks::writebacks 8229800 # number of writebacks 653system.cpu.dcache.writebacks::total 8229800 # number of writebacks 654system.cpu.dcache.ReadReq_mshr_hits::cpu.data 778718 # number of ReadReq MSHR hits 655system.cpu.dcache.ReadReq_mshr_hits::total 778718 # number of ReadReq MSHR hits 656system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1821021 # number of WriteReq MSHR hits 657system.cpu.dcache.WriteReq_mshr_hits::total 1821021 # number of WriteReq MSHR hits 658system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 152 # number of WriteLineReq MSHR hits 659system.cpu.dcache.WriteLineReq_mshr_hits::total 152 # number of WriteLineReq MSHR hits 660system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 69509 # number of LoadLockedReq MSHR hits 661system.cpu.dcache.LoadLockedReq_mshr_hits::total 69509 # number of LoadLockedReq MSHR hits 662system.cpu.dcache.demand_mshr_hits::cpu.data 2599739 # number of demand (read+write) MSHR hits 663system.cpu.dcache.demand_mshr_hits::total 2599739 # number of demand (read+write) MSHR hits 664system.cpu.dcache.overall_mshr_hits::cpu.data 2599739 # number of overall MSHR hits 665system.cpu.dcache.overall_mshr_hits::total 2599739 # number of overall MSHR hits 666system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5586710 # number of ReadReq MSHR misses 667system.cpu.dcache.ReadReq_mshr_misses::total 5586710 # number of ReadReq MSHR misses 668system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2308640 # number of WriteReq MSHR misses 669system.cpu.dcache.WriteReq_mshr_misses::total 2308640 # number of WriteReq MSHR misses 670system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1391918 # number of SoftPFReq MSHR misses 671system.cpu.dcache.SoftPFReq_mshr_misses::total 1391918 # number of SoftPFReq MSHR misses 672system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1238799 # number of WriteLineReq MSHR misses 673system.cpu.dcache.WriteLineReq_mshr_misses::total 1238799 # number of WriteLineReq MSHR misses 674system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 241139 # number of LoadLockedReq MSHR misses 675system.cpu.dcache.LoadLockedReq_mshr_misses::total 241139 # number of LoadLockedReq MSHR misses 676system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses 677system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses 678system.cpu.dcache.demand_mshr_misses::cpu.data 7895350 # number of demand (read+write) MSHR misses 679system.cpu.dcache.demand_mshr_misses::total 7895350 # number of demand (read+write) MSHR misses 680system.cpu.dcache.overall_mshr_misses::cpu.data 9287268 # number of overall MSHR misses 681system.cpu.dcache.overall_mshr_misses::total 9287268 # number of overall MSHR misses 682system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable 683system.cpu.dcache.ReadReq_mshr_uncacheable::total 33697 # number of ReadReq MSHR uncacheable 684system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable 685system.cpu.dcache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable 686system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses 687system.cpu.dcache.overall_mshr_uncacheable_misses::total 67403 # number of overall MSHR uncacheable misses 688system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 95942539500 # number of ReadReq MSHR miss cycles 689system.cpu.dcache.ReadReq_mshr_miss_latency::total 95942539500 # number of ReadReq MSHR miss cycles 690system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 106127468000 # number of WriteReq MSHR miss cycles 691system.cpu.dcache.WriteReq_mshr_miss_latency::total 106127468000 # number of WriteReq MSHR miss cycles 692system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 26584469000 # number of SoftPFReq MSHR miss cycles 693system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 26584469000 # number of SoftPFReq MSHR miss cycles 694system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 83210863500 # number of WriteLineReq MSHR miss cycles 695system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 83210863500 # number of WriteLineReq MSHR miss cycles 696system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3483152500 # number of LoadLockedReq MSHR miss cycles 697system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3483152500 # number of LoadLockedReq MSHR miss cycles 698system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81000 # number of StoreCondReq MSHR miss cycles 699system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81000 # number of StoreCondReq MSHR miss cycles 700system.cpu.dcache.demand_mshr_miss_latency::cpu.data 202070007500 # number of demand (read+write) MSHR miss cycles 701system.cpu.dcache.demand_mshr_miss_latency::total 202070007500 # number of demand (read+write) MSHR miss cycles 702system.cpu.dcache.overall_mshr_miss_latency::cpu.data 228654476500 # number of overall MSHR miss cycles 703system.cpu.dcache.overall_mshr_miss_latency::total 228654476500 # number of overall MSHR miss cycles 704system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831192500 # number of ReadReq MSHR uncacheable cycles 705system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831192500 # number of ReadReq MSHR uncacheable cycles 706system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5820427500 # number of WriteReq MSHR uncacheable cycles 707system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5820427500 # number of WriteReq MSHR uncacheable cycles 708system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11651620000 # number of overall MSHR uncacheable cycles 709system.cpu.dcache.overall_mshr_uncacheable_latency::total 11651620000 # number of overall MSHR uncacheable cycles 710system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032810 # mshr miss rate for ReadReq accesses 711system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032810 # mshr miss rate for ReadReq accesses 712system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015234 # mshr miss rate for WriteReq accesses 713system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015234 # mshr miss rate for WriteReq accesses 714system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.728061 # mshr miss rate for SoftPFReq accesses 715system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.728061 # mshr miss rate for SoftPFReq accesses 716system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.786666 # mshr miss rate for WriteLineReq accesses 717system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.786666 # mshr miss rate for WriteLineReq accesses 718system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057931 # mshr miss rate for LoadLockedReq accesses 719system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057931 # mshr miss rate for LoadLockedReq accesses 720system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses 721system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses 722system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024534 # mshr miss rate for demand accesses 723system.cpu.dcache.demand_mshr_miss_rate::total 0.024534 # mshr miss rate for demand accesses 724system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028689 # mshr miss rate for overall accesses 725system.cpu.dcache.overall_mshr_miss_rate::total 0.028689 # mshr miss rate for overall accesses 726system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17173.352384 # average ReadReq mshr miss latency 727system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17173.352384 # average ReadReq mshr miss latency 728system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45969.691247 # average WriteReq mshr miss latency 729system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45969.691247 # average WriteReq mshr miss latency 730system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 19099.163169 # average SoftPFReq mshr miss latency 731system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 19099.163169 # average SoftPFReq mshr miss latency 732system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 67170.593050 # average WriteLineReq mshr miss latency 733system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 67170.593050 # average WriteLineReq mshr miss latency 734system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14444.583829 # average LoadLockedReq mshr miss latency 735system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14444.583829 # average LoadLockedReq mshr miss latency 736system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81000 # average StoreCondReq mshr miss latency 737system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81000 # average StoreCondReq mshr miss latency 738system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25593.546518 # average overall mshr miss latency 739system.cpu.dcache.demand_avg_mshr_miss_latency::total 25593.546518 # average overall mshr miss latency 740system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24620.208709 # average overall mshr miss latency 741system.cpu.dcache.overall_avg_mshr_miss_latency::total 24620.208709 # average overall mshr miss latency 742system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173047.823248 # average ReadReq mshr uncacheable latency 743system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173047.823248 # average ReadReq mshr uncacheable latency 744system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172682.237584 # average WriteReq mshr uncacheable latency 745system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172682.237584 # average WriteReq mshr uncacheable latency 746system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 172865.006009 # average overall mshr uncacheable latency 747system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 172865.006009 # average overall mshr uncacheable latency 748system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 749system.cpu.icache.tags.replacements 24130706 # number of replacements 750system.cpu.icache.tags.tagsinuse 511.872431 # Cycle average of tags in use 751system.cpu.icache.tags.total_refs 414285199 # Total number of references to valid blocks. 752system.cpu.icache.tags.sampled_refs 24131218 # Sample count of references to valid blocks. 753system.cpu.icache.tags.avg_refs 17.168019 # Average number of references to valid blocks. 754system.cpu.icache.tags.warmup_cycle 39477111500 # Cycle when the warmup percentage was hit. 755system.cpu.icache.tags.occ_blocks::cpu.inst 511.872431 # Average occupied blocks per requestor 756system.cpu.icache.tags.occ_percent::cpu.inst 0.999751 # Average percentage of cache occupancy 757system.cpu.icache.tags.occ_percent::total 0.999751 # Average percentage of cache occupancy 758system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 759system.cpu.icache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id 760system.cpu.icache.tags.age_task_id_blocks_1024::1 287 # Occupied blocks per task id 761system.cpu.icache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id 762system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 763system.cpu.icache.tags.tag_accesses 462547654 # Number of tag accesses 764system.cpu.icache.tags.data_accesses 462547654 # Number of data accesses 765system.cpu.icache.ReadReq_hits::cpu.inst 414285199 # number of ReadReq hits 766system.cpu.icache.ReadReq_hits::total 414285199 # number of ReadReq hits 767system.cpu.icache.demand_hits::cpu.inst 414285199 # number of demand (read+write) hits 768system.cpu.icache.demand_hits::total 414285199 # number of demand (read+write) hits 769system.cpu.icache.overall_hits::cpu.inst 414285199 # number of overall hits 770system.cpu.icache.overall_hits::total 414285199 # number of overall hits 771system.cpu.icache.ReadReq_misses::cpu.inst 24131228 # number of ReadReq misses 772system.cpu.icache.ReadReq_misses::total 24131228 # number of ReadReq misses 773system.cpu.icache.demand_misses::cpu.inst 24131228 # number of demand (read+write) misses 774system.cpu.icache.demand_misses::total 24131228 # number of demand (read+write) misses 775system.cpu.icache.overall_misses::cpu.inst 24131228 # number of overall misses 776system.cpu.icache.overall_misses::total 24131228 # number of overall misses 777system.cpu.icache.ReadReq_miss_latency::cpu.inst 326882606500 # number of ReadReq miss cycles 778system.cpu.icache.ReadReq_miss_latency::total 326882606500 # number of ReadReq miss cycles 779system.cpu.icache.demand_miss_latency::cpu.inst 326882606500 # number of demand (read+write) miss cycles 780system.cpu.icache.demand_miss_latency::total 326882606500 # number of demand (read+write) miss cycles 781system.cpu.icache.overall_miss_latency::cpu.inst 326882606500 # number of overall miss cycles 782system.cpu.icache.overall_miss_latency::total 326882606500 # number of overall miss cycles 783system.cpu.icache.ReadReq_accesses::cpu.inst 438416427 # number of ReadReq accesses(hits+misses) 784system.cpu.icache.ReadReq_accesses::total 438416427 # number of ReadReq accesses(hits+misses) 785system.cpu.icache.demand_accesses::cpu.inst 438416427 # number of demand (read+write) accesses 786system.cpu.icache.demand_accesses::total 438416427 # number of demand (read+write) accesses 787system.cpu.icache.overall_accesses::cpu.inst 438416427 # number of overall (read+write) accesses 788system.cpu.icache.overall_accesses::total 438416427 # number of overall (read+write) accesses 789system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.055042 # miss rate for ReadReq accesses 790system.cpu.icache.ReadReq_miss_rate::total 0.055042 # miss rate for ReadReq accesses 791system.cpu.icache.demand_miss_rate::cpu.inst 0.055042 # miss rate for demand accesses 792system.cpu.icache.demand_miss_rate::total 0.055042 # miss rate for demand accesses 793system.cpu.icache.overall_miss_rate::cpu.inst 0.055042 # miss rate for overall accesses 794system.cpu.icache.overall_miss_rate::total 0.055042 # miss rate for overall accesses 795system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13546.041109 # average ReadReq miss latency 796system.cpu.icache.ReadReq_avg_miss_latency::total 13546.041109 # average ReadReq miss latency 797system.cpu.icache.demand_avg_miss_latency::cpu.inst 13546.041109 # average overall miss latency 798system.cpu.icache.demand_avg_miss_latency::total 13546.041109 # average overall miss latency 799system.cpu.icache.overall_avg_miss_latency::cpu.inst 13546.041109 # average overall miss latency 800system.cpu.icache.overall_avg_miss_latency::total 13546.041109 # average overall miss latency 801system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 802system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 803system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 804system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 805system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 806system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 807system.cpu.icache.fast_writes 0 # number of fast writes performed 808system.cpu.icache.cache_copies 0 # number of cache copies performed 809system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24131228 # number of ReadReq MSHR misses 810system.cpu.icache.ReadReq_mshr_misses::total 24131228 # number of ReadReq MSHR misses 811system.cpu.icache.demand_mshr_misses::cpu.inst 24131228 # number of demand (read+write) MSHR misses 812system.cpu.icache.demand_mshr_misses::total 24131228 # number of demand (read+write) MSHR misses 813system.cpu.icache.overall_mshr_misses::cpu.inst 24131228 # number of overall MSHR misses 814system.cpu.icache.overall_mshr_misses::total 24131228 # number of overall MSHR misses 815system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52309 # number of ReadReq MSHR uncacheable 816system.cpu.icache.ReadReq_mshr_uncacheable::total 52309 # number of ReadReq MSHR uncacheable 817system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52309 # number of overall MSHR uncacheable misses 818system.cpu.icache.overall_mshr_uncacheable_misses::total 52309 # number of overall MSHR uncacheable misses 819system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 302751379500 # number of ReadReq MSHR miss cycles 820system.cpu.icache.ReadReq_mshr_miss_latency::total 302751379500 # number of ReadReq MSHR miss cycles 821system.cpu.icache.demand_mshr_miss_latency::cpu.inst 302751379500 # number of demand (read+write) MSHR miss cycles 822system.cpu.icache.demand_mshr_miss_latency::total 302751379500 # number of demand (read+write) MSHR miss cycles 823system.cpu.icache.overall_mshr_miss_latency::cpu.inst 302751379500 # number of overall MSHR miss cycles 824system.cpu.icache.overall_mshr_miss_latency::total 302751379500 # number of overall MSHR miss cycles 825system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6746821500 # number of ReadReq MSHR uncacheable cycles 826system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6746821500 # number of ReadReq MSHR uncacheable cycles 827system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6746821500 # number of overall MSHR uncacheable cycles 828system.cpu.icache.overall_mshr_uncacheable_latency::total 6746821500 # number of overall MSHR uncacheable cycles 829system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.055042 # mshr miss rate for ReadReq accesses 830system.cpu.icache.ReadReq_mshr_miss_rate::total 0.055042 # mshr miss rate for ReadReq accesses 831system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.055042 # mshr miss rate for demand accesses 832system.cpu.icache.demand_mshr_miss_rate::total 0.055042 # mshr miss rate for demand accesses 833system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.055042 # mshr miss rate for overall accesses 834system.cpu.icache.overall_mshr_miss_rate::total 0.055042 # mshr miss rate for overall accesses 835system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12546.041150 # average ReadReq mshr miss latency 836system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12546.041150 # average ReadReq mshr miss latency 837system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12546.041150 # average overall mshr miss latency 838system.cpu.icache.demand_avg_mshr_miss_latency::total 12546.041150 # average overall mshr miss latency 839system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12546.041150 # average overall mshr miss latency 840system.cpu.icache.overall_avg_mshr_miss_latency::total 12546.041150 # average overall mshr miss latency 841system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 128980.127703 # average ReadReq mshr uncacheable latency 842system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 128980.127703 # average ReadReq mshr uncacheable latency 843system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 128980.127703 # average overall mshr uncacheable latency 844system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 128980.127703 # average overall mshr uncacheable latency 845system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 846system.cpu.l2cache.tags.replacements 1490067 # number of replacements 847system.cpu.l2cache.tags.tagsinuse 65247.296250 # Cycle average of tags in use 848system.cpu.l2cache.tags.total_refs 65785634 # Total number of references to valid blocks. 849system.cpu.l2cache.tags.sampled_refs 1553186 # Sample count of references to valid blocks. 850system.cpu.l2cache.tags.avg_refs 42.355284 # Average number of references to valid blocks. 851system.cpu.l2cache.tags.warmup_cycle 36608904000 # Cycle when the warmup percentage was hit. 852system.cpu.l2cache.tags.occ_blocks::writebacks 37009.506114 # Average occupied blocks per requestor 853system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 327.357473 # Average occupied blocks per requestor 854system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 390.452800 # Average occupied blocks per requestor 855system.cpu.l2cache.tags.occ_blocks::cpu.inst 8008.475299 # Average occupied blocks per requestor 856system.cpu.l2cache.tags.occ_blocks::cpu.data 19511.504564 # Average occupied blocks per requestor 857system.cpu.l2cache.tags.occ_percent::writebacks 0.564720 # Average percentage of cache occupancy 858system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004995 # Average percentage of cache occupancy 859system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.005958 # Average percentage of cache occupancy 860system.cpu.l2cache.tags.occ_percent::cpu.inst 0.122200 # Average percentage of cache occupancy 861system.cpu.l2cache.tags.occ_percent::cpu.data 0.297722 # Average percentage of cache occupancy 862system.cpu.l2cache.tags.occ_percent::total 0.995595 # Average percentage of cache occupancy 863system.cpu.l2cache.tags.occ_task_id_blocks::1023 261 # Occupied blocks per task id 864system.cpu.l2cache.tags.occ_task_id_blocks::1024 62858 # Occupied blocks per task id 865system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id 866system.cpu.l2cache.tags.age_task_id_blocks_1023::4 260 # Occupied blocks per task id 867system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 868system.cpu.l2cache.tags.age_task_id_blocks_1024::1 534 # Occupied blocks per task id 869system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2399 # Occupied blocks per task id 870system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5570 # Occupied blocks per task id 871system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54303 # Occupied blocks per task id 872system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003983 # Percentage of cache occupancy per task id 873system.cpu.l2cache.tags.occ_task_id_percent::1024 0.959137 # Percentage of cache occupancy per task id 874system.cpu.l2cache.tags.tag_accesses 572783914 # Number of tag accesses 875system.cpu.l2cache.tags.data_accesses 572783914 # Number of data accesses 876system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 922401 # number of ReadReq hits 877system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 283446 # number of ReadReq hits 878system.cpu.l2cache.ReadReq_hits::total 1205847 # number of ReadReq hits 879system.cpu.l2cache.Writeback_hits::writebacks 8229800 # number of Writeback hits 880system.cpu.l2cache.Writeback_hits::total 8229800 # number of Writeback hits 881system.cpu.l2cache.UpgradeReq_hits::cpu.data 10447 # number of UpgradeReq hits 882system.cpu.l2cache.UpgradeReq_hits::total 10447 # number of UpgradeReq hits 883system.cpu.l2cache.ReadExReq_hits::cpu.data 1641162 # number of ReadExReq hits 884system.cpu.l2cache.ReadExReq_hits::total 1641162 # number of ReadExReq hits 885system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24023948 # number of ReadCleanReq hits 886system.cpu.l2cache.ReadCleanReq_hits::total 24023948 # number of ReadCleanReq hits 887system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6905333 # number of ReadSharedReq hits 888system.cpu.l2cache.ReadSharedReq_hits::total 6905333 # number of ReadSharedReq hits 889system.cpu.l2cache.InvalidateReq_hits::cpu.data 707969 # number of InvalidateReq hits 890system.cpu.l2cache.InvalidateReq_hits::total 707969 # number of InvalidateReq hits 891system.cpu.l2cache.demand_hits::cpu.dtb.walker 922401 # number of demand (read+write) hits 892system.cpu.l2cache.demand_hits::cpu.itb.walker 283446 # number of demand (read+write) hits 893system.cpu.l2cache.demand_hits::cpu.inst 24023948 # number of demand (read+write) hits 894system.cpu.l2cache.demand_hits::cpu.data 8546495 # number of demand (read+write) hits 895system.cpu.l2cache.demand_hits::total 33776290 # number of demand (read+write) hits 896system.cpu.l2cache.overall_hits::cpu.dtb.walker 922401 # number of overall hits 897system.cpu.l2cache.overall_hits::cpu.itb.walker 283446 # number of overall hits 898system.cpu.l2cache.overall_hits::cpu.inst 24023948 # number of overall hits 899system.cpu.l2cache.overall_hits::cpu.data 8546495 # number of overall hits 900system.cpu.l2cache.overall_hits::total 33776290 # number of overall hits 901system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5566 # number of ReadReq misses 902system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 4603 # number of ReadReq misses 903system.cpu.l2cache.ReadReq_misses::total 10169 # number of ReadReq misses 904system.cpu.l2cache.UpgradeReq_misses::cpu.data 37678 # number of UpgradeReq misses 905system.cpu.l2cache.UpgradeReq_misses::total 37678 # number of UpgradeReq misses 906system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses 907system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses 908system.cpu.l2cache.ReadExReq_misses::cpu.data 619608 # number of ReadExReq misses 909system.cpu.l2cache.ReadExReq_misses::total 619608 # number of ReadExReq misses 910system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 107277 # number of ReadCleanReq misses 911system.cpu.l2cache.ReadCleanReq_misses::total 107277 # number of ReadCleanReq misses 912system.cpu.l2cache.ReadSharedReq_misses::cpu.data 314179 # number of ReadSharedReq misses 913system.cpu.l2cache.ReadSharedReq_misses::total 314179 # number of ReadSharedReq misses 914system.cpu.l2cache.InvalidateReq_misses::cpu.data 530830 # number of InvalidateReq misses 915system.cpu.l2cache.InvalidateReq_misses::total 530830 # number of InvalidateReq misses 916system.cpu.l2cache.demand_misses::cpu.dtb.walker 5566 # number of demand (read+write) misses 917system.cpu.l2cache.demand_misses::cpu.itb.walker 4603 # number of demand (read+write) misses 918system.cpu.l2cache.demand_misses::cpu.inst 107277 # number of demand (read+write) misses 919system.cpu.l2cache.demand_misses::cpu.data 933787 # number of demand (read+write) misses 920system.cpu.l2cache.demand_misses::total 1051233 # number of demand (read+write) misses 921system.cpu.l2cache.overall_misses::cpu.dtb.walker 5566 # number of overall misses 922system.cpu.l2cache.overall_misses::cpu.itb.walker 4603 # number of overall misses 923system.cpu.l2cache.overall_misses::cpu.inst 107277 # number of overall misses 924system.cpu.l2cache.overall_misses::cpu.data 933787 # number of overall misses 925system.cpu.l2cache.overall_misses::total 1051233 # number of overall misses 926system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 762054000 # number of ReadReq miss cycles 927system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 629329000 # number of ReadReq miss cycles 928system.cpu.l2cache.ReadReq_miss_latency::total 1391383000 # number of ReadReq miss cycles 929system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1497567500 # number of UpgradeReq miss cycles 930system.cpu.l2cache.UpgradeReq_miss_latency::total 1497567500 # number of UpgradeReq miss cycles 931system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 79500 # number of SCUpgradeReq miss cycles 932system.cpu.l2cache.SCUpgradeReq_miss_latency::total 79500 # number of SCUpgradeReq miss cycles 933system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 82257791500 # number of ReadExReq miss cycles 934system.cpu.l2cache.ReadExReq_miss_latency::total 82257791500 # number of ReadExReq miss cycles 935system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 14189953500 # number of ReadCleanReq miss cycles 936system.cpu.l2cache.ReadCleanReq_miss_latency::total 14189953500 # number of ReadCleanReq miss cycles 937system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 42401108000 # number of ReadSharedReq miss cycles 938system.cpu.l2cache.ReadSharedReq_miss_latency::total 42401108000 # number of ReadSharedReq miss cycles 939system.cpu.l2cache.InvalidateReq_miss_latency::cpu.data 73652413000 # number of InvalidateReq miss cycles 940system.cpu.l2cache.InvalidateReq_miss_latency::total 73652413000 # number of InvalidateReq miss cycles 941system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 762054000 # number of demand (read+write) miss cycles 942system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 629329000 # number of demand (read+write) miss cycles 943system.cpu.l2cache.demand_miss_latency::cpu.inst 14189953500 # number of demand (read+write) miss cycles 944system.cpu.l2cache.demand_miss_latency::cpu.data 124658899500 # number of demand (read+write) miss cycles 945system.cpu.l2cache.demand_miss_latency::total 140240236000 # number of demand (read+write) miss cycles 946system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 762054000 # number of overall miss cycles 947system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 629329000 # number of overall miss cycles 948system.cpu.l2cache.overall_miss_latency::cpu.inst 14189953500 # number of overall miss cycles 949system.cpu.l2cache.overall_miss_latency::cpu.data 124658899500 # number of overall miss cycles 950system.cpu.l2cache.overall_miss_latency::total 140240236000 # number of overall miss cycles 951system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 927967 # number of ReadReq accesses(hits+misses) 952system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 288049 # number of ReadReq accesses(hits+misses) 953system.cpu.l2cache.ReadReq_accesses::total 1216016 # number of ReadReq accesses(hits+misses) 954system.cpu.l2cache.Writeback_accesses::writebacks 8229800 # number of Writeback accesses(hits+misses) 955system.cpu.l2cache.Writeback_accesses::total 8229800 # number of Writeback accesses(hits+misses) 956system.cpu.l2cache.UpgradeReq_accesses::cpu.data 48125 # number of UpgradeReq accesses(hits+misses) 957system.cpu.l2cache.UpgradeReq_accesses::total 48125 # number of UpgradeReq accesses(hits+misses) 958system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 959system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) 960system.cpu.l2cache.ReadExReq_accesses::cpu.data 2260770 # number of ReadExReq accesses(hits+misses) 961system.cpu.l2cache.ReadExReq_accesses::total 2260770 # number of ReadExReq accesses(hits+misses) 962system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 24131225 # number of ReadCleanReq accesses(hits+misses) 963system.cpu.l2cache.ReadCleanReq_accesses::total 24131225 # number of ReadCleanReq accesses(hits+misses) 964system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7219512 # number of ReadSharedReq accesses(hits+misses) 965system.cpu.l2cache.ReadSharedReq_accesses::total 7219512 # number of ReadSharedReq accesses(hits+misses) 966system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1238799 # number of InvalidateReq accesses(hits+misses) 967system.cpu.l2cache.InvalidateReq_accesses::total 1238799 # number of InvalidateReq accesses(hits+misses) 968system.cpu.l2cache.demand_accesses::cpu.dtb.walker 927967 # number of demand (read+write) accesses 969system.cpu.l2cache.demand_accesses::cpu.itb.walker 288049 # number of demand (read+write) accesses 970system.cpu.l2cache.demand_accesses::cpu.inst 24131225 # number of demand (read+write) accesses 971system.cpu.l2cache.demand_accesses::cpu.data 9480282 # number of demand (read+write) accesses 972system.cpu.l2cache.demand_accesses::total 34827523 # number of demand (read+write) accesses 973system.cpu.l2cache.overall_accesses::cpu.dtb.walker 927967 # number of overall (read+write) accesses 974system.cpu.l2cache.overall_accesses::cpu.itb.walker 288049 # number of overall (read+write) accesses 975system.cpu.l2cache.overall_accesses::cpu.inst 24131225 # number of overall (read+write) accesses 976system.cpu.l2cache.overall_accesses::cpu.data 9480282 # number of overall (read+write) accesses 977system.cpu.l2cache.overall_accesses::total 34827523 # number of overall (read+write) accesses 978system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.005998 # miss rate for ReadReq accesses 979system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.015980 # miss rate for ReadReq accesses 980system.cpu.l2cache.ReadReq_miss_rate::total 0.008363 # miss rate for ReadReq accesses 981system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.782919 # miss rate for UpgradeReq accesses 982system.cpu.l2cache.UpgradeReq_miss_rate::total 0.782919 # miss rate for UpgradeReq accesses 983system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses 984system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 985system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.274069 # miss rate for ReadExReq accesses 986system.cpu.l2cache.ReadExReq_miss_rate::total 0.274069 # miss rate for ReadExReq accesses 987system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.004446 # miss rate for ReadCleanReq accesses 988system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.004446 # miss rate for ReadCleanReq accesses 989system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.043518 # miss rate for ReadSharedReq accesses 990system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.043518 # miss rate for ReadSharedReq accesses 991system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.428504 # miss rate for InvalidateReq accesses 992system.cpu.l2cache.InvalidateReq_miss_rate::total 0.428504 # miss rate for InvalidateReq accesses 993system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.005998 # miss rate for demand accesses 994system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.015980 # miss rate for demand accesses 995system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004446 # miss rate for demand accesses 996system.cpu.l2cache.demand_miss_rate::cpu.data 0.098498 # miss rate for demand accesses 997system.cpu.l2cache.demand_miss_rate::total 0.030184 # miss rate for demand accesses 998system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.005998 # miss rate for overall accesses 999system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.015980 # miss rate for overall accesses 1000system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004446 # miss rate for overall accesses 1001system.cpu.l2cache.overall_miss_rate::cpu.data 0.098498 # miss rate for overall accesses 1002system.cpu.l2cache.overall_miss_rate::total 0.030184 # miss rate for overall accesses 1003system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 136912.324829 # average ReadReq miss latency 1004system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 136721.485987 # average ReadReq miss latency 1005system.cpu.l2cache.ReadReq_avg_miss_latency::total 136825.941587 # average ReadReq miss latency 1006system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 39746.470089 # average UpgradeReq miss latency 1007system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 39746.470089 # average UpgradeReq miss latency 1008system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency 1009system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency 1010system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 132757.794444 # average ReadExReq miss latency 1011system.cpu.l2cache.ReadExReq_avg_miss_latency::total 132757.794444 # average ReadExReq miss latency 1012system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 132273.959003 # average ReadCleanReq miss latency 1013system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 132273.959003 # average ReadCleanReq miss latency 1014system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 134958.440889 # average ReadSharedReq miss latency 1015system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 134958.440889 # average ReadSharedReq miss latency 1016system.cpu.l2cache.InvalidateReq_avg_miss_latency::cpu.data 138749.529981 # average InvalidateReq miss latency 1017system.cpu.l2cache.InvalidateReq_avg_miss_latency::total 138749.529981 # average InvalidateReq miss latency 1018system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 136912.324829 # average overall miss latency 1019system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 136721.485987 # average overall miss latency 1020system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 132273.959003 # average overall miss latency 1021system.cpu.l2cache.demand_avg_miss_latency::cpu.data 133498.216938 # average overall miss latency 1022system.cpu.l2cache.demand_avg_miss_latency::total 133405.473382 # average overall miss latency 1023system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 136912.324829 # average overall miss latency 1024system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 136721.485987 # average overall miss latency 1025system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 132273.959003 # average overall miss latency 1026system.cpu.l2cache.overall_avg_miss_latency::cpu.data 133498.216938 # average overall miss latency 1027system.cpu.l2cache.overall_avg_miss_latency::total 133405.473382 # average overall miss latency 1028system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1029system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1030system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1031system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1032system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1033system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1034system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1035system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1036system.cpu.l2cache.writebacks::writebacks 1259612 # number of writebacks 1037system.cpu.l2cache.writebacks::total 1259612 # number of writebacks 1038system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 3 # number of ReadCleanReq MSHR hits 1039system.cpu.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits 1040system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 21 # number of ReadSharedReq MSHR hits 1041system.cpu.l2cache.ReadSharedReq_mshr_hits::total 21 # number of ReadSharedReq MSHR hits 1042system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits 1043system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits 1044system.cpu.l2cache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits 1045system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits 1046system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits 1047system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits 1048system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5566 # number of ReadReq MSHR misses 1049system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 4603 # number of ReadReq MSHR misses 1050system.cpu.l2cache.ReadReq_mshr_misses::total 10169 # number of ReadReq MSHR misses 1051system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1098 # number of CleanEvict MSHR misses 1052system.cpu.l2cache.CleanEvict_mshr_misses::total 1098 # number of CleanEvict MSHR misses 1053system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 37678 # number of UpgradeReq MSHR misses 1054system.cpu.l2cache.UpgradeReq_mshr_misses::total 37678 # number of UpgradeReq MSHR misses 1055system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses 1056system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses 1057system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 619608 # number of ReadExReq MSHR misses 1058system.cpu.l2cache.ReadExReq_mshr_misses::total 619608 # number of ReadExReq MSHR misses 1059system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 107274 # number of ReadCleanReq MSHR misses 1060system.cpu.l2cache.ReadCleanReq_mshr_misses::total 107274 # number of ReadCleanReq MSHR misses 1061system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 314158 # number of ReadSharedReq MSHR misses 1062system.cpu.l2cache.ReadSharedReq_mshr_misses::total 314158 # number of ReadSharedReq MSHR misses 1063system.cpu.l2cache.InvalidateReq_mshr_misses::cpu.data 530830 # number of InvalidateReq MSHR misses 1064system.cpu.l2cache.InvalidateReq_mshr_misses::total 530830 # number of InvalidateReq MSHR misses 1065system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5566 # number of demand (read+write) MSHR misses 1066system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 4603 # number of demand (read+write) MSHR misses 1067system.cpu.l2cache.demand_mshr_misses::cpu.inst 107274 # number of demand (read+write) MSHR misses 1068system.cpu.l2cache.demand_mshr_misses::cpu.data 933766 # number of demand (read+write) MSHR misses 1069system.cpu.l2cache.demand_mshr_misses::total 1051209 # number of demand (read+write) MSHR misses 1070system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5566 # number of overall MSHR misses 1071system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4603 # number of overall MSHR misses 1072system.cpu.l2cache.overall_mshr_misses::cpu.inst 107274 # number of overall MSHR misses 1073system.cpu.l2cache.overall_mshr_misses::cpu.data 933766 # number of overall MSHR misses 1074system.cpu.l2cache.overall_mshr_misses::total 1051209 # number of overall MSHR misses 1075system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 52309 # number of ReadReq MSHR uncacheable 1076system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33697 # number of ReadReq MSHR uncacheable 1077system.cpu.l2cache.ReadReq_mshr_uncacheable::total 86006 # number of ReadReq MSHR uncacheable 1078system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33706 # number of WriteReq MSHR uncacheable 1079system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33706 # number of WriteReq MSHR uncacheable 1080system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 52309 # number of overall MSHR uncacheable misses 1081system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67403 # number of overall MSHR uncacheable misses 1082system.cpu.l2cache.overall_mshr_uncacheable_misses::total 119712 # number of overall MSHR uncacheable misses 1083system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 706394000 # number of ReadReq MSHR miss cycles 1084system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 583299000 # number of ReadReq MSHR miss cycles 1085system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1289693000 # number of ReadReq MSHR miss cycles 1086system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 2666012000 # number of UpgradeReq MSHR miss cycles 1087system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 2666012000 # number of UpgradeReq MSHR miss cycles 1088system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 69500 # number of SCUpgradeReq MSHR miss cycles 1089system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 69500 # number of SCUpgradeReq MSHR miss cycles 1090system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 76061711500 # number of ReadExReq MSHR miss cycles 1091system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 76061711500 # number of ReadExReq MSHR miss cycles 1092system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 13116951000 # number of ReadCleanReq MSHR miss cycles 1093system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 13116951000 # number of ReadCleanReq MSHR miss cycles 1094system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 39257197500 # number of ReadSharedReq MSHR miss cycles 1095system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 39257197500 # number of ReadSharedReq MSHR miss cycles 1096system.cpu.l2cache.InvalidateReq_mshr_miss_latency::cpu.data 68344113000 # number of InvalidateReq MSHR miss cycles 1097system.cpu.l2cache.InvalidateReq_mshr_miss_latency::total 68344113000 # number of InvalidateReq MSHR miss cycles 1098system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 706394000 # number of demand (read+write) MSHR miss cycles 1099system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 583299000 # number of demand (read+write) MSHR miss cycles 1100system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13116951000 # number of demand (read+write) MSHR miss cycles 1101system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115318909000 # number of demand (read+write) MSHR miss cycles 1102system.cpu.l2cache.demand_mshr_miss_latency::total 129725553000 # number of demand (read+write) MSHR miss cycles 1103system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 706394000 # number of overall MSHR miss cycles 1104system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 583299000 # number of overall MSHR miss cycles 1105system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13116951000 # number of overall MSHR miss cycles 1106system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115318909000 # number of overall MSHR miss cycles 1107system.cpu.l2cache.overall_mshr_miss_latency::total 129725553000 # number of overall MSHR miss cycles 1108system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5936031500 # number of ReadReq MSHR uncacheable cycles 1109system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5409917000 # number of ReadReq MSHR uncacheable cycles 1110system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 11345948500 # number of ReadReq MSHR uncacheable cycles 1111system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5432186500 # number of WriteReq MSHR uncacheable cycles 1112system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5432186500 # number of WriteReq MSHR uncacheable cycles 1113system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 5936031500 # number of overall MSHR uncacheable cycles 1114system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10842103500 # number of overall MSHR uncacheable cycles 1115system.cpu.l2cache.overall_mshr_uncacheable_latency::total 16778135000 # number of overall MSHR uncacheable cycles 1116system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.005998 # mshr miss rate for ReadReq accesses 1117system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.015980 # mshr miss rate for ReadReq accesses 1118system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.008363 # mshr miss rate for ReadReq accesses 1119system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1120system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1121system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.782919 # mshr miss rate for UpgradeReq accesses 1122system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782919 # mshr miss rate for UpgradeReq accesses 1123system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1124system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1125system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.274069 # mshr miss rate for ReadExReq accesses 1126system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.274069 # mshr miss rate for ReadExReq accesses 1127system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004445 # mshr miss rate for ReadCleanReq accesses 1128system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004445 # mshr miss rate for ReadCleanReq accesses 1129system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043515 # mshr miss rate for ReadSharedReq accesses 1130system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043515 # mshr miss rate for ReadSharedReq accesses 1131system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.428504 # mshr miss rate for InvalidateReq accesses 1132system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.428504 # mshr miss rate for InvalidateReq accesses 1133system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.005998 # mshr miss rate for demand accesses 1134system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.015980 # mshr miss rate for demand accesses 1135system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004445 # mshr miss rate for demand accesses 1136system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.098496 # mshr miss rate for demand accesses 1137system.cpu.l2cache.demand_mshr_miss_rate::total 0.030183 # mshr miss rate for demand accesses 1138system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.005998 # mshr miss rate for overall accesses 1139system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.015980 # mshr miss rate for overall accesses 1140system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004445 # mshr miss rate for overall accesses 1141system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.098496 # mshr miss rate for overall accesses 1142system.cpu.l2cache.overall_mshr_miss_rate::total 0.030183 # mshr miss rate for overall accesses 1143system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 126912.324829 # average ReadReq mshr miss latency 1144system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 126721.485987 # average ReadReq mshr miss latency 1145system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 126825.941587 # average ReadReq mshr miss latency 1146system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 70757.789692 # average UpgradeReq mshr miss latency 1147system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 70757.789692 # average UpgradeReq mshr miss latency 1148system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 69500 # average SCUpgradeReq mshr miss latency 1149system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 69500 # average SCUpgradeReq mshr miss latency 1150system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 122757.794444 # average ReadExReq mshr miss latency 1151system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 122757.794444 # average ReadExReq mshr miss latency 1152system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 122275.211142 # average ReadCleanReq mshr miss latency 1153system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 122275.211142 # average ReadCleanReq mshr miss latency 1154system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 124960.043991 # average ReadSharedReq mshr miss latency 1155system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 124960.043991 # average ReadSharedReq mshr miss latency 1156system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 128749.529981 # average InvalidateReq mshr miss latency 1157system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 128749.529981 # average InvalidateReq mshr miss latency 1158system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 126912.324829 # average overall mshr miss latency 1159system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 126721.485987 # average overall mshr miss latency 1160system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 122275.211142 # average overall mshr miss latency 1161system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 123498.723449 # average overall mshr miss latency 1162system.cpu.l2cache.demand_avg_mshr_miss_latency::total 123406.052460 # average overall mshr miss latency 1163system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 126912.324829 # average overall mshr miss latency 1164system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 126721.485987 # average overall mshr miss latency 1165system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 122275.211142 # average overall mshr miss latency 1166system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 123498.723449 # average overall mshr miss latency 1167system.cpu.l2cache.overall_avg_mshr_miss_latency::total 123406.052460 # average overall mshr miss latency 1168system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113480.118144 # average ReadReq mshr uncacheable latency 1169system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 160545.953646 # average ReadReq mshr uncacheable latency 1170system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 131920.429970 # average ReadReq mshr uncacheable latency 1171system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 161163.783896 # average WriteReq mshr uncacheable latency 1172system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161163.783896 # average WriteReq mshr uncacheable latency 1173system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113480.118144 # average overall mshr uncacheable latency 1174system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 160854.910019 # average overall mshr uncacheable latency 1175system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 140154.161655 # average overall mshr uncacheable latency 1176system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1177system.cpu.toL2Bus.snoop_filter.tot_requests 70442734 # Total number of requests made to the snoop filter. 1178system.cpu.toL2Bus.snoop_filter.hit_single_requests 35592438 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1179system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4386 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1180system.cpu.toL2Bus.snoop_filter.tot_snoops 2280 # Total number of snoops made to the snoop filter. 1181system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2280 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1182system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1183system.cpu.toL2Bus.trans_dist::ReadReq 1728553 # Transaction distribution 1184system.cpu.toL2Bus.trans_dist::ReadResp 33080077 # Transaction distribution 1185system.cpu.toL2Bus.trans_dist::WriteReq 33706 # Transaction distribution 1186system.cpu.toL2Bus.trans_dist::WriteResp 33706 # Transaction distribution 1187system.cpu.toL2Bus.trans_dist::Writeback 9596069 # Transaction distribution 1188system.cpu.toL2Bus.trans_dist::CleanEvict 26854364 # Transaction distribution 1189system.cpu.toL2Bus.trans_dist::UpgradeReq 48128 # Transaction distribution 1190system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution 1191system.cpu.toL2Bus.trans_dist::UpgradeResp 48129 # Transaction distribution 1192system.cpu.toL2Bus.trans_dist::ReadExReq 2260770 # Transaction distribution 1193system.cpu.toL2Bus.trans_dist::ReadExResp 2260770 # Transaction distribution 1194system.cpu.toL2Bus.trans_dist::ReadCleanReq 24131228 # Transaction distribution 1195system.cpu.toL2Bus.trans_dist::ReadSharedReq 7228389 # Transaction distribution 1196system.cpu.toL2Bus.trans_dist::InvalidateReq 1345463 # Transaction distribution 1197system.cpu.toL2Bus.trans_dist::InvalidateResp 1238799 # Transaction distribution 1198system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 72494093 # Packet count per connected master and slave (bytes) 1199system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32387839 # Packet count per connected master and slave (bytes) 1200system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 691084 # Packet count per connected master and slave (bytes) 1201system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2167479 # Packet count per connected master and slave (bytes) 1202system.cpu.toL2Bus.pkt_count::total 107740495 # Packet count per connected master and slave (bytes) 1203system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1547746112 # Cumulative packet size per connected master and slave (bytes) 1204system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1133685906 # Cumulative packet size per connected master and slave (bytes) 1205system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2304392 # Cumulative packet size per connected master and slave (bytes) 1206system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7423736 # Cumulative packet size per connected master and slave (bytes) 1207system.cpu.toL2Bus.pkt_size::total 2691160146 # Cumulative packet size per connected master and slave (bytes) 1208system.cpu.toL2Bus.snoops 2148445 # Total snoops (count) 1209system.cpu.toL2Bus.snoop_fanout::samples 73231054 # Request fanout histogram 1210system.cpu.toL2Bus.snoop_fanout::mean 0.009642 # Request fanout histogram 1211system.cpu.toL2Bus.snoop_fanout::stdev 0.097721 # Request fanout histogram 1212system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1213system.cpu.toL2Bus.snoop_fanout::0 72524927 99.04% 99.04% # Request fanout histogram 1214system.cpu.toL2Bus.snoop_fanout::1 706127 0.96% 100.00% # Request fanout histogram 1215system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1216system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1217system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1218system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1219system.cpu.toL2Bus.snoop_fanout::total 73231054 # Request fanout histogram 1220system.cpu.toL2Bus.reqLayer0.occupancy 44001619997 # Layer occupancy (ticks) 1221system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1222system.cpu.toL2Bus.snoopLayer0.occupancy 1484887 # Layer occupancy (ticks) 1223system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1224system.cpu.toL2Bus.respLayer0.occupancy 36281501081 # Layer occupancy (ticks) 1225system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1226system.cpu.toL2Bus.respLayer1.occupancy 14914900069 # Layer occupancy (ticks) 1227system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1228system.cpu.toL2Bus.respLayer2.occupancy 403060948 # Layer occupancy (ticks) 1229system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1230system.cpu.toL2Bus.respLayer3.occupancy 1239526970 # Layer occupancy (ticks) 1231system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1232system.iobus.trans_dist::ReadReq 40325 # Transaction distribution 1233system.iobus.trans_dist::ReadResp 40325 # Transaction distribution 1234system.iobus.trans_dist::WriteReq 136571 # Transaction distribution 1235system.iobus.trans_dist::WriteResp 136571 # Transaction distribution 1236system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) 1237system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1238system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1239system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1240system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1241system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1242system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1243system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1244system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1245system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1246system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 1247system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 1248system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1249system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 1250system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 1251system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) 1252system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231008 # Packet count per connected master and slave (bytes) 1253system.iobus.pkt_count_system.realview.ide.dma::total 231008 # Packet count per connected master and slave (bytes) 1254system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1255system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 1256system.iobus.pkt_count::total 353792 # Packet count per connected master and slave (bytes) 1257system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) 1258system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1259system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1260system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1261system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1262system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1263system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1264system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1265system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1266system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1267system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 1268system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 1269system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1270system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 1271system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 1272system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) 1273system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334464 # Cumulative packet size per connected master and slave (bytes) 1274system.iobus.pkt_size_system.realview.ide.dma::total 7334464 # Cumulative packet size per connected master and slave (bytes) 1275system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1276system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 1277system.iobus.pkt_size::total 7492384 # Cumulative packet size per connected master and slave (bytes) 1278system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) 1279system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1280system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 1281system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1282system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 1283system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1284system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 1285system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1286system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 1287system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1288system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 1289system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1290system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 1291system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1292system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 1293system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1294system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 1295system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1296system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 1297system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1298system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) 1299system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1300system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 1301system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1302system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 1303system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1304system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 1305system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 1306system.iobus.reqLayer27.occupancy 565802629 # Layer occupancy (ticks) 1307system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 1308system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 1309system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 1310system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) 1311system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1312system.iobus.respLayer3.occupancy 147768000 # Layer occupancy (ticks) 1313system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1314system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 1315system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 1316system.iocache.tags.replacements 115486 # number of replacements 1317system.iocache.tags.tagsinuse 10.440024 # Cycle average of tags in use 1318system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 1319system.iocache.tags.sampled_refs 115502 # Sample count of references to valid blocks. 1320system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1321system.iocache.tags.warmup_cycle 13160095292000 # Cycle when the warmup percentage was hit. 1322system.iocache.tags.occ_blocks::realview.ethernet 3.520841 # Average occupied blocks per requestor 1323system.iocache.tags.occ_blocks::realview.ide 6.919182 # Average occupied blocks per requestor 1324system.iocache.tags.occ_percent::realview.ethernet 0.220053 # Average percentage of cache occupancy 1325system.iocache.tags.occ_percent::realview.ide 0.432449 # Average percentage of cache occupancy 1326system.iocache.tags.occ_percent::total 0.652501 # Average percentage of cache occupancy 1327system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1328system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1329system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1330system.iocache.tags.tag_accesses 1039893 # Number of tag accesses 1331system.iocache.tags.data_accesses 1039893 # Number of data accesses 1332system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1333system.iocache.ReadReq_misses::realview.ide 8840 # number of ReadReq misses 1334system.iocache.ReadReq_misses::total 8877 # number of ReadReq misses 1335system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1336system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1337system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1338system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1339system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 1340system.iocache.demand_misses::realview.ide 8840 # number of demand (read+write) misses 1341system.iocache.demand_misses::total 8880 # number of demand (read+write) misses 1342system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 1343system.iocache.overall_misses::realview.ide 8840 # number of overall misses 1344system.iocache.overall_misses::total 8880 # number of overall misses 1345system.iocache.ReadReq_miss_latency::realview.ethernet 5069000 # number of ReadReq miss cycles 1346system.iocache.ReadReq_miss_latency::realview.ide 1641330150 # number of ReadReq miss cycles 1347system.iocache.ReadReq_miss_latency::total 1646399150 # number of ReadReq miss cycles 1348system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 1349system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 1350system.iocache.WriteLineReq_miss_latency::realview.ide 13825092479 # number of WriteLineReq miss cycles 1351system.iocache.WriteLineReq_miss_latency::total 13825092479 # number of WriteLineReq miss cycles 1352system.iocache.demand_miss_latency::realview.ethernet 5420000 # number of demand (read+write) miss cycles 1353system.iocache.demand_miss_latency::realview.ide 1641330150 # number of demand (read+write) miss cycles 1354system.iocache.demand_miss_latency::total 1646750150 # number of demand (read+write) miss cycles 1355system.iocache.overall_miss_latency::realview.ethernet 5420000 # number of overall miss cycles 1356system.iocache.overall_miss_latency::realview.ide 1641330150 # number of overall miss cycles 1357system.iocache.overall_miss_latency::total 1646750150 # number of overall miss cycles 1358system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1359system.iocache.ReadReq_accesses::realview.ide 8840 # number of ReadReq accesses(hits+misses) 1360system.iocache.ReadReq_accesses::total 8877 # number of ReadReq accesses(hits+misses) 1361system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1362system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1363system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 1364system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 1365system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 1366system.iocache.demand_accesses::realview.ide 8840 # number of demand (read+write) accesses 1367system.iocache.demand_accesses::total 8880 # number of demand (read+write) accesses 1368system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 1369system.iocache.overall_accesses::realview.ide 8840 # number of overall (read+write) accesses 1370system.iocache.overall_accesses::total 8880 # number of overall (read+write) accesses 1371system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1372system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1373system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1374system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1375system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1376system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1377system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1378system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1379system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1380system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1381system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1382system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1383system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1384system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137000 # average ReadReq miss latency 1385system.iocache.ReadReq_avg_miss_latency::realview.ide 185670.831448 # average ReadReq miss latency 1386system.iocache.ReadReq_avg_miss_latency::total 185467.967782 # average ReadReq miss latency 1387system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 1388system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 1389system.iocache.WriteLineReq_avg_miss_latency::realview.ide 129613.482328 # average WriteLineReq miss latency 1390system.iocache.WriteLineReq_avg_miss_latency::total 129613.482328 # average WriteLineReq miss latency 1391system.iocache.demand_avg_miss_latency::realview.ethernet 135500 # average overall miss latency 1392system.iocache.demand_avg_miss_latency::realview.ide 185670.831448 # average overall miss latency 1393system.iocache.demand_avg_miss_latency::total 185444.836712 # average overall miss latency 1394system.iocache.overall_avg_miss_latency::realview.ethernet 135500 # average overall miss latency 1395system.iocache.overall_avg_miss_latency::realview.ide 185670.831448 # average overall miss latency 1396system.iocache.overall_avg_miss_latency::total 185444.836712 # average overall miss latency 1397system.iocache.blocked_cycles::no_mshrs 32333 # number of cycles access was blocked 1398system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1399system.iocache.blocked::no_mshrs 3346 # number of cycles access was blocked 1400system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1401system.iocache.avg_blocked_cycles::no_mshrs 9.663180 # average number of cycles each access was blocked 1402system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1403system.iocache.fast_writes 0 # number of fast writes performed 1404system.iocache.cache_copies 0 # number of cache copies performed 1405system.iocache.writebacks::writebacks 106631 # number of writebacks 1406system.iocache.writebacks::total 106631 # number of writebacks 1407system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 1408system.iocache.ReadReq_mshr_misses::realview.ide 8840 # number of ReadReq MSHR misses 1409system.iocache.ReadReq_mshr_misses::total 8877 # number of ReadReq MSHR misses 1410system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1411system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1412system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 1413system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 1414system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 1415system.iocache.demand_mshr_misses::realview.ide 8840 # number of demand (read+write) MSHR misses 1416system.iocache.demand_mshr_misses::total 8880 # number of demand (read+write) MSHR misses 1417system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 1418system.iocache.overall_mshr_misses::realview.ide 8840 # number of overall MSHR misses 1419system.iocache.overall_mshr_misses::total 8880 # number of overall MSHR misses 1420system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3219000 # number of ReadReq MSHR miss cycles 1421system.iocache.ReadReq_mshr_miss_latency::realview.ide 1199330150 # number of ReadReq MSHR miss cycles 1422system.iocache.ReadReq_mshr_miss_latency::total 1202549150 # number of ReadReq MSHR miss cycles 1423system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 1424system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 1425system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8491892479 # number of WriteLineReq MSHR miss cycles 1426system.iocache.WriteLineReq_mshr_miss_latency::total 8491892479 # number of WriteLineReq MSHR miss cycles 1427system.iocache.demand_mshr_miss_latency::realview.ethernet 3420000 # number of demand (read+write) MSHR miss cycles 1428system.iocache.demand_mshr_miss_latency::realview.ide 1199330150 # number of demand (read+write) MSHR miss cycles 1429system.iocache.demand_mshr_miss_latency::total 1202750150 # number of demand (read+write) MSHR miss cycles 1430system.iocache.overall_mshr_miss_latency::realview.ethernet 3420000 # number of overall MSHR miss cycles 1431system.iocache.overall_mshr_miss_latency::realview.ide 1199330150 # number of overall MSHR miss cycles 1432system.iocache.overall_mshr_miss_latency::total 1202750150 # number of overall MSHR miss cycles 1433system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1434system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1435system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1436system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1437system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1438system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1439system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1440system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 1441system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1442system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1443system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 1444system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1445system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1446system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87000 # average ReadReq mshr miss latency 1447system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 135670.831448 # average ReadReq mshr miss latency 1448system.iocache.ReadReq_avg_mshr_miss_latency::total 135467.967782 # average ReadReq mshr miss latency 1449system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 1450system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 1451system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 79613.482328 # average WriteLineReq mshr miss latency 1452system.iocache.WriteLineReq_avg_mshr_miss_latency::total 79613.482328 # average WriteLineReq mshr miss latency 1453system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency 1454system.iocache.demand_avg_mshr_miss_latency::realview.ide 135670.831448 # average overall mshr miss latency 1455system.iocache.demand_avg_mshr_miss_latency::total 135444.836712 # average overall mshr miss latency 1456system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85500 # average overall mshr miss latency 1457system.iocache.overall_avg_mshr_miss_latency::realview.ide 135670.831448 # average overall mshr miss latency 1458system.iocache.overall_avg_mshr_miss_latency::total 135444.836712 # average overall mshr miss latency 1459system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 1460system.membus.trans_dist::ReadReq 86006 # Transaction distribution 1461system.membus.trans_dist::ReadResp 526484 # Transaction distribution 1462system.membus.trans_dist::WriteReq 33706 # Transaction distribution 1463system.membus.trans_dist::WriteResp 33706 # Transaction distribution 1464system.membus.trans_dist::Writeback 1366243 # Transaction distribution 1465system.membus.trans_dist::CleanEvict 236394 # Transaction distribution 1466system.membus.trans_dist::UpgradeReq 38482 # Transaction distribution 1467system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution 1468system.membus.trans_dist::UpgradeResp 38483 # Transaction distribution 1469system.membus.trans_dist::ReadExReq 1149637 # Transaction distribution 1470system.membus.trans_dist::ReadExResp 1149637 # Transaction distribution 1471system.membus.trans_dist::ReadSharedReq 440478 # Transaction distribution 1472system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution 1473system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution 1474system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) 1475system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) 1476system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6916 # Packet count per connected master and slave (bytes) 1477system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4838609 # Packet count per connected master and slave (bytes) 1478system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4968261 # Packet count per connected master and slave (bytes) 1479system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 340944 # Packet count per connected master and slave (bytes) 1480system.membus.pkt_count_system.iocache.mem_side::total 340944 # Packet count per connected master and slave (bytes) 1481system.membus.pkt_count::total 5309205 # Packet count per connected master and slave (bytes) 1482system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) 1483system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) 1484system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13832 # Cumulative packet size per connected master and slave (bytes) 1485system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 185140076 # Cumulative packet size per connected master and slave (bytes) 1486system.membus.pkt_size_system.cpu.l2cache.mem_side::total 185310482 # Cumulative packet size per connected master and slave (bytes) 1487system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7218752 # Cumulative packet size per connected master and slave (bytes) 1488system.membus.pkt_size_system.iocache.mem_side::total 7218752 # Cumulative packet size per connected master and slave (bytes) 1489system.membus.pkt_size::total 192529234 # Cumulative packet size per connected master and slave (bytes) 1490system.membus.snoops 3380 # Total snoops (count) 1491system.membus.snoop_fanout::samples 3460550 # Request fanout histogram 1492system.membus.snoop_fanout::mean 1 # Request fanout histogram 1493system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1494system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1495system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1496system.membus.snoop_fanout::1 3460550 100.00% 100.00% # Request fanout histogram 1497system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1498system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1499system.membus.snoop_fanout::min_value 1 # Request fanout histogram 1500system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1501system.membus.snoop_fanout::total 3460550 # Request fanout histogram 1502system.membus.reqLayer0.occupancy 102447500 # Layer occupancy (ticks) 1503system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1504system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) 1505system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1506system.membus.reqLayer2.occupancy 5490500 # Layer occupancy (ticks) 1507system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1508system.membus.reqLayer5.occupancy 9255992894 # Layer occupancy (ticks) 1509system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1510system.membus.respLayer2.occupancy 8767241103 # Layer occupancy (ticks) 1511system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1512system.membus.respLayer3.occupancy 228448107 # Layer occupancy (ticks) 1513system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1514system.realview.ethernet.txBytes 966 # Bytes Transmitted 1515system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1516system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1517system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1518system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1519system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1520system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1521system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1522system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1523system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) 1524system.realview.ethernet.totPackets 3 # Total Packets 1525system.realview.ethernet.totBytes 966 # Total Bytes 1526system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 1527system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) 1528system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 1529system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1530system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 1531system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1532system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1533system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 1534system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1535system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1536system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 1537system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1538system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1539system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 1540system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1541system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1542system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 1543system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1544system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1545system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 1546system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1547system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1548system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1549system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1550system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1551system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1552system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1553system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1554system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1555system.realview.ethernet.droppedPackets 0 # number of packets dropped 1556system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks 1557system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks 1558system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks 1559system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks 1560system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks 1561system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks 1562system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks 1563system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks 1564system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks 1565system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks 1566 1567---------- End Simulation Statistics ---------- 1568