1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 51.643658 # Number of seconds simulated 4sim_ticks 51643657651000 # Number of ticks simulated 5final_tick 51643657651000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 290656 # Simulator instruction rate (inst/s) 8host_op_rate 346501 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 16573581112 # Simulator tick rate (ticks/s) 10host_mem_usage 686852 # Number of bytes of host memory used 11host_seconds 3116.02 # Real time elapsed on the host 12sim_insts 905689769 # Number of instructions simulated 13sim_ops 1079705427 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.dtb.walker 481856 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.itb.walker 390720 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.inst 7301696 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu.data 78480968 # Number of bytes read from this memory 21system.physmem.bytes_read::realview.ide 396608 # Number of bytes read from this memory 22system.physmem.bytes_read::total 87051848 # Number of bytes read from this memory 23system.physmem.bytes_inst_read::cpu.inst 7301696 # Number of instructions bytes read from this memory 24system.physmem.bytes_inst_read::total 7301696 # Number of instructions bytes read from this memory 25system.physmem.bytes_written::writebacks 106840192 # Number of bytes written to this memory 26system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory 27system.physmem.bytes_written::total 106860772 # Number of bytes written to this memory 28system.physmem.num_reads::cpu.dtb.walker 7529 # Number of read requests responded to by this memory 29system.physmem.num_reads::cpu.itb.walker 6105 # Number of read requests responded to by this memory 30system.physmem.num_reads::cpu.inst 114089 # Number of read requests responded to by this memory 31system.physmem.num_reads::cpu.data 1226278 # Number of read requests responded to by this memory 32system.physmem.num_reads::realview.ide 6197 # Number of read requests responded to by this memory 33system.physmem.num_reads::total 1360198 # Number of read requests responded to by this memory 34system.physmem.num_writes::writebacks 1669378 # Number of write requests responded to by this memory 35system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory 36system.physmem.num_writes::total 1671951 # Number of write requests responded to by this memory 37system.physmem.bw_read::cpu.dtb.walker 9330 # Total read bandwidth from this memory (bytes/s) 38system.physmem.bw_read::cpu.itb.walker 7566 # Total read bandwidth from this memory (bytes/s) 39system.physmem.bw_read::cpu.inst 141386 # Total read bandwidth from this memory (bytes/s) 40system.physmem.bw_read::cpu.data 1519663 # Total read bandwidth from this memory (bytes/s) 41system.physmem.bw_read::realview.ide 7680 # Total read bandwidth from this memory (bytes/s) 42system.physmem.bw_read::total 1685625 # Total read bandwidth from this memory (bytes/s) 43system.physmem.bw_inst_read::cpu.inst 141386 # Instruction read bandwidth from this memory (bytes/s) 44system.physmem.bw_inst_read::total 141386 # Instruction read bandwidth from this memory (bytes/s) 45system.physmem.bw_write::writebacks 2068796 # Write bandwidth from this memory (bytes/s) 46system.physmem.bw_write::cpu.data 399 # Write bandwidth from this memory (bytes/s) 47system.physmem.bw_write::total 2069194 # Write bandwidth from this memory (bytes/s) 48system.physmem.bw_total::writebacks 2068796 # Total bandwidth to/from this memory (bytes/s) 49system.physmem.bw_total::cpu.dtb.walker 9330 # Total bandwidth to/from this memory (bytes/s) 50system.physmem.bw_total::cpu.itb.walker 7566 # Total bandwidth to/from this memory (bytes/s) 51system.physmem.bw_total::cpu.inst 141386 # Total bandwidth to/from this memory (bytes/s) 52system.physmem.bw_total::cpu.data 1520062 # Total bandwidth to/from this memory (bytes/s) 53system.physmem.bw_total::realview.ide 7680 # Total bandwidth to/from this memory (bytes/s) 54system.physmem.bw_total::total 3754820 # Total bandwidth to/from this memory (bytes/s) 55system.physmem.readReqs 1360198 # Number of read requests accepted 56system.physmem.writeReqs 1671951 # Number of write requests accepted 57system.physmem.readBursts 1360198 # Number of DRAM read bursts, including those serviced by the write queue 58system.physmem.writeBursts 1671951 # Number of DRAM write bursts, including those merged in the write queue 59system.physmem.bytesReadDRAM 86990528 # Total number of bytes read from DRAM 60system.physmem.bytesReadWrQ 62144 # Total number of bytes read from write queue 61system.physmem.bytesWritten 106858944 # Total number of bytes written to DRAM 62system.physmem.bytesReadSys 87051848 # Total read bytes from the system interface side 63system.physmem.bytesWrittenSys 106860772 # Total written bytes from the system interface side 64system.physmem.servicedByWrQ 971 # Number of DRAM read bursts serviced by the write queue 65system.physmem.mergedWrBursts 2249 # Number of DRAM write bursts merged with an existing one 66system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 67system.physmem.perBankRdBursts::0 83237 # Per bank write bursts 68system.physmem.perBankRdBursts::1 85225 # Per bank write bursts 69system.physmem.perBankRdBursts::2 82489 # Per bank write bursts 70system.physmem.perBankRdBursts::3 80125 # Per bank write bursts 71system.physmem.perBankRdBursts::4 87648 # Per bank write bursts 72system.physmem.perBankRdBursts::5 94125 # Per bank write bursts 73system.physmem.perBankRdBursts::6 89556 # Per bank write bursts 74system.physmem.perBankRdBursts::7 88166 # Per bank write bursts 75system.physmem.perBankRdBursts::8 78937 # Per bank write bursts 76system.physmem.perBankRdBursts::9 92012 # Per bank write bursts 77system.physmem.perBankRdBursts::10 85547 # Per bank write bursts 78system.physmem.perBankRdBursts::11 87304 # Per bank write bursts 79system.physmem.perBankRdBursts::12 77322 # Per bank write bursts 80system.physmem.perBankRdBursts::13 84061 # Per bank write bursts 81system.physmem.perBankRdBursts::14 80795 # Per bank write bursts 82system.physmem.perBankRdBursts::15 82678 # Per bank write bursts 83system.physmem.perBankWrBursts::0 101181 # Per bank write bursts 84system.physmem.perBankWrBursts::1 102649 # Per bank write bursts 85system.physmem.perBankWrBursts::2 102280 # Per bank write bursts 86system.physmem.perBankWrBursts::3 101626 # Per bank write bursts 87system.physmem.perBankWrBursts::4 106705 # Per bank write bursts 88system.physmem.perBankWrBursts::5 111943 # Per bank write bursts 89system.physmem.perBankWrBursts::6 107546 # Per bank write bursts 90system.physmem.perBankWrBursts::7 108809 # Per bank write bursts 91system.physmem.perBankWrBursts::8 101631 # Per bank write bursts 92system.physmem.perBankWrBursts::9 107791 # Per bank write bursts 93system.physmem.perBankWrBursts::10 102979 # Per bank write bursts 94system.physmem.perBankWrBursts::11 104017 # Per bank write bursts 95system.physmem.perBankWrBursts::12 98121 # Per bank write bursts 96system.physmem.perBankWrBursts::13 104909 # Per bank write bursts 97system.physmem.perBankWrBursts::14 102656 # Per bank write bursts 98system.physmem.perBankWrBursts::15 104828 # Per bank write bursts 99system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 100system.physmem.numWrRetry 458 # Number of times write queue was full causing retry 101system.physmem.totGap 51643655791000 # Total gap between requests 102system.physmem.readPktSize::0 0 # Read request sizes (log2) 103system.physmem.readPktSize::1 0 # Read request sizes (log2) 104system.physmem.readPktSize::2 0 # Read request sizes (log2) 105system.physmem.readPktSize::3 13 # Read request sizes (log2) 106system.physmem.readPktSize::4 2 # Read request sizes (log2) 107system.physmem.readPktSize::5 0 # Read request sizes (log2) 108system.physmem.readPktSize::6 1360183 # Read request sizes (log2) 109system.physmem.writePktSize::0 0 # Write request sizes (log2) 110system.physmem.writePktSize::1 0 # Write request sizes (log2) 111system.physmem.writePktSize::2 1 # Write request sizes (log2) 112system.physmem.writePktSize::3 2572 # Write request sizes (log2) 113system.physmem.writePktSize::4 0 # Write request sizes (log2) 114system.physmem.writePktSize::5 0 # Write request sizes (log2) 115system.physmem.writePktSize::6 1669378 # Write request sizes (log2) 116system.physmem.rdQLenPdf::0 1282957 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::1 70161 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::2 871 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::3 328 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::4 466 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::5 444 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::6 571 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::7 445 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::8 945 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::9 570 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::10 281 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::11 269 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::12 186 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::13 159 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::14 112 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::15 100 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::16 95 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::17 95 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::18 86 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::19 78 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 141system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 142system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 143system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 144system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 148system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::15 31821 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::16 39955 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::17 90821 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::18 97628 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::19 100256 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::20 96883 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::21 101095 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::22 99439 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::23 101345 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::24 97950 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::25 101005 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::26 102593 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::27 99923 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::28 96951 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::29 96056 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::30 95043 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::31 92451 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::32 92535 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::33 2699 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::34 2382 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::35 2134 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::36 1926 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::37 1567 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::38 1406 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::39 1261 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::40 1311 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::41 1226 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::42 1115 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::43 953 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::44 1116 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::45 933 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::46 851 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::47 726 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::48 800 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::49 998 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::50 891 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::51 728 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::52 719 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::53 738 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::54 745 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::55 777 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::56 969 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::57 867 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::58 705 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::59 880 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::60 1479 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::61 1458 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::62 568 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::63 1009 # What write queue length does an incoming req see 212system.physmem.bytesPerActivate::samples 752315 # Bytes accessed per row activation 213system.physmem.bytesPerActivate::mean 257.670024 # Bytes accessed per row activation 214system.physmem.bytesPerActivate::gmean 155.219861 # Bytes accessed per row activation 215system.physmem.bytesPerActivate::stdev 291.691185 # Bytes accessed per row activation 216system.physmem.bytesPerActivate::0-127 319843 42.51% 42.51% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::128-255 192789 25.63% 68.14% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::256-383 70379 9.35% 77.50% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::384-511 39533 5.25% 82.75% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::512-639 27835 3.70% 86.45% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::640-767 18762 2.49% 88.94% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::768-895 14354 1.91% 90.85% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::896-1023 11626 1.55% 92.40% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::1024-1151 57194 7.60% 100.00% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::total 752315 # Bytes accessed per row activation 226system.physmem.rdPerTurnAround::samples 89671 # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::mean 15.157342 # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::stdev 22.777727 # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::0-255 89658 99.99% 99.99% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::256-511 7 0.01% 99.99% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::512-767 1 0.00% 99.99% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::768-1023 2 0.00% 100.00% # Reads before turning the bus around for writes 233system.physmem.rdPerTurnAround::1024-1279 1 0.00% 100.00% # Reads before turning the bus around for writes 234system.physmem.rdPerTurnAround::1536-1791 1 0.00% 100.00% # Reads before turning the bus around for writes 235system.physmem.rdPerTurnAround::5632-5887 1 0.00% 100.00% # Reads before turning the bus around for writes 236system.physmem.rdPerTurnAround::total 89671 # Reads before turning the bus around for writes 237system.physmem.wrPerTurnAround::samples 89671 # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::mean 18.619966 # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::gmean 17.881543 # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::stdev 7.948219 # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::16-23 81046 90.38% 90.38% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::24-31 5562 6.20% 96.58% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::32-39 1304 1.45% 98.04% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::40-47 395 0.44% 98.48% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::48-55 213 0.24% 98.72% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::56-63 159 0.18% 98.89% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::64-71 654 0.73% 99.62% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::72-79 203 0.23% 99.85% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::80-87 30 0.03% 99.88% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::88-95 3 0.00% 99.89% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::96-103 5 0.01% 99.89% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::104-111 17 0.02% 99.91% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::112-119 4 0.00% 99.92% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::120-127 4 0.00% 99.92% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::128-135 32 0.04% 99.96% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::136-143 13 0.01% 99.97% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::144-151 6 0.01% 99.98% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::152-159 1 0.00% 99.98% # Writes before turning the bus around for reads 259system.physmem.wrPerTurnAround::160-167 2 0.00% 99.98% # Writes before turning the bus around for reads 260system.physmem.wrPerTurnAround::168-175 2 0.00% 99.98% # Writes before turning the bus around for reads 261system.physmem.wrPerTurnAround::176-183 3 0.00% 99.99% # Writes before turning the bus around for reads 262system.physmem.wrPerTurnAround::184-191 1 0.00% 99.99% # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::192-199 10 0.01% 100.00% # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::total 89671 # Writes before turning the bus around for reads 267system.physmem.totQLat 40684785332 # Total ticks spent queuing 268system.physmem.totMemAccLat 66170291582 # Total ticks spent from burst creation until serviced by the DRAM 269system.physmem.totBusLat 6796135000 # Total ticks spent in databus transfers 270system.physmem.avgQLat 29932.30 # Average queueing delay per DRAM burst 271system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 272system.physmem.avgMemAccLat 48682.30 # Average memory access latency per DRAM burst 273system.physmem.avgRdBW 1.68 # Average DRAM read bandwidth in MiByte/s 274system.physmem.avgWrBW 2.07 # Average achieved write bandwidth in MiByte/s 275system.physmem.avgRdBWSys 1.69 # Average system read bandwidth in MiByte/s 276system.physmem.avgWrBWSys 2.07 # Average system write bandwidth in MiByte/s 277system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 278system.physmem.busUtil 0.03 # Data bus utilization in percentage 279system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 280system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 281system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 282system.physmem.avgWrQLen 24.41 # Average write queue length when enqueuing 283system.physmem.readRowHits 1052962 # Number of row buffer hits during reads 284system.physmem.writeRowHits 1223619 # Number of row buffer hits during writes 285system.physmem.readRowHitRate 77.47 # Row buffer hit rate for reads 286system.physmem.writeRowHitRate 73.28 # Row buffer hit rate for writes 287system.physmem.avgGap 17032031.01 # Average gap between requests 288system.physmem.pageHitRate 75.16 # Row buffer hit rate, read and write combined 289system.physmem_0.actEnergy 2732670780 # Energy for activate commands per rank (pJ) 290system.physmem_0.preEnergy 1452445170 # Energy for precharge commands per rank (pJ) 291system.physmem_0.readEnergy 4930676940 # Energy for read commands per rank (pJ) 292system.physmem_0.writeEnergy 4399097580 # Energy for write commands per rank (pJ) 293system.physmem_0.refreshEnergy 51881762400.000015 # Energy for refresh commands per rank (pJ) 294system.physmem_0.actBackEnergy 47976087180 # Energy for active background per rank (pJ) 295system.physmem_0.preBackEnergy 3104058720 # Energy for precharge background per rank (pJ) 296system.physmem_0.actPowerDownEnergy 109980529290 # Energy for active power-down per rank (pJ) 297system.physmem_0.prePowerDownEnergy 71485388640 # Energy for precharge power-down per rank (pJ) 298system.physmem_0.selfRefreshEnergy 12273611587950 # Energy for self refresh per rank (pJ) 299system.physmem_0.totalEnergy 12571576503750 # Total energy per rank (pJ) 300system.physmem_0.averagePower 243.429243 # Core power per rank (mW) 301system.physmem_0.totalIdleTime 51530314812756 # Total Idle time Per DRAM Rank 302system.physmem_0.memoryStateTime::IDLE 5413929000 # Time in different power states 303system.physmem_0.memoryStateTime::REF 22045432000 # Time in different power states 304system.physmem_0.memoryStateTime::SREF 51102968874750 # Time in different power states 305system.physmem_0.memoryStateTime::PRE_PDN 186159553736 # Time in different power states 306system.physmem_0.memoryStateTime::ACT 85883432494 # Time in different power states 307system.physmem_0.memoryStateTime::ACT_PDN 241186429020 # Time in different power states 308system.physmem_1.actEnergy 2638872600 # Energy for activate commands per rank (pJ) 309system.physmem_1.preEnergy 1402590255 # Energy for precharge commands per rank (pJ) 310system.physmem_1.readEnergy 4774203840 # Energy for read commands per rank (pJ) 311system.physmem_1.writeEnergy 4316585040 # Energy for write commands per rank (pJ) 312system.physmem_1.refreshEnergy 51214263360.000008 # Energy for refresh commands per rank (pJ) 313system.physmem_1.actBackEnergy 48316306500 # Energy for active background per rank (pJ) 314system.physmem_1.preBackEnergy 3067085280 # Energy for precharge background per rank (pJ) 315system.physmem_1.actPowerDownEnergy 106463182980 # Energy for active power-down per rank (pJ) 316system.physmem_1.prePowerDownEnergy 70942598400 # Energy for precharge power-down per rank (pJ) 317system.physmem_1.selfRefreshEnergy 12275647651350 # Energy for self refresh per rank (pJ) 318system.physmem_1.totalEnergy 12568805141895 # Total energy per rank (pJ) 319system.physmem_1.averagePower 243.375580 # Core power per rank (mW) 320system.physmem_1.totalIdleTime 51529660585796 # Total Idle time Per DRAM Rank 321system.physmem_1.memoryStateTime::IDLE 5336166484 # Time in different power states 322system.physmem_1.memoryStateTime::REF 21762952000 # Time in different power states 323system.physmem_1.memoryStateTime::SREF 51111446865750 # Time in different power states 324system.physmem_1.memoryStateTime::PRE_PDN 184746715790 # Time in different power states 325system.physmem_1.memoryStateTime::ACT 86892179220 # Time in different power states 326system.physmem_1.memoryStateTime::ACT_PDN 233472771756 # Time in different power states 327system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 328system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory 329system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory 330system.realview.nvmem.bytes_read::total 740 # Number of bytes read from this memory 331system.realview.nvmem.bytes_inst_read::cpu.inst 704 # Number of instructions bytes read from this memory 332system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory 333system.realview.nvmem.num_reads::cpu.inst 11 # Number of read requests responded to by this memory 334system.realview.nvmem.num_reads::cpu.data 5 # Number of read requests responded to by this memory 335system.realview.nvmem.num_reads::total 16 # Number of read requests responded to by this memory 336system.realview.nvmem.bw_read::cpu.inst 14 # Total read bandwidth from this memory (bytes/s) 337system.realview.nvmem.bw_read::cpu.data 1 # Total read bandwidth from this memory (bytes/s) 338system.realview.nvmem.bw_read::total 14 # Total read bandwidth from this memory (bytes/s) 339system.realview.nvmem.bw_inst_read::cpu.inst 14 # Instruction read bandwidth from this memory (bytes/s) 340system.realview.nvmem.bw_inst_read::total 14 # Instruction read bandwidth from this memory (bytes/s) 341system.realview.nvmem.bw_total::cpu.inst 14 # Total bandwidth to/from this memory (bytes/s) 342system.realview.nvmem.bw_total::cpu.data 1 # Total bandwidth to/from this memory (bytes/s) 343system.realview.nvmem.bw_total::total 14 # Total bandwidth to/from this memory (bytes/s) 344system.realview.vram.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 345system.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 346system.bridge.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 347system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 348system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 349system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 350system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. 351system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. 352system.cf0.dma_write_txs 1669 # Number of DMA write transactions. 353system.cpu.branchPred.lookups 230671595 # Number of BP lookups 354system.cpu.branchPred.condPredicted 148977251 # Number of conditional branches predicted 355system.cpu.branchPred.condIncorrect 12591272 # Number of conditional branches incorrect 356system.cpu.branchPred.BTBLookups 161205478 # Number of BTB lookups 357system.cpu.branchPred.BTBHits 94166388 # Number of BTB hits 358system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 359system.cpu.branchPred.BTBHitPct 58.413888 # BTB Hit Percentage 360system.cpu.branchPred.usedRAS 32707519 # Number of times the RAS was used to get a target. 361system.cpu.branchPred.RASInCorrect 2199358 # Number of incorrect RAS predictions. 362system.cpu.branchPred.indirectLookups 7428890 # Number of indirect predictor lookups. 363system.cpu.branchPred.indirectHits 5357971 # Number of indirect target hits. 364system.cpu.branchPred.indirectMisses 2070919 # Number of indirect misses. 365system.cpu.branchPredindirectMispredicted 851352 # Number of mispredicted indirect branches. 366system.cpu_clk_domain.clock 500 # Clock period in ticks 367system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 368system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 369system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 370system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 371system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 372system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 373system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 374system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 375system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 376system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 377system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 378system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 379system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 380system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 381system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 382system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 383system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 384system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 385system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 386system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 387system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 388system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 389system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 390system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 391system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 392system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 393system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 394system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 395system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 396system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 397system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 398system.cpu.dtb.walker.walks 612824 # Table walker walks requested 399system.cpu.dtb.walker.walksLong 612824 # Table walker walks initiated with long descriptors 400system.cpu.dtb.walker.walksLongTerminationLevel::Level2 25045 # Level at which table walker walks with long descriptors terminate 401system.cpu.dtb.walker.walksLongTerminationLevel::Level3 213625 # Level at which table walker walks with long descriptors terminate 402system.cpu.dtb.walker.walkWaitTime::samples 612824 # Table walker wait (enqueue to first request) latency 403system.cpu.dtb.walker.walkWaitTime::0 612824 100.00% 100.00% # Table walker wait (enqueue to first request) latency 404system.cpu.dtb.walker.walkWaitTime::total 612824 # Table walker wait (enqueue to first request) latency 405system.cpu.dtb.walker.walkCompletionTime::samples 238670 # Table walker service (enqueue to completion) latency 406system.cpu.dtb.walker.walkCompletionTime::mean 26656.848368 # Table walker service (enqueue to completion) latency 407system.cpu.dtb.walker.walkCompletionTime::gmean 22869.063207 # Table walker service (enqueue to completion) latency 408system.cpu.dtb.walker.walkCompletionTime::stdev 18178.269726 # Table walker service (enqueue to completion) latency 409system.cpu.dtb.walker.walkCompletionTime::0-65535 235680 98.75% 98.75% # Table walker service (enqueue to completion) latency 410system.cpu.dtb.walker.walkCompletionTime::65536-131071 2495 1.05% 99.79% # Table walker service (enqueue to completion) latency 411system.cpu.dtb.walker.walkCompletionTime::131072-196607 126 0.05% 99.85% # Table walker service (enqueue to completion) latency 412system.cpu.dtb.walker.walkCompletionTime::196608-262143 157 0.07% 99.91% # Table walker service (enqueue to completion) latency 413system.cpu.dtb.walker.walkCompletionTime::262144-327679 125 0.05% 99.96% # Table walker service (enqueue to completion) latency 414system.cpu.dtb.walker.walkCompletionTime::327680-393215 32 0.01% 99.98% # Table walker service (enqueue to completion) latency 415system.cpu.dtb.walker.walkCompletionTime::393216-458751 14 0.01% 99.98% # Table walker service (enqueue to completion) latency 416system.cpu.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 99.99% # Table walker service (enqueue to completion) latency 417system.cpu.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 99.99% # Table walker service (enqueue to completion) latency 418system.cpu.dtb.walker.walkCompletionTime::589824-655359 28 0.01% 100.00% # Table walker service (enqueue to completion) latency 419system.cpu.dtb.walker.walkCompletionTime::786432-851967 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 420system.cpu.dtb.walker.walkCompletionTime::917504-983039 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 421system.cpu.dtb.walker.walkCompletionTime::total 238670 # Table walker service (enqueue to completion) latency 422system.cpu.dtb.walker.walksPending::samples 411876000 # Table walker pending requests distribution 423system.cpu.dtb.walker.walksPending::0 411876000 100.00% 100.00% # Table walker pending requests distribution 424system.cpu.dtb.walker.walksPending::total 411876000 # Table walker pending requests distribution 425system.cpu.dtb.walker.walkPageSizes::4K 213626 89.51% 89.51% # Table walker page sizes translated 426system.cpu.dtb.walker.walkPageSizes::2M 25045 10.49% 100.00% # Table walker page sizes translated 427system.cpu.dtb.walker.walkPageSizes::total 238671 # Table walker page sizes translated 428system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 612824 # Table walker requests started/completed, data/inst 429system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 430system.cpu.dtb.walker.walkRequestOrigin_Requested::total 612824 # Table walker requests started/completed, data/inst 431system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 238671 # Table walker requests started/completed, data/inst 432system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 433system.cpu.dtb.walker.walkRequestOrigin_Completed::total 238671 # Table walker requests started/completed, data/inst 434system.cpu.dtb.walker.walkRequestOrigin::total 851495 # Table walker requests started/completed, data/inst 435system.cpu.dtb.inst_hits 0 # ITB inst hits 436system.cpu.dtb.inst_misses 0 # ITB inst misses 437system.cpu.dtb.read_hits 191427667 # DTB read hits 438system.cpu.dtb.read_misses 503751 # DTB read misses 439system.cpu.dtb.write_hits 170371453 # DTB write hits 440system.cpu.dtb.write_misses 109073 # DTB write misses 441system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed 442system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 443system.cpu.dtb.flush_tlb_mva_asid 50563 # Number of times TLB was flushed by MVA & ASID 444system.cpu.dtb.flush_tlb_asid 1145 # Number of times TLB was flushed by ASID 445system.cpu.dtb.flush_entries 82805 # Number of entries that have been flushed from TLB 446system.cpu.dtb.align_faults 891 # Number of TLB faults due to alignment restrictions 447system.cpu.dtb.prefetch_faults 16210 # Number of TLB faults due to prefetch 448system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 449system.cpu.dtb.perms_faults 24062 # Number of TLB faults due to permissions restrictions 450system.cpu.dtb.read_accesses 191931418 # DTB read accesses 451system.cpu.dtb.write_accesses 170480526 # DTB write accesses 452system.cpu.dtb.inst_accesses 0 # ITB inst accesses 453system.cpu.dtb.hits 361799120 # DTB hits 454system.cpu.dtb.misses 612824 # DTB misses 455system.cpu.dtb.accesses 362411944 # DTB accesses 456system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 457system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 458system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 459system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 460system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 461system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 462system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 463system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 464system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 465system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 466system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 467system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 468system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 469system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 470system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 471system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 472system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 473system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 474system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 475system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 476system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 477system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 478system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 479system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 480system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 481system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 482system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 483system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 484system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 485system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 486system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 487system.cpu.itb.walker.walks 137744 # Table walker walks requested 488system.cpu.itb.walker.walksLong 137744 # Table walker walks initiated with long descriptors 489system.cpu.itb.walker.walksLongTerminationLevel::Level2 1060 # Level at which table walker walks with long descriptors terminate 490system.cpu.itb.walker.walksLongTerminationLevel::Level3 119122 # Level at which table walker walks with long descriptors terminate 491system.cpu.itb.walker.walkWaitTime::samples 137744 # Table walker wait (enqueue to first request) latency 492system.cpu.itb.walker.walkWaitTime::0 137744 100.00% 100.00% # Table walker wait (enqueue to first request) latency 493system.cpu.itb.walker.walkWaitTime::total 137744 # Table walker wait (enqueue to first request) latency 494system.cpu.itb.walker.walkCompletionTime::samples 120182 # Table walker service (enqueue to completion) latency 495system.cpu.itb.walker.walkCompletionTime::mean 28731.482252 # Table walker service (enqueue to completion) latency 496system.cpu.itb.walker.walkCompletionTime::gmean 24330.551658 # Table walker service (enqueue to completion) latency 497system.cpu.itb.walker.walkCompletionTime::stdev 24049.037609 # Table walker service (enqueue to completion) latency 498system.cpu.itb.walker.walkCompletionTime::0-65535 116919 97.28% 97.28% # Table walker service (enqueue to completion) latency 499system.cpu.itb.walker.walkCompletionTime::65536-131071 2876 2.39% 99.68% # Table walker service (enqueue to completion) latency 500system.cpu.itb.walker.walkCompletionTime::131072-196607 146 0.12% 99.80% # Table walker service (enqueue to completion) latency 501system.cpu.itb.walker.walkCompletionTime::196608-262143 107 0.09% 99.89% # Table walker service (enqueue to completion) latency 502system.cpu.itb.walker.walkCompletionTime::262144-327679 36 0.03% 99.92% # Table walker service (enqueue to completion) latency 503system.cpu.itb.walker.walkCompletionTime::327680-393215 28 0.02% 99.94% # Table walker service (enqueue to completion) latency 504system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 99.94% # Table walker service (enqueue to completion) latency 505system.cpu.itb.walker.walkCompletionTime::524288-589823 3 0.00% 99.95% # Table walker service (enqueue to completion) latency 506system.cpu.itb.walker.walkCompletionTime::589824-655359 64 0.05% 100.00% # Table walker service (enqueue to completion) latency 507system.cpu.itb.walker.walkCompletionTime::total 120182 # Table walker service (enqueue to completion) latency 508system.cpu.itb.walker.walksPending::samples 411203500 # Table walker pending requests distribution 509system.cpu.itb.walker.walksPending::0 411203500 100.00% 100.00% # Table walker pending requests distribution 510system.cpu.itb.walker.walksPending::total 411203500 # Table walker pending requests distribution 511system.cpu.itb.walker.walkPageSizes::4K 119122 99.12% 99.12% # Table walker page sizes translated 512system.cpu.itb.walker.walkPageSizes::2M 1060 0.88% 100.00% # Table walker page sizes translated 513system.cpu.itb.walker.walkPageSizes::total 120182 # Table walker page sizes translated 514system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 515system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 137744 # Table walker requests started/completed, data/inst 516system.cpu.itb.walker.walkRequestOrigin_Requested::total 137744 # Table walker requests started/completed, data/inst 517system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 518system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 120182 # Table walker requests started/completed, data/inst 519system.cpu.itb.walker.walkRequestOrigin_Completed::total 120182 # Table walker requests started/completed, data/inst 520system.cpu.itb.walker.walkRequestOrigin::total 257926 # Table walker requests started/completed, data/inst 521system.cpu.itb.inst_hits 367199991 # ITB inst hits 522system.cpu.itb.inst_misses 137744 # ITB inst misses 523system.cpu.itb.read_hits 0 # DTB read hits 524system.cpu.itb.read_misses 0 # DTB read misses 525system.cpu.itb.write_hits 0 # DTB write hits 526system.cpu.itb.write_misses 0 # DTB write misses 527system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed 528system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 529system.cpu.itb.flush_tlb_mva_asid 50563 # Number of times TLB was flushed by MVA & ASID 530system.cpu.itb.flush_tlb_asid 1145 # Number of times TLB was flushed by ASID 531system.cpu.itb.flush_entries 59110 # Number of entries that have been flushed from TLB 532system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 533system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 534system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 535system.cpu.itb.perms_faults 331525 # Number of TLB faults due to permissions restrictions 536system.cpu.itb.read_accesses 0 # DTB read accesses 537system.cpu.itb.write_accesses 0 # DTB write accesses 538system.cpu.itb.inst_accesses 367337735 # ITB inst accesses 539system.cpu.itb.hits 367199991 # DTB hits 540system.cpu.itb.misses 137744 # DTB misses 541system.cpu.itb.accesses 367337735 # DTB accesses 542system.cpu.numPwrStateTransitions 33588 # Number of power state transitions 543system.cpu.pwrStateClkGateDist::samples 16794 # Distribution of time spent in the clock gated state 544system.cpu.pwrStateClkGateDist::mean 3006267839.468917 # Distribution of time spent in the clock gated state 545system.cpu.pwrStateClkGateDist::stdev 59370181603.459618 # Distribution of time spent in the clock gated state 546system.cpu.pwrStateClkGateDist::underflows 7493 44.62% 44.62% # Distribution of time spent in the clock gated state 547system.cpu.pwrStateClkGateDist::1000-5e+10 9266 55.17% 99.79% # Distribution of time spent in the clock gated state 548system.cpu.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.82% # Distribution of time spent in the clock gated state 549system.cpu.pwrStateClkGateDist::1e+11-1.5e+11 3 0.02% 99.84% # Distribution of time spent in the clock gated state 550system.cpu.pwrStateClkGateDist::1.5e+11-2e+11 1 0.01% 99.85% # Distribution of time spent in the clock gated state 551system.cpu.pwrStateClkGateDist::2e+11-2.5e+11 2 0.01% 99.86% # Distribution of time spent in the clock gated state 552system.cpu.pwrStateClkGateDist::2.5e+11-3e+11 2 0.01% 99.87% # Distribution of time spent in the clock gated state 553system.cpu.pwrStateClkGateDist::3e+11-3.5e+11 1 0.01% 99.87% # Distribution of time spent in the clock gated state 554system.cpu.pwrStateClkGateDist::4.5e+11-5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 555system.cpu.pwrStateClkGateDist::5e+11-5.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 556system.cpu.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 557system.cpu.pwrStateClkGateDist::overflows 18 0.11% 100.00% # Distribution of time spent in the clock gated state 558system.cpu.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 559system.cpu.pwrStateClkGateDist::max_value 1988777658384 # Distribution of time spent in the clock gated state 560system.cpu.pwrStateClkGateDist::total 16794 # Distribution of time spent in the clock gated state 561system.cpu.pwrStateResidencyTicks::ON 1156395554959 # Cumulative time (in ticks) in various power states 562system.cpu.pwrStateResidencyTicks::CLK_GATED 50487262096041 # Cumulative time (in ticks) in various power states 563system.cpu.numCycles 2312845645 # number of cpu cycles simulated 564system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 565system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 566system.cpu.committedInsts 905689769 # Number of instructions committed 567system.cpu.committedOps 1079705427 # Number of ops (including micro ops) committed 568system.cpu.discardedOps 38872378 # Number of ops (including micro ops) which were discarded before commit 569system.cpu.numFetchSuspends 7934 # Number of times Execute suspended instruction fetching 570system.cpu.quiesceCycles 100975614107 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 571system.cpu.cpi 2.553684 # CPI: cycles per instruction 572system.cpu.ipc 0.391591 # IPC: instructions per cycle 573system.cpu.op_class_0::No_OpClass 1 0.00% 0.00% # Class of committed instruction 574system.cpu.op_class_0::IntAlu 721452382 66.82% 66.82% # Class of committed instruction 575system.cpu.op_class_0::IntMult 2371003 0.22% 67.04% # Class of committed instruction 576system.cpu.op_class_0::IntDiv 100622 0.01% 67.05% # Class of committed instruction 577system.cpu.op_class_0::FloatAdd 8 0.00% 67.05% # Class of committed instruction 578system.cpu.op_class_0::FloatCmp 13 0.00% 67.05% # Class of committed instruction 579system.cpu.op_class_0::FloatCvt 21 0.00% 67.05% # Class of committed instruction 580system.cpu.op_class_0::FloatMult 0 0.00% 67.05% # Class of committed instruction 581system.cpu.op_class_0::FloatMultAcc 0 0.00% 67.05% # Class of committed instruction 582system.cpu.op_class_0::FloatDiv 0 0.00% 67.05% # Class of committed instruction 583system.cpu.op_class_0::FloatMisc 107773 0.01% 67.06% # Class of committed instruction 584system.cpu.op_class_0::FloatSqrt 0 0.00% 67.06% # Class of committed instruction 585system.cpu.op_class_0::SimdAdd 0 0.00% 67.06% # Class of committed instruction 586system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.06% # Class of committed instruction 587system.cpu.op_class_0::SimdAlu 0 0.00% 67.06% # Class of committed instruction 588system.cpu.op_class_0::SimdCmp 0 0.00% 67.06% # Class of committed instruction 589system.cpu.op_class_0::SimdCvt 0 0.00% 67.06% # Class of committed instruction 590system.cpu.op_class_0::SimdMisc 0 0.00% 67.06% # Class of committed instruction 591system.cpu.op_class_0::SimdMult 0 0.00% 67.06% # Class of committed instruction 592system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.06% # Class of committed instruction 593system.cpu.op_class_0::SimdShift 0 0.00% 67.06% # Class of committed instruction 594system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.06% # Class of committed instruction 595system.cpu.op_class_0::SimdSqrt 0 0.00% 67.06% # Class of committed instruction 596system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.06% # Class of committed instruction 597system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.06% # Class of committed instruction 598system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.06% # Class of committed instruction 599system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.06% # Class of committed instruction 600system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.06% # Class of committed instruction 601system.cpu.op_class_0::SimdFloatMisc 0 0.00% 67.06% # Class of committed instruction 602system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.06% # Class of committed instruction 603system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.06% # Class of committed instruction 604system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.06% # Class of committed instruction 605system.cpu.op_class_0::MemRead 185747611 17.20% 84.26% # Class of committed instruction 606system.cpu.op_class_0::MemWrite 169152555 15.67% 99.93% # Class of committed instruction 607system.cpu.op_class_0::FloatMemRead 112557 0.01% 99.94% # Class of committed instruction 608system.cpu.op_class_0::FloatMemWrite 660881 0.06% 100.00% # Class of committed instruction 609system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 610system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 611system.cpu.op_class_0::total 1079705427 # Class of committed instruction 612system.cpu.kern.inst.arm 0 # number of arm instructions executed 613system.cpu.kern.inst.quiesce 16794 # number of quiesce instructions executed 614system.cpu.tickCycles 1555844114 # Number of cycles that the object actually ticked 615system.cpu.idleCycles 757001531 # Total number of cycles that the object has spent stopped 616system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 617system.cpu.dcache.tags.replacements 11832637 # number of replacements 618system.cpu.dcache.tags.tagsinuse 511.995677 # Cycle average of tags in use 619system.cpu.dcache.tags.total_refs 345046750 # Total number of references to valid blocks. 620system.cpu.dcache.tags.sampled_refs 11833149 # Sample count of references to valid blocks. 621system.cpu.dcache.tags.avg_refs 29.159335 # Average number of references to valid blocks. 622system.cpu.dcache.tags.warmup_cycle 456752500 # Cycle when the warmup percentage was hit. 623system.cpu.dcache.tags.occ_blocks::cpu.data 511.995677 # Average occupied blocks per requestor 624system.cpu.dcache.tags.occ_percent::cpu.data 0.999992 # Average percentage of cache occupancy 625system.cpu.dcache.tags.occ_percent::total 0.999992 # Average percentage of cache occupancy 626system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 627system.cpu.dcache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 628system.cpu.dcache.tags.age_task_id_blocks_1024::1 398 # Occupied blocks per task id 629system.cpu.dcache.tags.age_task_id_blocks_1024::2 45 # Occupied blocks per task id 630system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 631system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 632system.cpu.dcache.tags.tag_accesses 1449239878 # Number of tag accesses 633system.cpu.dcache.tags.data_accesses 1449239878 # Number of data accesses 634system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 635system.cpu.dcache.ReadReq_hits::cpu.data 176307264 # number of ReadReq hits 636system.cpu.dcache.ReadReq_hits::total 176307264 # number of ReadReq hits 637system.cpu.dcache.WriteReq_hits::cpu.data 158900158 # number of WriteReq hits 638system.cpu.dcache.WriteReq_hits::total 158900158 # number of WriteReq hits 639system.cpu.dcache.SoftPFReq_hits::cpu.data 537417 # number of SoftPFReq hits 640system.cpu.dcache.SoftPFReq_hits::total 537417 # number of SoftPFReq hits 641system.cpu.dcache.WriteLineReq_hits::cpu.data 337852 # number of WriteLineReq hits 642system.cpu.dcache.WriteLineReq_hits::total 337852 # number of WriteLineReq hits 643system.cpu.dcache.LoadLockedReq_hits::cpu.data 4300418 # number of LoadLockedReq hits 644system.cpu.dcache.LoadLockedReq_hits::total 4300418 # number of LoadLockedReq hits 645system.cpu.dcache.StoreCondReq_hits::cpu.data 4627725 # number of StoreCondReq hits 646system.cpu.dcache.StoreCondReq_hits::total 4627725 # number of StoreCondReq hits 647system.cpu.dcache.demand_hits::cpu.data 335545274 # number of demand (read+write) hits 648system.cpu.dcache.demand_hits::total 335545274 # number of demand (read+write) hits 649system.cpu.dcache.overall_hits::cpu.data 336082691 # number of overall hits 650system.cpu.dcache.overall_hits::total 336082691 # number of overall hits 651system.cpu.dcache.ReadReq_misses::cpu.data 6490291 # number of ReadReq misses 652system.cpu.dcache.ReadReq_misses::total 6490291 # number of ReadReq misses 653system.cpu.dcache.WriteReq_misses::cpu.data 4646590 # number of WriteReq misses 654system.cpu.dcache.WriteReq_misses::total 4646590 # number of WriteReq misses 655system.cpu.dcache.SoftPFReq_misses::cpu.data 1620869 # number of SoftPFReq misses 656system.cpu.dcache.SoftPFReq_misses::total 1620869 # number of SoftPFReq misses 657system.cpu.dcache.WriteLineReq_misses::cpu.data 1254011 # number of WriteLineReq misses 658system.cpu.dcache.WriteLineReq_misses::total 1254011 # number of WriteLineReq misses 659system.cpu.dcache.LoadLockedReq_misses::cpu.data 329077 # number of LoadLockedReq misses 660system.cpu.dcache.LoadLockedReq_misses::total 329077 # number of LoadLockedReq misses 661system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses 662system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses 663system.cpu.dcache.demand_misses::cpu.data 12390892 # number of demand (read+write) misses 664system.cpu.dcache.demand_misses::total 12390892 # number of demand (read+write) misses 665system.cpu.dcache.overall_misses::cpu.data 14011761 # number of overall misses 666system.cpu.dcache.overall_misses::total 14011761 # number of overall misses 667system.cpu.dcache.ReadReq_miss_latency::cpu.data 114759870500 # number of ReadReq miss cycles 668system.cpu.dcache.ReadReq_miss_latency::total 114759870500 # number of ReadReq miss cycles 669system.cpu.dcache.WriteReq_miss_latency::cpu.data 196713087999 # number of WriteReq miss cycles 670system.cpu.dcache.WriteReq_miss_latency::total 196713087999 # number of WriteReq miss cycles 671system.cpu.dcache.WriteLineReq_miss_latency::cpu.data 27879484500 # number of WriteLineReq miss cycles 672system.cpu.dcache.WriteLineReq_miss_latency::total 27879484500 # number of WriteLineReq miss cycles 673system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5348350500 # number of LoadLockedReq miss cycles 674system.cpu.dcache.LoadLockedReq_miss_latency::total 5348350500 # number of LoadLockedReq miss cycles 675system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 83000 # number of StoreCondReq miss cycles 676system.cpu.dcache.StoreCondReq_miss_latency::total 83000 # number of StoreCondReq miss cycles 677system.cpu.dcache.demand_miss_latency::cpu.data 339352442999 # number of demand (read+write) miss cycles 678system.cpu.dcache.demand_miss_latency::total 339352442999 # number of demand (read+write) miss cycles 679system.cpu.dcache.overall_miss_latency::cpu.data 339352442999 # number of overall miss cycles 680system.cpu.dcache.overall_miss_latency::total 339352442999 # number of overall miss cycles 681system.cpu.dcache.ReadReq_accesses::cpu.data 182797555 # number of ReadReq accesses(hits+misses) 682system.cpu.dcache.ReadReq_accesses::total 182797555 # number of ReadReq accesses(hits+misses) 683system.cpu.dcache.WriteReq_accesses::cpu.data 163546748 # number of WriteReq accesses(hits+misses) 684system.cpu.dcache.WriteReq_accesses::total 163546748 # number of WriteReq accesses(hits+misses) 685system.cpu.dcache.SoftPFReq_accesses::cpu.data 2158286 # number of SoftPFReq accesses(hits+misses) 686system.cpu.dcache.SoftPFReq_accesses::total 2158286 # number of SoftPFReq accesses(hits+misses) 687system.cpu.dcache.WriteLineReq_accesses::cpu.data 1591863 # number of WriteLineReq accesses(hits+misses) 688system.cpu.dcache.WriteLineReq_accesses::total 1591863 # number of WriteLineReq accesses(hits+misses) 689system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4629495 # number of LoadLockedReq accesses(hits+misses) 690system.cpu.dcache.LoadLockedReq_accesses::total 4629495 # number of LoadLockedReq accesses(hits+misses) 691system.cpu.dcache.StoreCondReq_accesses::cpu.data 4627726 # number of StoreCondReq accesses(hits+misses) 692system.cpu.dcache.StoreCondReq_accesses::total 4627726 # number of StoreCondReq accesses(hits+misses) 693system.cpu.dcache.demand_accesses::cpu.data 347936166 # number of demand (read+write) accesses 694system.cpu.dcache.demand_accesses::total 347936166 # number of demand (read+write) accesses 695system.cpu.dcache.overall_accesses::cpu.data 350094452 # number of overall (read+write) accesses 696system.cpu.dcache.overall_accesses::total 350094452 # number of overall (read+write) accesses 697system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035505 # miss rate for ReadReq accesses 698system.cpu.dcache.ReadReq_miss_rate::total 0.035505 # miss rate for ReadReq accesses 699system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.028411 # miss rate for WriteReq accesses 700system.cpu.dcache.WriteReq_miss_rate::total 0.028411 # miss rate for WriteReq accesses 701system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.750998 # miss rate for SoftPFReq accesses 702system.cpu.dcache.SoftPFReq_miss_rate::total 0.750998 # miss rate for SoftPFReq accesses 703system.cpu.dcache.WriteLineReq_miss_rate::cpu.data 0.787763 # miss rate for WriteLineReq accesses 704system.cpu.dcache.WriteLineReq_miss_rate::total 0.787763 # miss rate for WriteLineReq accesses 705system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.071083 # miss rate for LoadLockedReq accesses 706system.cpu.dcache.LoadLockedReq_miss_rate::total 0.071083 # miss rate for LoadLockedReq accesses 707system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses 708system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses 709system.cpu.dcache.demand_miss_rate::cpu.data 0.035613 # miss rate for demand accesses 710system.cpu.dcache.demand_miss_rate::total 0.035613 # miss rate for demand accesses 711system.cpu.dcache.overall_miss_rate::cpu.data 0.040023 # miss rate for overall accesses 712system.cpu.dcache.overall_miss_rate::total 0.040023 # miss rate for overall accesses 713system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17681.775825 # average ReadReq miss latency 714system.cpu.dcache.ReadReq_avg_miss_latency::total 17681.775825 # average ReadReq miss latency 715system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42334.935512 # average WriteReq miss latency 716system.cpu.dcache.WriteReq_avg_miss_latency::total 42334.935512 # average WriteReq miss latency 717system.cpu.dcache.WriteLineReq_avg_miss_latency::cpu.data 22232.248760 # average WriteLineReq miss latency 718system.cpu.dcache.WriteLineReq_avg_miss_latency::total 22232.248760 # average WriteLineReq miss latency 719system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16252.580703 # average LoadLockedReq miss latency 720system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16252.580703 # average LoadLockedReq miss latency 721system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 83000 # average StoreCondReq miss latency 722system.cpu.dcache.StoreCondReq_avg_miss_latency::total 83000 # average StoreCondReq miss latency 723system.cpu.dcache.demand_avg_miss_latency::cpu.data 27387.248876 # average overall miss latency 724system.cpu.dcache.demand_avg_miss_latency::total 27387.248876 # average overall miss latency 725system.cpu.dcache.overall_avg_miss_latency::cpu.data 24219.114428 # average overall miss latency 726system.cpu.dcache.overall_avg_miss_latency::total 24219.114428 # average overall miss latency 727system.cpu.dcache.blocked_cycles::no_mshrs 135 # number of cycles access was blocked 728system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 729system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked 730system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 731system.cpu.dcache.avg_blocked_cycles::no_mshrs 67.500000 # average number of cycles each access was blocked 732system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 733system.cpu.dcache.writebacks::writebacks 9058668 # number of writebacks 734system.cpu.dcache.writebacks::total 9058668 # number of writebacks 735system.cpu.dcache.ReadReq_mshr_hits::cpu.data 331345 # number of ReadReq MSHR hits 736system.cpu.dcache.ReadReq_mshr_hits::total 331345 # number of ReadReq MSHR hits 737system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2059664 # number of WriteReq MSHR hits 738system.cpu.dcache.WriteReq_mshr_hits::total 2059664 # number of WriteReq MSHR hits 739system.cpu.dcache.WriteLineReq_mshr_hits::cpu.data 161 # number of WriteLineReq MSHR hits 740system.cpu.dcache.WriteLineReq_mshr_hits::total 161 # number of WriteLineReq MSHR hits 741system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 73138 # number of LoadLockedReq MSHR hits 742system.cpu.dcache.LoadLockedReq_mshr_hits::total 73138 # number of LoadLockedReq MSHR hits 743system.cpu.dcache.demand_mshr_hits::cpu.data 2391170 # number of demand (read+write) MSHR hits 744system.cpu.dcache.demand_mshr_hits::total 2391170 # number of demand (read+write) MSHR hits 745system.cpu.dcache.overall_mshr_hits::cpu.data 2391170 # number of overall MSHR hits 746system.cpu.dcache.overall_mshr_hits::total 2391170 # number of overall MSHR hits 747system.cpu.dcache.ReadReq_mshr_misses::cpu.data 6158946 # number of ReadReq MSHR misses 748system.cpu.dcache.ReadReq_mshr_misses::total 6158946 # number of ReadReq MSHR misses 749system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2586926 # number of WriteReq MSHR misses 750system.cpu.dcache.WriteReq_mshr_misses::total 2586926 # number of WriteReq MSHR misses 751system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1613436 # number of SoftPFReq MSHR misses 752system.cpu.dcache.SoftPFReq_mshr_misses::total 1613436 # number of SoftPFReq MSHR misses 753system.cpu.dcache.WriteLineReq_mshr_misses::cpu.data 1253850 # number of WriteLineReq MSHR misses 754system.cpu.dcache.WriteLineReq_mshr_misses::total 1253850 # number of WriteLineReq MSHR misses 755system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 255939 # number of LoadLockedReq MSHR misses 756system.cpu.dcache.LoadLockedReq_mshr_misses::total 255939 # number of LoadLockedReq MSHR misses 757system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses 758system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses 759system.cpu.dcache.demand_mshr_misses::cpu.data 9999722 # number of demand (read+write) MSHR misses 760system.cpu.dcache.demand_mshr_misses::total 9999722 # number of demand (read+write) MSHR misses 761system.cpu.dcache.overall_mshr_misses::cpu.data 11613158 # number of overall MSHR misses 762system.cpu.dcache.overall_mshr_misses::total 11613158 # number of overall MSHR misses 763system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33608 # number of ReadReq MSHR uncacheable 764system.cpu.dcache.ReadReq_mshr_uncacheable::total 33608 # number of ReadReq MSHR uncacheable 765system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33620 # number of WriteReq MSHR uncacheable 766system.cpu.dcache.WriteReq_mshr_uncacheable::total 33620 # number of WriteReq MSHR uncacheable 767system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67228 # number of overall MSHR uncacheable misses 768system.cpu.dcache.overall_mshr_uncacheable_misses::total 67228 # number of overall MSHR uncacheable misses 769system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 101472833000 # number of ReadReq MSHR miss cycles 770system.cpu.dcache.ReadReq_mshr_miss_latency::total 101472833000 # number of ReadReq MSHR miss cycles 771system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 102652778000 # number of WriteReq MSHR miss cycles 772system.cpu.dcache.WriteReq_mshr_miss_latency::total 102652778000 # number of WriteReq MSHR miss cycles 773system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 27900020500 # number of SoftPFReq MSHR miss cycles 774system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 27900020500 # number of SoftPFReq MSHR miss cycles 775system.cpu.dcache.WriteLineReq_mshr_miss_latency::cpu.data 26619580500 # number of WriteLineReq MSHR miss cycles 776system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 26619580500 # number of WriteLineReq MSHR miss cycles 777system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3678632000 # number of LoadLockedReq MSHR miss cycles 778system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3678632000 # number of LoadLockedReq MSHR miss cycles 779system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 82000 # number of StoreCondReq MSHR miss cycles 780system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 82000 # number of StoreCondReq MSHR miss cycles 781system.cpu.dcache.demand_mshr_miss_latency::cpu.data 230745191500 # number of demand (read+write) MSHR miss cycles 782system.cpu.dcache.demand_mshr_miss_latency::total 230745191500 # number of demand (read+write) MSHR miss cycles 783system.cpu.dcache.overall_mshr_miss_latency::cpu.data 258645212000 # number of overall MSHR miss cycles 784system.cpu.dcache.overall_mshr_miss_latency::total 258645212000 # number of overall MSHR miss cycles 785system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 6209488500 # number of ReadReq MSHR uncacheable cycles 786system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 6209488500 # number of ReadReq MSHR uncacheable cycles 787system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 6209488500 # number of overall MSHR uncacheable cycles 788system.cpu.dcache.overall_mshr_uncacheable_latency::total 6209488500 # number of overall MSHR uncacheable cycles 789system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033693 # mshr miss rate for ReadReq accesses 790system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033693 # mshr miss rate for ReadReq accesses 791system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015818 # mshr miss rate for WriteReq accesses 792system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015818 # mshr miss rate for WriteReq accesses 793system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.747554 # mshr miss rate for SoftPFReq accesses 794system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.747554 # mshr miss rate for SoftPFReq accesses 795system.cpu.dcache.WriteLineReq_mshr_miss_rate::cpu.data 0.787662 # mshr miss rate for WriteLineReq accesses 796system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 0.787662 # mshr miss rate for WriteLineReq accesses 797system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.055284 # mshr miss rate for LoadLockedReq accesses 798system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.055284 # mshr miss rate for LoadLockedReq accesses 799system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses 800system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses 801system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.028740 # mshr miss rate for demand accesses 802system.cpu.dcache.demand_mshr_miss_rate::total 0.028740 # mshr miss rate for demand accesses 803system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.033171 # mshr miss rate for overall accesses 804system.cpu.dcache.overall_mshr_miss_rate::total 0.033171 # mshr miss rate for overall accesses 805system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16475.681553 # average ReadReq mshr miss latency 806system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16475.681553 # average ReadReq mshr miss latency 807system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39681.373955 # average WriteReq mshr miss latency 808system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39681.373955 # average WriteReq mshr miss latency 809system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 17292.300717 # average SoftPFReq mshr miss latency 810system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 17292.300717 # average SoftPFReq mshr miss latency 811system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::cpu.data 21230.275153 # average WriteLineReq mshr miss latency 812system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 21230.275153 # average WriteLineReq mshr miss latency 813system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14373.081086 # average LoadLockedReq mshr miss latency 814system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14373.081086 # average LoadLockedReq mshr miss latency 815system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82000 # average StoreCondReq mshr miss latency 816system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82000 # average StoreCondReq mshr miss latency 817system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23075.160639 # average overall mshr miss latency 818system.cpu.dcache.demand_avg_mshr_miss_latency::total 23075.160639 # average overall mshr miss latency 819system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22271.737972 # average overall mshr miss latency 820system.cpu.dcache.overall_avg_mshr_miss_latency::total 22271.737972 # average overall mshr miss latency 821system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 184762.214354 # average ReadReq mshr uncacheable latency 822system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184762.214354 # average ReadReq mshr uncacheable latency 823system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 92364.617421 # average overall mshr uncacheable latency 824system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 92364.617421 # average overall mshr uncacheable latency 825system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 826system.cpu.icache.tags.replacements 25121901 # number of replacements 827system.cpu.icache.tags.tagsinuse 511.967924 # Cycle average of tags in use 828system.cpu.icache.tags.total_refs 341735076 # Total number of references to valid blocks. 829system.cpu.icache.tags.sampled_refs 25122413 # Sample count of references to valid blocks. 830system.cpu.icache.tags.avg_refs 13.602797 # Average number of references to valid blocks. 831system.cpu.icache.tags.warmup_cycle 17226930500 # Cycle when the warmup percentage was hit. 832system.cpu.icache.tags.occ_blocks::cpu.inst 511.967924 # Average occupied blocks per requestor 833system.cpu.icache.tags.occ_percent::cpu.inst 0.999937 # Average percentage of cache occupancy 834system.cpu.icache.tags.occ_percent::total 0.999937 # Average percentage of cache occupancy 835system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 836system.cpu.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id 837system.cpu.icache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id 838system.cpu.icache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id 839system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 840system.cpu.icache.tags.tag_accesses 391979921 # Number of tag accesses 841system.cpu.icache.tags.data_accesses 391979921 # Number of data accesses 842system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 843system.cpu.icache.ReadReq_hits::cpu.inst 341735076 # number of ReadReq hits 844system.cpu.icache.ReadReq_hits::total 341735076 # number of ReadReq hits 845system.cpu.icache.demand_hits::cpu.inst 341735076 # number of demand (read+write) hits 846system.cpu.icache.demand_hits::total 341735076 # number of demand (read+write) hits 847system.cpu.icache.overall_hits::cpu.inst 341735076 # number of overall hits 848system.cpu.icache.overall_hits::total 341735076 # number of overall hits 849system.cpu.icache.ReadReq_misses::cpu.inst 25122423 # number of ReadReq misses 850system.cpu.icache.ReadReq_misses::total 25122423 # number of ReadReq misses 851system.cpu.icache.demand_misses::cpu.inst 25122423 # number of demand (read+write) misses 852system.cpu.icache.demand_misses::total 25122423 # number of demand (read+write) misses 853system.cpu.icache.overall_misses::cpu.inst 25122423 # number of overall misses 854system.cpu.icache.overall_misses::total 25122423 # number of overall misses 855system.cpu.icache.ReadReq_miss_latency::cpu.inst 337360587000 # number of ReadReq miss cycles 856system.cpu.icache.ReadReq_miss_latency::total 337360587000 # number of ReadReq miss cycles 857system.cpu.icache.demand_miss_latency::cpu.inst 337360587000 # number of demand (read+write) miss cycles 858system.cpu.icache.demand_miss_latency::total 337360587000 # number of demand (read+write) miss cycles 859system.cpu.icache.overall_miss_latency::cpu.inst 337360587000 # number of overall miss cycles 860system.cpu.icache.overall_miss_latency::total 337360587000 # number of overall miss cycles 861system.cpu.icache.ReadReq_accesses::cpu.inst 366857499 # number of ReadReq accesses(hits+misses) 862system.cpu.icache.ReadReq_accesses::total 366857499 # number of ReadReq accesses(hits+misses) 863system.cpu.icache.demand_accesses::cpu.inst 366857499 # number of demand (read+write) accesses 864system.cpu.icache.demand_accesses::total 366857499 # number of demand (read+write) accesses 865system.cpu.icache.overall_accesses::cpu.inst 366857499 # number of overall (read+write) accesses 866system.cpu.icache.overall_accesses::total 366857499 # number of overall (read+write) accesses 867system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.068480 # miss rate for ReadReq accesses 868system.cpu.icache.ReadReq_miss_rate::total 0.068480 # miss rate for ReadReq accesses 869system.cpu.icache.demand_miss_rate::cpu.inst 0.068480 # miss rate for demand accesses 870system.cpu.icache.demand_miss_rate::total 0.068480 # miss rate for demand accesses 871system.cpu.icache.overall_miss_rate::cpu.inst 0.068480 # miss rate for overall accesses 872system.cpu.icache.overall_miss_rate::total 0.068480 # miss rate for overall accesses 873system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13428.664385 # average ReadReq miss latency 874system.cpu.icache.ReadReq_avg_miss_latency::total 13428.664385 # average ReadReq miss latency 875system.cpu.icache.demand_avg_miss_latency::cpu.inst 13428.664385 # average overall miss latency 876system.cpu.icache.demand_avg_miss_latency::total 13428.664385 # average overall miss latency 877system.cpu.icache.overall_avg_miss_latency::cpu.inst 13428.664385 # average overall miss latency 878system.cpu.icache.overall_avg_miss_latency::total 13428.664385 # average overall miss latency 879system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 880system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 881system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 882system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 883system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 884system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 885system.cpu.icache.writebacks::writebacks 25121901 # number of writebacks 886system.cpu.icache.writebacks::total 25121901 # number of writebacks 887system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25122423 # number of ReadReq MSHR misses 888system.cpu.icache.ReadReq_mshr_misses::total 25122423 # number of ReadReq MSHR misses 889system.cpu.icache.demand_mshr_misses::cpu.inst 25122423 # number of demand (read+write) MSHR misses 890system.cpu.icache.demand_mshr_misses::total 25122423 # number of demand (read+write) MSHR misses 891system.cpu.icache.overall_mshr_misses::cpu.inst 25122423 # number of overall MSHR misses 892system.cpu.icache.overall_mshr_misses::total 25122423 # number of overall MSHR misses 893system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 4291 # number of ReadReq MSHR uncacheable 894system.cpu.icache.ReadReq_mshr_uncacheable::total 4291 # number of ReadReq MSHR uncacheable 895system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 4291 # number of overall MSHR uncacheable misses 896system.cpu.icache.overall_mshr_uncacheable_misses::total 4291 # number of overall MSHR uncacheable misses 897system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 312238165000 # number of ReadReq MSHR miss cycles 898system.cpu.icache.ReadReq_mshr_miss_latency::total 312238165000 # number of ReadReq MSHR miss cycles 899system.cpu.icache.demand_mshr_miss_latency::cpu.inst 312238165000 # number of demand (read+write) MSHR miss cycles 900system.cpu.icache.demand_mshr_miss_latency::total 312238165000 # number of demand (read+write) MSHR miss cycles 901system.cpu.icache.overall_mshr_miss_latency::cpu.inst 312238165000 # number of overall MSHR miss cycles 902system.cpu.icache.overall_mshr_miss_latency::total 312238165000 # number of overall MSHR miss cycles 903system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 366344000 # number of ReadReq MSHR uncacheable cycles 904system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 366344000 # number of ReadReq MSHR uncacheable cycles 905system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 366344000 # number of overall MSHR uncacheable cycles 906system.cpu.icache.overall_mshr_uncacheable_latency::total 366344000 # number of overall MSHR uncacheable cycles 907system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.068480 # mshr miss rate for ReadReq accesses 908system.cpu.icache.ReadReq_mshr_miss_rate::total 0.068480 # mshr miss rate for ReadReq accesses 909system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.068480 # mshr miss rate for demand accesses 910system.cpu.icache.demand_mshr_miss_rate::total 0.068480 # mshr miss rate for demand accesses 911system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.068480 # mshr miss rate for overall accesses 912system.cpu.icache.overall_mshr_miss_rate::total 0.068480 # mshr miss rate for overall accesses 913system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12428.664425 # average ReadReq mshr miss latency 914system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12428.664425 # average ReadReq mshr miss latency 915system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12428.664425 # average overall mshr miss latency 916system.cpu.icache.demand_avg_mshr_miss_latency::total 12428.664425 # average overall mshr miss latency 917system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12428.664425 # average overall mshr miss latency 918system.cpu.icache.overall_avg_mshr_miss_latency::total 12428.664425 # average overall mshr miss latency 919system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 85374.970869 # average ReadReq mshr uncacheable latency 920system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 85374.970869 # average ReadReq mshr uncacheable latency 921system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 85374.970869 # average overall mshr uncacheable latency 922system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 85374.970869 # average overall mshr uncacheable latency 923system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 924system.cpu.l2cache.tags.replacements 1823253 # number of replacements 925system.cpu.l2cache.tags.tagsinuse 65445.001874 # Cycle average of tags in use 926system.cpu.l2cache.tags.total_refs 72021344 # Total number of references to valid blocks. 927system.cpu.l2cache.tags.sampled_refs 1886697 # Sample count of references to valid blocks. 928system.cpu.l2cache.tags.avg_refs 38.173244 # Average number of references to valid blocks. 929system.cpu.l2cache.tags.warmup_cycle 2050526000 # Cycle when the warmup percentage was hit. 930system.cpu.l2cache.tags.occ_blocks::writebacks 9044.623983 # Average occupied blocks per requestor 931system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 456.585654 # Average occupied blocks per requestor 932system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 458.430752 # Average occupied blocks per requestor 933system.cpu.l2cache.tags.occ_blocks::cpu.inst 7955.769070 # Average occupied blocks per requestor 934system.cpu.l2cache.tags.occ_blocks::cpu.data 47529.592416 # Average occupied blocks per requestor 935system.cpu.l2cache.tags.occ_percent::writebacks 0.138010 # Average percentage of cache occupancy 936system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.006967 # Average percentage of cache occupancy 937system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006995 # Average percentage of cache occupancy 938system.cpu.l2cache.tags.occ_percent::cpu.inst 0.121395 # Average percentage of cache occupancy 939system.cpu.l2cache.tags.occ_percent::cpu.data 0.725244 # Average percentage of cache occupancy 940system.cpu.l2cache.tags.occ_percent::total 0.998611 # Average percentage of cache occupancy 941system.cpu.l2cache.tags.occ_task_id_blocks::1023 236 # Occupied blocks per task id 942system.cpu.l2cache.tags.occ_task_id_blocks::1024 63208 # Occupied blocks per task id 943system.cpu.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id 944system.cpu.l2cache.tags.age_task_id_blocks_1023::4 233 # Occupied blocks per task id 945system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 946system.cpu.l2cache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id 947system.cpu.l2cache.tags.age_task_id_blocks_1024::2 882 # Occupied blocks per task id 948system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5962 # Occupied blocks per task id 949system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56005 # Occupied blocks per task id 950system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003601 # Percentage of cache occupancy per task id 951system.cpu.l2cache.tags.occ_task_id_percent::1024 0.964478 # Percentage of cache occupancy per task id 952system.cpu.l2cache.tags.tag_accesses 604501194 # Number of tag accesses 953system.cpu.l2cache.tags.data_accesses 604501194 # Number of data accesses 954system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 955system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 1016248 # number of ReadReq hits 956system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 265268 # number of ReadReq hits 957system.cpu.l2cache.ReadReq_hits::total 1281516 # number of ReadReq hits 958system.cpu.l2cache.WritebackDirty_hits::writebacks 9058668 # number of WritebackDirty hits 959system.cpu.l2cache.WritebackDirty_hits::total 9058668 # number of WritebackDirty hits 960system.cpu.l2cache.WritebackClean_hits::writebacks 25118324 # number of WritebackClean hits 961system.cpu.l2cache.WritebackClean_hits::total 25118324 # number of WritebackClean hits 962system.cpu.l2cache.UpgradeReq_hits::cpu.data 31922 # number of UpgradeReq hits 963system.cpu.l2cache.UpgradeReq_hits::total 31922 # number of UpgradeReq hits 964system.cpu.l2cache.ReadExReq_hits::cpu.data 1691397 # number of ReadExReq hits 965system.cpu.l2cache.ReadExReq_hits::total 1691397 # number of ReadExReq hits 966system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 25012596 # number of ReadCleanReq hits 967system.cpu.l2cache.ReadCleanReq_hits::total 25012596 # number of ReadCleanReq hits 968system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7660453 # number of ReadSharedReq hits 969system.cpu.l2cache.ReadSharedReq_hits::total 7660453 # number of ReadSharedReq hits 970system.cpu.l2cache.InvalidateReq_hits::cpu.data 687915 # number of InvalidateReq hits 971system.cpu.l2cache.InvalidateReq_hits::total 687915 # number of InvalidateReq hits 972system.cpu.l2cache.demand_hits::cpu.dtb.walker 1016248 # number of demand (read+write) hits 973system.cpu.l2cache.demand_hits::cpu.itb.walker 265268 # number of demand (read+write) hits 974system.cpu.l2cache.demand_hits::cpu.inst 25012596 # number of demand (read+write) hits 975system.cpu.l2cache.demand_hits::cpu.data 9351850 # number of demand (read+write) hits 976system.cpu.l2cache.demand_hits::total 35645962 # number of demand (read+write) hits 977system.cpu.l2cache.overall_hits::cpu.dtb.walker 1016248 # number of overall hits 978system.cpu.l2cache.overall_hits::cpu.itb.walker 265268 # number of overall hits 979system.cpu.l2cache.overall_hits::cpu.inst 25012596 # number of overall hits 980system.cpu.l2cache.overall_hits::cpu.data 9351850 # number of overall hits 981system.cpu.l2cache.overall_hits::total 35645962 # number of overall hits 982system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7529 # number of ReadReq misses 983system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6105 # number of ReadReq misses 984system.cpu.l2cache.ReadReq_misses::total 13634 # number of ReadReq misses 985system.cpu.l2cache.UpgradeReq_misses::cpu.data 3989 # number of UpgradeReq misses 986system.cpu.l2cache.UpgradeReq_misses::total 3989 # number of UpgradeReq misses 987system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses 988system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses 989system.cpu.l2cache.ReadExReq_misses::cpu.data 859845 # number of ReadExReq misses 990system.cpu.l2cache.ReadExReq_misses::total 859845 # number of ReadExReq misses 991system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 109826 # number of ReadCleanReq misses 992system.cpu.l2cache.ReadCleanReq_misses::total 109826 # number of ReadCleanReq misses 993system.cpu.l2cache.ReadSharedReq_misses::cpu.data 367641 # number of ReadSharedReq misses 994system.cpu.l2cache.ReadSharedReq_misses::total 367641 # number of ReadSharedReq misses 995system.cpu.l2cache.InvalidateReq_misses::cpu.data 565935 # number of InvalidateReq misses 996system.cpu.l2cache.InvalidateReq_misses::total 565935 # number of InvalidateReq misses 997system.cpu.l2cache.demand_misses::cpu.dtb.walker 7529 # number of demand (read+write) misses 998system.cpu.l2cache.demand_misses::cpu.itb.walker 6105 # number of demand (read+write) misses 999system.cpu.l2cache.demand_misses::cpu.inst 109826 # number of demand (read+write) misses 1000system.cpu.l2cache.demand_misses::cpu.data 1227486 # number of demand (read+write) misses 1001system.cpu.l2cache.demand_misses::total 1350946 # number of demand (read+write) misses 1002system.cpu.l2cache.overall_misses::cpu.dtb.walker 7529 # number of overall misses 1003system.cpu.l2cache.overall_misses::cpu.itb.walker 6105 # number of overall misses 1004system.cpu.l2cache.overall_misses::cpu.inst 109826 # number of overall misses 1005system.cpu.l2cache.overall_misses::cpu.data 1227486 # number of overall misses 1006system.cpu.l2cache.overall_misses::total 1350946 # number of overall misses 1007system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 877005000 # number of ReadReq miss cycles 1008system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 644825000 # number of ReadReq miss cycles 1009system.cpu.l2cache.ReadReq_miss_latency::total 1521830000 # number of ReadReq miss cycles 1010system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 72113000 # number of UpgradeReq miss cycles 1011system.cpu.l2cache.UpgradeReq_miss_latency::total 72113000 # number of UpgradeReq miss cycles 1012system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 80500 # number of SCUpgradeReq miss cycles 1013system.cpu.l2cache.SCUpgradeReq_miss_latency::total 80500 # number of SCUpgradeReq miss cycles 1014system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 80528268500 # number of ReadExReq miss cycles 1015system.cpu.l2cache.ReadExReq_miss_latency::total 80528268500 # number of ReadExReq miss cycles 1016system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 11692993000 # number of ReadCleanReq miss cycles 1017system.cpu.l2cache.ReadCleanReq_miss_latency::total 11692993000 # number of ReadCleanReq miss cycles 1018system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 40327835000 # number of ReadSharedReq miss cycles 1019system.cpu.l2cache.ReadSharedReq_miss_latency::total 40327835000 # number of ReadSharedReq miss cycles 1020system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 877005000 # number of demand (read+write) miss cycles 1021system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 644825000 # number of demand (read+write) miss cycles 1022system.cpu.l2cache.demand_miss_latency::cpu.inst 11692993000 # number of demand (read+write) miss cycles 1023system.cpu.l2cache.demand_miss_latency::cpu.data 120856103500 # number of demand (read+write) miss cycles 1024system.cpu.l2cache.demand_miss_latency::total 134070926500 # number of demand (read+write) miss cycles 1025system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 877005000 # number of overall miss cycles 1026system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 644825000 # number of overall miss cycles 1027system.cpu.l2cache.overall_miss_latency::cpu.inst 11692993000 # number of overall miss cycles 1028system.cpu.l2cache.overall_miss_latency::cpu.data 120856103500 # number of overall miss cycles 1029system.cpu.l2cache.overall_miss_latency::total 134070926500 # number of overall miss cycles 1030system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 1023777 # number of ReadReq accesses(hits+misses) 1031system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 271373 # number of ReadReq accesses(hits+misses) 1032system.cpu.l2cache.ReadReq_accesses::total 1295150 # number of ReadReq accesses(hits+misses) 1033system.cpu.l2cache.WritebackDirty_accesses::writebacks 9058668 # number of WritebackDirty accesses(hits+misses) 1034system.cpu.l2cache.WritebackDirty_accesses::total 9058668 # number of WritebackDirty accesses(hits+misses) 1035system.cpu.l2cache.WritebackClean_accesses::writebacks 25118324 # number of WritebackClean accesses(hits+misses) 1036system.cpu.l2cache.WritebackClean_accesses::total 25118324 # number of WritebackClean accesses(hits+misses) 1037system.cpu.l2cache.UpgradeReq_accesses::cpu.data 35911 # number of UpgradeReq accesses(hits+misses) 1038system.cpu.l2cache.UpgradeReq_accesses::total 35911 # number of UpgradeReq accesses(hits+misses) 1039system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) 1040system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) 1041system.cpu.l2cache.ReadExReq_accesses::cpu.data 2551242 # number of ReadExReq accesses(hits+misses) 1042system.cpu.l2cache.ReadExReq_accesses::total 2551242 # number of ReadExReq accesses(hits+misses) 1043system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 25122422 # number of ReadCleanReq accesses(hits+misses) 1044system.cpu.l2cache.ReadCleanReq_accesses::total 25122422 # number of ReadCleanReq accesses(hits+misses) 1045system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 8028094 # number of ReadSharedReq accesses(hits+misses) 1046system.cpu.l2cache.ReadSharedReq_accesses::total 8028094 # number of ReadSharedReq accesses(hits+misses) 1047system.cpu.l2cache.InvalidateReq_accesses::cpu.data 1253850 # number of InvalidateReq accesses(hits+misses) 1048system.cpu.l2cache.InvalidateReq_accesses::total 1253850 # number of InvalidateReq accesses(hits+misses) 1049system.cpu.l2cache.demand_accesses::cpu.dtb.walker 1023777 # number of demand (read+write) accesses 1050system.cpu.l2cache.demand_accesses::cpu.itb.walker 271373 # number of demand (read+write) accesses 1051system.cpu.l2cache.demand_accesses::cpu.inst 25122422 # number of demand (read+write) accesses 1052system.cpu.l2cache.demand_accesses::cpu.data 10579336 # number of demand (read+write) accesses 1053system.cpu.l2cache.demand_accesses::total 36996908 # number of demand (read+write) accesses 1054system.cpu.l2cache.overall_accesses::cpu.dtb.walker 1023777 # number of overall (read+write) accesses 1055system.cpu.l2cache.overall_accesses::cpu.itb.walker 271373 # number of overall (read+write) accesses 1056system.cpu.l2cache.overall_accesses::cpu.inst 25122422 # number of overall (read+write) accesses 1057system.cpu.l2cache.overall_accesses::cpu.data 10579336 # number of overall (read+write) accesses 1058system.cpu.l2cache.overall_accesses::total 36996908 # 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miss rate for ReadCleanReq accesses 1070system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.045794 # miss rate for ReadSharedReq accesses 1071system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.045794 # miss rate for ReadSharedReq accesses 1072system.cpu.l2cache.InvalidateReq_miss_rate::cpu.data 0.451358 # miss rate for InvalidateReq accesses 1073system.cpu.l2cache.InvalidateReq_miss_rate::total 0.451358 # miss rate for InvalidateReq accesses 1074system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.007354 # miss rate for demand accesses 1075system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022497 # miss rate for demand accesses 1076system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004372 # miss rate for demand accesses 1077system.cpu.l2cache.demand_miss_rate::cpu.data 0.116027 # miss rate for demand accesses 1078system.cpu.l2cache.demand_miss_rate::total 0.036515 # miss rate for demand accesses 1079system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.007354 # miss rate for overall accesses 1080system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022497 # miss rate for overall accesses 1081system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004372 # miss rate for overall accesses 1082system.cpu.l2cache.overall_miss_rate::cpu.data 0.116027 # miss rate for overall accesses 1083system.cpu.l2cache.overall_miss_rate::total 0.036515 # miss rate for overall accesses 1084system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 116483.596759 # average ReadReq miss latency 1085system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 105622.440622 # average ReadReq miss latency 1086system.cpu.l2cache.ReadReq_avg_miss_latency::total 111620.214170 # average ReadReq miss latency 1087system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 18077.964402 # average UpgradeReq miss latency 1088system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 18077.964402 # average UpgradeReq miss latency 1089system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80500 # average SCUpgradeReq miss latency 1090system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80500 # 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number of overall MSHR hits 1123system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits 1124system.cpu.l2cache.overall_mshr_hits::total 24 # number of overall MSHR hits 1125system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7529 # number of ReadReq MSHR misses 1126system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6105 # number of ReadReq MSHR misses 1127system.cpu.l2cache.ReadReq_mshr_misses::total 13634 # number of ReadReq MSHR misses 1128system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1 # number of CleanEvict MSHR misses 1129system.cpu.l2cache.CleanEvict_mshr_misses::total 1 # number of CleanEvict MSHR misses 1130system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 3989 # number of UpgradeReq MSHR misses 1131system.cpu.l2cache.UpgradeReq_mshr_misses::total 3989 # number of UpgradeReq MSHR misses 1132system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses 1133system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # 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number of overall MSHR miss cycles 1183system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 108580170549 # number of overall MSHR miss cycles 1184system.cpu.l2cache.overall_mshr_miss_latency::total 120560235052 # number of overall MSHR miss cycles 1185system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 299820000 # number of ReadReq MSHR uncacheable cycles 1186system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5789264500 # number of ReadReq MSHR uncacheable cycles 1187system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6089084500 # number of ReadReq MSHR uncacheable cycles 1188system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 299820000 # number of overall MSHR uncacheable cycles 1189system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 5789264500 # number of overall MSHR uncacheable cycles 1190system.cpu.l2cache.overall_mshr_uncacheable_latency::total 6089084500 # number of overall MSHR uncacheable cycles 1191system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.007354 # mshr miss rate for ReadReq accesses 1192system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.022497 # mshr miss rate for ReadReq accesses 1193system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010527 # mshr miss rate for ReadReq accesses 1194system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 1195system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 1196system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.111080 # mshr miss rate for UpgradeReq accesses 1197system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.111080 # mshr miss rate for UpgradeReq accesses 1198system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses 1199system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1200system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.337030 # mshr miss rate for ReadExReq accesses 1201system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.337030 # mshr miss rate for ReadExReq accesses 1202system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.004372 # mshr miss rate for ReadCleanReq accesses 1203system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.004372 # mshr miss rate for ReadCleanReq accesses 1204system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.045792 # mshr miss rate for ReadSharedReq accesses 1205system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.045792 # mshr miss rate for ReadSharedReq accesses 1206system.cpu.l2cache.InvalidateReq_mshr_miss_rate::cpu.data 0.451358 # mshr miss rate for InvalidateReq accesses 1207system.cpu.l2cache.InvalidateReq_mshr_miss_rate::total 0.451358 # mshr miss rate for InvalidateReq accesses 1208system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.007354 # mshr miss rate for demand accesses 1209system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.022497 # mshr miss rate for demand accesses 1210system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004372 # mshr miss rate for demand accesses 1211system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.116025 # mshr miss rate for demand accesses 1212system.cpu.l2cache.demand_mshr_miss_rate::total 0.036514 # mshr miss rate for demand accesses 1213system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.007354 # mshr miss rate for overall accesses 1214system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.022497 # mshr miss rate for overall accesses 1215system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004372 # mshr miss rate for overall accesses 1216system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.116025 # mshr miss rate for overall accesses 1217system.cpu.l2cache.overall_mshr_miss_rate::total 0.036514 # mshr miss rate for overall accesses 1218system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 106483.596759 # average ReadReq mshr miss latency 1219system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 95622.440622 # average ReadReq mshr miss latency 1220system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 101620.214170 # average ReadReq mshr miss latency 1221system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 19087.365254 # average UpgradeReq mshr miss latency 1222system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19087.365254 # average UpgradeReq mshr miss latency 1223system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70500 # average SCUpgradeReq mshr miss latency 1224system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70500 # average SCUpgradeReq mshr miss latency 1225system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 83654.399923 # average ReadExReq mshr miss latency 1226system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 83654.399923 # average ReadExReq mshr miss latency 1227system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 96468.663525 # average ReadCleanReq mshr miss latency 1228system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 96468.663525 # average ReadCleanReq mshr miss latency 1229system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 99696.569130 # average ReadSharedReq mshr miss latency 1230system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 99696.569130 # average ReadSharedReq mshr miss latency 1231system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu.data 20598.429150 # average InvalidateReq mshr miss latency 1232system.cpu.l2cache.InvalidateReq_avg_mshr_miss_latency::total 20598.429150 # average InvalidateReq mshr miss latency 1233system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 106483.596759 # average overall mshr miss latency 1234system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 95622.440622 # average overall mshr miss latency 1235system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 96468.663525 # average overall mshr miss latency 1236system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88458.945068 # average overall mshr miss latency 1237system.cpu.l2cache.demand_avg_mshr_miss_latency::total 89242.928202 # average overall mshr miss latency 1238system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 106483.596759 # average overall mshr miss latency 1239system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 95622.440622 # average overall mshr miss latency 1240system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 96468.663525 # average overall mshr miss latency 1241system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88458.945068 # average overall mshr miss latency 1242system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89242.928202 # average overall mshr miss latency 1243system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 69871.824749 # average ReadReq mshr uncacheable latency 1244system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 172258.524756 # average ReadReq mshr uncacheable latency 1245system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 160666.099369 # average ReadReq mshr uncacheable latency 1246system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 69871.824749 # average overall mshr uncacheable latency 1247system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 86113.888558 # average overall mshr uncacheable latency 1248system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 85139.396524 # average overall mshr uncacheable latency 1249system.cpu.toL2Bus.snoop_filter.tot_requests 74678701 # Total number of requests made to the snoop filter. 1250system.cpu.toL2Bus.snoop_filter.hit_single_requests 37723093 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1251system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4208 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1252system.cpu.toL2Bus.snoop_filter.tot_snoops 1985 # Total number of snoops made to the snoop filter. 1253system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1985 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1254system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1255system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1256system.cpu.toL2Bus.trans_dist::ReadReq 1826986 # Transaction distribution 1257system.cpu.toL2Bus.trans_dist::ReadResp 34978302 # Transaction distribution 1258system.cpu.toL2Bus.trans_dist::WriteReq 33620 # Transaction distribution 1259system.cpu.toL2Bus.trans_dist::WriteResp 33620 # Transaction distribution 1260system.cpu.toL2Bus.trans_dist::WritebackDirty 10621415 # Transaction distribution 1261system.cpu.toL2Bus.trans_dist::WritebackClean 25121901 # Transaction distribution 1262system.cpu.toL2Bus.trans_dist::CleanEvict 3034475 # Transaction distribution 1263system.cpu.toL2Bus.trans_dist::UpgradeReq 35914 # Transaction distribution 1264system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution 1265system.cpu.toL2Bus.trans_dist::UpgradeResp 35915 # Transaction distribution 1266system.cpu.toL2Bus.trans_dist::ReadExReq 2551242 # Transaction distribution 1267system.cpu.toL2Bus.trans_dist::ReadExResp 2551242 # Transaction distribution 1268system.cpu.toL2Bus.trans_dist::ReadCleanReq 25122423 # Transaction distribution 1269system.cpu.toL2Bus.trans_dist::ReadSharedReq 8030982 # Transaction distribution 1270system.cpu.toL2Bus.trans_dist::InvalidateReq 1284314 # Transaction distribution 1271system.cpu.toL2Bus.trans_dist::InvalidateResp 1253880 # Transaction distribution 1272system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 75375327 # Packet count per connected master and slave (bytes) 1273system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 35706122 # Packet count per connected master and slave (bytes) 1274system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 683214 # Packet count per connected master and slave (bytes) 1275system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2401023 # Packet count per connected master and slave (bytes) 1276system.cpu.toL2Bus.pkt_count::total 114165686 # Packet count per connected master and slave (bytes) 1277system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3215911232 # Cumulative packet size per connected master and slave (bytes) 1278system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1257073518 # Cumulative packet size per connected master and slave (bytes) 1279system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2170984 # Cumulative packet size per connected master and slave (bytes) 1280system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 8190216 # Cumulative packet size per connected master and slave (bytes) 1281system.cpu.toL2Bus.pkt_size::total 4483345950 # Cumulative packet size per connected master and slave (bytes) 1282system.cpu.toL2Bus.snoops 2351379 # Total snoops (count) 1283system.cpu.toL2Bus.snoopTraffic 104018568 # Total snoop traffic (bytes) 1284system.cpu.toL2Bus.snoop_fanout::samples 40708735 # Request fanout histogram 1285system.cpu.toL2Bus.snoop_fanout::mean 0.018149 # Request fanout histogram 1286system.cpu.toL2Bus.snoop_fanout::stdev 0.133491 # Request fanout histogram 1287system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1288system.cpu.toL2Bus.snoop_fanout::0 39969899 98.19% 98.19% # Request fanout histogram 1289system.cpu.toL2Bus.snoop_fanout::1 738836 1.81% 100.00% # Request fanout histogram 1290system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1291system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1292system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1293system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1294system.cpu.toL2Bus.snoop_fanout::total 40708735 # Request fanout histogram 1295system.cpu.toL2Bus.reqLayer0.occupancy 72100713496 # Layer occupancy (ticks) 1296system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1297system.cpu.toL2Bus.snoopLayer0.occupancy 1533365 # Layer occupancy (ticks) 1298system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1299system.cpu.toL2Bus.respLayer0.occupancy 37694541038 # Layer occupancy (ticks) 1300system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 1301system.cpu.toL2Bus.respLayer1.occupancy 16565349400 # Layer occupancy (ticks) 1302system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1303system.cpu.toL2Bus.respLayer2.occupancy 411872936 # Layer occupancy (ticks) 1304system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1305system.cpu.toL2Bus.respLayer3.occupancy 1377265960 # Layer occupancy (ticks) 1306system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1307system.iobus.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1308system.iobus.trans_dist::ReadReq 40237 # Transaction distribution 1309system.iobus.trans_dist::ReadResp 40237 # Transaction distribution 1310system.iobus.trans_dist::WriteReq 136485 # Transaction distribution 1311system.iobus.trans_dist::WriteResp 136485 # Transaction distribution 1312system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47478 # Packet count per connected master and slave (bytes) 1313system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 1314system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 1315system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 1316system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 1317system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 1318system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 1319system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 1320system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 1321system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 1322system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 1323system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 1324system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 1325system.iobus.pkt_count_system.bridge.master::total 122360 # Packet count per connected master and slave (bytes) 1326system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231004 # Packet count per connected master and slave (bytes) 1327system.iobus.pkt_count_system.realview.ide.dma::total 231004 # Packet count per connected master and slave (bytes) 1328system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 1329system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 1330system.iobus.pkt_count::total 353444 # Packet count per connected master and slave (bytes) 1331system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47498 # Cumulative packet size per connected master and slave (bytes) 1332system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 1333system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 1334system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 1335system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 1336system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 1337system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1338system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1339system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1340system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 1341system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 1342system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 1343system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 1344system.iobus.pkt_size_system.bridge.master::total 155490 # Cumulative packet size per connected master and slave (bytes) 1345system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334448 # Cumulative packet size per connected master and slave (bytes) 1346system.iobus.pkt_size_system.realview.ide.dma::total 7334448 # Cumulative packet size per connected master and slave (bytes) 1347system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 1348system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 1349system.iobus.pkt_size::total 7492024 # Cumulative packet size per connected master and slave (bytes) 1350system.iobus.reqLayer0.occupancy 37126500 # Layer occupancy (ticks) 1351system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 1352system.iobus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) 1353system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 1354system.iobus.reqLayer2.occupancy 334500 # Layer occupancy (ticks) 1355system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 1356system.iobus.reqLayer3.occupancy 10000 # Layer occupancy (ticks) 1357system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 1358system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) 1359system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 1360system.iobus.reqLayer10.occupancy 10000 # Layer occupancy (ticks) 1361system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 1362system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks) 1363system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 1364system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) 1365system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 1366system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) 1367system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 1368system.iobus.reqLayer16.occupancy 16000 # Layer occupancy (ticks) 1369system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 1370system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) 1371system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 1372system.iobus.reqLayer23.occupancy 25225000 # Layer occupancy (ticks) 1373system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 1374system.iobus.reqLayer24.occupancy 36490500 # Layer occupancy (ticks) 1375system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 1376system.iobus.reqLayer25.occupancy 569036756 # Layer occupancy (ticks) 1377system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 1378system.iobus.respLayer0.occupancy 92542000 # Layer occupancy (ticks) 1379system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 1380system.iobus.respLayer3.occupancy 147764000 # Layer occupancy (ticks) 1381system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 1382system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 1383system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 1384system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1385system.iocache.tags.replacements 115484 # number of replacements 1386system.iocache.tags.tagsinuse 10.444243 # Cycle average of tags in use 1387system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 1388system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. 1389system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 1390system.iocache.tags.warmup_cycle 13137487927000 # Cycle when the warmup percentage was hit. 1391system.iocache.tags.occ_blocks::realview.ethernet 5.867221 # Average occupied blocks per requestor 1392system.iocache.tags.occ_blocks::realview.ide 4.577022 # Average occupied blocks per requestor 1393system.iocache.tags.occ_percent::realview.ethernet 0.366701 # Average percentage of cache occupancy 1394system.iocache.tags.occ_percent::realview.ide 0.286064 # Average percentage of cache occupancy 1395system.iocache.tags.occ_percent::total 0.652765 # Average percentage of cache occupancy 1396system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 1397system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1398system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 1399system.iocache.tags.tag_accesses 1039875 # Number of tag accesses 1400system.iocache.tags.data_accesses 1039875 # Number of data accesses 1401system.iocache.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1402system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 1403system.iocache.ReadReq_misses::realview.ide 8838 # number of ReadReq misses 1404system.iocache.ReadReq_misses::total 8875 # number of ReadReq misses 1405system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 1406system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 1407system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses 1408system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses 1409system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 1410system.iocache.demand_misses::realview.ide 115502 # number of demand (read+write) misses 1411system.iocache.demand_misses::total 115542 # number of demand (read+write) misses 1412system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 1413system.iocache.overall_misses::realview.ide 115502 # number of overall misses 1414system.iocache.overall_misses::total 115542 # number of overall misses 1415system.iocache.ReadReq_miss_latency::realview.ethernet 5086000 # number of ReadReq miss cycles 1416system.iocache.ReadReq_miss_latency::realview.ide 2014766150 # number of ReadReq miss cycles 1417system.iocache.ReadReq_miss_latency::total 2019852150 # number of ReadReq miss cycles 1418system.iocache.WriteReq_miss_latency::realview.ethernet 351000 # number of WriteReq miss cycles 1419system.iocache.WriteReq_miss_latency::total 351000 # number of WriteReq miss cycles 1420system.iocache.WriteLineReq_miss_latency::realview.ide 13376583606 # number of WriteLineReq miss cycles 1421system.iocache.WriteLineReq_miss_latency::total 13376583606 # number of WriteLineReq miss cycles 1422system.iocache.demand_miss_latency::realview.ethernet 5437000 # number of demand (read+write) miss cycles 1423system.iocache.demand_miss_latency::realview.ide 15391349756 # number of demand (read+write) miss cycles 1424system.iocache.demand_miss_latency::total 15396786756 # number of demand (read+write) miss cycles 1425system.iocache.overall_miss_latency::realview.ethernet 5437000 # number of overall miss cycles 1426system.iocache.overall_miss_latency::realview.ide 15391349756 # number of overall miss cycles 1427system.iocache.overall_miss_latency::total 15396786756 # number of overall miss cycles 1428system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 1429system.iocache.ReadReq_accesses::realview.ide 8838 # number of ReadReq accesses(hits+misses) 1430system.iocache.ReadReq_accesses::total 8875 # number of ReadReq accesses(hits+misses) 1431system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 1432system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 1433system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses) 1434system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses) 1435system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 1436system.iocache.demand_accesses::realview.ide 115502 # number of demand (read+write) accesses 1437system.iocache.demand_accesses::total 115542 # number of demand (read+write) accesses 1438system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 1439system.iocache.overall_accesses::realview.ide 115502 # number of overall (read+write) accesses 1440system.iocache.overall_accesses::total 115542 # number of overall (read+write) accesses 1441system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 1442system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 1443system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 1444system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 1445system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 1446system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 1447system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 1448system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 1449system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 1450system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 1451system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 1452system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 1453system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 1454system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137459.459459 # average ReadReq miss latency 1455system.iocache.ReadReq_avg_miss_latency::realview.ide 227966.298936 # average ReadReq miss latency 1456system.iocache.ReadReq_avg_miss_latency::total 227588.974648 # average ReadReq miss latency 1457system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117000 # average WriteReq miss latency 1458system.iocache.WriteReq_avg_miss_latency::total 117000 # average WriteReq miss latency 1459system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125408.606521 # average WriteLineReq miss latency 1460system.iocache.WriteLineReq_avg_miss_latency::total 125408.606521 # average WriteLineReq miss latency 1461system.iocache.demand_avg_miss_latency::realview.ethernet 135925 # average overall miss latency 1462system.iocache.demand_avg_miss_latency::realview.ide 133256.131980 # average overall miss latency 1463system.iocache.demand_avg_miss_latency::total 133257.055928 # average overall miss latency 1464system.iocache.overall_avg_miss_latency::realview.ethernet 135925 # average overall miss latency 1465system.iocache.overall_avg_miss_latency::realview.ide 133256.131980 # average overall miss latency 1466system.iocache.overall_avg_miss_latency::total 133257.055928 # average overall miss latency 1467system.iocache.blocked_cycles::no_mshrs 51744 # number of cycles access was blocked 1468system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1469system.iocache.blocked::no_mshrs 3369 # number of cycles access was blocked 1470system.iocache.blocked::no_targets 0 # number of cycles access was blocked 1471system.iocache.avg_blocked_cycles::no_mshrs 15.358860 # average number of cycles each access was blocked 1472system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1473system.iocache.writebacks::writebacks 106631 # number of writebacks 1474system.iocache.writebacks::total 106631 # number of writebacks 1475system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 1476system.iocache.ReadReq_mshr_misses::realview.ide 8838 # number of ReadReq MSHR misses 1477system.iocache.ReadReq_mshr_misses::total 8875 # number of ReadReq MSHR misses 1478system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 1479system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 1480system.iocache.WriteLineReq_mshr_misses::realview.ide 106664 # number of WriteLineReq MSHR misses 1481system.iocache.WriteLineReq_mshr_misses::total 106664 # number of WriteLineReq MSHR misses 1482system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 1483system.iocache.demand_mshr_misses::realview.ide 115502 # number of demand (read+write) MSHR misses 1484system.iocache.demand_mshr_misses::total 115542 # number of demand (read+write) MSHR misses 1485system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 1486system.iocache.overall_mshr_misses::realview.ide 115502 # number of overall MSHR misses 1487system.iocache.overall_mshr_misses::total 115542 # number of overall MSHR misses 1488system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3236000 # number of ReadReq MSHR miss cycles 1489system.iocache.ReadReq_mshr_miss_latency::realview.ide 1572866150 # number of ReadReq MSHR miss cycles 1490system.iocache.ReadReq_mshr_miss_latency::total 1576102150 # number of ReadReq MSHR miss cycles 1491system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles 1492system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles 1493system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8037847459 # number of WriteLineReq MSHR miss cycles 1494system.iocache.WriteLineReq_mshr_miss_latency::total 8037847459 # number of WriteLineReq MSHR miss cycles 1495system.iocache.demand_mshr_miss_latency::realview.ethernet 3437000 # number of demand (read+write) MSHR miss cycles 1496system.iocache.demand_mshr_miss_latency::realview.ide 9610713609 # number of demand (read+write) MSHR miss cycles 1497system.iocache.demand_mshr_miss_latency::total 9614150609 # number of demand (read+write) MSHR miss cycles 1498system.iocache.overall_mshr_miss_latency::realview.ethernet 3437000 # number of overall MSHR miss cycles 1499system.iocache.overall_mshr_miss_latency::realview.ide 9610713609 # number of overall MSHR miss cycles 1500system.iocache.overall_mshr_miss_latency::total 9614150609 # number of overall MSHR miss cycles 1501system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 1502system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 1503system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 1504system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 1505system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 1506system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 1507system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 1508system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 1509system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 1510system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1511system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 1512system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 1513system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1514system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 87459.459459 # average ReadReq mshr miss latency 1515system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 177966.298936 # average ReadReq mshr miss latency 1516system.iocache.ReadReq_avg_mshr_miss_latency::total 177588.974648 # average ReadReq mshr miss latency 1517system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency 1518system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency 1519system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75356.703846 # average WriteLineReq mshr miss latency 1520system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75356.703846 # average WriteLineReq mshr miss latency 1521system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency 1522system.iocache.demand_avg_mshr_miss_latency::realview.ide 83208.200802 # average overall mshr miss latency 1523system.iocache.demand_avg_mshr_miss_latency::total 83209.141343 # average overall mshr miss latency 1524system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 85925 # average overall mshr miss latency 1525system.iocache.overall_avg_mshr_miss_latency::realview.ide 83208.200802 # average overall mshr miss latency 1526system.iocache.overall_avg_mshr_miss_latency::total 83209.141343 # average overall mshr miss latency 1527system.membus.snoop_filter.tot_requests 3974449 # Total number of requests made to the snoop filter. 1528system.membus.snoop_filter.hit_single_requests 1973040 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1529system.membus.snoop_filter.hit_multi_requests 3773 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1530system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1531system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1532system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1533system.membus.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1534system.membus.trans_dist::ReadReq 37899 # Transaction distribution 1535system.membus.trans_dist::ReadResp 537851 # Transaction distribution 1536system.membus.trans_dist::WriteReq 33620 # Transaction distribution 1537system.membus.trans_dist::WriteResp 33620 # Transaction distribution 1538system.membus.trans_dist::WritebackDirty 1669378 # Transaction distribution 1539system.membus.trans_dist::CleanEvict 268224 # Transaction distribution 1540system.membus.trans_dist::UpgradeReq 4552 # Transaction distribution 1541system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution 1542system.membus.trans_dist::UpgradeResp 7 # Transaction distribution 1543system.membus.trans_dist::ReadExReq 859285 # Transaction distribution 1544system.membus.trans_dist::ReadExResp 859285 # Transaction distribution 1545system.membus.trans_dist::ReadSharedReq 499952 # Transaction distribution 1546system.membus.trans_dist::InvalidateReq 672599 # Transaction distribution 1547system.membus.trans_dist::InvalidateResp 30234 # Transaction distribution 1548system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122360 # Packet count per connected master and slave (bytes) 1549system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) 1550system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6910 # Packet count per connected master and slave (bytes) 1551system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5106407 # Packet count per connected master and slave (bytes) 1552system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5235709 # Packet count per connected master and slave (bytes) 1553system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 237223 # Packet count per connected master and slave (bytes) 1554system.membus.pkt_count_system.iocache.mem_side::total 237223 # Packet count per connected master and slave (bytes) 1555system.membus.pkt_count::total 5472932 # Packet count per connected master and slave (bytes) 1556system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155490 # Cumulative packet size per connected master and slave (bytes) 1557system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) 1558system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13820 # Cumulative packet size per connected master and slave (bytes) 1559system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 186691628 # Cumulative packet size per connected master and slave (bytes) 1560system.membus.pkt_size_system.cpu.l2cache.mem_side::total 186861678 # Cumulative packet size per connected master and slave (bytes) 1561system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7220992 # Cumulative packet size per connected master and slave (bytes) 1562system.membus.pkt_size_system.iocache.mem_side::total 7220992 # Cumulative packet size per connected master and slave (bytes) 1563system.membus.pkt_size::total 194082670 # Cumulative packet size per connected master and slave (bytes) 1564system.membus.snoops 33575 # Total snoops (count) 1565system.membus.snoopTraffic 213376 # Total snoop traffic (bytes) 1566system.membus.snoop_fanout::samples 2107909 # Request fanout histogram 1567system.membus.snoop_fanout::mean 0.016147 # Request fanout histogram 1568system.membus.snoop_fanout::stdev 0.126040 # Request fanout histogram 1569system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1570system.membus.snoop_fanout::0 2073873 98.39% 98.39% # Request fanout histogram 1571system.membus.snoop_fanout::1 34036 1.61% 100.00% # Request fanout histogram 1572system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1573system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1574system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1575system.membus.snoop_fanout::max_value 1 # Request fanout histogram 1576system.membus.snoop_fanout::total 2107909 # Request fanout histogram 1577system.membus.reqLayer0.occupancy 99276000 # Layer occupancy (ticks) 1578system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 1579system.membus.reqLayer1.occupancy 18828 # Layer occupancy (ticks) 1580system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 1581system.membus.reqLayer2.occupancy 5601000 # Layer occupancy (ticks) 1582system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 1583system.membus.reqLayer5.occupancy 10934593718 # Layer occupancy (ticks) 1584system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 1585system.membus.respLayer2.occupancy 7287611424 # Layer occupancy (ticks) 1586system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 1587system.membus.respLayer3.occupancy 76573457 # Layer occupancy (ticks) 1588system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 1589system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1590system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1591system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1592system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1593system.realview.gic.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1594system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1595system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1596system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 1597system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 1598system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 1599system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 1600system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 1601system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 1602system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1603system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1604system.realview.ethernet.txBytes 966 # Bytes Transmitted 1605system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 1606system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 1607system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 1608system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 1609system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 1610system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 1611system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 1612system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 1613system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) 1614system.realview.ethernet.totPackets 3 # Total Packets 1615system.realview.ethernet.totBytes 966 # Total Bytes 1616system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 1617system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) 1618system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 1619system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 1620system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 1621system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 1622system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 1623system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 1624system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 1625system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 1626system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 1627system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 1628system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 1629system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 1630system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 1631system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 1632system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 1633system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 1634system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 1635system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 1636system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 1637system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 1638system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 1639system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 1640system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 1641system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 1642system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 1643system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 1644system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 1645system.realview.ethernet.droppedPackets 0 # number of packets dropped 1646system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1647system.realview.ide.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1648system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1649system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1650system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1651system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1652system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1653system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 1654system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 1655system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 1656system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 1657system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1658system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1659system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1660system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1661system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1662system.realview.uart.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1663system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1664system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1665system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1666system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1667system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1668system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 51643657651000 # Cumulative time (in ticks) in various power states 1669 1670---------- End Simulation Statistics ---------- 1671