config.ini revision 8893
1[root] 2type=Root 3children=system 4full_system=true 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=LinuxArmSystem 11children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver 12atags_addr=256 13boot_loader=/dist/m5/system/binaries/boot.arm 14boot_loader_mem=system.realview.nvmem 15boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 16flags_addr=268435504 17gic_cpu_addr=520093952 18init_param=0 19kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 20load_addr_mask=268435455 21machine_type=RealView_PBX 22mem_mode=timing 23memories=system.physmem system.realview.nvmem 24midr_regval=890224640 25num_work_ids=16 26physmem=system.physmem 27readfile=tests/halt.sh 28symbolfile= 29work_begin_ckpt_count=0 30work_begin_cpu_id_exit=-1 31work_begin_exit_count=0 32work_cpus_ckpt_count=0 33work_end_ckpt_count=0 34work_end_exit_count=0 35work_item_id=-1 36system_port=system.membus.slave[0] 37 38[system.bridge] 39type=Bridge 40delay=50000 41nack_delay=4000 42ranges=268435456:520093695 1073741824:1610612735 43req_size=16 44resp_size=16 45write_ack=false 46master=system.iobus.slave[0] 47slave=system.membus.master[0] 48 49[system.cf0] 50type=IdeDisk 51children=image 52delay=1000000 53driveID=master 54image=system.cf0.image 55 56[system.cf0.image] 57type=CowDiskImage 58children=child 59child=system.cf0.image.child 60image_file= 61read_only=false 62table_size=65536 63 64[system.cf0.image.child] 65type=RawDiskImage 66image_file=/dist/m5/system/disks/linux-arm-ael.img 67read_only=true 68 69[system.cpu] 70type=DerivO3CPU 71children=dcache dtb fuPool icache interrupts itb tracer 72BTBEntries=4096 73BTBTagSize=16 74LFSTSize=1024 75LQEntries=32 76LSQCheckLoads=true 77LSQDepCheckShift=4 78RASSize=16 79SQEntries=32 80SSITSize=1024 81activity=0 82backComSize=5 83cachePorts=200 84checker=Null 85choiceCtrBits=2 86choicePredictorSize=8192 87clock=500 88commitToDecodeDelay=1 89commitToFetchDelay=1 90commitToIEWDelay=1 91commitToRenameDelay=1 92commitWidth=8 93cpu_id=0 94decodeToFetchDelay=1 95decodeToRenameDelay=1 96decodeWidth=8 97defer_registration=false 98dispatchWidth=8 99do_checkpoint_insts=true 100do_quiesce=true 101do_statistics_insts=true 102dtb=system.cpu.dtb 103fetchToDecodeDelay=1 104fetchTrapLatency=1 105fetchWidth=8 106forwardComSize=5 107fuPool=system.cpu.fuPool 108function_trace=false 109function_trace_start=0 110globalCtrBits=2 111globalHistoryBits=13 112globalPredictorSize=8192 113iewToCommitDelay=1 114iewToDecodeDelay=1 115iewToFetchDelay=1 116iewToRenameDelay=1 117instShiftAmt=2 118interrupts=system.cpu.interrupts 119issueToExecuteDelay=1 120issueWidth=8 121itb=system.cpu.itb 122localCtrBits=2 123localHistoryBits=11 124localHistoryTableSize=2048 125localPredictorSize=2048 126max_insts_all_threads=0 127max_insts_any_thread=0 128max_loads_all_threads=0 129max_loads_any_thread=0 130needsTSO=false 131numIQEntries=64 132numPhysFloatRegs=256 133numPhysIntRegs=256 134numROBEntries=192 135numRobs=1 136numThreads=1 137phase=0 138predType=tournament 139profile=0 140progress_interval=0 141renameToDecodeDelay=1 142renameToFetchDelay=1 143renameToIEWDelay=2 144renameToROBDelay=1 145renameWidth=8 146smtCommitPolicy=RoundRobin 147smtFetchPolicy=SingleThread 148smtIQPolicy=Partitioned 149smtIQThreshold=100 150smtLSQPolicy=Partitioned 151smtLSQThreshold=100 152smtNumFetchingThreads=1 153smtROBPolicy=Partitioned 154smtROBThreshold=100 155squashWidth=8 156store_set_clear_period=250000 157system=system 158tracer=system.cpu.tracer 159trapLatency=13 160wbDepth=1 161wbWidth=8 162workload= 163dcache_port=system.cpu.dcache.cpu_side 164icache_port=system.cpu.icache.cpu_side 165 166[system.cpu.dcache] 167type=BaseCache 168addr_ranges=0:18446744073709551615 169assoc=4 170block_size=64 171forward_snoops=true 172hash_delay=1 173is_top_level=true 174latency=1000 175max_miss_count=0 176mshrs=4 177prefetch_on_access=false 178prefetcher=Null 179prioritizeRequests=false 180repl=Null 181size=32768 182subblock_size=0 183system=system 184tgts_per_mshr=20 185trace_addr=0 186two_queue=false 187write_buffers=8 188cpu_side=system.cpu.dcache_port 189mem_side=system.toL2Bus.slave[1] 190 191[system.cpu.dtb] 192type=ArmTLB 193children=walker 194size=64 195walker=system.cpu.dtb.walker 196 197[system.cpu.dtb.walker] 198type=ArmTableWalker 199max_backoff=100000 200min_backoff=0 201sys=system 202port=system.toL2Bus.slave[3] 203 204[system.cpu.fuPool] 205type=FUPool 206children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 207FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 208 209[system.cpu.fuPool.FUList0] 210type=FUDesc 211children=opList 212count=6 213opList=system.cpu.fuPool.FUList0.opList 214 215[system.cpu.fuPool.FUList0.opList] 216type=OpDesc 217issueLat=1 218opClass=IntAlu 219opLat=1 220 221[system.cpu.fuPool.FUList1] 222type=FUDesc 223children=opList0 opList1 224count=2 225opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 226 227[system.cpu.fuPool.FUList1.opList0] 228type=OpDesc 229issueLat=1 230opClass=IntMult 231opLat=3 232 233[system.cpu.fuPool.FUList1.opList1] 234type=OpDesc 235issueLat=19 236opClass=IntDiv 237opLat=20 238 239[system.cpu.fuPool.FUList2] 240type=FUDesc 241children=opList0 opList1 opList2 242count=4 243opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 244 245[system.cpu.fuPool.FUList2.opList0] 246type=OpDesc 247issueLat=1 248opClass=FloatAdd 249opLat=2 250 251[system.cpu.fuPool.FUList2.opList1] 252type=OpDesc 253issueLat=1 254opClass=FloatCmp 255opLat=2 256 257[system.cpu.fuPool.FUList2.opList2] 258type=OpDesc 259issueLat=1 260opClass=FloatCvt 261opLat=2 262 263[system.cpu.fuPool.FUList3] 264type=FUDesc 265children=opList0 opList1 opList2 266count=2 267opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 268 269[system.cpu.fuPool.FUList3.opList0] 270type=OpDesc 271issueLat=1 272opClass=FloatMult 273opLat=4 274 275[system.cpu.fuPool.FUList3.opList1] 276type=OpDesc 277issueLat=12 278opClass=FloatDiv 279opLat=12 280 281[system.cpu.fuPool.FUList3.opList2] 282type=OpDesc 283issueLat=24 284opClass=FloatSqrt 285opLat=24 286 287[system.cpu.fuPool.FUList4] 288type=FUDesc 289children=opList 290count=0 291opList=system.cpu.fuPool.FUList4.opList 292 293[system.cpu.fuPool.FUList4.opList] 294type=OpDesc 295issueLat=1 296opClass=MemRead 297opLat=1 298 299[system.cpu.fuPool.FUList5] 300type=FUDesc 301children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 302count=4 303opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 304 305[system.cpu.fuPool.FUList5.opList00] 306type=OpDesc 307issueLat=1 308opClass=SimdAdd 309opLat=1 310 311[system.cpu.fuPool.FUList5.opList01] 312type=OpDesc 313issueLat=1 314opClass=SimdAddAcc 315opLat=1 316 317[system.cpu.fuPool.FUList5.opList02] 318type=OpDesc 319issueLat=1 320opClass=SimdAlu 321opLat=1 322 323[system.cpu.fuPool.FUList5.opList03] 324type=OpDesc 325issueLat=1 326opClass=SimdCmp 327opLat=1 328 329[system.cpu.fuPool.FUList5.opList04] 330type=OpDesc 331issueLat=1 332opClass=SimdCvt 333opLat=1 334 335[system.cpu.fuPool.FUList5.opList05] 336type=OpDesc 337issueLat=1 338opClass=SimdMisc 339opLat=1 340 341[system.cpu.fuPool.FUList5.opList06] 342type=OpDesc 343issueLat=1 344opClass=SimdMult 345opLat=1 346 347[system.cpu.fuPool.FUList5.opList07] 348type=OpDesc 349issueLat=1 350opClass=SimdMultAcc 351opLat=1 352 353[system.cpu.fuPool.FUList5.opList08] 354type=OpDesc 355issueLat=1 356opClass=SimdShift 357opLat=1 358 359[system.cpu.fuPool.FUList5.opList09] 360type=OpDesc 361issueLat=1 362opClass=SimdShiftAcc 363opLat=1 364 365[system.cpu.fuPool.FUList5.opList10] 366type=OpDesc 367issueLat=1 368opClass=SimdSqrt 369opLat=1 370 371[system.cpu.fuPool.FUList5.opList11] 372type=OpDesc 373issueLat=1 374opClass=SimdFloatAdd 375opLat=1 376 377[system.cpu.fuPool.FUList5.opList12] 378type=OpDesc 379issueLat=1 380opClass=SimdFloatAlu 381opLat=1 382 383[system.cpu.fuPool.FUList5.opList13] 384type=OpDesc 385issueLat=1 386opClass=SimdFloatCmp 387opLat=1 388 389[system.cpu.fuPool.FUList5.opList14] 390type=OpDesc 391issueLat=1 392opClass=SimdFloatCvt 393opLat=1 394 395[system.cpu.fuPool.FUList5.opList15] 396type=OpDesc 397issueLat=1 398opClass=SimdFloatDiv 399opLat=1 400 401[system.cpu.fuPool.FUList5.opList16] 402type=OpDesc 403issueLat=1 404opClass=SimdFloatMisc 405opLat=1 406 407[system.cpu.fuPool.FUList5.opList17] 408type=OpDesc 409issueLat=1 410opClass=SimdFloatMult 411opLat=1 412 413[system.cpu.fuPool.FUList5.opList18] 414type=OpDesc 415issueLat=1 416opClass=SimdFloatMultAcc 417opLat=1 418 419[system.cpu.fuPool.FUList5.opList19] 420type=OpDesc 421issueLat=1 422opClass=SimdFloatSqrt 423opLat=1 424 425[system.cpu.fuPool.FUList6] 426type=FUDesc 427children=opList 428count=0 429opList=system.cpu.fuPool.FUList6.opList 430 431[system.cpu.fuPool.FUList6.opList] 432type=OpDesc 433issueLat=1 434opClass=MemWrite 435opLat=1 436 437[system.cpu.fuPool.FUList7] 438type=FUDesc 439children=opList0 opList1 440count=4 441opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 442 443[system.cpu.fuPool.FUList7.opList0] 444type=OpDesc 445issueLat=1 446opClass=MemRead 447opLat=1 448 449[system.cpu.fuPool.FUList7.opList1] 450type=OpDesc 451issueLat=1 452opClass=MemWrite 453opLat=1 454 455[system.cpu.fuPool.FUList8] 456type=FUDesc 457children=opList 458count=1 459opList=system.cpu.fuPool.FUList8.opList 460 461[system.cpu.fuPool.FUList8.opList] 462type=OpDesc 463issueLat=3 464opClass=IprAccess 465opLat=3 466 467[system.cpu.icache] 468type=BaseCache 469addr_ranges=0:18446744073709551615 470assoc=1 471block_size=64 472forward_snoops=true 473hash_delay=1 474is_top_level=true 475latency=1000 476max_miss_count=0 477mshrs=4 478prefetch_on_access=false 479prefetcher=Null 480prioritizeRequests=false 481repl=Null 482size=32768 483subblock_size=0 484system=system 485tgts_per_mshr=20 486trace_addr=0 487two_queue=false 488write_buffers=8 489cpu_side=system.cpu.icache_port 490mem_side=system.toL2Bus.slave[0] 491 492[system.cpu.interrupts] 493type=ArmInterrupts 494 495[system.cpu.itb] 496type=ArmTLB 497children=walker 498size=64 499walker=system.cpu.itb.walker 500 501[system.cpu.itb.walker] 502type=ArmTableWalker 503max_backoff=100000 504min_backoff=0 505sys=system 506port=system.toL2Bus.slave[2] 507 508[system.cpu.tracer] 509type=ExeTracer 510 511[system.intrctrl] 512type=IntrControl 513sys=system 514 515[system.iobus] 516type=Bus 517block_size=64 518bus_id=0 519clock=1000 520header_cycles=1 521use_default_range=false 522width=64 523master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side 524slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma 525 526[system.iocache] 527type=BaseCache 528addr_ranges=0:268435455 529assoc=8 530block_size=64 531forward_snoops=false 532hash_delay=1 533is_top_level=false 534latency=50000 535max_miss_count=0 536mshrs=20 537prefetch_on_access=false 538prefetcher=Null 539prioritizeRequests=false 540repl=Null 541size=1024 542subblock_size=0 543system=system 544tgts_per_mshr=12 545trace_addr=0 546two_queue=false 547write_buffers=8 548cpu_side=system.iobus.master[25] 549mem_side=system.membus.slave[1] 550 551[system.l2c] 552type=BaseCache 553addr_ranges=0:18446744073709551615 554assoc=8 555block_size=64 556forward_snoops=true 557hash_delay=1 558is_top_level=false 559latency=10000 560max_miss_count=0 561mshrs=92 562prefetch_on_access=false 563prefetcher=Null 564prioritizeRequests=false 565repl=Null 566size=4194304 567subblock_size=0 568system=system 569tgts_per_mshr=16 570trace_addr=0 571two_queue=false 572write_buffers=8 573cpu_side=system.toL2Bus.master[0] 574mem_side=system.membus.slave[2] 575 576[system.membus] 577type=Bus 578children=badaddr_responder 579block_size=64 580bus_id=1 581clock=1000 582header_cycles=1 583use_default_range=false 584width=64 585default=system.membus.badaddr_responder.pio 586master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio 587slave=system.system_port system.iocache.mem_side system.l2c.mem_side 588 589[system.membus.badaddr_responder] 590type=IsaFake 591fake_mem=false 592pio_addr=0 593pio_latency=1000 594pio_size=8 595ret_bad_addr=true 596ret_data16=65535 597ret_data32=4294967295 598ret_data64=18446744073709551615 599ret_data8=255 600system=system 601update_data=false 602warn_access=warn 603pio=system.membus.default 604 605[system.physmem] 606type=PhysicalMemory 607file= 608latency=30000 609latency_var=0 610null=false 611range=0:134217727 612zero=false 613port=system.membus.master[2] 614 615[system.realview] 616type=RealView 617children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake 618intrctrl=system.intrctrl 619max_mem_size=268435456 620mem_start_addr=0 621pci_cfg_base=0 622system=system 623 624[system.realview.a9scu] 625type=A9SCU 626pio_addr=520093696 627pio_latency=1000 628system=system 629pio=system.membus.master[5] 630 631[system.realview.aaci_fake] 632type=AmbaFake 633amba_id=0 634ignore_access=false 635pio_addr=268451840 636pio_latency=1000 637system=system 638pio=system.iobus.master[21] 639 640[system.realview.cf_ctrl] 641type=IdeController 642BAR0=402653184 643BAR0LegacyIO=true 644BAR0Size=16 645BAR1=402653440 646BAR1LegacyIO=true 647BAR1Size=1 648BAR2=1 649BAR2LegacyIO=false 650BAR2Size=8 651BAR3=1 652BAR3LegacyIO=false 653BAR3Size=4 654BAR4=1 655BAR4LegacyIO=false 656BAR4Size=16 657BAR5=1 658BAR5LegacyIO=false 659BAR5Size=0 660BIST=0 661CacheLineSize=0 662CardbusCIS=0 663ClassCode=1 664Command=1 665DeviceID=28945 666ExpansionROM=0 667HeaderType=0 668InterruptLine=31 669InterruptPin=1 670LatencyTimer=0 671MaximumLatency=0 672MinimumGrant=0 673ProgIF=133 674Revision=0 675Status=640 676SubClassCode=1 677SubsystemID=0 678SubsystemVendorID=0 679VendorID=32902 680config_latency=20000 681ctrl_offset=2 682disks=system.cf0 683io_shift=1 684max_backoff_delay=10000000 685min_backoff_delay=4000 686pci_bus=2 687pci_dev=7 688pci_func=0 689pio_latency=1000 690platform=system.realview 691system=system 692config=system.iobus.master[8] 693dma=system.iobus.slave[2] 694pio=system.iobus.master[7] 695 696[system.realview.clcd] 697type=Pl111 698amba_id=1315089 699clock=41667 700gic=system.realview.gic 701int_num=55 702max_backoff_delay=10000000 703min_backoff_delay=4000 704pio_addr=268566528 705pio_latency=10000 706system=system 707vnc=system.vncserver 708dma=system.iobus.slave[1] 709pio=system.iobus.master[4] 710 711[system.realview.dmac_fake] 712type=AmbaFake 713amba_id=0 714ignore_access=false 715pio_addr=268632064 716pio_latency=1000 717system=system 718pio=system.iobus.master[9] 719 720[system.realview.flash_fake] 721type=IsaFake 722fake_mem=true 723pio_addr=1073741824 724pio_latency=1000 725pio_size=536870912 726ret_bad_addr=false 727ret_data16=65535 728ret_data32=4294967295 729ret_data64=18446744073709551615 730ret_data8=255 731system=system 732update_data=false 733warn_access= 734pio=system.iobus.master[24] 735 736[system.realview.gic] 737type=Gic 738cpu_addr=520093952 739cpu_pio_delay=10000 740dist_addr=520097792 741dist_pio_delay=10000 742int_latency=10000 743it_lines=128 744platform=system.realview 745system=system 746pio=system.membus.master[3] 747 748[system.realview.gpio0_fake] 749type=AmbaFake 750amba_id=0 751ignore_access=false 752pio_addr=268513280 753pio_latency=1000 754system=system 755pio=system.iobus.master[16] 756 757[system.realview.gpio1_fake] 758type=AmbaFake 759amba_id=0 760ignore_access=false 761pio_addr=268517376 762pio_latency=1000 763system=system 764pio=system.iobus.master[17] 765 766[system.realview.gpio2_fake] 767type=AmbaFake 768amba_id=0 769ignore_access=false 770pio_addr=268521472 771pio_latency=1000 772system=system 773pio=system.iobus.master[18] 774 775[system.realview.kmi0] 776type=Pl050 777amba_id=1314896 778gic=system.realview.gic 779int_delay=1000000 780int_num=52 781is_mouse=false 782pio_addr=268460032 783pio_latency=1000 784system=system 785vnc=system.vncserver 786pio=system.iobus.master[5] 787 788[system.realview.kmi1] 789type=Pl050 790amba_id=1314896 791gic=system.realview.gic 792int_delay=1000000 793int_num=53 794is_mouse=true 795pio_addr=268464128 796pio_latency=1000 797system=system 798vnc=system.vncserver 799pio=system.iobus.master[6] 800 801[system.realview.l2x0_fake] 802type=IsaFake 803fake_mem=false 804pio_addr=520101888 805pio_latency=1000 806pio_size=4095 807ret_bad_addr=false 808ret_data16=65535 809ret_data32=4294967295 810ret_data64=18446744073709551615 811ret_data8=255 812system=system 813update_data=false 814warn_access= 815pio=system.membus.master[4] 816 817[system.realview.local_cpu_timer] 818type=CpuLocalTimer 819clock=1000 820gic=system.realview.gic 821int_num_timer=29 822int_num_watchdog=30 823pio_addr=520095232 824pio_latency=1000 825system=system 826pio=system.membus.master[6] 827 828[system.realview.mmc_fake] 829type=AmbaFake 830amba_id=0 831ignore_access=false 832pio_addr=268455936 833pio_latency=1000 834system=system 835pio=system.iobus.master[22] 836 837[system.realview.nvmem] 838type=PhysicalMemory 839file= 840latency=30000 841latency_var=0 842null=false 843range=2147483648:2214592511 844zero=true 845port=system.membus.master[1] 846 847[system.realview.realview_io] 848type=RealViewCtrl 849idreg=0 850pio_addr=268435456 851pio_latency=1000 852proc_id0=201326592 853proc_id1=201327138 854system=system 855pio=system.iobus.master[1] 856 857[system.realview.rtc_fake] 858type=AmbaFake 859amba_id=266289 860ignore_access=false 861pio_addr=268529664 862pio_latency=1000 863system=system 864pio=system.iobus.master[23] 865 866[system.realview.sci_fake] 867type=AmbaFake 868amba_id=0 869ignore_access=false 870pio_addr=268492800 871pio_latency=1000 872system=system 873pio=system.iobus.master[20] 874 875[system.realview.smc_fake] 876type=AmbaFake 877amba_id=0 878ignore_access=false 879pio_addr=269357056 880pio_latency=1000 881system=system 882pio=system.iobus.master[13] 883 884[system.realview.sp810_fake] 885type=AmbaFake 886amba_id=0 887ignore_access=true 888pio_addr=268439552 889pio_latency=1000 890system=system 891pio=system.iobus.master[14] 892 893[system.realview.ssp_fake] 894type=AmbaFake 895amba_id=0 896ignore_access=false 897pio_addr=268488704 898pio_latency=1000 899system=system 900pio=system.iobus.master[19] 901 902[system.realview.timer0] 903type=Sp804 904amba_id=1316868 905clock0=1000000 906clock1=1000000 907gic=system.realview.gic 908int_num0=36 909int_num1=36 910pio_addr=268505088 911pio_latency=1000 912system=system 913pio=system.iobus.master[2] 914 915[system.realview.timer1] 916type=Sp804 917amba_id=1316868 918clock0=1000000 919clock1=1000000 920gic=system.realview.gic 921int_num0=37 922int_num1=37 923pio_addr=268509184 924pio_latency=1000 925system=system 926pio=system.iobus.master[3] 927 928[system.realview.uart] 929type=Pl011 930end_on_eot=false 931gic=system.realview.gic 932int_delay=100000 933int_num=44 934pio_addr=268472320 935pio_latency=1000 936platform=system.realview 937system=system 938terminal=system.terminal 939pio=system.iobus.master[0] 940 941[system.realview.uart1_fake] 942type=AmbaFake 943amba_id=0 944ignore_access=false 945pio_addr=268476416 946pio_latency=1000 947system=system 948pio=system.iobus.master[10] 949 950[system.realview.uart2_fake] 951type=AmbaFake 952amba_id=0 953ignore_access=false 954pio_addr=268480512 955pio_latency=1000 956system=system 957pio=system.iobus.master[11] 958 959[system.realview.uart3_fake] 960type=AmbaFake 961amba_id=0 962ignore_access=false 963pio_addr=268484608 964pio_latency=1000 965system=system 966pio=system.iobus.master[12] 967 968[system.realview.watchdog_fake] 969type=AmbaFake 970amba_id=0 971ignore_access=false 972pio_addr=268500992 973pio_latency=1000 974system=system 975pio=system.iobus.master[15] 976 977[system.terminal] 978type=Terminal 979intr_control=system.intrctrl 980number=0 981output=true 982port=3456 983 984[system.toL2Bus] 985type=Bus 986block_size=64 987bus_id=0 988clock=1000 989header_cycles=1 990use_default_range=false 991width=64 992master=system.l2c.cpu_side 993slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 994 995[system.vncserver] 996type=VncServer 997frame_capture=false 998number=0 999port=5900 1000 1001