config.ini revision 8660
11736SN/A[root] 21736SN/Atype=Root 31736SN/Achildren=system 41736SN/Atime_sync_enable=false 51736SN/Atime_sync_period=100000000000 61736SN/Atime_sync_spin_threshold=100000000 71736SN/A 81736SN/A[system] 91736SN/Atype=LinuxArmSystem 101736SN/Achildren=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver 111736SN/Aboot_cpu_frequency=500 121736SN/Aboot_loader=/dist/m5/system/binaries/boot.arm 131736SN/Aboot_loader_mem=system.nvmem 141736SN/Aboot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 151736SN/Aflags_addr=268435504 161736SN/Agic_cpu_addr=520093952 171736SN/Ainit_param=0 181736SN/Akernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 191736SN/Aload_addr_mask=268435455 201736SN/Amachine_type=RealView_PBX 211736SN/Amem_mode=timing 221736SN/Amemories=system.nvmem system.physmem 231736SN/Amidr_regval=890224640 241736SN/Anum_work_ids=16 251736SN/Aphysmem=system.physmem 262665Ssaidi@eecs.umich.edureadfile=tests/halt.sh 272665Ssaidi@eecs.umich.edusymbolfile= 282665Ssaidi@eecs.umich.eduwork_begin_ckpt_count=0 291736SN/Awork_begin_cpu_id_exit=-1 302889Sbinkertn@umich.eduwork_begin_exit_count=0 312655Sstever@eecs.umich.eduwork_cpus_ckpt_count=0 322667Sstever@eecs.umich.eduwork_end_ckpt_count=0 332763Sstever@eecs.umich.eduwork_end_exit_count=0 342667Sstever@eecs.umich.eduwork_item_id=-1 352667Sstever@eecs.umich.edu 362667Sstever@eecs.umich.edu[system.bridge] 372868Sktlim@umich.edutype=Bridge 382655Sstever@eecs.umich.edudelay=50000 392667Sstever@eecs.umich.edufilter_ranges_a=0:18446744073709551615 402667Sstever@eecs.umich.edufilter_ranges_b=0:268435455 411530SN/Anack_delay=4000 421530SN/Areq_size_a=16 431530SN/Areq_size_b=16 441530SN/Aresp_size_a=16 451530SN/Aresp_size_b=16 461530SN/Awrite_ack=false 472667Sstever@eecs.umich.eduside_a=system.iobus.port[0] 482667Sstever@eecs.umich.eduside_b=system.membus.port[0] 492667Sstever@eecs.umich.edu 501692SN/A[system.cf0] 511869SN/Atype=IdeDisk 521869SN/Achildren=image 531869SN/Adelay=1000000 541869SN/AdriveID=master 551692SN/Aimage=system.cf0.image 561869SN/A 571869SN/A[system.cf0.image] 581869SN/Atype=CowDiskImage 591581SN/Achildren=child 601530SN/Achild=system.cf0.image.child 611530SN/Aimage_file= 621530SN/Aread_only=false 632667Sstever@eecs.umich.edutable_size=65536 641530SN/A 651530SN/A[system.cf0.image.child] 661530SN/Atype=RawDiskImage 671530SN/Aimage_file=/dist/m5/system/disks/linux-arm-ael.img 681530SN/Aread_only=true 692738Sstever@eecs.umich.edu 702738Sstever@eecs.umich.edu[system.cpu] 712738Sstever@eecs.umich.edutype=DerivO3CPU 722740Sstever@eecs.umich.educhildren=dcache dtb fuPool icache interrupts itb tracer 732738Sstever@eecs.umich.eduBTBEntries=4096 742889Sbinkertn@umich.eduBTBTagSize=16 752889Sbinkertn@umich.eduLFSTSize=1024 762667Sstever@eecs.umich.eduLQEntries=32 772667Sstever@eecs.umich.eduLSQCheckLoads=true 782667Sstever@eecs.umich.eduLSQDepCheckShift=4 792667Sstever@eecs.umich.eduRASSize=16 802667Sstever@eecs.umich.eduSQEntries=32 812762Sstever@eecs.umich.eduSSITSize=1024 822667Sstever@eecs.umich.eduactivity=0 832667Sstever@eecs.umich.edubackComSize=5 842667Sstever@eecs.umich.educachePorts=200 852763Sstever@eecs.umich.educhecker=Null 862738Sstever@eecs.umich.educhoiceCtrBits=2 872738Sstever@eecs.umich.educhoicePredictorSize=8192 882763Sstever@eecs.umich.educlock=500 892667Sstever@eecs.umich.educommitToDecodeDelay=1 902667Sstever@eecs.umich.educommitToFetchDelay=1 912667Sstever@eecs.umich.educommitToIEWDelay=1 922667Sstever@eecs.umich.educommitToRenameDelay=1 932667Sstever@eecs.umich.educommitWidth=8 942667Sstever@eecs.umich.educpu_id=0 952667Sstever@eecs.umich.edudecodeToFetchDelay=1 962667Sstever@eecs.umich.edudecodeToRenameDelay=1 972667Sstever@eecs.umich.edudecodeWidth=8 982667Sstever@eecs.umich.edudefer_registration=false 991527SN/AdispatchWidth=8 1002667Sstever@eecs.umich.edudo_checkpoint_insts=true 1012667Sstever@eecs.umich.edudo_quiesce=true 1022763Sstever@eecs.umich.edudo_statistics_insts=true 1031511SN/Adtb=system.cpu.dtb 1042667Sstever@eecs.umich.edufetchToDecodeDelay=1 1052763Sstever@eecs.umich.edufetchTrapLatency=1 1062655Sstever@eecs.umich.edufetchWidth=8 1072667Sstever@eecs.umich.eduforwardComSize=5 1082667Sstever@eecs.umich.edufuPool=system.cpu.fuPool 1092667Sstever@eecs.umich.edufunction_trace=false 1102667Sstever@eecs.umich.edufunction_trace_start=0 1112797Sktlim@umich.eduglobalCtrBits=2 1122860Sktlim@umich.eduglobalHistoryBits=13 1132839Sktlim@umich.eduglobalPredictorSize=8192 1142860Sktlim@umich.eduiewToCommitDelay=1 1152860Sktlim@umich.eduiewToDecodeDelay=1 1162860Sktlim@umich.eduiewToFetchDelay=1 1172860Sktlim@umich.eduiewToRenameDelay=1 1182860Sktlim@umich.eduinstShiftAmt=2 1192860Sktlim@umich.eduinterrupts=system.cpu.interrupts 1202860Sktlim@umich.eduissueToExecuteDelay=1 1212860Sktlim@umich.eduissueWidth=8 1222860Sktlim@umich.eduitb=system.cpu.itb 1232860Sktlim@umich.edulocalCtrBits=2 1242839Sktlim@umich.edulocalHistoryBits=11 1252839Sktlim@umich.edulocalHistoryTableSize=2048 1262839Sktlim@umich.edulocalPredictorSize=2048 1272797Sktlim@umich.edumax_insts_all_threads=0 1282839Sktlim@umich.edumax_insts_any_thread=0 1292797Sktlim@umich.edumax_loads_all_threads=0 1302860Sktlim@umich.edumax_loads_any_thread=0 1312860Sktlim@umich.edunumIQEntries=64 1322839Sktlim@umich.edunumPhysFloatRegs=256 1332860Sktlim@umich.edunumPhysIntRegs=256 1342797Sktlim@umich.edunumROBEntries=192 1352797Sktlim@umich.edunumRobs=1 1362797Sktlim@umich.edunumThreads=1 1372797Sktlim@umich.eduphase=0 1382868Sktlim@umich.edupredType=tournament 1392797Sktlim@umich.eduprofile=0 1402797Sktlim@umich.eduprogress_interval=0 1412839Sktlim@umich.edurenameToDecodeDelay=1 1422797Sktlim@umich.edurenameToFetchDelay=1 1432868Sktlim@umich.edurenameToIEWDelay=2 1442797Sktlim@umich.edurenameToROBDelay=1 1452797Sktlim@umich.edurenameWidth=8 1462868Sktlim@umich.edusmtCommitPolicy=RoundRobin 1472797Sktlim@umich.edusmtFetchPolicy=SingleThread 1482868Sktlim@umich.edusmtIQPolicy=Partitioned 1492865Sktlim@umich.edusmtIQThreshold=100 1502797Sktlim@umich.edusmtLSQPolicy=Partitioned 1512797Sktlim@umich.edusmtLSQThreshold=100 1522797Sktlim@umich.edusmtNumFetchingThreads=1 1532797Sktlim@umich.edusmtROBPolicy=Partitioned 1542797Sktlim@umich.edusmtROBThreshold=100 1552839Sktlim@umich.edusquashWidth=8 1562797Sktlim@umich.edustore_set_clear_period=250000 1572797Sktlim@umich.edusystem=system 1582797Sktlim@umich.edutracer=system.cpu.tracer 1592797Sktlim@umich.edutrapLatency=13 1602797Sktlim@umich.eduwbDepth=1 1612797Sktlim@umich.eduwbWidth=8 1622797Sktlim@umich.edudcache_port=system.cpu.dcache.cpu_side 1632797Sktlim@umich.eduicache_port=system.cpu.icache.cpu_side 1642839Sktlim@umich.edu 1652797Sktlim@umich.edu[system.cpu.dcache] 1662797Sktlim@umich.edutype=BaseCache 1672797Sktlim@umich.eduaddr_range=0:18446744073709551615 1682797Sktlim@umich.eduassoc=4 1692797Sktlim@umich.edublock_size=64 1702797Sktlim@umich.eduforward_snoops=true 1712797Sktlim@umich.eduhash_delay=1 1722797Sktlim@umich.eduis_top_level=true 1732797Sktlim@umich.edulatency=1000 1742797Sktlim@umich.edumax_miss_count=0 1752797Sktlim@umich.edumshrs=4 1762797Sktlim@umich.edunum_cpus=1 1772797Sktlim@umich.eduprefetch_data_accesses_only=false 1782797Sktlim@umich.eduprefetch_degree=1 1792797Sktlim@umich.eduprefetch_latency=10000 1802797Sktlim@umich.eduprefetch_on_access=false 1812797Sktlim@umich.eduprefetch_past_page=false 1822797Sktlim@umich.eduprefetch_policy=none 1832797Sktlim@umich.eduprefetch_serial_squash=false 1842797Sktlim@umich.eduprefetch_use_cpu_id=true 1852839Sktlim@umich.eduprefetcher_size=100 1862839Sktlim@umich.eduprioritizeRequests=false 1872797Sktlim@umich.edurepl=Null 1882797Sktlim@umich.edusize=32768 1892839Sktlim@umich.edusubblock_size=0 1902839Sktlim@umich.edutgts_per_mshr=20 1912797Sktlim@umich.edutrace_addr=0 1922839Sktlim@umich.edutwo_queue=false 1932797Sktlim@umich.eduwrite_buffers=8 1942839Sktlim@umich.educpu_side=system.cpu.dcache_port 1952797Sktlim@umich.edumem_side=system.toL2Bus.port[2] 1962797Sktlim@umich.edu 1972797Sktlim@umich.edu[system.cpu.dtb] 1982797Sktlim@umich.edutype=ArmTLB 1992797Sktlim@umich.educhildren=walker 2002797Sktlim@umich.edusize=64 2012797Sktlim@umich.eduwalker=system.cpu.dtb.walker 2022797Sktlim@umich.edu 2032797Sktlim@umich.edu[system.cpu.dtb.walker] 204type=ArmTableWalker 205max_backoff=100000 206min_backoff=0 207sys=system 208port=system.toL2Bus.port[4] 209 210[system.cpu.fuPool] 211type=FUPool 212children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 213FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 214 215[system.cpu.fuPool.FUList0] 216type=FUDesc 217children=opList 218count=6 219opList=system.cpu.fuPool.FUList0.opList 220 221[system.cpu.fuPool.FUList0.opList] 222type=OpDesc 223issueLat=1 224opClass=IntAlu 225opLat=1 226 227[system.cpu.fuPool.FUList1] 228type=FUDesc 229children=opList0 opList1 230count=2 231opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 232 233[system.cpu.fuPool.FUList1.opList0] 234type=OpDesc 235issueLat=1 236opClass=IntMult 237opLat=3 238 239[system.cpu.fuPool.FUList1.opList1] 240type=OpDesc 241issueLat=19 242opClass=IntDiv 243opLat=20 244 245[system.cpu.fuPool.FUList2] 246type=FUDesc 247children=opList0 opList1 opList2 248count=4 249opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 250 251[system.cpu.fuPool.FUList2.opList0] 252type=OpDesc 253issueLat=1 254opClass=FloatAdd 255opLat=2 256 257[system.cpu.fuPool.FUList2.opList1] 258type=OpDesc 259issueLat=1 260opClass=FloatCmp 261opLat=2 262 263[system.cpu.fuPool.FUList2.opList2] 264type=OpDesc 265issueLat=1 266opClass=FloatCvt 267opLat=2 268 269[system.cpu.fuPool.FUList3] 270type=FUDesc 271children=opList0 opList1 opList2 272count=2 273opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 274 275[system.cpu.fuPool.FUList3.opList0] 276type=OpDesc 277issueLat=1 278opClass=FloatMult 279opLat=4 280 281[system.cpu.fuPool.FUList3.opList1] 282type=OpDesc 283issueLat=12 284opClass=FloatDiv 285opLat=12 286 287[system.cpu.fuPool.FUList3.opList2] 288type=OpDesc 289issueLat=24 290opClass=FloatSqrt 291opLat=24 292 293[system.cpu.fuPool.FUList4] 294type=FUDesc 295children=opList 296count=0 297opList=system.cpu.fuPool.FUList4.opList 298 299[system.cpu.fuPool.FUList4.opList] 300type=OpDesc 301issueLat=1 302opClass=MemRead 303opLat=1 304 305[system.cpu.fuPool.FUList5] 306type=FUDesc 307children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 308count=4 309opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 310 311[system.cpu.fuPool.FUList5.opList00] 312type=OpDesc 313issueLat=1 314opClass=SimdAdd 315opLat=1 316 317[system.cpu.fuPool.FUList5.opList01] 318type=OpDesc 319issueLat=1 320opClass=SimdAddAcc 321opLat=1 322 323[system.cpu.fuPool.FUList5.opList02] 324type=OpDesc 325issueLat=1 326opClass=SimdAlu 327opLat=1 328 329[system.cpu.fuPool.FUList5.opList03] 330type=OpDesc 331issueLat=1 332opClass=SimdCmp 333opLat=1 334 335[system.cpu.fuPool.FUList5.opList04] 336type=OpDesc 337issueLat=1 338opClass=SimdCvt 339opLat=1 340 341[system.cpu.fuPool.FUList5.opList05] 342type=OpDesc 343issueLat=1 344opClass=SimdMisc 345opLat=1 346 347[system.cpu.fuPool.FUList5.opList06] 348type=OpDesc 349issueLat=1 350opClass=SimdMult 351opLat=1 352 353[system.cpu.fuPool.FUList5.opList07] 354type=OpDesc 355issueLat=1 356opClass=SimdMultAcc 357opLat=1 358 359[system.cpu.fuPool.FUList5.opList08] 360type=OpDesc 361issueLat=1 362opClass=SimdShift 363opLat=1 364 365[system.cpu.fuPool.FUList5.opList09] 366type=OpDesc 367issueLat=1 368opClass=SimdShiftAcc 369opLat=1 370 371[system.cpu.fuPool.FUList5.opList10] 372type=OpDesc 373issueLat=1 374opClass=SimdSqrt 375opLat=1 376 377[system.cpu.fuPool.FUList5.opList11] 378type=OpDesc 379issueLat=1 380opClass=SimdFloatAdd 381opLat=1 382 383[system.cpu.fuPool.FUList5.opList12] 384type=OpDesc 385issueLat=1 386opClass=SimdFloatAlu 387opLat=1 388 389[system.cpu.fuPool.FUList5.opList13] 390type=OpDesc 391issueLat=1 392opClass=SimdFloatCmp 393opLat=1 394 395[system.cpu.fuPool.FUList5.opList14] 396type=OpDesc 397issueLat=1 398opClass=SimdFloatCvt 399opLat=1 400 401[system.cpu.fuPool.FUList5.opList15] 402type=OpDesc 403issueLat=1 404opClass=SimdFloatDiv 405opLat=1 406 407[system.cpu.fuPool.FUList5.opList16] 408type=OpDesc 409issueLat=1 410opClass=SimdFloatMisc 411opLat=1 412 413[system.cpu.fuPool.FUList5.opList17] 414type=OpDesc 415issueLat=1 416opClass=SimdFloatMult 417opLat=1 418 419[system.cpu.fuPool.FUList5.opList18] 420type=OpDesc 421issueLat=1 422opClass=SimdFloatMultAcc 423opLat=1 424 425[system.cpu.fuPool.FUList5.opList19] 426type=OpDesc 427issueLat=1 428opClass=SimdFloatSqrt 429opLat=1 430 431[system.cpu.fuPool.FUList6] 432type=FUDesc 433children=opList 434count=0 435opList=system.cpu.fuPool.FUList6.opList 436 437[system.cpu.fuPool.FUList6.opList] 438type=OpDesc 439issueLat=1 440opClass=MemWrite 441opLat=1 442 443[system.cpu.fuPool.FUList7] 444type=FUDesc 445children=opList0 opList1 446count=4 447opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 448 449[system.cpu.fuPool.FUList7.opList0] 450type=OpDesc 451issueLat=1 452opClass=MemRead 453opLat=1 454 455[system.cpu.fuPool.FUList7.opList1] 456type=OpDesc 457issueLat=1 458opClass=MemWrite 459opLat=1 460 461[system.cpu.fuPool.FUList8] 462type=FUDesc 463children=opList 464count=1 465opList=system.cpu.fuPool.FUList8.opList 466 467[system.cpu.fuPool.FUList8.opList] 468type=OpDesc 469issueLat=3 470opClass=IprAccess 471opLat=3 472 473[system.cpu.icache] 474type=BaseCache 475addr_range=0:18446744073709551615 476assoc=1 477block_size=64 478forward_snoops=true 479hash_delay=1 480is_top_level=true 481latency=1000 482max_miss_count=0 483mshrs=4 484num_cpus=1 485prefetch_data_accesses_only=false 486prefetch_degree=1 487prefetch_latency=10000 488prefetch_on_access=false 489prefetch_past_page=false 490prefetch_policy=none 491prefetch_serial_squash=false 492prefetch_use_cpu_id=true 493prefetcher_size=100 494prioritizeRequests=false 495repl=Null 496size=32768 497subblock_size=0 498tgts_per_mshr=20 499trace_addr=0 500two_queue=false 501write_buffers=8 502cpu_side=system.cpu.icache_port 503mem_side=system.toL2Bus.port[1] 504 505[system.cpu.interrupts] 506type=ArmInterrupts 507 508[system.cpu.itb] 509type=ArmTLB 510children=walker 511size=64 512walker=system.cpu.itb.walker 513 514[system.cpu.itb.walker] 515type=ArmTableWalker 516max_backoff=100000 517min_backoff=0 518sys=system 519port=system.toL2Bus.port[3] 520 521[system.cpu.tracer] 522type=ExeTracer 523 524[system.intrctrl] 525type=IntrControl 526sys=system 527 528[system.iobus] 529type=Bus 530block_size=64 531bus_id=0 532clock=1000 533header_cycles=1 534use_default_range=false 535width=64 536port=system.bridge.side_a system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc_fake.pio system.realview.flash_fake.pio system.iocache.cpu_side system.realview.cf_ctrl.config system.realview.cf_ctrl.dma system.realview.clcd.dma 537 538[system.iocache] 539type=BaseCache 540addr_range=0:268435455 541assoc=8 542block_size=64 543forward_snoops=false 544hash_delay=1 545is_top_level=false 546latency=50000 547max_miss_count=0 548mshrs=20 549num_cpus=1 550prefetch_data_accesses_only=false 551prefetch_degree=1 552prefetch_latency=500000 553prefetch_on_access=false 554prefetch_past_page=false 555prefetch_policy=none 556prefetch_serial_squash=false 557prefetch_use_cpu_id=true 558prefetcher_size=100 559prioritizeRequests=false 560repl=Null 561size=1024 562subblock_size=0 563tgts_per_mshr=12 564trace_addr=0 565two_queue=false 566write_buffers=8 567cpu_side=system.iobus.port[25] 568mem_side=system.membus.port[7] 569 570[system.l2c] 571type=BaseCache 572addr_range=0:18446744073709551615 573assoc=8 574block_size=64 575forward_snoops=true 576hash_delay=1 577is_top_level=false 578latency=10000 579max_miss_count=0 580mshrs=92 581num_cpus=1 582prefetch_data_accesses_only=false 583prefetch_degree=1 584prefetch_latency=100000 585prefetch_on_access=false 586prefetch_past_page=false 587prefetch_policy=none 588prefetch_serial_squash=false 589prefetch_use_cpu_id=true 590prefetcher_size=100 591prioritizeRequests=false 592repl=Null 593size=4194304 594subblock_size=0 595tgts_per_mshr=16 596trace_addr=0 597two_queue=false 598write_buffers=8 599cpu_side=system.toL2Bus.port[0] 600mem_side=system.membus.port[8] 601 602[system.membus] 603type=Bus 604children=badaddr_responder 605block_size=64 606bus_id=1 607clock=1000 608header_cycles=1 609use_default_range=false 610width=64 611default=system.membus.badaddr_responder.pio 612port=system.bridge.side_b system.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.iocache.mem_side system.l2c.mem_side 613 614[system.membus.badaddr_responder] 615type=IsaFake 616fake_mem=false 617pio_addr=0 618pio_latency=1000 619pio_size=8 620platform=system.realview 621ret_bad_addr=true 622ret_data16=65535 623ret_data32=4294967295 624ret_data64=18446744073709551615 625ret_data8=255 626system=system 627update_data=false 628warn_access=warn 629pio=system.membus.default 630 631[system.nvmem] 632type=PhysicalMemory 633file= 634latency=30000 635latency_var=0 636null=false 637range=2147483648:2214592511 638zero=true 639port=system.membus.port[1] 640 641[system.physmem] 642type=PhysicalMemory 643file= 644latency=30000 645latency_var=0 646null=false 647range=0:134217727 648zero=true 649port=system.membus.port[2] 650 651[system.realview] 652type=RealView 653children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake realview_io rtc_fake sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake 654intrctrl=system.intrctrl 655pci_cfg_base=0 656system=system 657 658[system.realview.a9scu] 659type=A9SCU 660pio_addr=520093696 661pio_latency=1000 662platform=system.realview 663system=system 664pio=system.membus.port[5] 665 666[system.realview.aaci_fake] 667type=AmbaFake 668amba_id=0 669ignore_access=false 670pio_addr=268451840 671pio_latency=1000 672platform=system.realview 673system=system 674pio=system.iobus.port[21] 675 676[system.realview.cf_ctrl] 677type=IdeController 678BAR0=402653184 679BAR0LegacyIO=true 680BAR0Size=16 681BAR1=402653440 682BAR1LegacyIO=true 683BAR1Size=1 684BAR2=1 685BAR2LegacyIO=false 686BAR2Size=8 687BAR3=1 688BAR3LegacyIO=false 689BAR3Size=4 690BAR4=1 691BAR4LegacyIO=false 692BAR4Size=16 693BAR5=1 694BAR5LegacyIO=false 695BAR5Size=0 696BIST=0 697CacheLineSize=0 698CardbusCIS=0 699ClassCode=1 700Command=1 701DeviceID=28945 702ExpansionROM=0 703HeaderType=0 704InterruptLine=31 705InterruptPin=1 706LatencyTimer=0 707MaximumLatency=0 708MinimumGrant=0 709ProgIF=133 710Revision=0 711Status=640 712SubClassCode=1 713SubsystemID=0 714SubsystemVendorID=0 715VendorID=32902 716config_latency=20000 717ctrl_offset=2 718disks=system.cf0 719io_shift=1 720max_backoff_delay=10000000 721min_backoff_delay=4000 722pci_bus=2 723pci_dev=7 724pci_func=0 725pio_latency=1000 726platform=system.realview 727system=system 728config=system.iobus.port[26] 729dma=system.iobus.port[27] 730pio=system.iobus.port[8] 731 732[system.realview.clcd] 733type=Pl111 734amba_id=1315089 735clock=41667 736gic=system.realview.gic 737int_num=55 738max_backoff_delay=10000000 739min_backoff_delay=4000 740pio_addr=268566528 741pio_latency=10000 742platform=system.realview 743system=system 744vnc=system.vncserver 745dma=system.iobus.port[28] 746pio=system.iobus.port[5] 747 748[system.realview.dmac_fake] 749type=AmbaFake 750amba_id=0 751ignore_access=false 752pio_addr=268632064 753pio_latency=1000 754platform=system.realview 755system=system 756pio=system.iobus.port[9] 757 758[system.realview.flash_fake] 759type=IsaFake 760fake_mem=true 761pio_addr=1073741824 762pio_latency=1000 763pio_size=536870912 764platform=system.realview 765ret_bad_addr=false 766ret_data16=65535 767ret_data32=4294967295 768ret_data64=18446744073709551615 769ret_data8=255 770system=system 771update_data=false 772warn_access= 773pio=system.iobus.port[24] 774 775[system.realview.gic] 776type=Gic 777cpu_addr=520093952 778cpu_pio_delay=10000 779dist_addr=520097792 780dist_pio_delay=10000 781int_latency=10000 782it_lines=128 783platform=system.realview 784system=system 785pio=system.membus.port[3] 786 787[system.realview.gpio0_fake] 788type=AmbaFake 789amba_id=0 790ignore_access=false 791pio_addr=268513280 792pio_latency=1000 793platform=system.realview 794system=system 795pio=system.iobus.port[16] 796 797[system.realview.gpio1_fake] 798type=AmbaFake 799amba_id=0 800ignore_access=false 801pio_addr=268517376 802pio_latency=1000 803platform=system.realview 804system=system 805pio=system.iobus.port[17] 806 807[system.realview.gpio2_fake] 808type=AmbaFake 809amba_id=0 810ignore_access=false 811pio_addr=268521472 812pio_latency=1000 813platform=system.realview 814system=system 815pio=system.iobus.port[18] 816 817[system.realview.kmi0] 818type=Pl050 819amba_id=1314896 820gic=system.realview.gic 821int_delay=1000000 822int_num=52 823is_mouse=false 824pio_addr=268460032 825pio_latency=1000 826platform=system.realview 827system=system 828vnc=system.vncserver 829pio=system.iobus.port[6] 830 831[system.realview.kmi1] 832type=Pl050 833amba_id=1314896 834gic=system.realview.gic 835int_delay=1000000 836int_num=53 837is_mouse=true 838pio_addr=268464128 839pio_latency=1000 840platform=system.realview 841system=system 842vnc=system.vncserver 843pio=system.iobus.port[7] 844 845[system.realview.l2x0_fake] 846type=IsaFake 847fake_mem=false 848pio_addr=520101888 849pio_latency=1000 850pio_size=4095 851platform=system.realview 852ret_bad_addr=false 853ret_data16=65535 854ret_data32=4294967295 855ret_data64=18446744073709551615 856ret_data8=255 857system=system 858update_data=false 859warn_access= 860pio=system.membus.port[4] 861 862[system.realview.local_cpu_timer] 863type=CpuLocalTimer 864clock=1000 865gic=system.realview.gic 866int_num_timer=29 867int_num_watchdog=30 868pio_addr=520095232 869pio_latency=1000 870platform=system.realview 871system=system 872pio=system.membus.port[6] 873 874[system.realview.mmc_fake] 875type=AmbaFake 876amba_id=0 877ignore_access=false 878pio_addr=268455936 879pio_latency=1000 880platform=system.realview 881system=system 882pio=system.iobus.port[22] 883 884[system.realview.realview_io] 885type=RealViewCtrl 886idreg=0 887pio_addr=268435456 888pio_latency=1000 889platform=system.realview 890proc_id0=201326592 891proc_id1=201327138 892system=system 893pio=system.iobus.port[2] 894 895[system.realview.rtc_fake] 896type=AmbaFake 897amba_id=266289 898ignore_access=false 899pio_addr=268529664 900pio_latency=1000 901platform=system.realview 902system=system 903pio=system.iobus.port[23] 904 905[system.realview.sci_fake] 906type=AmbaFake 907amba_id=0 908ignore_access=false 909pio_addr=268492800 910pio_latency=1000 911platform=system.realview 912system=system 913pio=system.iobus.port[20] 914 915[system.realview.smc_fake] 916type=AmbaFake 917amba_id=0 918ignore_access=false 919pio_addr=269357056 920pio_latency=1000 921platform=system.realview 922system=system 923pio=system.iobus.port[13] 924 925[system.realview.sp810_fake] 926type=AmbaFake 927amba_id=0 928ignore_access=true 929pio_addr=268439552 930pio_latency=1000 931platform=system.realview 932system=system 933pio=system.iobus.port[14] 934 935[system.realview.ssp_fake] 936type=AmbaFake 937amba_id=0 938ignore_access=false 939pio_addr=268488704 940pio_latency=1000 941platform=system.realview 942system=system 943pio=system.iobus.port[19] 944 945[system.realview.timer0] 946type=Sp804 947amba_id=1316868 948clock0=1000000 949clock1=1000000 950gic=system.realview.gic 951int_num0=36 952int_num1=36 953pio_addr=268505088 954pio_latency=1000 955platform=system.realview 956system=system 957pio=system.iobus.port[3] 958 959[system.realview.timer1] 960type=Sp804 961amba_id=1316868 962clock0=1000000 963clock1=1000000 964gic=system.realview.gic 965int_num0=37 966int_num1=37 967pio_addr=268509184 968pio_latency=1000 969platform=system.realview 970system=system 971pio=system.iobus.port[4] 972 973[system.realview.uart] 974type=Pl011 975end_on_eot=false 976gic=system.realview.gic 977int_delay=100000 978int_num=44 979pio_addr=268472320 980pio_latency=1000 981platform=system.realview 982system=system 983terminal=system.terminal 984pio=system.iobus.port[1] 985 986[system.realview.uart1_fake] 987type=AmbaFake 988amba_id=0 989ignore_access=false 990pio_addr=268476416 991pio_latency=1000 992platform=system.realview 993system=system 994pio=system.iobus.port[10] 995 996[system.realview.uart2_fake] 997type=AmbaFake 998amba_id=0 999ignore_access=false 1000pio_addr=268480512 1001pio_latency=1000 1002platform=system.realview 1003system=system 1004pio=system.iobus.port[11] 1005 1006[system.realview.uart3_fake] 1007type=AmbaFake 1008amba_id=0 1009ignore_access=false 1010pio_addr=268484608 1011pio_latency=1000 1012platform=system.realview 1013system=system 1014pio=system.iobus.port[12] 1015 1016[system.realview.watchdog_fake] 1017type=AmbaFake 1018amba_id=0 1019ignore_access=false 1020pio_addr=268500992 1021pio_latency=1000 1022platform=system.realview 1023system=system 1024pio=system.iobus.port[15] 1025 1026[system.terminal] 1027type=Terminal 1028intr_control=system.intrctrl 1029number=0 1030output=true 1031port=3456 1032 1033[system.toL2Bus] 1034type=Bus 1035block_size=64 1036bus_id=0 1037clock=1000 1038header_cycles=1 1039use_default_range=false 1040width=64 1041port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 1042 1043[system.vncserver] 1044type=VncServer 1045frame_capture=false 1046number=0 1047port=5900 1048 1049