stats.txt revision 9838
15703SN/A 25703SN/A---------- Begin Simulation Statistics ---------- 39797Sandreas.hansson@arm.comsim_seconds 1.860201 # Number of seconds simulated 49797Sandreas.hansson@arm.comsim_ticks 1860200687500 # Number of ticks simulated 59797Sandreas.hansson@arm.comfinal_tick 1860200687500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 65703SN/Asim_freq 1000000000000 # Frequency of simulated ticks 79838Sandreas.hansson@arm.comhost_inst_rate 95880 # Simulator instruction rate (inst/s) 89838Sandreas.hansson@arm.comhost_op_rate 95880 # Simulator op (including micro ops) rate (op/s) 99838Sandreas.hansson@arm.comhost_tick_rate 3366492305 # Simulator tick rate (ticks/s) 109838Sandreas.hansson@arm.comhost_mem_usage 308824 # Number of bytes of host memory used 119838Sandreas.hansson@arm.comhost_seconds 552.56 # Real time elapsed on the host 129797Sandreas.hansson@arm.comsim_insts 52979577 # Number of instructions simulated 139797Sandreas.hansson@arm.comsim_ops 52979577 # Number of ops (including micro ops) simulated 149729Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 963968 # Number of bytes read from this memory 159797Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.data 24879296 # Number of bytes read from this memory 169729Sandreas.hansson@arm.comsystem.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory 179797Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 28495552 # Number of bytes read from this memory 189729Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 963968 # Number of instructions bytes read from this memory 199729Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 963968 # Number of instructions bytes read from this memory 209797Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 7515968 # Number of bytes written to this memory 219797Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 7515968 # Number of bytes written to this memory 229729Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 15062 # Number of read requests responded to by this memory 239797Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.data 388739 # Number of read requests responded to by this memory 249729Sandreas.hansson@arm.comsystem.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory 259797Sandreas.hansson@arm.comsystem.physmem.num_reads::total 445243 # Number of read requests responded to by this memory 269797Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 117437 # Number of write requests responded to by this memory 279797Sandreas.hansson@arm.comsystem.physmem.num_writes::total 117437 # Number of write requests responded to by this memory 289797Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 518206 # Total read bandwidth from this memory (bytes/s) 299797Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.data 13374523 # Total read bandwidth from this memory (bytes/s) 309797Sandreas.hansson@arm.comsystem.physmem.bw_read::tsunami.ide 1425807 # Total read bandwidth from this memory (bytes/s) 319797Sandreas.hansson@arm.comsystem.physmem.bw_read::total 15318536 # Total read bandwidth from this memory (bytes/s) 329797Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 518206 # Instruction read bandwidth from this memory (bytes/s) 339797Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 518206 # Instruction read bandwidth from this memory (bytes/s) 349797Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 4040407 # Write bandwidth from this memory (bytes/s) 359797Sandreas.hansson@arm.comsystem.physmem.bw_write::total 4040407 # Write bandwidth from this memory (bytes/s) 369797Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 4040407 # Total bandwidth to/from this memory (bytes/s) 379797Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 518206 # Total bandwidth to/from this memory (bytes/s) 389797Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.data 13374523 # Total bandwidth to/from this memory (bytes/s) 399797Sandreas.hansson@arm.comsystem.physmem.bw_total::tsunami.ide 1425807 # Total bandwidth to/from this memory (bytes/s) 409797Sandreas.hansson@arm.comsystem.physmem.bw_total::total 19358943 # Total bandwidth to/from this memory (bytes/s) 419838Sandreas.hansson@arm.comsystem.physmem.readReqs 445243 # Total number of read requests accepted by DRAM controller 429838Sandreas.hansson@arm.comsystem.physmem.writeReqs 117437 # Total number of write requests accepted by DRAM controller 439838Sandreas.hansson@arm.comsystem.physmem.readBursts 445243 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 449838Sandreas.hansson@arm.comsystem.physmem.writeBursts 117437 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts 459797Sandreas.hansson@arm.comsystem.physmem.bytesRead 28495552 # Total number of bytes read from memory 469797Sandreas.hansson@arm.comsystem.physmem.bytesWritten 7515968 # Total number of bytes written to memory 479797Sandreas.hansson@arm.comsystem.physmem.bytesConsumedRd 28495552 # bytesRead derated as per pkt->getSize() 489797Sandreas.hansson@arm.comsystem.physmem.bytesConsumedWr 7515968 # bytesWritten derated as per pkt->getSize() 499838Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 55 # Number of DRAM read bursts serviced by write Q 509797Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWrite 175 # Reqs where no action is needed 519797Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::0 28218 # Track reads on a per bank basis 529797Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::1 27974 # Track reads on a per bank basis 539797Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::2 28424 # Track reads on a per bank basis 549797Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::3 28004 # Track reads on a per bank basis 559797Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::4 27799 # Track reads on a per bank basis 569797Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::5 27230 # Track reads on a per bank basis 579797Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::6 27265 # Track reads on a per bank basis 589797Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::7 27330 # Track reads on a per bank basis 599797Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::8 27697 # Track reads on a per bank basis 609797Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::9 27264 # Track reads on a per bank basis 619797Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::10 28015 # Track reads on a per bank basis 629797Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::11 27528 # Track reads on a per bank basis 639729Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::12 27551 # Track reads on a per bank basis 649797Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::13 28243 # Track reads on a per bank basis 659797Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::14 28325 # Track reads on a per bank basis 669797Sandreas.hansson@arm.comsystem.physmem.perBankRdReqs::15 28321 # Track reads on a per bank basis 679797Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::0 7923 # Track writes on a per bank basis 689797Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::1 7495 # Track writes on a per bank basis 699797Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::2 7940 # Track writes on a per bank basis 709797Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::3 7495 # Track writes on a per bank basis 719797Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::4 7349 # Track writes on a per bank basis 729797Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::5 6687 # Track writes on a per bank basis 739797Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::6 6775 # Track writes on a per bank basis 749797Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::7 6715 # Track writes on a per bank basis 759797Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::8 7135 # Track writes on a per bank basis 769797Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::9 6683 # Track writes on a per bank basis 779797Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::10 7403 # Track writes on a per bank basis 789797Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::11 6968 # Track writes on a per bank basis 799797Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::12 7111 # Track writes on a per bank basis 809797Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::13 7888 # Track writes on a per bank basis 819797Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::14 8047 # Track writes on a per bank basis 829797Sandreas.hansson@arm.comsystem.physmem.perBankWrReqs::15 7823 # Track writes on a per bank basis 839312Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 849729Sandreas.hansson@arm.comsystem.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry 859797Sandreas.hansson@arm.comsystem.physmem.totGap 1860195209000 # Total gap between requests 869312Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Categorize read packet sizes 879312Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Categorize read packet sizes 889312Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Categorize read packet sizes 899312Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Categorize read packet sizes 909312Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Categorize read packet sizes 919312Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Categorize read packet sizes 929797Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 445243 # Categorize read packet sizes 939568Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Categorize write packet sizes 949568Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Categorize write packet sizes 959568Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Categorize write packet sizes 969568Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Categorize write packet sizes 979568Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Categorize write packet sizes 989568Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Categorize write packet sizes 999797Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 117437 # Categorize write packet sizes 1009797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 330882 # What read queue length does an incoming req see 1019797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 62598 # What read queue length does an incoming req see 1029797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 19901 # What read queue length does an incoming req see 1039797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 6571 # What read queue length does an incoming req see 1049797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 3340 # What read queue length does an incoming req see 1059797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 3039 # What read queue length does an incoming req see 1069797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 1564 # What read queue length does an incoming req see 1079797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 1518 # What read queue length does an incoming req see 1089797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 1479 # What read queue length does an incoming req see 1099797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 1464 # What read queue length does an incoming req see 1109797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 1426 # What read queue length does an incoming req see 1119797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 1412 # What read queue length does an incoming req see 1129797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 1394 # What read queue length does an incoming req see 1139797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 2035 # What read queue length does an incoming req see 1149797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 2333 # What read queue length does an incoming req see 1159797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 2204 # What read queue length does an incoming req see 1169797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 1198 # What read queue length does an incoming req see 1179797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 482 # What read queue length does an incoming req see 1189797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 211 # What read queue length does an incoming req see 1199797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 120 # What read queue length does an incoming req see 1209797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see 1219797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see 1229797Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1329729Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 3515 # What write queue length does an incoming req see 1339797Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 3753 # What write queue length does an incoming req see 1349797Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 4814 # What write queue length does an incoming req see 1359797Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 5103 # What write queue length does an incoming req see 1369797Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 5104 # What write queue length does an incoming req see 1379729Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 5105 # What write queue length does an incoming req see 1389729Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 5105 # What write queue length does an incoming req see 1399729Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 5105 # What write queue length does an incoming req see 1409729Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 5105 # What write queue length does an incoming req see 1419729Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 5106 # What write queue length does an incoming req see 1429729Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 5106 # What write queue length does an incoming req see 1439729Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 5106 # What write queue length does an incoming req see 1449729Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 5106 # What write queue length does an incoming req see 1459797Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 5106 # What write queue length does an incoming req see 1469797Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 5106 # What write queue length does an incoming req see 1479797Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 5106 # What write queue length does an incoming req see 1489797Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 5106 # What write queue length does an incoming req see 1499797Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 5106 # What write queue length does an incoming req see 1509797Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 5106 # What write queue length does an incoming req see 1519797Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 5106 # What write queue length does an incoming req see 1529797Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 5106 # What write queue length does an incoming req see 1539797Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 5106 # What write queue length does an incoming req see 1549729Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 5105 # What write queue length does an incoming req see 1559729Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 1591 # What write queue length does an incoming req see 1569797Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 1353 # What write queue length does an incoming req see 1579797Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 292 # What write queue length does an incoming req see 1589797Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see 1599797Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see 1609729Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see 1619729Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see 1629729Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see 1639729Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see 1649797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 37668 # Bytes accessed per row activation 1659797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 955.810131 # Bytes accessed per row activation 1669797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 232.523406 # Bytes accessed per row activation 1679797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 2430.690638 # Bytes accessed per row activation 1689797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::64-67 13031 34.59% 34.59% # Bytes accessed per row activation 1699797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-131 5648 14.99% 49.59% # Bytes accessed per row activation 1709797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::192-195 3558 9.45% 59.03% # Bytes accessed per row activation 1719797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-259 2240 5.95% 64.98% # Bytes accessed per row activation 1729797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::320-323 1644 4.36% 69.35% # Bytes accessed per row activation 1739797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-387 1436 3.81% 73.16% # Bytes accessed per row activation 1749797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::448-451 989 2.63% 75.78% # Bytes accessed per row activation 1759797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-515 804 2.13% 77.92% # Bytes accessed per row activation 1769797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::576-579 676 1.79% 79.71% # Bytes accessed per row activation 1779797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-643 516 1.37% 81.08% # Bytes accessed per row activation 1789797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::704-707 573 1.52% 82.60% # Bytes accessed per row activation 1799797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-771 541 1.44% 84.04% # Bytes accessed per row activation 1809797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::832-835 276 0.73% 84.77% # Bytes accessed per row activation 1819797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-899 231 0.61% 85.39% # Bytes accessed per row activation 1829797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::960-963 160 0.42% 85.81% # Bytes accessed per row activation 1839797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1027 263 0.70% 86.51% # Bytes accessed per row activation 1849797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1088-1091 87 0.23% 86.74% # Bytes accessed per row activation 1859797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1152-1155 129 0.34% 87.08% # Bytes accessed per row activation 1869797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1216-1219 75 0.20% 87.28% # Bytes accessed per row activation 1879797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1280-1283 153 0.41% 87.69% # Bytes accessed per row activation 1889797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1344-1347 242 0.64% 88.33% # Bytes accessed per row activation 1899797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1408-1411 113 0.30% 88.63% # Bytes accessed per row activation 1909797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1472-1475 462 1.23% 89.86% # Bytes accessed per row activation 1919797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1536-1539 590 1.57% 91.42% # Bytes accessed per row activation 1929797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1600-1603 81 0.22% 91.64% # Bytes accessed per row activation 1939797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1664-1667 28 0.07% 91.71% # Bytes accessed per row activation 1949797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1728-1731 16 0.04% 91.75% # Bytes accessed per row activation 1959797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1792-1795 89 0.24% 91.99% # Bytes accessed per row activation 1969797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1856-1859 26 0.07% 92.06% # Bytes accessed per row activation 1979797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1920-1923 8 0.02% 92.08% # Bytes accessed per row activation 1989797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1984-1987 14 0.04% 92.12% # Bytes accessed per row activation 1999797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2048-2051 43 0.11% 92.23% # Bytes accessed per row activation 2009797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2112-2115 28 0.07% 92.31% # Bytes accessed per row activation 2019797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2176-2179 4 0.01% 92.32% # Bytes accessed per row activation 2029797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2240-2243 1 0.00% 92.32% # Bytes accessed per row activation 2039797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2304-2307 18 0.05% 92.37% # Bytes accessed per row activation 2049797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2368-2371 7 0.02% 92.39% # Bytes accessed per row activation 2059797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2432-2435 3 0.01% 92.39% # Bytes accessed per row activation 2069797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2496-2499 5 0.01% 92.41% # Bytes accessed per row activation 2079797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2560-2563 3 0.01% 92.42% # Bytes accessed per row activation 2089797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2624-2627 4 0.01% 92.43% # Bytes accessed per row activation 2099797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2688-2691 5 0.01% 92.44% # Bytes accessed per row activation 2109797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2816-2819 3 0.01% 92.45% # Bytes accessed per row activation 2119797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2880-2883 3 0.01% 92.46% # Bytes accessed per row activation 2129797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::2944-2947 3 0.01% 92.46% # Bytes accessed per row activation 2139797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::3072-3075 6 0.02% 92.48% # Bytes accessed per row activation 2149797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::3136-3139 2 0.01% 92.48% # Bytes accessed per row activation 2159797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::3200-3203 1 0.00% 92.49% # Bytes accessed per row activation 2169797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::3264-3267 2 0.01% 92.49% # Bytes accessed per row activation 2179797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::3392-3395 3 0.01% 92.50% # Bytes accessed per row activation 2189797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::3456-3459 1 0.00% 92.50% # Bytes accessed per row activation 2199797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::3520-3523 2 0.01% 92.51% # Bytes accessed per row activation 2209797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::3584-3587 3 0.01% 92.52% # Bytes accessed per row activation 2219797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::3648-3651 2 0.01% 92.52% # Bytes accessed per row activation 2229797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::3712-3715 1 0.00% 92.52% # Bytes accessed per row activation 2239797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::3776-3779 2 0.01% 92.53% # Bytes accessed per row activation 2249797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::3904-3907 1 0.00% 92.53% # Bytes accessed per row activation 2259797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::3968-3971 1 0.00% 92.53% # Bytes accessed per row activation 2269797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::4032-4035 3 0.01% 92.54% # Bytes accessed per row activation 2279797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::4096-4099 1 0.00% 92.55% # Bytes accessed per row activation 2289797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::4160-4163 1 0.00% 92.55% # Bytes accessed per row activation 2299797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::4224-4227 1 0.00% 92.55% # Bytes accessed per row activation 2309797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::4288-4291 1 0.00% 92.55% # Bytes accessed per row activation 2319797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::4352-4355 1 0.00% 92.56% # Bytes accessed per row activation 2329797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::4416-4419 1 0.00% 92.56% # Bytes accessed per row activation 2339797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::4480-4483 1 0.00% 92.56% # Bytes accessed per row activation 2349797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::4544-4547 1 0.00% 92.56% # Bytes accessed per row activation 2359797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::4608-4611 2 0.01% 92.57% # Bytes accessed per row activation 2369797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::4800-4803 1 0.00% 92.57% # Bytes accessed per row activation 2379797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::4864-4867 1 0.00% 92.57% # Bytes accessed per row activation 2389797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::4928-4931 2 0.01% 92.58% # Bytes accessed per row activation 2399797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::4992-4995 2 0.01% 92.59% # Bytes accessed per row activation 2409797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::5120-5123 2 0.01% 92.59% # Bytes accessed per row activation 2419797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::5248-5251 1 0.00% 92.59% # Bytes accessed per row activation 2429797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::5312-5315 1 0.00% 92.60% # Bytes accessed per row activation 2439797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::5504-5507 1 0.00% 92.60% # Bytes accessed per row activation 2449797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::5568-5571 1 0.00% 92.60% # Bytes accessed per row activation 2459797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::5696-5699 2 0.01% 92.61% # Bytes accessed per row activation 2469797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::5824-5827 3 0.01% 92.61% # Bytes accessed per row activation 2479797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::5888-5891 1 0.00% 92.62% # Bytes accessed per row activation 2489797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::6016-6019 1 0.00% 92.62% # Bytes accessed per row activation 2499797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::6336-6339 1 0.00% 92.62% # Bytes accessed per row activation 2509797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::6400-6403 1 0.00% 92.63% # Bytes accessed per row activation 2519797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::6592-6595 2 0.01% 92.63% # Bytes accessed per row activation 2529797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::6656-6659 1 0.00% 92.63% # Bytes accessed per row activation 2539797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::6720-6723 1 0.00% 92.64% # Bytes accessed per row activation 2549797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::6848-6851 1 0.00% 92.64% # Bytes accessed per row activation 2559797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::7040-7043 1 0.00% 92.64% # Bytes accessed per row activation 2569797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::7168-7171 4 0.01% 92.65% # Bytes accessed per row activation 2579797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::7232-7235 1 0.00% 92.65% # Bytes accessed per row activation 2589797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::7296-7299 2 0.01% 92.66% # Bytes accessed per row activation 2599797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::7360-7363 2 0.01% 92.66% # Bytes accessed per row activation 2609797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::7424-7427 1 0.00% 92.67% # Bytes accessed per row activation 2619797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::7808-7811 3 0.01% 92.68% # Bytes accessed per row activation 2629797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::7872-7875 1 0.00% 92.68% # Bytes accessed per row activation 2639797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::7936-7939 2 0.01% 92.68% # Bytes accessed per row activation 2649797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::8000-8003 2 0.01% 92.69% # Bytes accessed per row activation 2659797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::8064-8067 2 0.01% 92.69% # Bytes accessed per row activation 2669797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::8128-8131 5 0.01% 92.71% # Bytes accessed per row activation 2679797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::8192-8195 2432 6.46% 99.16% # Bytes accessed per row activation 2689797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::8704-8707 1 0.00% 99.17% # Bytes accessed per row activation 2699797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::8960-8963 1 0.00% 99.17% # Bytes accessed per row activation 2709797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::9088-9091 1 0.00% 99.17% # Bytes accessed per row activation 2719797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::10688-10691 1 0.00% 99.17% # Bytes accessed per row activation 2729797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::10816-10819 1 0.00% 99.18% # Bytes accessed per row activation 2739797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::13696-13699 2 0.01% 99.18% # Bytes accessed per row activation 2749797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::13760-13763 1 0.00% 99.18% # Bytes accessed per row activation 2759797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::14080-14083 1 0.00% 99.19% # Bytes accessed per row activation 2769797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::14464-14467 3 0.01% 99.20% # Bytes accessed per row activation 2779797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::14528-14531 1 0.00% 99.20% # Bytes accessed per row activation 2789797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::14592-14595 1 0.00% 99.20% # Bytes accessed per row activation 2799797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::14784-14787 1 0.00% 99.20% # Bytes accessed per row activation 2809797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::14848-14851 2 0.01% 99.21% # Bytes accessed per row activation 2819729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::14976-14979 1 0.00% 99.21% # Bytes accessed per row activation 2829797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::15040-15043 1 0.00% 99.21% # Bytes accessed per row activation 2839797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::15168-15171 1 0.00% 99.22% # Bytes accessed per row activation 2849729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::15232-15235 1 0.00% 99.22% # Bytes accessed per row activation 2859797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::15296-15299 3 0.01% 99.23% # Bytes accessed per row activation 2869797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::15360-15363 13 0.03% 99.26% # Bytes accessed per row activation 2879797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::15872-15875 1 0.00% 99.26% # Bytes accessed per row activation 2889797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::16000-16003 1 0.00% 99.27% # Bytes accessed per row activation 2899729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::16192-16195 1 0.00% 99.27% # Bytes accessed per row activation 2909729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::16384-16387 240 0.64% 99.91% # Bytes accessed per row activation 2919729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::16448-16451 5 0.01% 99.92% # Bytes accessed per row activation 2929797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::16512-16515 4 0.01% 99.93% # Bytes accessed per row activation 2939797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::16576-16579 4 0.01% 99.94% # Bytes accessed per row activation 2949797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::16640-16643 5 0.01% 99.95% # Bytes accessed per row activation 2959797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::16704-16707 5 0.01% 99.97% # Bytes accessed per row activation 2969797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::16768-16771 3 0.01% 99.98% # Bytes accessed per row activation 2979729Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation 2989797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::16960-16963 2 0.01% 99.98% # Bytes accessed per row activation 2999797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::17024-17027 1 0.00% 99.99% # Bytes accessed per row activation 3009797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::17088-17091 5 0.01% 100.00% # Bytes accessed per row activation 3019797Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 37668 # Bytes accessed per row activation 3029797Sandreas.hansson@arm.comsystem.physmem.totQLat 6113897250 # Total cycles spent in queuing delays 3039797Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 13475242250 # Sum of mem lat for all requests 3049797Sandreas.hansson@arm.comsystem.physmem.totBusLat 2225940000 # Total cycles spent in databus access 3059797Sandreas.hansson@arm.comsystem.physmem.totBankLat 5135405000 # Total cycles spent in bank access 3069797Sandreas.hansson@arm.comsystem.physmem.avgQLat 13733.29 # Average queueing delay per request 3079797Sandreas.hansson@arm.comsystem.physmem.avgBankLat 11535.36 # Average bank access latency per request 3089490Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per request 3099797Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 30268.66 # Average memory access latency 3109797Sandreas.hansson@arm.comsystem.physmem.avgRdBW 15.32 # Average achieved read bandwidth in MB/s 3119729Sandreas.hansson@arm.comsystem.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MB/s 3129797Sandreas.hansson@arm.comsystem.physmem.avgConsumedRdBW 15.32 # Average consumed read bandwidth in MB/s 3139729Sandreas.hansson@arm.comsystem.physmem.avgConsumedWrBW 4.04 # Average consumed write bandwidth in MB/s 3149490Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 3159490Sandreas.hansson@arm.comsystem.physmem.busUtil 0.15 # Data bus utilization in percentage 3169312Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 0.01 # Average read queue length over time 3179797Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 9.67 # Average write queue length over time 3189797Sandreas.hansson@arm.comsystem.physmem.readRowHits 430049 # Number of row buffer hits during reads 3199797Sandreas.hansson@arm.comsystem.physmem.writeRowHits 94886 # Number of row buffer hits during writes 3209797Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 96.60 # Row buffer hit rate for reads 3219797Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes 3229797Sandreas.hansson@arm.comsystem.physmem.avgGap 3305955.80 # Average gap between requests 3239797Sandreas.hansson@arm.comsystem.membus.throughput 19401806 # Throughput (bytes/s) 3249797Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 295958 # Transaction distribution 3259797Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 295878 # Transaction distribution 3269729Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 9598 # Transaction distribution 3279729Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 9598 # Transaction distribution 3289797Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 117437 # Transaction distribution 3299797Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 178 # Transaction distribution 3309797Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 178 # Transaction distribution 3319797Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 156851 # Transaction distribution 3329797Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 156851 # Transaction distribution 3339797Sandreas.hansson@arm.comsystem.membus.trans_dist::BadAddressError 80 # Transaction distribution 3349729Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) 3359797Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884153 # Packet count per connected master and slave (bytes) 3369797Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 160 # Packet count per connected master and slave (bytes) 3379797Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::total 917369 # Packet count per connected master and slave (bytes) 3389729Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes) 3399729Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes) 3409797Sandreas.hansson@arm.comsystem.membus.pkt_count::total 1042048 # Packet count per connected master and slave (bytes) 3419729Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) 3429797Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30702464 # Cumulative packet size per connected master and slave (bytes) 3439797Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30746612 # Cumulative packet size per connected master and slave (bytes) 3449729Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes) 3459729Sandreas.hansson@arm.comsystem.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes) 3469797Sandreas.hansson@arm.comsystem.membus.tot_pkt_size::total 36055668 # Cumulative packet size per connected master and slave (bytes) 3479797Sandreas.hansson@arm.comsystem.membus.data_through_bus 36055668 # Total data (bytes) 3489729Sandreas.hansson@arm.comsystem.membus.snoop_data_through_bus 35584 # Total snoop data (bytes) 3499797Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 29849000 # Layer occupancy (ticks) 3509729Sandreas.hansson@arm.comsystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3519797Sandreas.hansson@arm.comsystem.membus.reqLayer1.occupancy 1552225748 # Layer occupancy (ticks) 3529729Sandreas.hansson@arm.comsystem.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 3539797Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 97500 # Layer occupancy (ticks) 3549729Sandreas.hansson@arm.comsystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3559797Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 3765192546 # Layer occupancy (ticks) 3569729Sandreas.hansson@arm.comsystem.membus.respLayer1.utilization 0.2 # Layer utilization (%) 3579797Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 376215241 # Layer occupancy (ticks) 3589729Sandreas.hansson@arm.comsystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3599838Sandreas.hansson@arm.comsystem.iocache.tags.replacements 41685 # number of replacements 3609838Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 1.261083 # Cycle average of tags in use 3619838Sandreas.hansson@arm.comsystem.iocache.tags.total_refs 0 # Total number of references to valid blocks. 3629838Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 3639838Sandreas.hansson@arm.comsystem.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 3649838Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 1710344305000 # Cycle when the warmup percentage was hit. 3659838Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::tsunami.ide 1.261083 # Average occupied blocks per requestor 3669838Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::tsunami.ide 0.078818 # Average percentage of cache occupancy 3679838Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.078818 # Average percentage of cache occupancy 3688835SAli.Saidi@ARM.comsystem.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 3698464SN/Asystem.iocache.ReadReq_misses::total 173 # number of ReadReq misses 3708835SAli.Saidi@ARM.comsystem.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 3718464SN/Asystem.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 3728835SAli.Saidi@ARM.comsystem.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 3738464SN/Asystem.iocache.demand_misses::total 41725 # number of demand (read+write) misses 3748835SAli.Saidi@ARM.comsystem.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 3758464SN/Asystem.iocache.overall_misses::total 41725 # number of overall misses 3769797Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::tsunami.ide 21345883 # number of ReadReq miss cycles 3779797Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 21345883 # number of ReadReq miss cycles 3789797Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::tsunami.ide 10482445518 # number of WriteReq miss cycles 3799797Sandreas.hansson@arm.comsystem.iocache.WriteReq_miss_latency::total 10482445518 # number of WriteReq miss cycles 3809797Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::tsunami.ide 10503791401 # number of demand (read+write) miss cycles 3819797Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 10503791401 # number of demand (read+write) miss cycles 3829797Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::tsunami.ide 10503791401 # number of overall miss cycles 3839797Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 10503791401 # number of overall miss cycles 3848835SAli.Saidi@ARM.comsystem.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 3858464SN/Asystem.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 3868835SAli.Saidi@ARM.comsystem.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 3878464SN/Asystem.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 3888835SAli.Saidi@ARM.comsystem.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 3898464SN/Asystem.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 3908835SAli.Saidi@ARM.comsystem.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 3918464SN/Asystem.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 3928835SAli.Saidi@ARM.comsystem.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 3939055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 3948835SAli.Saidi@ARM.comsystem.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 3959055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 3968835SAli.Saidi@ARM.comsystem.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 3979055Ssaidi@eecs.umich.edusystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 3988835SAli.Saidi@ARM.comsystem.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 3999055Ssaidi@eecs.umich.edusystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 4009797Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::tsunami.ide 123386.606936 # average ReadReq miss latency 4019797Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 123386.606936 # average ReadReq miss latency 4029797Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::tsunami.ide 252272.947584 # average WriteReq miss latency 4039797Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_miss_latency::total 252272.947584 # average WriteReq miss latency 4049797Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::tsunami.ide 251738.559641 # average overall miss latency 4059797Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 251738.559641 # average overall miss latency 4069797Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::tsunami.ide 251738.559641 # average overall miss latency 4079797Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 251738.559641 # average overall miss latency 4089797Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 274094 # number of cycles access was blocked 4098464SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 4109797Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 27191 # number of cycles access was blocked 4118464SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 4129797Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 10.080321 # average number of cycles each access was blocked 4138983Snate@binkert.orgsystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 4148464SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 4158464SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 4168835SAli.Saidi@ARM.comsystem.iocache.writebacks::writebacks 41512 # number of writebacks 4178835SAli.Saidi@ARM.comsystem.iocache.writebacks::total 41512 # number of writebacks 4188835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 4198835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 4208835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 4218835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 4228835SAli.Saidi@ARM.comsystem.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 4238835SAli.Saidi@ARM.comsystem.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 4248835SAli.Saidi@ARM.comsystem.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 4258835SAli.Saidi@ARM.comsystem.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 4269797Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12348383 # number of ReadReq MSHR miss cycles 4279797Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 12348383 # number of ReadReq MSHR miss cycles 4289797Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8320362536 # number of WriteReq MSHR miss cycles 4299797Sandreas.hansson@arm.comsystem.iocache.WriteReq_mshr_miss_latency::total 8320362536 # number of WriteReq MSHR miss cycles 4309797Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::tsunami.ide 8332710919 # number of demand (read+write) MSHR miss cycles 4319797Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 8332710919 # number of demand (read+write) MSHR miss cycles 4329797Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::tsunami.ide 8332710919 # number of overall MSHR miss cycles 4339797Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 8332710919 # number of overall MSHR miss cycles 4348835SAli.Saidi@ARM.comsystem.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 4359055Ssaidi@eecs.umich.edusystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 4368835SAli.Saidi@ARM.comsystem.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 4379055Ssaidi@eecs.umich.edusystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 4388835SAli.Saidi@ARM.comsystem.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 4399055Ssaidi@eecs.umich.edusystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 4408835SAli.Saidi@ARM.comsystem.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 4419055Ssaidi@eecs.umich.edusystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 4429797Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71377.936416 # average ReadReq mshr miss latency 4439797Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 71377.936416 # average ReadReq mshr miss latency 4449797Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 200239.760685 # average WriteReq mshr miss latency 4459797Sandreas.hansson@arm.comsystem.iocache.WriteReq_avg_mshr_miss_latency::total 200239.760685 # average WriteReq mshr miss latency 4469797Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199705.474392 # average overall mshr miss latency 4479797Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 199705.474392 # average overall mshr miss latency 4489797Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199705.474392 # average overall mshr miss latency 4499797Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 199705.474392 # average overall mshr miss latency 4508464SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 4518464SN/Asystem.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 4528464SN/Asystem.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 4538464SN/Asystem.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 4548464SN/Asystem.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 4558464SN/Asystem.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 4568464SN/Asystem.disk0.dma_write_txs 395 # Number of DMA write transactions. 4578464SN/Asystem.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 4588464SN/Asystem.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 4598464SN/Asystem.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 4608464SN/Asystem.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 4618464SN/Asystem.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 4628464SN/Asystem.disk2.dma_write_txs 1 # Number of DMA write transactions. 4639797Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 13856452 # Number of BP lookups 4649797Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 11625252 # Number of conditional branches predicted 4659797Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 398822 # Number of conditional branches incorrect 4669797Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 9666189 # Number of BTB lookups 4679797Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 5826807 # Number of BTB hits 4689481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 4699797Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 60.280292 # BTB Hit Percentage 4709797Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 904750 # Number of times the RAS was used to get a target. 4719797Sandreas.hansson@arm.comsystem.cpu.branchPred.RASInCorrect 39047 # Number of incorrect RAS predictions. 4728464SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 4738464SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 4748464SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 4758464SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 4769797Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 9922890 # DTB read hits 4779797Sandreas.hansson@arm.comsystem.cpu.dtb.read_misses 41426 # DTB read misses 4789797Sandreas.hansson@arm.comsystem.cpu.dtb.read_acv 537 # DTB read access violations 4799797Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 941977 # DTB read accesses 4809797Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 6601888 # DTB write hits 4819797Sandreas.hansson@arm.comsystem.cpu.dtb.write_misses 10414 # DTB write misses 4829797Sandreas.hansson@arm.comsystem.cpu.dtb.write_acv 409 # DTB write access violations 4839797Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 338180 # DTB write accesses 4849797Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits 16524778 # DTB hits 4859797Sandreas.hansson@arm.comsystem.cpu.dtb.data_misses 51840 # DTB misses 4869797Sandreas.hansson@arm.comsystem.cpu.dtb.data_acv 946 # DTB access violations 4879797Sandreas.hansson@arm.comsystem.cpu.dtb.data_accesses 1280157 # DTB accesses 4889797Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits 1306702 # ITB hits 4899797Sandreas.hansson@arm.comsystem.cpu.itb.fetch_misses 37996 # ITB misses 4909797Sandreas.hansson@arm.comsystem.cpu.itb.fetch_acv 1078 # ITB acv 4919797Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses 1344698 # ITB accesses 4928464SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 4938464SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 4948464SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 4958464SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 4968464SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 4978464SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 4988464SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 4998464SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 5008464SN/Asystem.cpu.itb.data_hits 0 # DTB hits 5018464SN/Asystem.cpu.itb.data_misses 0 # DTB misses 5028464SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 5038464SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 5049797Sandreas.hansson@arm.comsystem.cpu.numCycles 120724090 # number of cpu cycles simulated 5058464SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 5068464SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 5079797Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 28054756 # Number of cycles fetch is stalled on an Icache miss 5089797Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 70765698 # Number of instructions fetch has processed 5099797Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 13856452 # Number of branches that fetch encountered 5109797Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 6731557 # Number of branches that fetch has predicted taken 5119797Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 13261846 # Number of cycles fetch has run and was not squashing or blocked 5129797Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1996538 # Number of cycles fetch has spent squashing 5139797Sandreas.hansson@arm.comsystem.cpu.fetch.BlockedCycles 38180961 # Number of cycles fetch has spent blocked 5149797Sandreas.hansson@arm.comsystem.cpu.fetch.MiscStallCycles 33921 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 5159797Sandreas.hansson@arm.comsystem.cpu.fetch.PendingTrapStallCycles 253688 # Number of stall cycles due to pending traps 5169797Sandreas.hansson@arm.comsystem.cpu.fetch.PendingQuiesceStallCycles 362223 # Number of stall cycles due to pending quiesce instructions 5179797Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheWaitRetryStallCycles 233 # Number of stall cycles due to full MSHR 5189797Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 8553305 # Number of cache lines fetched 5199797Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 264520 # Number of outstanding Icache misses that were squashed 5209797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 81438491 # Number of instructions fetched each cycle (Total) 5219797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 0.868947 # Number of instructions fetched each cycle (Total) 5229797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.211995 # Number of instructions fetched each cycle (Total) 5238464SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 5249797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 68176645 83.72% 83.72% # Number of instructions fetched each cycle (Total) 5259797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 854498 1.05% 84.76% # Number of instructions fetched each cycle (Total) 5269797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 1700203 2.09% 86.85% # Number of instructions fetched each cycle (Total) 5279797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 823613 1.01% 87.86% # Number of instructions fetched each cycle (Total) 5289797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 2757448 3.39% 91.25% # Number of instructions fetched each cycle (Total) 5299797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 566024 0.70% 91.94% # Number of instructions fetched each cycle (Total) 5309797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 644448 0.79% 92.74% # Number of instructions fetched each cycle (Total) 5319797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 1011541 1.24% 93.98% # Number of instructions fetched each cycle (Total) 5329797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 4904071 6.02% 100.00% # Number of instructions fetched each cycle (Total) 5338464SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 5348464SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 5358464SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 5369797Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 81438491 # Number of instructions fetched each cycle (Total) 5379797Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.114778 # Number of branch fetches per cycle 5389797Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.586177 # Number of inst fetches per cycle 5399797Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 29237679 # Number of cycles decode is idle 5409797Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 37865551 # Number of cycles decode is blocked 5419797Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 12126902 # Number of cycles decode is running 5429797Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 959687 # Number of cycles decode is unblocking 5439797Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 1248671 # Number of cycles decode is squashing 5449797Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 585551 # Number of times decode resolved a branch 5459797Sandreas.hansson@arm.comsystem.cpu.decode.BranchMispred 42601 # Number of times decode detected a branch misprediction 5469797Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 69445978 # Number of instructions handled by decode 5479797Sandreas.hansson@arm.comsystem.cpu.decode.SquashedInsts 129475 # Number of squashed instructions handled by decode 5489797Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 1248671 # Number of cycles rename is squashing 5499797Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 30384491 # Number of cycles rename is idle 5509797Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 14146796 # Number of cycles rename is blocking 5519797Sandreas.hansson@arm.comsystem.cpu.rename.serializeStallCycles 20012830 # count of cycles rename stalled for serializing inst 5529797Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 11334710 # Number of cycles rename is running 5539797Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 4310991 # Number of cycles rename is unblocking 5549797Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 65667162 # Number of instructions processed by rename 5559797Sandreas.hansson@arm.comsystem.cpu.rename.ROBFullEvents 7173 # Number of times rename has blocked due to ROB full 5569797Sandreas.hansson@arm.comsystem.cpu.rename.IQFullEvents 505660 # Number of times rename has blocked due to IQ full 5579797Sandreas.hansson@arm.comsystem.cpu.rename.LSQFullEvents 1537414 # Number of times rename has blocked due to LSQ full 5589797Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 43855524 # Number of destination operands rename has renamed 5599797Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 79710296 # Number of register rename lookups that rename has made 5609797Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 79230933 # Number of integer rename lookups 5619797Sandreas.hansson@arm.comsystem.cpu.rename.fp_rename_lookups 479363 # Number of floating rename lookups 5629797Sandreas.hansson@arm.comsystem.cpu.rename.CommittedMaps 38179970 # Number of HB maps that are committed 5639797Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 5675546 # Number of HB maps that are undone due to squashing 5649797Sandreas.hansson@arm.comsystem.cpu.rename.serializingInsts 1682539 # count of serializing insts renamed 5659797Sandreas.hansson@arm.comsystem.cpu.rename.tempSerializingInsts 240064 # count of temporary serializing insts renamed 5669797Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 12233478 # count of insts added to the skid buffer 5679797Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 10440283 # Number of loads inserted to the mem dependence unit. 5689797Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 6900737 # Number of stores inserted to the mem dependence unit. 5699797Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 1318689 # Number of conflicting loads. 5709797Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingStores 855517 # Number of conflicting stores. 5719797Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 58206235 # Number of instructions added to the IQ (excludes non-spec) 5729797Sandreas.hansson@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 2050936 # Number of non-speculative instructions added to the IQ 5739797Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 56823082 # Number of instructions issued 5749797Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsIssued 100209 # Number of squashed instructions issued 5759797Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 6920159 # Number of squashed instructions iterated over during squash; mainly for profiling 5769797Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 3549975 # Number of squashed operands that are examined and possibly removed from graph 5779797Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 1389936 # Number of squashed non-spec instructions that were removed 5789797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 81438491 # Number of insts issued each cycle 5799797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.697742 # Number of insts issued each cycle 5809797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.359996 # Number of insts issued each cycle 5818464SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 5829797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 56732960 69.66% 69.66% # Number of insts issued each cycle 5839797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 10881055 13.36% 83.02% # Number of insts issued each cycle 5849797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 5157432 6.33% 89.36% # Number of insts issued each cycle 5859797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 3394617 4.17% 93.53% # Number of insts issued each cycle 5869797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 2629816 3.23% 96.76% # Number of insts issued each cycle 5879797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 1458992 1.79% 98.55% # Number of insts issued each cycle 5889797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 753848 0.93% 99.47% # Number of insts issued each cycle 5899797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 332168 0.41% 99.88% # Number of insts issued each cycle 5909797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 97603 0.12% 100.00% # Number of insts issued each cycle 5918464SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 5928464SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 5938464SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 5949797Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 81438491 # Number of insts issued each cycle 5958464SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 5969797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 91824 11.60% 11.60% # attempts to use FU when none available 5979797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 11.60% # attempts to use FU when none available 5989797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 11.60% # attempts to use FU when none available 5999797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 11.60% # attempts to use FU when none available 6009797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 11.60% # attempts to use FU when none available 6019797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 11.60% # attempts to use FU when none available 6029797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 11.60% # attempts to use FU when none available 6039797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 11.60% # attempts to use FU when none available 6049797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.60% # attempts to use FU when none available 6059797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 11.60% # attempts to use FU when none available 6069797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.60% # attempts to use FU when none available 6079797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 11.60% # attempts to use FU when none available 6089797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 11.60% # attempts to use FU when none available 6099797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 11.60% # attempts to use FU when none available 6109797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 11.60% # attempts to use FU when none available 6119797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 11.60% # attempts to use FU when none available 6129797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.60% # attempts to use FU when none available 6139797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 11.60% # attempts to use FU when none available 6149797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.60% # attempts to use FU when none available 6159797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.60% # attempts to use FU when none available 6169797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.60% # attempts to use FU when none available 6179797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.60% # attempts to use FU when none available 6189797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.60% # attempts to use FU when none available 6199797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.60% # attempts to use FU when none available 6209797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.60% # attempts to use FU when none available 6219797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.60% # attempts to use FU when none available 6229797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.60% # attempts to use FU when none available 6239797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.60% # attempts to use FU when none available 6249797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.60% # attempts to use FU when none available 6259797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 372747 47.08% 58.68% # attempts to use FU when none available 6269797Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 327090 41.32% 100.00% # attempts to use FU when none available 6278464SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 6288464SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 6299348SAli.Saidi@ARM.comsystem.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued 6309797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 38740473 68.18% 68.19% # Type of FU issued 6319797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 61726 0.11% 68.30% # Type of FU issued 6329797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued 6339797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.34% # Type of FU issued 6349797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.34% # Type of FU issued 6359797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.34% # Type of FU issued 6369797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.34% # Type of FU issued 6379797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.35% # Type of FU issued 6389797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.35% # Type of FU issued 6399797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.35% # Type of FU issued 6409797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.35% # Type of FU issued 6419797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.35% # Type of FU issued 6429797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.35% # Type of FU issued 6439797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.35% # Type of FU issued 6449797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.35% # Type of FU issued 6459797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.35% # Type of FU issued 6469797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.35% # Type of FU issued 6479797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.35% # Type of FU issued 6489797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.35% # Type of FU issued 6499797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.35% # Type of FU issued 6509797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.35% # Type of FU issued 6519797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.35% # Type of FU issued 6529797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.35% # Type of FU issued 6539797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.35% # Type of FU issued 6549797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.35% # Type of FU issued 6559797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.35% # Type of FU issued 6569797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.35% # Type of FU issued 6579797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.35% # Type of FU issued 6589797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.35% # Type of FU issued 6599797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 10354642 18.22% 86.57% # Type of FU issued 6609797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 6680643 11.76% 98.33% # Type of FU issued 6619797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IprAccess 949069 1.67% 100.00% # Type of FU issued 6628464SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 6639797Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 56823082 # Type of FU issued 6649797Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.470686 # Inst issue rate 6659797Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 791661 # FU busy when requested 6669797Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.013932 # FU busy rate (busy events/executed inst) 6679797Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 195283781 # Number of integer instruction queue reads 6689797Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 66854445 # Number of integer instruction queue writes 6699797Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 55585028 # Number of integer instruction queue wakeup accesses 6709797Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_reads 692743 # Number of floating instruction queue reads 6719797Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_writes 336682 # Number of floating instruction queue writes 6729797Sandreas.hansson@arm.comsystem.cpu.iq.fp_inst_queue_wakeup_accesses 327940 # Number of floating instruction queue wakeup accesses 6739797Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 57245966 # Number of integer alu accesses 6749797Sandreas.hansson@arm.comsystem.cpu.iq.fp_alu_accesses 361491 # Number of floating point alu accesses 6759797Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 598566 # Number of loads that had data forwarded from stores 6768464SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 6779797Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1347977 # Number of loads squashed 6789797Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 3312 # Number of memory responses ignored because the instruction is squashed 6799797Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 14180 # Number of memory ordering violations 6809797Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 522824 # Number of stores squashed 6818464SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 6828464SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 6839797Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.rescheduledLoads 17906 # Number of loads that were rescheduled 6849797Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 181081 # Number of times an access to memory failed due to the cache being blocked 6858464SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 6869797Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 1248671 # Number of cycles IEW is squashing 6879797Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 10233873 # Number of cycles IEW is blocking 6889797Sandreas.hansson@arm.comsystem.cpu.iew.iewUnblockCycles 701956 # Number of cycles IEW is unblocking 6899797Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 63782733 # Number of instructions dispatched to IQ 6909797Sandreas.hansson@arm.comsystem.cpu.iew.iewDispSquashedInsts 684936 # Number of squashed instructions skipped by dispatch 6919797Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 10440283 # Number of dispatched load instructions 6929797Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 6900737 # Number of dispatched store instructions 6939797Sandreas.hansson@arm.comsystem.cpu.iew.iewDispNonSpecInsts 1806230 # Number of dispatched non-speculative instructions 6949797Sandreas.hansson@arm.comsystem.cpu.iew.iewIQFullEvents 512408 # Number of times the IQ has become full, causing a stall 6959797Sandreas.hansson@arm.comsystem.cpu.iew.iewLSQFullEvents 17686 # Number of times the LSQ has become full, causing a stall 6969797Sandreas.hansson@arm.comsystem.cpu.iew.memOrderViolationEvents 14180 # Number of memory order violations 6979797Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 202063 # Number of branches that were predicted taken incorrectly 6989797Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 410564 # Number of branches that were predicted not taken incorrectly 6999797Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 612627 # Number of branch mispredicts detected at execute 7009797Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 56356224 # Number of executed instructions 7019797Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 9992501 # Number of load instructions executed 7029797Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 466857 # Number of squashed instructions skipped in execute 7038464SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 7049797Sandreas.hansson@arm.comsystem.cpu.iew.exec_nop 3525562 # number of nop insts executed 7059797Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 16620030 # number of memory reference insts executed 7069797Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 8925380 # Number of branches executed 7079797Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 6627529 # Number of stores executed 7089797Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.466818 # Inst execution rate 7099797Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 56027730 # cumulative count of insts sent to commit 7109797Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 55912968 # cumulative count of insts written-back 7119797Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 27713014 # num instructions producing a value 7129797Sandreas.hansson@arm.comsystem.cpu.iew.wb_consumers 37524402 # num instructions consuming a value 7138464SN/Asystem.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 7149797Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.463147 # insts written-back per cycle 7159797Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.738533 # average fanout of values written-back 7168464SN/Asystem.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 7179797Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 7495675 # The number of squashed insts skipped by commit 7189797Sandreas.hansson@arm.comsystem.cpu.commit.commitNonSpecStalls 661000 # The number of times commit has been forced to stall to communicate backwards 7199797Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 567647 # The number of times a branch was mispredicted 7209797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 80189820 # Number of insts commited each cycle 7219797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.700468 # Number of insts commited each cycle 7229797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.629642 # Number of insts commited each cycle 7238241SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 7249797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 59377156 74.05% 74.05% # Number of insts commited each cycle 7259797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 8657171 10.80% 84.84% # Number of insts commited each cycle 7269797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 4615541 5.76% 90.60% # Number of insts commited each cycle 7279797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 2519398 3.14% 93.74% # Number of insts commited each cycle 7289797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 1507686 1.88% 95.62% # Number of insts commited each cycle 7299797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 611065 0.76% 96.38% # Number of insts commited each cycle 7309797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 523948 0.65% 97.03% # Number of insts commited each cycle 7319797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 528681 0.66% 97.69% # Number of insts commited each cycle 7329797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 1849174 2.31% 100.00% # Number of insts commited each cycle 7338241SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 7348241SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 7358241SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 7369797Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 80189820 # Number of insts commited each cycle 7379797Sandreas.hansson@arm.comsystem.cpu.commit.committedInsts 56170363 # Number of instructions committed 7389797Sandreas.hansson@arm.comsystem.cpu.commit.committedOps 56170363 # Number of ops (including micro ops) committed 7398464SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 7409797Sandreas.hansson@arm.comsystem.cpu.commit.refs 15470219 # Number of memory references committed 7419797Sandreas.hansson@arm.comsystem.cpu.commit.loads 9092306 # Number of loads committed 7429797Sandreas.hansson@arm.comsystem.cpu.commit.membars 226376 # Number of memory barriers committed 7439797Sandreas.hansson@arm.comsystem.cpu.commit.branches 8439998 # Number of branches committed 7448517SN/Asystem.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. 7459797Sandreas.hansson@arm.comsystem.cpu.commit.int_insts 52019946 # Number of committed integer instructions. 7469797Sandreas.hansson@arm.comsystem.cpu.commit.function_calls 740578 # Number of function calls committed. 7479797Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 1849174 # number cycles where commit BW limit reached 7488464SN/Asystem.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 7499797Sandreas.hansson@arm.comsystem.cpu.rob.rob_reads 141757103 # The number of ROB reads 7509797Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 128582546 # The number of ROB writes 7519797Sandreas.hansson@arm.comsystem.cpu.timesIdled 1193264 # Number of times that the entire CPU went into an idle state and unscheduled itself 7529797Sandreas.hansson@arm.comsystem.cpu.idleCycles 39285599 # Total number of cycles that the CPU has spent unscheduled due to idling 7539797Sandreas.hansson@arm.comsystem.cpu.quiesceCycles 3599670846 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 7549797Sandreas.hansson@arm.comsystem.cpu.committedInsts 52979577 # Number of Instructions Simulated 7559797Sandreas.hansson@arm.comsystem.cpu.committedOps 52979577 # Number of Ops (including micro ops) Simulated 7569797Sandreas.hansson@arm.comsystem.cpu.committedInsts_total 52979577 # Number of Instructions Simulated 7579797Sandreas.hansson@arm.comsystem.cpu.cpi 2.278691 # CPI: Cycles Per Instruction 7589797Sandreas.hansson@arm.comsystem.cpu.cpi_total 2.278691 # CPI: Total CPI of All Threads 7599797Sandreas.hansson@arm.comsystem.cpu.ipc 0.438848 # IPC: Instructions Per Cycle 7609797Sandreas.hansson@arm.comsystem.cpu.ipc_total 0.438848 # IPC: Total IPC of All Threads 7619797Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 73899188 # number of integer regfile reads 7629797Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 40322867 # number of integer regfile writes 7639797Sandreas.hansson@arm.comsystem.cpu.fp_regfile_reads 166085 # number of floating regfile reads 7649797Sandreas.hansson@arm.comsystem.cpu.fp_regfile_writes 167427 # number of floating regfile writes 7659797Sandreas.hansson@arm.comsystem.cpu.misc_regfile_reads 1985758 # number of misc regfile reads 7669729Sandreas.hansson@arm.comsystem.cpu.misc_regfile_writes 938984 # number of misc regfile writes 7678464SN/Asystem.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 7688464SN/Asystem.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 7698464SN/Asystem.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 7708464SN/Asystem.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 7718464SN/Asystem.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 7728983Snate@binkert.orgsystem.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 7738464SN/Asystem.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 7748464SN/Asystem.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 7758983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 7768464SN/Asystem.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 7778464SN/Asystem.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 7788983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 7798464SN/Asystem.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 7808464SN/Asystem.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 7818983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 7828464SN/Asystem.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 7838464SN/Asystem.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 7848983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 7858464SN/Asystem.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 7868464SN/Asystem.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 7878983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 7888464SN/Asystem.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 7898464SN/Asystem.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 7908983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 7918464SN/Asystem.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 7928464SN/Asystem.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 7938983Snate@binkert.orgsystem.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 7948464SN/Asystem.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 7958983Snate@binkert.orgsystem.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 7968464SN/Asystem.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 7978464SN/Asystem.tsunami.ethernet.droppedPackets 0 # number of packets dropped 7989797Sandreas.hansson@arm.comsystem.iobus.throughput 1454551 # Throughput (bytes/s) 7999729Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 7103 # Transaction distribution 8009729Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 7103 # Transaction distribution 8019729Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 51150 # Transaction distribution 8029729Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 51150 # Transaction distribution 8039729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) 8049729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 8059729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 8069729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 8079729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 8089729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 8099729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 8109729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 8119729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 8129729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 8139729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 8149729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 8159729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes) 8169729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 8179729Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) 8189729Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes) 8199729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) 8209729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 8219729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 8229729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 8239729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 8249729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 8259729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 8269729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 8279729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 8289729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 8299729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 8309729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 8319729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes) 8329729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 8339729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 8349729Sandreas.hansson@arm.comsystem.iobus.tot_pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) 8359729Sandreas.hansson@arm.comsystem.iobus.data_through_bus 2705756 # Total data (bytes) 8369729Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 4663000 # Layer occupancy (ticks) 8379729Sandreas.hansson@arm.comsystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 8389729Sandreas.hansson@arm.comsystem.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 8399729Sandreas.hansson@arm.comsystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 8409729Sandreas.hansson@arm.comsystem.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 8419729Sandreas.hansson@arm.comsystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 8429729Sandreas.hansson@arm.comsystem.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 8439729Sandreas.hansson@arm.comsystem.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 8449729Sandreas.hansson@arm.comsystem.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) 8459729Sandreas.hansson@arm.comsystem.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 8469729Sandreas.hansson@arm.comsystem.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) 8479729Sandreas.hansson@arm.comsystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 8489729Sandreas.hansson@arm.comsystem.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) 8499729Sandreas.hansson@arm.comsystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 8509729Sandreas.hansson@arm.comsystem.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 8519729Sandreas.hansson@arm.comsystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 8529729Sandreas.hansson@arm.comsystem.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 8539729Sandreas.hansson@arm.comsystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 8549729Sandreas.hansson@arm.comsystem.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 8559729Sandreas.hansson@arm.comsystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 8569729Sandreas.hansson@arm.comsystem.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 8579729Sandreas.hansson@arm.comsystem.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 8589797Sandreas.hansson@arm.comsystem.iobus.reqLayer29.occupancy 378268160 # Layer occupancy (ticks) 8599729Sandreas.hansson@arm.comsystem.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 8609729Sandreas.hansson@arm.comsystem.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 8619729Sandreas.hansson@arm.comsystem.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 8629729Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) 8639729Sandreas.hansson@arm.comsystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 8649797Sandreas.hansson@arm.comsystem.iobus.respLayer1.occupancy 43098759 # Layer occupancy (ticks) 8659729Sandreas.hansson@arm.comsystem.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 8669797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.throughput 111927083 # Throughput (bytes/s) 8679797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadReq 2117675 # Transaction distribution 8689797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 2117578 # Transaction distribution 8699729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution 8709729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution 8719797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::Writeback 840831 # Transaction distribution 8729729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeReq 64 # Transaction distribution 8739797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 8749797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::UpgradeResp 66 # Transaction distribution 8759797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 342614 # Transaction distribution 8769797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 301063 # Transaction distribution 8779797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::BadAddressError 80 # Transaction distribution 8789838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2019865 # Packet count per connected master and slave (bytes) 8799838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3677460 # Packet count per connected master and slave (bytes) 8809838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 5697325 # Packet count per connected master and slave (bytes) 8819838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64631872 # Cumulative packet size per connected master and slave (bytes) 8829838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143567348 # Cumulative packet size per connected master and slave (bytes) 8839838Sandreas.hansson@arm.comsystem.cpu.toL2Bus.tot_pkt_size::total 208199220 # Cumulative packet size per connected master and slave (bytes) 8849797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.data_through_bus 208189172 # Total data (bytes) 8859797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_data_through_bus 17664 # Total snoop data (bytes) 8869797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 2480161498 # Layer occupancy (ticks) 8879729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 8889729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) 8899729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 8909797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 1518735644 # Layer occupancy (ticks) 8919729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 8929797Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 2194600669 # Layer occupancy (ticks) 8939729Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 8949838Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 1009263 # number of replacements 8959838Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 509.727374 # Cycle average of tags in use 8969838Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 7487430 # Total number of references to valid blocks. 8979838Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 1009771 # Sample count of references to valid blocks. 8989838Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 7.414978 # Average number of references to valid blocks. 8999838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 25799742250 # Cycle when the warmup percentage was hit. 9009838Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 509.727374 # Average occupied blocks per requestor 9019838Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.995561 # Average percentage of cache occupancy 9029838Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.995561 # Average percentage of cache occupancy 9039797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 7487431 # number of ReadReq hits 9049797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 7487431 # number of ReadReq hits 9059797Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 7487431 # number of demand (read+write) hits 9069797Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 7487431 # number of demand (read+write) hits 9079797Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 7487431 # number of overall hits 9089797Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 7487431 # number of overall hits 9099797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 1065872 # number of ReadReq misses 9109797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_misses::total 1065872 # number of ReadReq misses 9119797Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::cpu.inst 1065872 # number of demand (read+write) misses 9129797Sandreas.hansson@arm.comsystem.cpu.icache.demand_misses::total 1065872 # number of demand (read+write) misses 9139797Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::cpu.inst 1065872 # number of overall misses 9149797Sandreas.hansson@arm.comsystem.cpu.icache.overall_misses::total 1065872 # number of overall misses 9159797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 14976021459 # number of ReadReq miss cycles 9169797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 14976021459 # number of ReadReq miss cycles 9179797Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 14976021459 # number of demand (read+write) miss cycles 9189797Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 14976021459 # number of demand (read+write) miss cycles 9199797Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 14976021459 # number of overall miss cycles 9209797Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 14976021459 # number of overall miss cycles 9219797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 8553303 # number of ReadReq accesses(hits+misses) 9229797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 8553303 # number of ReadReq accesses(hits+misses) 9239797Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 8553303 # number of demand (read+write) accesses 9249797Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 8553303 # number of demand (read+write) accesses 9259797Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 8553303 # number of overall (read+write) accesses 9269797Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 8553303 # number of overall (read+write) accesses 9279797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124615 # miss rate for ReadReq accesses 9289797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.124615 # miss rate for ReadReq accesses 9299797Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.124615 # miss rate for demand accesses 9309797Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.124615 # miss rate for demand accesses 9319797Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.124615 # miss rate for overall accesses 9329797Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.124615 # miss rate for overall accesses 9339797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14050.487731 # average ReadReq miss latency 9349797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 14050.487731 # average ReadReq miss latency 9359797Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 14050.487731 # average overall miss latency 9369797Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 14050.487731 # average overall miss latency 9379797Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 14050.487731 # average overall miss latency 9389797Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 14050.487731 # average overall miss latency 9399797Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 8372 # number of cycles access was blocked 9409797Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 9419797Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 186 # number of cycles access was blocked 9429797Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 9439797Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs 45.010753 # average number of cycles each access was blocked 9449797Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 9458464SN/Asystem.cpu.icache.fast_writes 0 # number of fast writes performed 9468464SN/Asystem.cpu.icache.cache_copies 0 # number of cache copies performed 9479797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 55880 # number of ReadReq MSHR hits 9489797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 55880 # number of ReadReq MSHR hits 9499797Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 55880 # number of demand (read+write) MSHR hits 9509797Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 55880 # number of demand (read+write) MSHR hits 9519797Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 55880 # number of overall MSHR hits 9529797Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 55880 # number of overall MSHR hits 9539797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 1009992 # number of ReadReq MSHR misses 9549797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 1009992 # number of ReadReq MSHR misses 9559797Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 1009992 # number of demand (read+write) MSHR misses 9569797Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 1009992 # number of demand (read+write) MSHR misses 9579797Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 1009992 # number of overall MSHR misses 9589797Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 1009992 # number of overall MSHR misses 9599797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12273344851 # number of ReadReq MSHR miss cycles 9609797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 12273344851 # number of ReadReq MSHR miss cycles 9619797Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 12273344851 # number of demand (read+write) MSHR miss cycles 9629797Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 12273344851 # number of demand (read+write) MSHR miss cycles 9639797Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 12273344851 # number of overall MSHR miss cycles 9649797Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 12273344851 # number of overall MSHR miss cycles 9659797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118082 # mshr miss rate for ReadReq accesses 9669797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.118082 # mshr miss rate for ReadReq accesses 9679797Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118082 # mshr miss rate for demand accesses 9689797Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.118082 # mshr miss rate for demand accesses 9699797Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118082 # mshr miss rate for overall accesses 9709797Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.118082 # mshr miss rate for overall accesses 9719797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12151.922838 # average ReadReq mshr miss latency 9729797Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12151.922838 # average ReadReq mshr miss latency 9739797Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12151.922838 # average overall mshr miss latency 9749797Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 12151.922838 # average overall mshr miss latency 9759797Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12151.922838 # average overall mshr miss latency 9769797Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 12151.922838 # average overall mshr miss latency 9778464SN/Asystem.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 9789838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 338298 # number of replacements 9799838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 65343.107599 # Cycle average of tags in use 9809838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 2545731 # Total number of references to valid blocks. 9819838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 403463 # Sample count of references to valid blocks. 9829838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 6.309701 # Average number of references to valid blocks. 9839838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 5353022750 # Cycle when the warmup percentage was hit. 9849797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 53859.326644 # Average occupied blocks per requestor 9859838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 5308.706799 # Average occupied blocks per requestor 9869838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 6175.074156 # Average occupied blocks per requestor 9879797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.821828 # Average percentage of cache occupancy 9889797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.081004 # Average percentage of cache occupancy 9899797Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.094224 # Average percentage of cache occupancy 9909838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.997057 # Average percentage of cache occupancy 9919797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.inst 994809 # number of ReadReq hits 9929797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::cpu.data 826788 # number of ReadReq hits 9939797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_hits::total 1821597 # number of ReadReq hits 9949797Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::writebacks 840831 # number of Writeback hits 9959797Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_hits::total 840831 # number of Writeback hits 9969797Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 9979797Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits 9989797Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits 9999797Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits 10009797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 185623 # number of ReadExReq hits 10019797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 185623 # number of ReadExReq hits 10029797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 994809 # number of demand (read+write) hits 10039797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 1012411 # number of demand (read+write) hits 10049797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_hits::total 2007220 # number of demand (read+write) hits 10059797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 994809 # number of overall hits 10069797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 1012411 # number of overall hits 10079797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_hits::total 2007220 # number of overall hits 10089729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.inst 15064 # number of ReadReq misses 10099797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::cpu.data 273792 # number of ReadReq misses 10109797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_misses::total 288856 # number of ReadReq misses 10119797Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::cpu.data 38 # number of UpgradeReq misses 10129797Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_misses::total 38 # number of UpgradeReq misses 10139797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 115439 # number of ReadExReq misses 10149797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 115439 # number of ReadExReq misses 10159729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 15064 # number of demand (read+write) misses 10169797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 389231 # number of demand (read+write) misses 10179797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 404295 # number of demand (read+write) misses 10189729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 15064 # number of overall misses 10199797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 389231 # number of overall misses 10209797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 404295 # number of overall misses 10219797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1289741743 # number of ReadReq miss cycles 10229797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::cpu.data 17221594730 # number of ReadReq miss cycles 10239797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_latency::total 18511336473 # number of ReadReq miss cycles 10249797Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 285497 # number of UpgradeReq miss cycles 10259797Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_latency::total 285497 # number of UpgradeReq miss cycles 10269797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9397410357 # number of ReadExReq miss cycles 10279797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 9397410357 # number of ReadExReq miss cycles 10289797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 1289741743 # number of demand (read+write) miss cycles 10299797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 26619005087 # number of demand (read+write) miss cycles 10309797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 27908746830 # number of demand (read+write) miss cycles 10319797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 1289741743 # number of overall miss cycles 10329797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 26619005087 # number of overall miss cycles 10339797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 27908746830 # number of overall miss cycles 10349797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.inst 1009873 # number of ReadReq accesses(hits+misses) 10359797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::cpu.data 1100580 # number of ReadReq accesses(hits+misses) 10369797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_accesses::total 2110453 # number of ReadReq accesses(hits+misses) 10379797Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::writebacks 840831 # number of Writeback accesses(hits+misses) 10389797Sandreas.hansson@arm.comsystem.cpu.l2cache.Writeback_accesses::total 840831 # number of Writeback accesses(hits+misses) 10399729Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::cpu.data 64 # number of UpgradeReq accesses(hits+misses) 10409729Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_accesses::total 64 # number of UpgradeReq accesses(hits+misses) 10419797Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 10429797Sandreas.hansson@arm.comsystem.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 10439797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 301062 # number of ReadExReq accesses(hits+misses) 10449797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 301062 # number of ReadExReq accesses(hits+misses) 10459797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 1009873 # number of demand (read+write) accesses 10469797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 1401642 # number of demand (read+write) accesses 10479797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 2411515 # number of demand (read+write) accesses 10489797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 1009873 # number of overall (read+write) accesses 10499797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 1401642 # number of overall (read+write) accesses 10509797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 2411515 # number of overall (read+write) accesses 10519797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014917 # miss rate for ReadReq accesses 10529797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248771 # miss rate for ReadReq accesses 10539797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_miss_rate::total 0.136869 # miss rate for ReadReq accesses 10549797Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.593750 # miss rate for UpgradeReq accesses 10559797Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_miss_rate::total 0.593750 # miss rate for UpgradeReq accesses 10569797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383439 # miss rate for ReadExReq accesses 10579797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.383439 # miss rate for ReadExReq accesses 10589797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.014917 # miss rate for demand accesses 10599797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.277696 # miss rate for demand accesses 10609797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.167652 # miss rate for demand accesses 10619797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.014917 # miss rate for overall accesses 10629797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.277696 # miss rate for overall accesses 10639797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.167652 # miss rate for overall accesses 10649797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 85617.481612 # average ReadReq miss latency 10659797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62900.284632 # average ReadReq miss latency 10669797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_miss_latency::total 64084.999006 # average ReadReq miss latency 10679797Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7513.078947 # average UpgradeReq miss latency 10689797Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7513.078947 # average UpgradeReq miss latency 10699797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81405.853802 # average ReadExReq miss latency 10709797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 81405.853802 # average ReadExReq miss latency 10719797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85617.481612 # average overall miss latency 10729797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 68388.707701 # average overall miss latency 10739797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 69030.650466 # average overall miss latency 10749797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85617.481612 # average overall miss latency 10759797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 68388.707701 # average overall miss latency 10769797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 69030.650466 # average overall miss latency 10779285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 10789285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 10799285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 10809285Sandreas.hansson@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 10819285Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 10829285Sandreas.hansson@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 10839285Sandreas.hansson@arm.comsystem.cpu.l2cache.fast_writes 0 # number of fast writes performed 10849285Sandreas.hansson@arm.comsystem.cpu.l2cache.cache_copies 0 # number of cache copies performed 10859797Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::writebacks 75925 # number of writebacks 10869797Sandreas.hansson@arm.comsystem.cpu.l2cache.writebacks::total 75925 # number of writebacks 10879285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 10889285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 10899285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 10909285Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 10919285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 10929285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 10939729Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15063 # number of ReadReq MSHR misses 10949797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273792 # number of ReadReq MSHR misses 10959797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_misses::total 288855 # number of ReadReq MSHR misses 10969797Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 38 # number of UpgradeReq MSHR misses 10979797Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_misses::total 38 # number of UpgradeReq MSHR misses 10989797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115439 # number of ReadExReq MSHR misses 10999797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 115439 # number of ReadExReq MSHR misses 11009729Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 15063 # number of demand (read+write) MSHR misses 11019797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 389231 # number of demand (read+write) MSHR misses 11029797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 404294 # number of demand (read+write) MSHR misses 11039729Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 15063 # number of overall MSHR misses 11049797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 389231 # number of overall MSHR misses 11059797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 404294 # number of overall MSHR misses 11069797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1098682007 # number of ReadReq MSHR miss cycles 11079797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13807789270 # number of ReadReq MSHR miss cycles 11089797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_latency::total 14906471277 # number of ReadReq MSHR miss cycles 11099797Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 531034 # number of UpgradeReq MSHR miss cycles 11109797Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 531034 # number of UpgradeReq MSHR miss cycles 11119797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7972002643 # number of ReadExReq MSHR miss cycles 11129797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7972002643 # number of ReadExReq MSHR miss cycles 11139797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1098682007 # number of demand (read+write) MSHR miss cycles 11149797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21779791913 # number of demand (read+write) MSHR miss cycles 11159797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 22878473920 # number of demand (read+write) MSHR miss cycles 11169797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1098682007 # number of overall MSHR miss cycles 11179797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21779791913 # number of overall MSHR miss cycles 11189797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 22878473920 # number of overall MSHR miss cycles 11199797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333925000 # number of ReadReq MSHR uncacheable cycles 11209797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333925000 # number of ReadReq MSHR uncacheable cycles 11219797Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882616000 # number of WriteReq MSHR uncacheable cycles 11229797Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882616000 # number of WriteReq MSHR uncacheable cycles 11239797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216541000 # number of overall MSHR uncacheable cycles 11249797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216541000 # number of overall MSHR uncacheable cycles 11259797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014916 # mshr miss rate for ReadReq accesses 11269797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248771 # mshr miss rate for ReadReq accesses 11279797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136869 # mshr miss rate for ReadReq accesses 11289797Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.593750 # mshr miss rate for UpgradeReq accesses 11299797Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.593750 # mshr miss rate for UpgradeReq accesses 11309797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383439 # mshr miss rate for ReadExReq accesses 11319797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383439 # mshr miss rate for ReadExReq accesses 11329797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014916 # mshr miss rate for demand accesses 11339797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277696 # mshr miss rate for demand accesses 11349797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.167651 # mshr miss rate for demand accesses 11359797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014916 # mshr miss rate for overall accesses 11369797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277696 # mshr miss rate for overall accesses 11379797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.167651 # mshr miss rate for overall accesses 11389797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 72939.122817 # average ReadReq mshr miss latency 11399797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50431.675396 # average ReadReq mshr miss latency 11409797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51605.377359 # average ReadReq mshr miss latency 11419797Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13974.578947 # average UpgradeReq mshr miss latency 11429797Sandreas.hansson@arm.comsystem.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13974.578947 # average UpgradeReq mshr miss latency 11439797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69058.140169 # average ReadExReq mshr miss latency 11449797Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69058.140169 # average ReadExReq mshr miss latency 11459797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72939.122817 # average overall mshr miss latency 11469797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55955.953953 # average overall mshr miss latency 11479797Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 56588.705051 # average overall mshr miss latency 11489797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72939.122817 # average overall mshr miss latency 11499797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55955.953953 # average overall mshr miss latency 11509797Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 56588.705051 # average overall mshr miss latency 11519285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 11529285Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 11539285Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 11549285Sandreas.hansson@arm.comsystem.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 11559285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 11569285Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 11579285Sandreas.hansson@arm.comsystem.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 11589838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 1401048 # number of replacements 11599838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 511.994535 # Cycle average of tags in use 11609838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 11808107 # Total number of references to valid blocks. 11619838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.sampled_refs 1401560 # Sample count of references to valid blocks. 11629838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 8.424974 # Average number of references to valid blocks. 11639838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 25348250 # Cycle when the warmup percentage was hit. 11649838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 511.994535 # Average occupied blocks per requestor 11659838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy 11669838Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy 11679797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 7202464 # number of ReadReq hits 11689797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 7202464 # number of ReadReq hits 11699797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 4203713 # number of WriteReq hits 11709797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_hits::total 4203713 # number of WriteReq hits 11719797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 186169 # number of LoadLockedReq hits 11729797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 186169 # number of LoadLockedReq hits 11739797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 215520 # number of StoreCondReq hits 11749797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 215520 # number of StoreCondReq hits 11759797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 11406177 # number of demand (read+write) hits 11769797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 11406177 # number of demand (read+write) hits 11779797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 11406177 # number of overall hits 11789797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 11406177 # number of overall hits 11799797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 1806828 # number of ReadReq misses 11809797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_misses::total 1806828 # number of ReadReq misses 11819797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 1943975 # number of WriteReq misses 11829797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_misses::total 1943975 # number of WriteReq misses 11839797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::cpu.data 22707 # number of LoadLockedReq misses 11849797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_misses::total 22707 # number of LoadLockedReq misses 11859797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 11869797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 11879797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::cpu.data 3750803 # number of demand (read+write) misses 11889797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_misses::total 3750803 # number of demand (read+write) misses 11899797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::cpu.data 3750803 # number of overall misses 11909797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_misses::total 3750803 # number of overall misses 11919797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 39803546178 # number of ReadReq miss cycles 11929797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 39803546178 # number of ReadReq miss cycles 11939797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 76325479834 # number of WriteReq miss cycles 11949797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 76325479834 # number of WriteReq miss cycles 11959797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 321955499 # number of LoadLockedReq miss cycles 11969797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_latency::total 321955499 # number of LoadLockedReq miss cycles 11979797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles 11989797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles 11999797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 116129026012 # number of demand (read+write) miss cycles 12009797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 116129026012 # number of demand (read+write) miss cycles 12019797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 116129026012 # number of overall miss cycles 12029797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 116129026012 # number of overall miss cycles 12039797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 9009292 # number of ReadReq accesses(hits+misses) 12049797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 9009292 # number of ReadReq accesses(hits+misses) 12059797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 6147688 # number of WriteReq accesses(hits+misses) 12069797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 6147688 # number of WriteReq accesses(hits+misses) 12079797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 208876 # number of LoadLockedReq accesses(hits+misses) 12089797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 208876 # number of LoadLockedReq accesses(hits+misses) 12099797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 215522 # number of StoreCondReq accesses(hits+misses) 12109797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 215522 # number of StoreCondReq accesses(hits+misses) 12119797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 15156980 # number of demand (read+write) accesses 12129797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 15156980 # number of demand (read+write) accesses 12139797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 15156980 # number of overall (read+write) accesses 12149797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 15156980 # number of overall (read+write) accesses 12159797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200552 # miss rate for ReadReq accesses 12169797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.200552 # miss rate for ReadReq accesses 12179797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316212 # miss rate for WriteReq accesses 12189797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.316212 # miss rate for WriteReq accesses 12199797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108710 # miss rate for LoadLockedReq accesses 12209797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_miss_rate::total 0.108710 # miss rate for LoadLockedReq accesses 12219797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses 12229797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses 12239797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.247464 # miss rate for demand accesses 12249797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.247464 # miss rate for demand accesses 12259797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.247464 # miss rate for overall accesses 12269797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.247464 # miss rate for overall accesses 12279797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22029.515913 # average ReadReq miss latency 12289797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 22029.515913 # average ReadReq miss latency 12299797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39262.583024 # average WriteReq miss latency 12309797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 39262.583024 # average WriteReq miss latency 12319797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14178.689347 # average LoadLockedReq miss latency 12329797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14178.689347 # average LoadLockedReq miss latency 12339797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency 12349797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency 12359797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 30961.110464 # average overall miss latency 12369797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 30961.110464 # average overall miss latency 12379797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 30961.110464 # average overall miss latency 12389797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 30961.110464 # average overall miss latency 12399797Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 2958985 # number of cycles access was blocked 12409729Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 733 # number of cycles access was blocked 12419797Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_mshrs 97398 # number of cycles access was blocked 12429620Snilay@cs.wisc.edusystem.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked 12439797Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 30.380347 # average number of cycles each access was blocked 12449729Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets 104.714286 # average number of cycles each access was blocked 12459348SAli.Saidi@ARM.comsystem.cpu.dcache.fast_writes 0 # number of fast writes performed 12469348SAli.Saidi@ARM.comsystem.cpu.dcache.cache_copies 0 # number of cache copies performed 12479797Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::writebacks 840831 # number of writebacks 12489797Sandreas.hansson@arm.comsystem.cpu.dcache.writebacks::total 840831 # number of writebacks 12499797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 723109 # number of ReadReq MSHR hits 12509797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 723109 # number of ReadReq MSHR hits 12519797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643505 # number of WriteReq MSHR hits 12529797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 1643505 # number of WriteReq MSHR hits 12539797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5191 # number of LoadLockedReq MSHR hits 12549797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_hits::total 5191 # number of LoadLockedReq MSHR hits 12559797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 2366614 # number of demand (read+write) MSHR hits 12569797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_hits::total 2366614 # number of demand (read+write) MSHR hits 12579797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 2366614 # number of overall MSHR hits 12589797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_hits::total 2366614 # number of overall MSHR hits 12599797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083719 # number of ReadReq MSHR misses 12609797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 1083719 # number of ReadReq MSHR misses 12619797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 300470 # number of WriteReq MSHR misses 12629797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 300470 # number of WriteReq MSHR misses 12639797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17516 # number of LoadLockedReq MSHR misses 12649797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_misses::total 17516 # number of LoadLockedReq MSHR misses 12659797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 12669797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 12679797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 1384189 # number of demand (read+write) MSHR misses 12689797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_misses::total 1384189 # number of demand (read+write) MSHR misses 12699797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 1384189 # number of overall MSHR misses 12709797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_misses::total 1384189 # number of overall MSHR misses 12719797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26582228002 # number of ReadReq MSHR miss cycles 12729797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 26582228002 # number of ReadReq MSHR miss cycles 12739797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11613303338 # number of WriteReq MSHR miss cycles 12749797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 11613303338 # number of WriteReq MSHR miss cycles 12759797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 201814751 # number of LoadLockedReq MSHR miss cycles 12769797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 201814751 # number of LoadLockedReq MSHR miss cycles 12779797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles 12789797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles 12799797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 38195531340 # number of demand (read+write) MSHR miss cycles 12809797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 38195531340 # number of demand (read+write) MSHR miss cycles 12819797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 38195531340 # number of overall MSHR miss cycles 12829797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 38195531340 # number of overall MSHR miss cycles 12839797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424015000 # number of ReadReq MSHR uncacheable cycles 12849797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424015000 # number of ReadReq MSHR uncacheable cycles 12859797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997805998 # number of WriteReq MSHR uncacheable cycles 12869797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997805998 # number of WriteReq MSHR uncacheable cycles 12879797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421820998 # number of overall MSHR uncacheable cycles 12889797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_uncacheable_latency::total 3421820998 # number of overall MSHR uncacheable cycles 12899797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120289 # mshr miss rate for ReadReq accesses 12909797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120289 # mshr miss rate for ReadReq accesses 12919797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048875 # mshr miss rate for WriteReq accesses 12929797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048875 # mshr miss rate for WriteReq accesses 12939797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083858 # mshr miss rate for LoadLockedReq accesses 12949797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083858 # mshr miss rate for LoadLockedReq accesses 12959797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses 12969797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses 12979797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091324 # mshr miss rate for demand accesses 12989797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.091324 # mshr miss rate for demand accesses 12999797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091324 # mshr miss rate for overall accesses 13009797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.091324 # mshr miss rate for overall accesses 13019797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24528.709012 # average ReadReq mshr miss latency 13029797Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24528.709012 # average ReadReq mshr miss latency 13039797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38650.458741 # average WriteReq mshr miss latency 13049797Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38650.458741 # average WriteReq mshr miss latency 13059797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11521.737326 # average LoadLockedReq mshr miss latency 13069797Sandreas.hansson@arm.comsystem.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11521.737326 # average LoadLockedReq mshr miss latency 13079797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency 13089797Sandreas.hansson@arm.comsystem.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency 13099797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27594.158991 # average overall mshr miss latency 13109797Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 27594.158991 # average overall mshr miss latency 13119797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27594.158991 # average overall mshr miss latency 13129797Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 27594.158991 # average overall mshr miss latency 13139348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 13149348SAli.Saidi@ARM.comsystem.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 13159348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 13169348SAli.Saidi@ARM.comsystem.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 13179348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 13189348SAli.Saidi@ARM.comsystem.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 13199348SAli.Saidi@ARM.comsystem.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 13205703SN/Asystem.cpu.kern.inst.arm 0 # number of arm instructions executed 13219797Sandreas.hansson@arm.comsystem.cpu.kern.inst.quiesce 6440 # number of quiesce instructions executed 13229729Sandreas.hansson@arm.comsystem.cpu.kern.inst.hwrei 211017 # number of hwrei instructions executed 13239797Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::0 74663 40.97% 40.97% # number of times we switched to this ipl 13249285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 13259729Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl 13269797Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::31 105573 57.93% 100.00% # number of times we switched to this ipl 13279797Sandreas.hansson@arm.comsystem.cpu.kern.ipl_count::total 182247 # number of times we switched to this ipl 13289797Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::0 73296 49.32% 49.32% # number of times we switched to this ipl from a different ipl 13299285Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 13309729Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl 13319797Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::31 73296 49.32% 100.00% # number of times we switched to this ipl from a different ipl 13329797Sandreas.hansson@arm.comsystem.cpu.kern.ipl_good::total 148603 # number of times we switched to this ipl from a different ipl 13339797Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::0 1818706968000 97.77% 97.77% # number of cycles we spent at this ipl 13349797Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::21 64176500 0.00% 97.77% # number of cycles we spent at this ipl 13359797Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::22 554827000 0.03% 97.80% # number of cycles we spent at this ipl 13369797Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::31 40873882000 2.20% 100.00% # number of cycles we spent at this ipl 13379797Sandreas.hansson@arm.comsystem.cpu.kern.ipl_ticks::total 1860199853500 # number of cycles we spent at this ipl 13389797Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl 13396127SN/Asystem.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 13406127SN/Asystem.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 13419797Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::31 0.694268 # fraction of swpipl calls that actually changed the ipl 13429797Sandreas.hansson@arm.comsystem.cpu.kern.ipl_used::total 0.815393 # fraction of swpipl calls that actually changed the ipl 13436291SN/Asystem.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 13446291SN/Asystem.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 13456291SN/Asystem.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 13466291SN/Asystem.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 13476291SN/Asystem.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 13486291SN/Asystem.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 13496291SN/Asystem.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 13506291SN/Asystem.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 13516291SN/Asystem.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 13526291SN/Asystem.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 13536291SN/Asystem.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 13546291SN/Asystem.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 13556291SN/Asystem.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 13566291SN/Asystem.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 13576291SN/Asystem.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 13586291SN/Asystem.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 13596291SN/Asystem.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 13606291SN/Asystem.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 13616291SN/Asystem.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 13626291SN/Asystem.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 13636291SN/Asystem.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 13646291SN/Asystem.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 13656291SN/Asystem.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 13666291SN/Asystem.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 13676291SN/Asystem.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 13686291SN/Asystem.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 13696291SN/Asystem.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 13706291SN/Asystem.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 13716291SN/Asystem.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 13726291SN/Asystem.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 13736127SN/Asystem.cpu.kern.syscall::total 326 # number of syscalls executed 13748464SN/Asystem.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 13758464SN/Asystem.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 13768464SN/Asystem.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 13778464SN/Asystem.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 13789285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed 13799285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 13809199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 13819797Sandreas.hansson@arm.comsystem.cpu.kern.callpal::swpipl 175130 91.22% 93.43% # number of callpals executed 13829797Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed 13839285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 13849199Sandreas.hansson@arm.comsystem.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 13859285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 13869285Sandreas.hansson@arm.comsystem.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 13879729Sandreas.hansson@arm.comsystem.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed 13888464SN/Asystem.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 13898464SN/Asystem.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 13909729Sandreas.hansson@arm.comsystem.cpu.kern.callpal::total 191976 # number of callpals executed 13919729Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::kernel 5853 # number of protection mode switches 13929797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::user 1739 # number of protection mode switches 13939729Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch::idle 2094 # number of protection mode switches 13949797Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::kernel 1909 13959797Sandreas.hansson@arm.comsystem.cpu.kern.mode_good::user 1739 13968517SN/Asystem.cpu.kern.mode_good::idle 170 13979797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::kernel 0.326158 # fraction of useful protection mode switches 13988464SN/Asystem.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 13999729Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches 14009797Sandreas.hansson@arm.comsystem.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches 14019797Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::kernel 29671097000 1.60% 1.60% # number of ticks spent at the given mode 14029797Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::user 2774842500 0.15% 1.74% # number of ticks spent at the given mode 14039797Sandreas.hansson@arm.comsystem.cpu.kern.mode_ticks::idle 1827753906000 98.26% 100.00% # number of ticks spent at the given mode 14048517SN/Asystem.cpu.kern.swap_context 4177 # number of times the context was actually changed 14055703SN/A 14065703SN/A---------- End Simulation Statistics ---------- 1407