stats.txt revision 9838
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.860201 # Number of seconds simulated 4sim_ticks 1860200687500 # Number of ticks simulated 5final_tick 1860200687500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 95880 # Simulator instruction rate (inst/s) 8host_op_rate 95880 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3366492305 # Simulator tick rate (ticks/s) 10host_mem_usage 308824 # Number of bytes of host memory used 11host_seconds 552.56 # Real time elapsed on the host 12sim_insts 52979577 # Number of instructions simulated 13sim_ops 52979577 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 963968 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 24879296 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory 17system.physmem.bytes_read::total 28495552 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 963968 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 963968 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 7515968 # Number of bytes written to this memory 21system.physmem.bytes_written::total 7515968 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 15062 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 388739 # Number of read requests responded to by this memory 24system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 445243 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 117437 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 117437 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 518206 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 13374523 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::tsunami.ide 1425807 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 15318536 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 518206 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 518206 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 4040407 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 4040407 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 4040407 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 518206 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 13374523 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1425807 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 19358943 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.readReqs 445243 # Total number of read requests accepted by DRAM controller 42system.physmem.writeReqs 117437 # Total number of write requests accepted by DRAM controller 43system.physmem.readBursts 445243 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 44system.physmem.writeBursts 117437 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts 45system.physmem.bytesRead 28495552 # Total number of bytes read from memory 46system.physmem.bytesWritten 7515968 # Total number of bytes written to memory 47system.physmem.bytesConsumedRd 28495552 # bytesRead derated as per pkt->getSize() 48system.physmem.bytesConsumedWr 7515968 # bytesWritten derated as per pkt->getSize() 49system.physmem.servicedByWrQ 55 # Number of DRAM read bursts serviced by write Q 50system.physmem.neitherReadNorWrite 175 # Reqs where no action is needed 51system.physmem.perBankRdReqs::0 28218 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::1 27974 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::2 28424 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::3 28004 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::4 27799 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::5 27230 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::6 27265 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::7 27330 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::8 27697 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::9 27264 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::10 28015 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::11 27528 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::12 27551 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::13 28243 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::14 28325 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::15 28321 # Track reads on a per bank basis 67system.physmem.perBankWrReqs::0 7923 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::1 7495 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::2 7940 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::3 7495 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::4 7349 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::5 6687 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::6 6775 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::7 6715 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::8 7135 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::9 6683 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::10 7403 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::11 6968 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::12 7111 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::13 7888 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::14 8047 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::15 7823 # Track writes on a per bank basis 83system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 84system.physmem.numWrRetry 1 # Number of times wr buffer was full causing retry 85system.physmem.totGap 1860195209000 # Total gap between requests 86system.physmem.readPktSize::0 0 # Categorize read packet sizes 87system.physmem.readPktSize::1 0 # Categorize read packet sizes 88system.physmem.readPktSize::2 0 # Categorize read packet sizes 89system.physmem.readPktSize::3 0 # Categorize read packet sizes 90system.physmem.readPktSize::4 0 # Categorize read packet sizes 91system.physmem.readPktSize::5 0 # Categorize read packet sizes 92system.physmem.readPktSize::6 445243 # Categorize read packet sizes 93system.physmem.writePktSize::0 0 # Categorize write packet sizes 94system.physmem.writePktSize::1 0 # Categorize write packet sizes 95system.physmem.writePktSize::2 0 # Categorize write packet sizes 96system.physmem.writePktSize::3 0 # Categorize write packet sizes 97system.physmem.writePktSize::4 0 # Categorize write packet sizes 98system.physmem.writePktSize::5 0 # Categorize write packet sizes 99system.physmem.writePktSize::6 117437 # Categorize write packet sizes 100system.physmem.rdQLenPdf::0 330882 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 62598 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 19901 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 6571 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 3340 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 3039 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 1564 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 1518 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 1479 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 1464 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 1426 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 1412 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 1394 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 2035 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 2333 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 2204 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 1198 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 482 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 211 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 120 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 6 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 3 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 3515 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 3753 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 4814 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 5103 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 5104 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 5105 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 5105 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 5105 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 5105 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 5106 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 5106 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 5106 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 5106 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 5106 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 5106 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 5106 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 5106 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 5106 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 5106 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 5106 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 5106 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 5106 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 5105 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 1591 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 1353 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 292 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 2 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 1 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 1 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 1 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see 164system.physmem.bytesPerActivate::samples 37668 # Bytes accessed per row activation 165system.physmem.bytesPerActivate::mean 955.810131 # Bytes accessed per row activation 166system.physmem.bytesPerActivate::gmean 232.523406 # Bytes accessed per row activation 167system.physmem.bytesPerActivate::stdev 2430.690638 # Bytes accessed per row activation 168system.physmem.bytesPerActivate::64-67 13031 34.59% 34.59% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::128-131 5648 14.99% 49.59% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::192-195 3558 9.45% 59.03% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::256-259 2240 5.95% 64.98% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::320-323 1644 4.36% 69.35% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::384-387 1436 3.81% 73.16% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::448-451 989 2.63% 75.78% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::512-515 804 2.13% 77.92% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::576-579 676 1.79% 79.71% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::640-643 516 1.37% 81.08% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::704-707 573 1.52% 82.60% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::768-771 541 1.44% 84.04% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::832-835 276 0.73% 84.77% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::896-899 231 0.61% 85.39% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::960-963 160 0.42% 85.81% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1024-1027 263 0.70% 86.51% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1088-1091 87 0.23% 86.74% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1152-1155 129 0.34% 87.08% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1216-1219 75 0.20% 87.28% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1280-1283 153 0.41% 87.69% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1344-1347 242 0.64% 88.33% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::1408-1411 113 0.30% 88.63% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::1472-1475 462 1.23% 89.86% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::1536-1539 590 1.57% 91.42% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::1600-1603 81 0.22% 91.64% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1664-1667 28 0.07% 91.71% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1728-1731 16 0.04% 91.75% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1792-1795 89 0.24% 91.99% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1856-1859 26 0.07% 92.06% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::1920-1923 8 0.02% 92.08% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::1984-1987 14 0.04% 92.12% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::2048-2051 43 0.11% 92.23% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::2112-2115 28 0.07% 92.31% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::2176-2179 4 0.01% 92.32% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::2240-2243 1 0.00% 92.32% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::2304-2307 18 0.05% 92.37% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::2368-2371 7 0.02% 92.39% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::2432-2435 3 0.01% 92.39% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::2496-2499 5 0.01% 92.41% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::2560-2563 3 0.01% 92.42% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::2624-2627 4 0.01% 92.43% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2688-2691 5 0.01% 92.44% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2816-2819 3 0.01% 92.45% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2880-2883 3 0.01% 92.46% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::2944-2947 3 0.01% 92.46% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::3072-3075 6 0.02% 92.48% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::3136-3139 2 0.01% 92.48% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::3200-3203 1 0.00% 92.49% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::3264-3267 2 0.01% 92.49% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::3392-3395 3 0.01% 92.50% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::3456-3459 1 0.00% 92.50% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::3520-3523 2 0.01% 92.51% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::3584-3587 3 0.01% 92.52% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::3648-3651 2 0.01% 92.52% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::3712-3715 1 0.00% 92.52% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::3776-3779 2 0.01% 92.53% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3904-3907 1 0.00% 92.53% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3968-3971 1 0.00% 92.53% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::4032-4035 3 0.01% 92.54% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::4096-4099 1 0.00% 92.55% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::4160-4163 1 0.00% 92.55% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::4224-4227 1 0.00% 92.55% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::4288-4291 1 0.00% 92.55% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::4352-4355 1 0.00% 92.56% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::4416-4419 1 0.00% 92.56% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::4480-4483 1 0.00% 92.56% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::4544-4547 1 0.00% 92.56% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::4608-4611 2 0.01% 92.57% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::4800-4803 1 0.00% 92.57% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::4864-4867 1 0.00% 92.57% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::4928-4931 2 0.01% 92.58% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::4992-4995 2 0.01% 92.59% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::5120-5123 2 0.01% 92.59% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::5248-5251 1 0.00% 92.59% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::5312-5315 1 0.00% 92.60% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::5504-5507 1 0.00% 92.60% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::5568-5571 1 0.00% 92.60% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::5696-5699 2 0.01% 92.61% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::5824-5827 3 0.01% 92.61% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::5888-5891 1 0.00% 92.62% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::6016-6019 1 0.00% 92.62% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::6336-6339 1 0.00% 92.62% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::6400-6403 1 0.00% 92.63% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::6592-6595 2 0.01% 92.63% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::6656-6659 1 0.00% 92.63% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::6720-6723 1 0.00% 92.64% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::6848-6851 1 0.00% 92.64% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::7040-7043 1 0.00% 92.64% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::7168-7171 4 0.01% 92.65% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::7232-7235 1 0.00% 92.65% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::7296-7299 2 0.01% 92.66% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::7360-7363 2 0.01% 92.66% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::7424-7427 1 0.00% 92.67% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::7808-7811 3 0.01% 92.68% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::7872-7875 1 0.00% 92.68% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::7936-7939 2 0.01% 92.68% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::8000-8003 2 0.01% 92.69% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::8064-8067 2 0.01% 92.69% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::8128-8131 5 0.01% 92.71% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::8192-8195 2432 6.46% 99.16% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::8704-8707 1 0.00% 99.17% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::8960-8963 1 0.00% 99.17% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::9088-9091 1 0.00% 99.17% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::10688-10691 1 0.00% 99.17% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::10816-10819 1 0.00% 99.18% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::13696-13699 2 0.01% 99.18% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::13760-13763 1 0.00% 99.18% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.19% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::14464-14467 3 0.01% 99.20% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::14528-14531 1 0.00% 99.20% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.20% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.20% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::14848-14851 2 0.01% 99.21% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::14976-14979 1 0.00% 99.21% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.21% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::15168-15171 1 0.00% 99.22% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.22% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::15296-15299 3 0.01% 99.23% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::15360-15363 13 0.03% 99.26% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::15872-15875 1 0.00% 99.26% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::16000-16003 1 0.00% 99.27% # Bytes accessed per row activation 289system.physmem.bytesPerActivate::16192-16195 1 0.00% 99.27% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::16384-16387 240 0.64% 99.91% # Bytes accessed per row activation 291system.physmem.bytesPerActivate::16448-16451 5 0.01% 99.92% # Bytes accessed per row activation 292system.physmem.bytesPerActivate::16512-16515 4 0.01% 99.93% # Bytes accessed per row activation 293system.physmem.bytesPerActivate::16576-16579 4 0.01% 99.94% # Bytes accessed per row activation 294system.physmem.bytesPerActivate::16640-16643 5 0.01% 99.95% # Bytes accessed per row activation 295system.physmem.bytesPerActivate::16704-16707 5 0.01% 99.97% # Bytes accessed per row activation 296system.physmem.bytesPerActivate::16768-16771 3 0.01% 99.98% # Bytes accessed per row activation 297system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation 298system.physmem.bytesPerActivate::16960-16963 2 0.01% 99.98% # Bytes accessed per row activation 299system.physmem.bytesPerActivate::17024-17027 1 0.00% 99.99% # Bytes accessed per row activation 300system.physmem.bytesPerActivate::17088-17091 5 0.01% 100.00% # Bytes accessed per row activation 301system.physmem.bytesPerActivate::total 37668 # Bytes accessed per row activation 302system.physmem.totQLat 6113897250 # Total cycles spent in queuing delays 303system.physmem.totMemAccLat 13475242250 # Sum of mem lat for all requests 304system.physmem.totBusLat 2225940000 # Total cycles spent in databus access 305system.physmem.totBankLat 5135405000 # Total cycles spent in bank access 306system.physmem.avgQLat 13733.29 # Average queueing delay per request 307system.physmem.avgBankLat 11535.36 # Average bank access latency per request 308system.physmem.avgBusLat 5000.00 # Average bus latency per request 309system.physmem.avgMemAccLat 30268.66 # Average memory access latency 310system.physmem.avgRdBW 15.32 # Average achieved read bandwidth in MB/s 311system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MB/s 312system.physmem.avgConsumedRdBW 15.32 # Average consumed read bandwidth in MB/s 313system.physmem.avgConsumedWrBW 4.04 # Average consumed write bandwidth in MB/s 314system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 315system.physmem.busUtil 0.15 # Data bus utilization in percentage 316system.physmem.avgRdQLen 0.01 # Average read queue length over time 317system.physmem.avgWrQLen 9.67 # Average write queue length over time 318system.physmem.readRowHits 430049 # Number of row buffer hits during reads 319system.physmem.writeRowHits 94886 # Number of row buffer hits during writes 320system.physmem.readRowHitRate 96.60 # Row buffer hit rate for reads 321system.physmem.writeRowHitRate 80.80 # Row buffer hit rate for writes 322system.physmem.avgGap 3305955.80 # Average gap between requests 323system.membus.throughput 19401806 # Throughput (bytes/s) 324system.membus.trans_dist::ReadReq 295958 # Transaction distribution 325system.membus.trans_dist::ReadResp 295878 # Transaction distribution 326system.membus.trans_dist::WriteReq 9598 # Transaction distribution 327system.membus.trans_dist::WriteResp 9598 # Transaction distribution 328system.membus.trans_dist::Writeback 117437 # Transaction distribution 329system.membus.trans_dist::UpgradeReq 178 # Transaction distribution 330system.membus.trans_dist::UpgradeResp 178 # Transaction distribution 331system.membus.trans_dist::ReadExReq 156851 # Transaction distribution 332system.membus.trans_dist::ReadExResp 156851 # Transaction distribution 333system.membus.trans_dist::BadAddressError 80 # Transaction distribution 334system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) 335system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884153 # Packet count per connected master and slave (bytes) 336system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 160 # Packet count per connected master and slave (bytes) 337system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917369 # Packet count per connected master and slave (bytes) 338system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124679 # Packet count per connected master and slave (bytes) 339system.membus.pkt_count_system.iocache.mem_side::total 124679 # Packet count per connected master and slave (bytes) 340system.membus.pkt_count::total 1042048 # Packet count per connected master and slave (bytes) 341system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) 342system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30702464 # Cumulative packet size per connected master and slave (bytes) 343system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30746612 # Cumulative packet size per connected master and slave (bytes) 344system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5309056 # Cumulative packet size per connected master and slave (bytes) 345system.membus.tot_pkt_size_system.iocache.mem_side::total 5309056 # Cumulative packet size per connected master and slave (bytes) 346system.membus.tot_pkt_size::total 36055668 # Cumulative packet size per connected master and slave (bytes) 347system.membus.data_through_bus 36055668 # Total data (bytes) 348system.membus.snoop_data_through_bus 35584 # Total snoop data (bytes) 349system.membus.reqLayer0.occupancy 29849000 # Layer occupancy (ticks) 350system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 351system.membus.reqLayer1.occupancy 1552225748 # Layer occupancy (ticks) 352system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) 353system.membus.reqLayer2.occupancy 97500 # Layer occupancy (ticks) 354system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 355system.membus.respLayer1.occupancy 3765192546 # Layer occupancy (ticks) 356system.membus.respLayer1.utilization 0.2 # Layer utilization (%) 357system.membus.respLayer2.occupancy 376215241 # Layer occupancy (ticks) 358system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 359system.iocache.tags.replacements 41685 # number of replacements 360system.iocache.tags.tagsinuse 1.261083 # Cycle average of tags in use 361system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 362system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. 363system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 364system.iocache.tags.warmup_cycle 1710344305000 # Cycle when the warmup percentage was hit. 365system.iocache.tags.occ_blocks::tsunami.ide 1.261083 # Average occupied blocks per requestor 366system.iocache.tags.occ_percent::tsunami.ide 0.078818 # Average percentage of cache occupancy 367system.iocache.tags.occ_percent::total 0.078818 # Average percentage of cache occupancy 368system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses 369system.iocache.ReadReq_misses::total 173 # number of ReadReq misses 370system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 371system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 372system.iocache.demand_misses::tsunami.ide 41725 # number of demand (read+write) misses 373system.iocache.demand_misses::total 41725 # number of demand (read+write) misses 374system.iocache.overall_misses::tsunami.ide 41725 # number of overall misses 375system.iocache.overall_misses::total 41725 # number of overall misses 376system.iocache.ReadReq_miss_latency::tsunami.ide 21345883 # number of ReadReq miss cycles 377system.iocache.ReadReq_miss_latency::total 21345883 # number of ReadReq miss cycles 378system.iocache.WriteReq_miss_latency::tsunami.ide 10482445518 # number of WriteReq miss cycles 379system.iocache.WriteReq_miss_latency::total 10482445518 # number of WriteReq miss cycles 380system.iocache.demand_miss_latency::tsunami.ide 10503791401 # number of demand (read+write) miss cycles 381system.iocache.demand_miss_latency::total 10503791401 # number of demand (read+write) miss cycles 382system.iocache.overall_miss_latency::tsunami.ide 10503791401 # number of overall miss cycles 383system.iocache.overall_miss_latency::total 10503791401 # number of overall miss cycles 384system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) 385system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) 386system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) 387system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) 388system.iocache.demand_accesses::tsunami.ide 41725 # number of demand (read+write) accesses 389system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses 390system.iocache.overall_accesses::tsunami.ide 41725 # number of overall (read+write) accesses 391system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses 392system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 393system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 394system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 395system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 396system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 397system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 398system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 399system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 400system.iocache.ReadReq_avg_miss_latency::tsunami.ide 123386.606936 # average ReadReq miss latency 401system.iocache.ReadReq_avg_miss_latency::total 123386.606936 # average ReadReq miss latency 402system.iocache.WriteReq_avg_miss_latency::tsunami.ide 252272.947584 # average WriteReq miss latency 403system.iocache.WriteReq_avg_miss_latency::total 252272.947584 # average WriteReq miss latency 404system.iocache.demand_avg_miss_latency::tsunami.ide 251738.559641 # average overall miss latency 405system.iocache.demand_avg_miss_latency::total 251738.559641 # average overall miss latency 406system.iocache.overall_avg_miss_latency::tsunami.ide 251738.559641 # average overall miss latency 407system.iocache.overall_avg_miss_latency::total 251738.559641 # average overall miss latency 408system.iocache.blocked_cycles::no_mshrs 274094 # number of cycles access was blocked 409system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 410system.iocache.blocked::no_mshrs 27191 # number of cycles access was blocked 411system.iocache.blocked::no_targets 0 # number of cycles access was blocked 412system.iocache.avg_blocked_cycles::no_mshrs 10.080321 # average number of cycles each access was blocked 413system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 414system.iocache.fast_writes 0 # number of fast writes performed 415system.iocache.cache_copies 0 # number of cache copies performed 416system.iocache.writebacks::writebacks 41512 # number of writebacks 417system.iocache.writebacks::total 41512 # number of writebacks 418system.iocache.ReadReq_mshr_misses::tsunami.ide 173 # number of ReadReq MSHR misses 419system.iocache.ReadReq_mshr_misses::total 173 # number of ReadReq MSHR misses 420system.iocache.WriteReq_mshr_misses::tsunami.ide 41552 # number of WriteReq MSHR misses 421system.iocache.WriteReq_mshr_misses::total 41552 # number of WriteReq MSHR misses 422system.iocache.demand_mshr_misses::tsunami.ide 41725 # number of demand (read+write) MSHR misses 423system.iocache.demand_mshr_misses::total 41725 # number of demand (read+write) MSHR misses 424system.iocache.overall_mshr_misses::tsunami.ide 41725 # number of overall MSHR misses 425system.iocache.overall_mshr_misses::total 41725 # number of overall MSHR misses 426system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12348383 # number of ReadReq MSHR miss cycles 427system.iocache.ReadReq_mshr_miss_latency::total 12348383 # number of ReadReq MSHR miss cycles 428system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8320362536 # number of WriteReq MSHR miss cycles 429system.iocache.WriteReq_mshr_miss_latency::total 8320362536 # number of WriteReq MSHR miss cycles 430system.iocache.demand_mshr_miss_latency::tsunami.ide 8332710919 # number of demand (read+write) MSHR miss cycles 431system.iocache.demand_mshr_miss_latency::total 8332710919 # number of demand (read+write) MSHR miss cycles 432system.iocache.overall_mshr_miss_latency::tsunami.ide 8332710919 # number of overall MSHR miss cycles 433system.iocache.overall_mshr_miss_latency::total 8332710919 # number of overall MSHR miss cycles 434system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses 435system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 436system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses 437system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 438system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses 439system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 440system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses 441system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 442system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 71377.936416 # average ReadReq mshr miss latency 443system.iocache.ReadReq_avg_mshr_miss_latency::total 71377.936416 # average ReadReq mshr miss latency 444system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 200239.760685 # average WriteReq mshr miss latency 445system.iocache.WriteReq_avg_mshr_miss_latency::total 200239.760685 # average WriteReq mshr miss latency 446system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 199705.474392 # average overall mshr miss latency 447system.iocache.demand_avg_mshr_miss_latency::total 199705.474392 # average overall mshr miss latency 448system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 199705.474392 # average overall mshr miss latency 449system.iocache.overall_avg_mshr_miss_latency::total 199705.474392 # average overall mshr miss latency 450system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 451system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 452system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 453system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 454system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 455system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 456system.disk0.dma_write_txs 395 # Number of DMA write transactions. 457system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 458system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 459system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 460system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 461system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 462system.disk2.dma_write_txs 1 # Number of DMA write transactions. 463system.cpu.branchPred.lookups 13856452 # Number of BP lookups 464system.cpu.branchPred.condPredicted 11625252 # Number of conditional branches predicted 465system.cpu.branchPred.condIncorrect 398822 # Number of conditional branches incorrect 466system.cpu.branchPred.BTBLookups 9666189 # Number of BTB lookups 467system.cpu.branchPred.BTBHits 5826807 # Number of BTB hits 468system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 469system.cpu.branchPred.BTBHitPct 60.280292 # BTB Hit Percentage 470system.cpu.branchPred.usedRAS 904750 # Number of times the RAS was used to get a target. 471system.cpu.branchPred.RASInCorrect 39047 # Number of incorrect RAS predictions. 472system.cpu.dtb.fetch_hits 0 # ITB hits 473system.cpu.dtb.fetch_misses 0 # ITB misses 474system.cpu.dtb.fetch_acv 0 # ITB acv 475system.cpu.dtb.fetch_accesses 0 # ITB accesses 476system.cpu.dtb.read_hits 9922890 # DTB read hits 477system.cpu.dtb.read_misses 41426 # DTB read misses 478system.cpu.dtb.read_acv 537 # DTB read access violations 479system.cpu.dtb.read_accesses 941977 # DTB read accesses 480system.cpu.dtb.write_hits 6601888 # DTB write hits 481system.cpu.dtb.write_misses 10414 # DTB write misses 482system.cpu.dtb.write_acv 409 # DTB write access violations 483system.cpu.dtb.write_accesses 338180 # DTB write accesses 484system.cpu.dtb.data_hits 16524778 # DTB hits 485system.cpu.dtb.data_misses 51840 # DTB misses 486system.cpu.dtb.data_acv 946 # DTB access violations 487system.cpu.dtb.data_accesses 1280157 # DTB accesses 488system.cpu.itb.fetch_hits 1306702 # ITB hits 489system.cpu.itb.fetch_misses 37996 # ITB misses 490system.cpu.itb.fetch_acv 1078 # ITB acv 491system.cpu.itb.fetch_accesses 1344698 # ITB accesses 492system.cpu.itb.read_hits 0 # DTB read hits 493system.cpu.itb.read_misses 0 # DTB read misses 494system.cpu.itb.read_acv 0 # DTB read access violations 495system.cpu.itb.read_accesses 0 # DTB read accesses 496system.cpu.itb.write_hits 0 # DTB write hits 497system.cpu.itb.write_misses 0 # DTB write misses 498system.cpu.itb.write_acv 0 # DTB write access violations 499system.cpu.itb.write_accesses 0 # DTB write accesses 500system.cpu.itb.data_hits 0 # DTB hits 501system.cpu.itb.data_misses 0 # DTB misses 502system.cpu.itb.data_acv 0 # DTB access violations 503system.cpu.itb.data_accesses 0 # DTB accesses 504system.cpu.numCycles 120724090 # number of cpu cycles simulated 505system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 506system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 507system.cpu.fetch.icacheStallCycles 28054756 # Number of cycles fetch is stalled on an Icache miss 508system.cpu.fetch.Insts 70765698 # Number of instructions fetch has processed 509system.cpu.fetch.Branches 13856452 # Number of branches that fetch encountered 510system.cpu.fetch.predictedBranches 6731557 # Number of branches that fetch has predicted taken 511system.cpu.fetch.Cycles 13261846 # Number of cycles fetch has run and was not squashing or blocked 512system.cpu.fetch.SquashCycles 1996538 # Number of cycles fetch has spent squashing 513system.cpu.fetch.BlockedCycles 38180961 # Number of cycles fetch has spent blocked 514system.cpu.fetch.MiscStallCycles 33921 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 515system.cpu.fetch.PendingTrapStallCycles 253688 # Number of stall cycles due to pending traps 516system.cpu.fetch.PendingQuiesceStallCycles 362223 # Number of stall cycles due to pending quiesce instructions 517system.cpu.fetch.IcacheWaitRetryStallCycles 233 # Number of stall cycles due to full MSHR 518system.cpu.fetch.CacheLines 8553305 # Number of cache lines fetched 519system.cpu.fetch.IcacheSquashes 264520 # Number of outstanding Icache misses that were squashed 520system.cpu.fetch.rateDist::samples 81438491 # Number of instructions fetched each cycle (Total) 521system.cpu.fetch.rateDist::mean 0.868947 # Number of instructions fetched each cycle (Total) 522system.cpu.fetch.rateDist::stdev 2.211995 # Number of instructions fetched each cycle (Total) 523system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 524system.cpu.fetch.rateDist::0 68176645 83.72% 83.72% # Number of instructions fetched each cycle (Total) 525system.cpu.fetch.rateDist::1 854498 1.05% 84.76% # Number of instructions fetched each cycle (Total) 526system.cpu.fetch.rateDist::2 1700203 2.09% 86.85% # Number of instructions fetched each cycle (Total) 527system.cpu.fetch.rateDist::3 823613 1.01% 87.86% # Number of instructions fetched each cycle (Total) 528system.cpu.fetch.rateDist::4 2757448 3.39% 91.25% # Number of instructions fetched each cycle (Total) 529system.cpu.fetch.rateDist::5 566024 0.70% 91.94% # Number of instructions fetched each cycle (Total) 530system.cpu.fetch.rateDist::6 644448 0.79% 92.74% # Number of instructions fetched each cycle (Total) 531system.cpu.fetch.rateDist::7 1011541 1.24% 93.98% # Number of instructions fetched each cycle (Total) 532system.cpu.fetch.rateDist::8 4904071 6.02% 100.00% # Number of instructions fetched each cycle (Total) 533system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 534system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 535system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 536system.cpu.fetch.rateDist::total 81438491 # Number of instructions fetched each cycle (Total) 537system.cpu.fetch.branchRate 0.114778 # Number of branch fetches per cycle 538system.cpu.fetch.rate 0.586177 # Number of inst fetches per cycle 539system.cpu.decode.IdleCycles 29237679 # Number of cycles decode is idle 540system.cpu.decode.BlockedCycles 37865551 # Number of cycles decode is blocked 541system.cpu.decode.RunCycles 12126902 # Number of cycles decode is running 542system.cpu.decode.UnblockCycles 959687 # Number of cycles decode is unblocking 543system.cpu.decode.SquashCycles 1248671 # Number of cycles decode is squashing 544system.cpu.decode.BranchResolved 585551 # Number of times decode resolved a branch 545system.cpu.decode.BranchMispred 42601 # Number of times decode detected a branch misprediction 546system.cpu.decode.DecodedInsts 69445978 # Number of instructions handled by decode 547system.cpu.decode.SquashedInsts 129475 # Number of squashed instructions handled by decode 548system.cpu.rename.SquashCycles 1248671 # Number of cycles rename is squashing 549system.cpu.rename.IdleCycles 30384491 # Number of cycles rename is idle 550system.cpu.rename.BlockCycles 14146796 # Number of cycles rename is blocking 551system.cpu.rename.serializeStallCycles 20012830 # count of cycles rename stalled for serializing inst 552system.cpu.rename.RunCycles 11334710 # Number of cycles rename is running 553system.cpu.rename.UnblockCycles 4310991 # Number of cycles rename is unblocking 554system.cpu.rename.RenamedInsts 65667162 # Number of instructions processed by rename 555system.cpu.rename.ROBFullEvents 7173 # Number of times rename has blocked due to ROB full 556system.cpu.rename.IQFullEvents 505660 # Number of times rename has blocked due to IQ full 557system.cpu.rename.LSQFullEvents 1537414 # Number of times rename has blocked due to LSQ full 558system.cpu.rename.RenamedOperands 43855524 # Number of destination operands rename has renamed 559system.cpu.rename.RenameLookups 79710296 # Number of register rename lookups that rename has made 560system.cpu.rename.int_rename_lookups 79230933 # Number of integer rename lookups 561system.cpu.rename.fp_rename_lookups 479363 # Number of floating rename lookups 562system.cpu.rename.CommittedMaps 38179970 # Number of HB maps that are committed 563system.cpu.rename.UndoneMaps 5675546 # Number of HB maps that are undone due to squashing 564system.cpu.rename.serializingInsts 1682539 # count of serializing insts renamed 565system.cpu.rename.tempSerializingInsts 240064 # count of temporary serializing insts renamed 566system.cpu.rename.skidInsts 12233478 # count of insts added to the skid buffer 567system.cpu.memDep0.insertedLoads 10440283 # Number of loads inserted to the mem dependence unit. 568system.cpu.memDep0.insertedStores 6900737 # Number of stores inserted to the mem dependence unit. 569system.cpu.memDep0.conflictingLoads 1318689 # Number of conflicting loads. 570system.cpu.memDep0.conflictingStores 855517 # Number of conflicting stores. 571system.cpu.iq.iqInstsAdded 58206235 # Number of instructions added to the IQ (excludes non-spec) 572system.cpu.iq.iqNonSpecInstsAdded 2050936 # Number of non-speculative instructions added to the IQ 573system.cpu.iq.iqInstsIssued 56823082 # Number of instructions issued 574system.cpu.iq.iqSquashedInstsIssued 100209 # Number of squashed instructions issued 575system.cpu.iq.iqSquashedInstsExamined 6920159 # Number of squashed instructions iterated over during squash; mainly for profiling 576system.cpu.iq.iqSquashedOperandsExamined 3549975 # Number of squashed operands that are examined and possibly removed from graph 577system.cpu.iq.iqSquashedNonSpecRemoved 1389936 # Number of squashed non-spec instructions that were removed 578system.cpu.iq.issued_per_cycle::samples 81438491 # Number of insts issued each cycle 579system.cpu.iq.issued_per_cycle::mean 0.697742 # Number of insts issued each cycle 580system.cpu.iq.issued_per_cycle::stdev 1.359996 # Number of insts issued each cycle 581system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 582system.cpu.iq.issued_per_cycle::0 56732960 69.66% 69.66% # Number of insts issued each cycle 583system.cpu.iq.issued_per_cycle::1 10881055 13.36% 83.02% # Number of insts issued each cycle 584system.cpu.iq.issued_per_cycle::2 5157432 6.33% 89.36% # Number of insts issued each cycle 585system.cpu.iq.issued_per_cycle::3 3394617 4.17% 93.53% # Number of insts issued each cycle 586system.cpu.iq.issued_per_cycle::4 2629816 3.23% 96.76% # Number of insts issued each cycle 587system.cpu.iq.issued_per_cycle::5 1458992 1.79% 98.55% # Number of insts issued each cycle 588system.cpu.iq.issued_per_cycle::6 753848 0.93% 99.47% # Number of insts issued each cycle 589system.cpu.iq.issued_per_cycle::7 332168 0.41% 99.88% # Number of insts issued each cycle 590system.cpu.iq.issued_per_cycle::8 97603 0.12% 100.00% # Number of insts issued each cycle 591system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 592system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 593system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 594system.cpu.iq.issued_per_cycle::total 81438491 # Number of insts issued each cycle 595system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 596system.cpu.iq.fu_full::IntAlu 91824 11.60% 11.60% # attempts to use FU when none available 597system.cpu.iq.fu_full::IntMult 0 0.00% 11.60% # attempts to use FU when none available 598system.cpu.iq.fu_full::IntDiv 0 0.00% 11.60% # attempts to use FU when none available 599system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.60% # attempts to use FU when none available 600system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.60% # attempts to use FU when none available 601system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.60% # attempts to use FU when none available 602system.cpu.iq.fu_full::FloatMult 0 0.00% 11.60% # attempts to use FU when none available 603system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.60% # attempts to use FU when none available 604system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.60% # attempts to use FU when none available 605system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.60% # attempts to use FU when none available 606system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.60% # attempts to use FU when none available 607system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.60% # attempts to use FU when none available 608system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.60% # attempts to use FU when none available 609system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.60% # attempts to use FU when none available 610system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.60% # attempts to use FU when none available 611system.cpu.iq.fu_full::SimdMult 0 0.00% 11.60% # attempts to use FU when none available 612system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.60% # attempts to use FU when none available 613system.cpu.iq.fu_full::SimdShift 0 0.00% 11.60% # attempts to use FU when none available 614system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.60% # attempts to use FU when none available 615system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.60% # attempts to use FU when none available 616system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.60% # attempts to use FU when none available 617system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.60% # attempts to use FU when none available 618system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.60% # attempts to use FU when none available 619system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.60% # attempts to use FU when none available 620system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.60% # attempts to use FU when none available 621system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.60% # attempts to use FU when none available 622system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.60% # attempts to use FU when none available 623system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.60% # attempts to use FU when none available 624system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.60% # attempts to use FU when none available 625system.cpu.iq.fu_full::MemRead 372747 47.08% 58.68% # attempts to use FU when none available 626system.cpu.iq.fu_full::MemWrite 327090 41.32% 100.00% # attempts to use FU when none available 627system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 628system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 629system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued 630system.cpu.iq.FU_type_0::IntAlu 38740473 68.18% 68.19% # Type of FU issued 631system.cpu.iq.FU_type_0::IntMult 61726 0.11% 68.30% # Type of FU issued 632system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.30% # Type of FU issued 633system.cpu.iq.FU_type_0::FloatAdd 25607 0.05% 68.34% # Type of FU issued 634system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.34% # Type of FU issued 635system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.34% # Type of FU issued 636system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.34% # Type of FU issued 637system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.35% # Type of FU issued 638system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.35% # Type of FU issued 639system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.35% # Type of FU issued 640system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.35% # Type of FU issued 641system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.35% # Type of FU issued 642system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.35% # Type of FU issued 643system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.35% # Type of FU issued 644system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.35% # Type of FU issued 645system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.35% # Type of FU issued 646system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.35% # Type of FU issued 647system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.35% # Type of FU issued 648system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.35% # Type of FU issued 649system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.35% # Type of FU issued 650system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.35% # Type of FU issued 651system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.35% # Type of FU issued 652system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.35% # Type of FU issued 653system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.35% # Type of FU issued 654system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.35% # Type of FU issued 655system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.35% # Type of FU issued 656system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.35% # Type of FU issued 657system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.35% # Type of FU issued 658system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.35% # Type of FU issued 659system.cpu.iq.FU_type_0::MemRead 10354642 18.22% 86.57% # Type of FU issued 660system.cpu.iq.FU_type_0::MemWrite 6680643 11.76% 98.33% # Type of FU issued 661system.cpu.iq.FU_type_0::IprAccess 949069 1.67% 100.00% # Type of FU issued 662system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 663system.cpu.iq.FU_type_0::total 56823082 # Type of FU issued 664system.cpu.iq.rate 0.470686 # Inst issue rate 665system.cpu.iq.fu_busy_cnt 791661 # FU busy when requested 666system.cpu.iq.fu_busy_rate 0.013932 # FU busy rate (busy events/executed inst) 667system.cpu.iq.int_inst_queue_reads 195283781 # Number of integer instruction queue reads 668system.cpu.iq.int_inst_queue_writes 66854445 # Number of integer instruction queue writes 669system.cpu.iq.int_inst_queue_wakeup_accesses 55585028 # Number of integer instruction queue wakeup accesses 670system.cpu.iq.fp_inst_queue_reads 692743 # Number of floating instruction queue reads 671system.cpu.iq.fp_inst_queue_writes 336682 # Number of floating instruction queue writes 672system.cpu.iq.fp_inst_queue_wakeup_accesses 327940 # Number of floating instruction queue wakeup accesses 673system.cpu.iq.int_alu_accesses 57245966 # Number of integer alu accesses 674system.cpu.iq.fp_alu_accesses 361491 # Number of floating point alu accesses 675system.cpu.iew.lsq.thread0.forwLoads 598566 # Number of loads that had data forwarded from stores 676system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 677system.cpu.iew.lsq.thread0.squashedLoads 1347977 # Number of loads squashed 678system.cpu.iew.lsq.thread0.ignoredResponses 3312 # Number of memory responses ignored because the instruction is squashed 679system.cpu.iew.lsq.thread0.memOrderViolation 14180 # Number of memory ordering violations 680system.cpu.iew.lsq.thread0.squashedStores 522824 # Number of stores squashed 681system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 682system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 683system.cpu.iew.lsq.thread0.rescheduledLoads 17906 # Number of loads that were rescheduled 684system.cpu.iew.lsq.thread0.cacheBlocked 181081 # Number of times an access to memory failed due to the cache being blocked 685system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 686system.cpu.iew.iewSquashCycles 1248671 # Number of cycles IEW is squashing 687system.cpu.iew.iewBlockCycles 10233873 # Number of cycles IEW is blocking 688system.cpu.iew.iewUnblockCycles 701956 # Number of cycles IEW is unblocking 689system.cpu.iew.iewDispatchedInsts 63782733 # Number of instructions dispatched to IQ 690system.cpu.iew.iewDispSquashedInsts 684936 # Number of squashed instructions skipped by dispatch 691system.cpu.iew.iewDispLoadInsts 10440283 # Number of dispatched load instructions 692system.cpu.iew.iewDispStoreInsts 6900737 # Number of dispatched store instructions 693system.cpu.iew.iewDispNonSpecInsts 1806230 # Number of dispatched non-speculative instructions 694system.cpu.iew.iewIQFullEvents 512408 # Number of times the IQ has become full, causing a stall 695system.cpu.iew.iewLSQFullEvents 17686 # Number of times the LSQ has become full, causing a stall 696system.cpu.iew.memOrderViolationEvents 14180 # Number of memory order violations 697system.cpu.iew.predictedTakenIncorrect 202063 # Number of branches that were predicted taken incorrectly 698system.cpu.iew.predictedNotTakenIncorrect 410564 # Number of branches that were predicted not taken incorrectly 699system.cpu.iew.branchMispredicts 612627 # Number of branch mispredicts detected at execute 700system.cpu.iew.iewExecutedInsts 56356224 # Number of executed instructions 701system.cpu.iew.iewExecLoadInsts 9992501 # Number of load instructions executed 702system.cpu.iew.iewExecSquashedInsts 466857 # Number of squashed instructions skipped in execute 703system.cpu.iew.exec_swp 0 # number of swp insts executed 704system.cpu.iew.exec_nop 3525562 # number of nop insts executed 705system.cpu.iew.exec_refs 16620030 # number of memory reference insts executed 706system.cpu.iew.exec_branches 8925380 # Number of branches executed 707system.cpu.iew.exec_stores 6627529 # Number of stores executed 708system.cpu.iew.exec_rate 0.466818 # Inst execution rate 709system.cpu.iew.wb_sent 56027730 # cumulative count of insts sent to commit 710system.cpu.iew.wb_count 55912968 # cumulative count of insts written-back 711system.cpu.iew.wb_producers 27713014 # num instructions producing a value 712system.cpu.iew.wb_consumers 37524402 # num instructions consuming a value 713system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 714system.cpu.iew.wb_rate 0.463147 # insts written-back per cycle 715system.cpu.iew.wb_fanout 0.738533 # average fanout of values written-back 716system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 717system.cpu.commit.commitSquashedInsts 7495675 # The number of squashed insts skipped by commit 718system.cpu.commit.commitNonSpecStalls 661000 # The number of times commit has been forced to stall to communicate backwards 719system.cpu.commit.branchMispredicts 567647 # The number of times a branch was mispredicted 720system.cpu.commit.committed_per_cycle::samples 80189820 # Number of insts commited each cycle 721system.cpu.commit.committed_per_cycle::mean 0.700468 # Number of insts commited each cycle 722system.cpu.commit.committed_per_cycle::stdev 1.629642 # Number of insts commited each cycle 723system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 724system.cpu.commit.committed_per_cycle::0 59377156 74.05% 74.05% # Number of insts commited each cycle 725system.cpu.commit.committed_per_cycle::1 8657171 10.80% 84.84% # Number of insts commited each cycle 726system.cpu.commit.committed_per_cycle::2 4615541 5.76% 90.60% # Number of insts commited each cycle 727system.cpu.commit.committed_per_cycle::3 2519398 3.14% 93.74% # Number of insts commited each cycle 728system.cpu.commit.committed_per_cycle::4 1507686 1.88% 95.62% # Number of insts commited each cycle 729system.cpu.commit.committed_per_cycle::5 611065 0.76% 96.38% # Number of insts commited each cycle 730system.cpu.commit.committed_per_cycle::6 523948 0.65% 97.03% # Number of insts commited each cycle 731system.cpu.commit.committed_per_cycle::7 528681 0.66% 97.69% # Number of insts commited each cycle 732system.cpu.commit.committed_per_cycle::8 1849174 2.31% 100.00% # Number of insts commited each cycle 733system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 734system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 735system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 736system.cpu.commit.committed_per_cycle::total 80189820 # Number of insts commited each cycle 737system.cpu.commit.committedInsts 56170363 # Number of instructions committed 738system.cpu.commit.committedOps 56170363 # Number of ops (including micro ops) committed 739system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 740system.cpu.commit.refs 15470219 # Number of memory references committed 741system.cpu.commit.loads 9092306 # Number of loads committed 742system.cpu.commit.membars 226376 # Number of memory barriers committed 743system.cpu.commit.branches 8439998 # Number of branches committed 744system.cpu.commit.fp_insts 324384 # Number of committed floating point instructions. 745system.cpu.commit.int_insts 52019946 # Number of committed integer instructions. 746system.cpu.commit.function_calls 740578 # Number of function calls committed. 747system.cpu.commit.bw_lim_events 1849174 # number cycles where commit BW limit reached 748system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 749system.cpu.rob.rob_reads 141757103 # The number of ROB reads 750system.cpu.rob.rob_writes 128582546 # The number of ROB writes 751system.cpu.timesIdled 1193264 # Number of times that the entire CPU went into an idle state and unscheduled itself 752system.cpu.idleCycles 39285599 # Total number of cycles that the CPU has spent unscheduled due to idling 753system.cpu.quiesceCycles 3599670846 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 754system.cpu.committedInsts 52979577 # Number of Instructions Simulated 755system.cpu.committedOps 52979577 # Number of Ops (including micro ops) Simulated 756system.cpu.committedInsts_total 52979577 # Number of Instructions Simulated 757system.cpu.cpi 2.278691 # CPI: Cycles Per Instruction 758system.cpu.cpi_total 2.278691 # CPI: Total CPI of All Threads 759system.cpu.ipc 0.438848 # IPC: Instructions Per Cycle 760system.cpu.ipc_total 0.438848 # IPC: Total IPC of All Threads 761system.cpu.int_regfile_reads 73899188 # number of integer regfile reads 762system.cpu.int_regfile_writes 40322867 # number of integer regfile writes 763system.cpu.fp_regfile_reads 166085 # number of floating regfile reads 764system.cpu.fp_regfile_writes 167427 # number of floating regfile writes 765system.cpu.misc_regfile_reads 1985758 # number of misc regfile reads 766system.cpu.misc_regfile_writes 938984 # number of misc regfile writes 767system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 768system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 769system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 770system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 771system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 772system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 773system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 774system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 775system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 776system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 777system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 778system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 779system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 780system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 781system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 782system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 783system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 784system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 785system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 786system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 787system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 788system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 789system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 790system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 791system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 792system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 793system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 794system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 795system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 796system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 797system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 798system.iobus.throughput 1454551 # Throughput (bytes/s) 799system.iobus.trans_dist::ReadReq 7103 # Transaction distribution 800system.iobus.trans_dist::ReadResp 7103 # Transaction distribution 801system.iobus.trans_dist::WriteReq 51150 # Transaction distribution 802system.iobus.trans_dist::WriteResp 51150 # Transaction distribution 803system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) 804system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) 805system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 806system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 807system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) 808system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18120 # Packet count per connected master and slave (bytes) 809system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 810system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 811system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 812system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 813system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 814system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 815system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes) 816system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) 817system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) 818system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes) 819system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) 820system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) 821system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 822system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 823system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) 824system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) 825system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 826system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 827system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 828system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 829system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 830system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 831system.iobus.tot_pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes) 832system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) 833system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) 834system.iobus.tot_pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) 835system.iobus.data_through_bus 2705756 # Total data (bytes) 836system.iobus.reqLayer0.occupancy 4663000 # Layer occupancy (ticks) 837system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 838system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) 839system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 840system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) 841system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 842system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) 843system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) 844system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) 845system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) 846system.iobus.reqLayer23.occupancy 13484000 # Layer occupancy (ticks) 847system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 848system.iobus.reqLayer24.occupancy 1887000 # Layer occupancy (ticks) 849system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 850system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) 851system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 852system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) 853system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 854system.iobus.reqLayer27.occupancy 76000 # Layer occupancy (ticks) 855system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 856system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) 857system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 858system.iobus.reqLayer29.occupancy 378268160 # Layer occupancy (ticks) 859system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) 860system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) 861system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) 862system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) 863system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 864system.iobus.respLayer1.occupancy 43098759 # Layer occupancy (ticks) 865system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) 866system.cpu.toL2Bus.throughput 111927083 # Throughput (bytes/s) 867system.cpu.toL2Bus.trans_dist::ReadReq 2117675 # Transaction distribution 868system.cpu.toL2Bus.trans_dist::ReadResp 2117578 # Transaction distribution 869system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution 870system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution 871system.cpu.toL2Bus.trans_dist::Writeback 840831 # Transaction distribution 872system.cpu.toL2Bus.trans_dist::UpgradeReq 64 # Transaction distribution 873system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution 874system.cpu.toL2Bus.trans_dist::UpgradeResp 66 # Transaction distribution 875system.cpu.toL2Bus.trans_dist::ReadExReq 342614 # Transaction distribution 876system.cpu.toL2Bus.trans_dist::ReadExResp 301063 # Transaction distribution 877system.cpu.toL2Bus.trans_dist::BadAddressError 80 # Transaction distribution 878system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2019865 # Packet count per connected master and slave (bytes) 879system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3677460 # Packet count per connected master and slave (bytes) 880system.cpu.toL2Bus.pkt_count::total 5697325 # Packet count per connected master and slave (bytes) 881system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64631872 # Cumulative packet size per connected master and slave (bytes) 882system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143567348 # Cumulative packet size per connected master and slave (bytes) 883system.cpu.toL2Bus.tot_pkt_size::total 208199220 # Cumulative packet size per connected master and slave (bytes) 884system.cpu.toL2Bus.data_through_bus 208189172 # Total data (bytes) 885system.cpu.toL2Bus.snoop_data_through_bus 17664 # Total snoop data (bytes) 886system.cpu.toL2Bus.reqLayer0.occupancy 2480161498 # Layer occupancy (ticks) 887system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 888system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) 889system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 890system.cpu.toL2Bus.respLayer0.occupancy 1518735644 # Layer occupancy (ticks) 891system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 892system.cpu.toL2Bus.respLayer1.occupancy 2194600669 # Layer occupancy (ticks) 893system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) 894system.cpu.icache.tags.replacements 1009263 # number of replacements 895system.cpu.icache.tags.tagsinuse 509.727374 # Cycle average of tags in use 896system.cpu.icache.tags.total_refs 7487430 # Total number of references to valid blocks. 897system.cpu.icache.tags.sampled_refs 1009771 # Sample count of references to valid blocks. 898system.cpu.icache.tags.avg_refs 7.414978 # Average number of references to valid blocks. 899system.cpu.icache.tags.warmup_cycle 25799742250 # Cycle when the warmup percentage was hit. 900system.cpu.icache.tags.occ_blocks::cpu.inst 509.727374 # Average occupied blocks per requestor 901system.cpu.icache.tags.occ_percent::cpu.inst 0.995561 # Average percentage of cache occupancy 902system.cpu.icache.tags.occ_percent::total 0.995561 # Average percentage of cache occupancy 903system.cpu.icache.ReadReq_hits::cpu.inst 7487431 # number of ReadReq hits 904system.cpu.icache.ReadReq_hits::total 7487431 # number of ReadReq hits 905system.cpu.icache.demand_hits::cpu.inst 7487431 # number of demand (read+write) hits 906system.cpu.icache.demand_hits::total 7487431 # number of demand (read+write) hits 907system.cpu.icache.overall_hits::cpu.inst 7487431 # number of overall hits 908system.cpu.icache.overall_hits::total 7487431 # number of overall hits 909system.cpu.icache.ReadReq_misses::cpu.inst 1065872 # number of ReadReq misses 910system.cpu.icache.ReadReq_misses::total 1065872 # number of ReadReq misses 911system.cpu.icache.demand_misses::cpu.inst 1065872 # number of demand (read+write) misses 912system.cpu.icache.demand_misses::total 1065872 # number of demand (read+write) misses 913system.cpu.icache.overall_misses::cpu.inst 1065872 # number of overall misses 914system.cpu.icache.overall_misses::total 1065872 # number of overall misses 915system.cpu.icache.ReadReq_miss_latency::cpu.inst 14976021459 # number of ReadReq miss cycles 916system.cpu.icache.ReadReq_miss_latency::total 14976021459 # number of ReadReq miss cycles 917system.cpu.icache.demand_miss_latency::cpu.inst 14976021459 # number of demand (read+write) miss cycles 918system.cpu.icache.demand_miss_latency::total 14976021459 # number of demand (read+write) miss cycles 919system.cpu.icache.overall_miss_latency::cpu.inst 14976021459 # number of overall miss cycles 920system.cpu.icache.overall_miss_latency::total 14976021459 # number of overall miss cycles 921system.cpu.icache.ReadReq_accesses::cpu.inst 8553303 # number of ReadReq accesses(hits+misses) 922system.cpu.icache.ReadReq_accesses::total 8553303 # number of ReadReq accesses(hits+misses) 923system.cpu.icache.demand_accesses::cpu.inst 8553303 # number of demand (read+write) accesses 924system.cpu.icache.demand_accesses::total 8553303 # number of demand (read+write) accesses 925system.cpu.icache.overall_accesses::cpu.inst 8553303 # number of overall (read+write) accesses 926system.cpu.icache.overall_accesses::total 8553303 # number of overall (read+write) accesses 927system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124615 # miss rate for ReadReq accesses 928system.cpu.icache.ReadReq_miss_rate::total 0.124615 # miss rate for ReadReq accesses 929system.cpu.icache.demand_miss_rate::cpu.inst 0.124615 # miss rate for demand accesses 930system.cpu.icache.demand_miss_rate::total 0.124615 # miss rate for demand accesses 931system.cpu.icache.overall_miss_rate::cpu.inst 0.124615 # miss rate for overall accesses 932system.cpu.icache.overall_miss_rate::total 0.124615 # miss rate for overall accesses 933system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14050.487731 # average ReadReq miss latency 934system.cpu.icache.ReadReq_avg_miss_latency::total 14050.487731 # average ReadReq miss latency 935system.cpu.icache.demand_avg_miss_latency::cpu.inst 14050.487731 # average overall miss latency 936system.cpu.icache.demand_avg_miss_latency::total 14050.487731 # average overall miss latency 937system.cpu.icache.overall_avg_miss_latency::cpu.inst 14050.487731 # average overall miss latency 938system.cpu.icache.overall_avg_miss_latency::total 14050.487731 # average overall miss latency 939system.cpu.icache.blocked_cycles::no_mshrs 8372 # number of cycles access was blocked 940system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 941system.cpu.icache.blocked::no_mshrs 186 # number of cycles access was blocked 942system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 943system.cpu.icache.avg_blocked_cycles::no_mshrs 45.010753 # average number of cycles each access was blocked 944system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 945system.cpu.icache.fast_writes 0 # number of fast writes performed 946system.cpu.icache.cache_copies 0 # number of cache copies performed 947system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55880 # number of ReadReq MSHR hits 948system.cpu.icache.ReadReq_mshr_hits::total 55880 # number of ReadReq MSHR hits 949system.cpu.icache.demand_mshr_hits::cpu.inst 55880 # number of demand (read+write) MSHR hits 950system.cpu.icache.demand_mshr_hits::total 55880 # number of demand (read+write) MSHR hits 951system.cpu.icache.overall_mshr_hits::cpu.inst 55880 # number of overall MSHR hits 952system.cpu.icache.overall_mshr_hits::total 55880 # number of overall MSHR hits 953system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1009992 # number of ReadReq MSHR misses 954system.cpu.icache.ReadReq_mshr_misses::total 1009992 # number of ReadReq MSHR misses 955system.cpu.icache.demand_mshr_misses::cpu.inst 1009992 # number of demand (read+write) MSHR misses 956system.cpu.icache.demand_mshr_misses::total 1009992 # number of demand (read+write) MSHR misses 957system.cpu.icache.overall_mshr_misses::cpu.inst 1009992 # number of overall MSHR misses 958system.cpu.icache.overall_mshr_misses::total 1009992 # number of overall MSHR misses 959system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12273344851 # number of ReadReq MSHR miss cycles 960system.cpu.icache.ReadReq_mshr_miss_latency::total 12273344851 # number of ReadReq MSHR miss cycles 961system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12273344851 # number of demand (read+write) MSHR miss cycles 962system.cpu.icache.demand_mshr_miss_latency::total 12273344851 # number of demand (read+write) MSHR miss cycles 963system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12273344851 # number of overall MSHR miss cycles 964system.cpu.icache.overall_mshr_miss_latency::total 12273344851 # number of overall MSHR miss cycles 965system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.118082 # mshr miss rate for ReadReq accesses 966system.cpu.icache.ReadReq_mshr_miss_rate::total 0.118082 # mshr miss rate for ReadReq accesses 967system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.118082 # mshr miss rate for demand accesses 968system.cpu.icache.demand_mshr_miss_rate::total 0.118082 # mshr miss rate for demand accesses 969system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.118082 # mshr miss rate for overall accesses 970system.cpu.icache.overall_mshr_miss_rate::total 0.118082 # mshr miss rate for overall accesses 971system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12151.922838 # average ReadReq mshr miss latency 972system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12151.922838 # average ReadReq mshr miss latency 973system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12151.922838 # average overall mshr miss latency 974system.cpu.icache.demand_avg_mshr_miss_latency::total 12151.922838 # average overall mshr miss latency 975system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12151.922838 # average overall mshr miss latency 976system.cpu.icache.overall_avg_mshr_miss_latency::total 12151.922838 # average overall mshr miss latency 977system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 978system.cpu.l2cache.tags.replacements 338298 # number of replacements 979system.cpu.l2cache.tags.tagsinuse 65343.107599 # Cycle average of tags in use 980system.cpu.l2cache.tags.total_refs 2545731 # Total number of references to valid blocks. 981system.cpu.l2cache.tags.sampled_refs 403463 # Sample count of references to valid blocks. 982system.cpu.l2cache.tags.avg_refs 6.309701 # Average number of references to valid blocks. 983system.cpu.l2cache.tags.warmup_cycle 5353022750 # Cycle when the warmup percentage was hit. 984system.cpu.l2cache.tags.occ_blocks::writebacks 53859.326644 # Average occupied blocks per requestor 985system.cpu.l2cache.tags.occ_blocks::cpu.inst 5308.706799 # Average occupied blocks per requestor 986system.cpu.l2cache.tags.occ_blocks::cpu.data 6175.074156 # Average occupied blocks per requestor 987system.cpu.l2cache.tags.occ_percent::writebacks 0.821828 # Average percentage of cache occupancy 988system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081004 # Average percentage of cache occupancy 989system.cpu.l2cache.tags.occ_percent::cpu.data 0.094224 # Average percentage of cache occupancy 990system.cpu.l2cache.tags.occ_percent::total 0.997057 # Average percentage of cache occupancy 991system.cpu.l2cache.ReadReq_hits::cpu.inst 994809 # number of ReadReq hits 992system.cpu.l2cache.ReadReq_hits::cpu.data 826788 # number of ReadReq hits 993system.cpu.l2cache.ReadReq_hits::total 1821597 # number of ReadReq hits 994system.cpu.l2cache.Writeback_hits::writebacks 840831 # number of Writeback hits 995system.cpu.l2cache.Writeback_hits::total 840831 # number of Writeback hits 996system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits 997system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits 998system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits 999system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits 1000system.cpu.l2cache.ReadExReq_hits::cpu.data 185623 # number of ReadExReq hits 1001system.cpu.l2cache.ReadExReq_hits::total 185623 # number of ReadExReq hits 1002system.cpu.l2cache.demand_hits::cpu.inst 994809 # number of demand (read+write) hits 1003system.cpu.l2cache.demand_hits::cpu.data 1012411 # number of demand (read+write) hits 1004system.cpu.l2cache.demand_hits::total 2007220 # number of demand (read+write) hits 1005system.cpu.l2cache.overall_hits::cpu.inst 994809 # number of overall hits 1006system.cpu.l2cache.overall_hits::cpu.data 1012411 # number of overall hits 1007system.cpu.l2cache.overall_hits::total 2007220 # number of overall hits 1008system.cpu.l2cache.ReadReq_misses::cpu.inst 15064 # number of ReadReq misses 1009system.cpu.l2cache.ReadReq_misses::cpu.data 273792 # number of ReadReq misses 1010system.cpu.l2cache.ReadReq_misses::total 288856 # number of ReadReq misses 1011system.cpu.l2cache.UpgradeReq_misses::cpu.data 38 # number of UpgradeReq misses 1012system.cpu.l2cache.UpgradeReq_misses::total 38 # number of UpgradeReq misses 1013system.cpu.l2cache.ReadExReq_misses::cpu.data 115439 # number of ReadExReq misses 1014system.cpu.l2cache.ReadExReq_misses::total 115439 # number of ReadExReq misses 1015system.cpu.l2cache.demand_misses::cpu.inst 15064 # number of demand (read+write) misses 1016system.cpu.l2cache.demand_misses::cpu.data 389231 # number of demand (read+write) misses 1017system.cpu.l2cache.demand_misses::total 404295 # number of demand (read+write) misses 1018system.cpu.l2cache.overall_misses::cpu.inst 15064 # number of overall misses 1019system.cpu.l2cache.overall_misses::cpu.data 389231 # number of overall misses 1020system.cpu.l2cache.overall_misses::total 404295 # number of overall misses 1021system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1289741743 # number of ReadReq miss cycles 1022system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17221594730 # number of ReadReq miss cycles 1023system.cpu.l2cache.ReadReq_miss_latency::total 18511336473 # number of ReadReq miss cycles 1024system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 285497 # number of UpgradeReq miss cycles 1025system.cpu.l2cache.UpgradeReq_miss_latency::total 285497 # number of UpgradeReq miss cycles 1026system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9397410357 # number of ReadExReq miss cycles 1027system.cpu.l2cache.ReadExReq_miss_latency::total 9397410357 # number of ReadExReq miss cycles 1028system.cpu.l2cache.demand_miss_latency::cpu.inst 1289741743 # number of demand (read+write) miss cycles 1029system.cpu.l2cache.demand_miss_latency::cpu.data 26619005087 # number of demand (read+write) miss cycles 1030system.cpu.l2cache.demand_miss_latency::total 27908746830 # number of demand (read+write) miss cycles 1031system.cpu.l2cache.overall_miss_latency::cpu.inst 1289741743 # number of overall miss cycles 1032system.cpu.l2cache.overall_miss_latency::cpu.data 26619005087 # number of overall miss cycles 1033system.cpu.l2cache.overall_miss_latency::total 27908746830 # number of overall miss cycles 1034system.cpu.l2cache.ReadReq_accesses::cpu.inst 1009873 # number of ReadReq accesses(hits+misses) 1035system.cpu.l2cache.ReadReq_accesses::cpu.data 1100580 # number of ReadReq accesses(hits+misses) 1036system.cpu.l2cache.ReadReq_accesses::total 2110453 # number of ReadReq accesses(hits+misses) 1037system.cpu.l2cache.Writeback_accesses::writebacks 840831 # number of Writeback accesses(hits+misses) 1038system.cpu.l2cache.Writeback_accesses::total 840831 # number of Writeback accesses(hits+misses) 1039system.cpu.l2cache.UpgradeReq_accesses::cpu.data 64 # number of UpgradeReq accesses(hits+misses) 1040system.cpu.l2cache.UpgradeReq_accesses::total 64 # number of UpgradeReq accesses(hits+misses) 1041system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) 1042system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) 1043system.cpu.l2cache.ReadExReq_accesses::cpu.data 301062 # number of ReadExReq accesses(hits+misses) 1044system.cpu.l2cache.ReadExReq_accesses::total 301062 # number of ReadExReq accesses(hits+misses) 1045system.cpu.l2cache.demand_accesses::cpu.inst 1009873 # number of demand (read+write) accesses 1046system.cpu.l2cache.demand_accesses::cpu.data 1401642 # number of demand (read+write) accesses 1047system.cpu.l2cache.demand_accesses::total 2411515 # number of demand (read+write) accesses 1048system.cpu.l2cache.overall_accesses::cpu.inst 1009873 # number of overall (read+write) accesses 1049system.cpu.l2cache.overall_accesses::cpu.data 1401642 # number of overall (read+write) accesses 1050system.cpu.l2cache.overall_accesses::total 2411515 # number of overall (read+write) accesses 1051system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014917 # miss rate for ReadReq accesses 1052system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248771 # miss rate for ReadReq accesses 1053system.cpu.l2cache.ReadReq_miss_rate::total 0.136869 # miss rate for ReadReq accesses 1054system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.593750 # miss rate for UpgradeReq accesses 1055system.cpu.l2cache.UpgradeReq_miss_rate::total 0.593750 # miss rate for UpgradeReq accesses 1056system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383439 # miss rate for ReadExReq accesses 1057system.cpu.l2cache.ReadExReq_miss_rate::total 0.383439 # miss rate for ReadExReq accesses 1058system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014917 # miss rate for demand accesses 1059system.cpu.l2cache.demand_miss_rate::cpu.data 0.277696 # miss rate for demand accesses 1060system.cpu.l2cache.demand_miss_rate::total 0.167652 # miss rate for demand accesses 1061system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014917 # miss rate for overall accesses 1062system.cpu.l2cache.overall_miss_rate::cpu.data 0.277696 # miss rate for overall accesses 1063system.cpu.l2cache.overall_miss_rate::total 0.167652 # miss rate for overall accesses 1064system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 85617.481612 # average ReadReq miss latency 1065system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62900.284632 # average ReadReq miss latency 1066system.cpu.l2cache.ReadReq_avg_miss_latency::total 64084.999006 # average ReadReq miss latency 1067system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 7513.078947 # average UpgradeReq miss latency 1068system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 7513.078947 # average UpgradeReq miss latency 1069system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81405.853802 # average ReadExReq miss latency 1070system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81405.853802 # average ReadExReq miss latency 1071system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85617.481612 # average overall miss latency 1072system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68388.707701 # average overall miss latency 1073system.cpu.l2cache.demand_avg_miss_latency::total 69030.650466 # average overall miss latency 1074system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85617.481612 # average overall miss latency 1075system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68388.707701 # average overall miss latency 1076system.cpu.l2cache.overall_avg_miss_latency::total 69030.650466 # average overall miss latency 1077system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1078system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1079system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1080system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1081system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1082system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1083system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1084system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1085system.cpu.l2cache.writebacks::writebacks 75925 # number of writebacks 1086system.cpu.l2cache.writebacks::total 75925 # number of writebacks 1087system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 1088system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits 1089system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1090system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits 1091system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1092system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits 1093system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15063 # number of ReadReq MSHR misses 1094system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273792 # number of ReadReq MSHR misses 1095system.cpu.l2cache.ReadReq_mshr_misses::total 288855 # number of ReadReq MSHR misses 1096system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 38 # number of UpgradeReq MSHR misses 1097system.cpu.l2cache.UpgradeReq_mshr_misses::total 38 # number of UpgradeReq MSHR misses 1098system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115439 # number of ReadExReq MSHR misses 1099system.cpu.l2cache.ReadExReq_mshr_misses::total 115439 # number of ReadExReq MSHR misses 1100system.cpu.l2cache.demand_mshr_misses::cpu.inst 15063 # number of demand (read+write) MSHR misses 1101system.cpu.l2cache.demand_mshr_misses::cpu.data 389231 # number of demand (read+write) MSHR misses 1102system.cpu.l2cache.demand_mshr_misses::total 404294 # number of demand (read+write) MSHR misses 1103system.cpu.l2cache.overall_mshr_misses::cpu.inst 15063 # number of overall MSHR misses 1104system.cpu.l2cache.overall_mshr_misses::cpu.data 389231 # number of overall MSHR misses 1105system.cpu.l2cache.overall_mshr_misses::total 404294 # number of overall MSHR misses 1106system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1098682007 # number of ReadReq MSHR miss cycles 1107system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13807789270 # number of ReadReq MSHR miss cycles 1108system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14906471277 # number of ReadReq MSHR miss cycles 1109system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 531034 # number of UpgradeReq MSHR miss cycles 1110system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 531034 # number of UpgradeReq MSHR miss cycles 1111system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7972002643 # number of ReadExReq MSHR miss cycles 1112system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7972002643 # number of ReadExReq MSHR miss cycles 1113system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1098682007 # number of demand (read+write) MSHR miss cycles 1114system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 21779791913 # number of demand (read+write) MSHR miss cycles 1115system.cpu.l2cache.demand_mshr_miss_latency::total 22878473920 # number of demand (read+write) MSHR miss cycles 1116system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1098682007 # number of overall MSHR miss cycles 1117system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 21779791913 # number of overall MSHR miss cycles 1118system.cpu.l2cache.overall_mshr_miss_latency::total 22878473920 # number of overall MSHR miss cycles 1119system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333925000 # number of ReadReq MSHR uncacheable cycles 1120system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333925000 # number of ReadReq MSHR uncacheable cycles 1121system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1882616000 # number of WriteReq MSHR uncacheable cycles 1122system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1882616000 # number of WriteReq MSHR uncacheable cycles 1123system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3216541000 # number of overall MSHR uncacheable cycles 1124system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3216541000 # number of overall MSHR uncacheable cycles 1125system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014916 # mshr miss rate for ReadReq accesses 1126system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248771 # mshr miss rate for ReadReq accesses 1127system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.136869 # mshr miss rate for ReadReq accesses 1128system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.593750 # mshr miss rate for UpgradeReq accesses 1129system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.593750 # mshr miss rate for UpgradeReq accesses 1130system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383439 # mshr miss rate for ReadExReq accesses 1131system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383439 # mshr miss rate for ReadExReq accesses 1132system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014916 # mshr miss rate for demand accesses 1133system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277696 # mshr miss rate for demand accesses 1134system.cpu.l2cache.demand_mshr_miss_rate::total 0.167651 # mshr miss rate for demand accesses 1135system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014916 # mshr miss rate for overall accesses 1136system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277696 # mshr miss rate for overall accesses 1137system.cpu.l2cache.overall_mshr_miss_rate::total 0.167651 # mshr miss rate for overall accesses 1138system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 72939.122817 # average ReadReq mshr miss latency 1139system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50431.675396 # average ReadReq mshr miss latency 1140system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51605.377359 # average ReadReq mshr miss latency 1141system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13974.578947 # average UpgradeReq mshr miss latency 1142system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13974.578947 # average UpgradeReq mshr miss latency 1143system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69058.140169 # average ReadExReq mshr miss latency 1144system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69058.140169 # average ReadExReq mshr miss latency 1145system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72939.122817 # average overall mshr miss latency 1146system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55955.953953 # average overall mshr miss latency 1147system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56588.705051 # average overall mshr miss latency 1148system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72939.122817 # average overall mshr miss latency 1149system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55955.953953 # average overall mshr miss latency 1150system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56588.705051 # average overall mshr miss latency 1151system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1152system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1153system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1154system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1155system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1156system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1157system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1158system.cpu.dcache.tags.replacements 1401048 # number of replacements 1159system.cpu.dcache.tags.tagsinuse 511.994535 # Cycle average of tags in use 1160system.cpu.dcache.tags.total_refs 11808107 # Total number of references to valid blocks. 1161system.cpu.dcache.tags.sampled_refs 1401560 # Sample count of references to valid blocks. 1162system.cpu.dcache.tags.avg_refs 8.424974 # Average number of references to valid blocks. 1163system.cpu.dcache.tags.warmup_cycle 25348250 # Cycle when the warmup percentage was hit. 1164system.cpu.dcache.tags.occ_blocks::cpu.data 511.994535 # Average occupied blocks per requestor 1165system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy 1166system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy 1167system.cpu.dcache.ReadReq_hits::cpu.data 7202464 # number of ReadReq hits 1168system.cpu.dcache.ReadReq_hits::total 7202464 # number of ReadReq hits 1169system.cpu.dcache.WriteReq_hits::cpu.data 4203713 # number of WriteReq hits 1170system.cpu.dcache.WriteReq_hits::total 4203713 # number of WriteReq hits 1171system.cpu.dcache.LoadLockedReq_hits::cpu.data 186169 # number of LoadLockedReq hits 1172system.cpu.dcache.LoadLockedReq_hits::total 186169 # number of LoadLockedReq hits 1173system.cpu.dcache.StoreCondReq_hits::cpu.data 215520 # number of StoreCondReq hits 1174system.cpu.dcache.StoreCondReq_hits::total 215520 # number of StoreCondReq hits 1175system.cpu.dcache.demand_hits::cpu.data 11406177 # number of demand (read+write) hits 1176system.cpu.dcache.demand_hits::total 11406177 # number of demand (read+write) hits 1177system.cpu.dcache.overall_hits::cpu.data 11406177 # number of overall hits 1178system.cpu.dcache.overall_hits::total 11406177 # number of overall hits 1179system.cpu.dcache.ReadReq_misses::cpu.data 1806828 # number of ReadReq misses 1180system.cpu.dcache.ReadReq_misses::total 1806828 # number of ReadReq misses 1181system.cpu.dcache.WriteReq_misses::cpu.data 1943975 # number of WriteReq misses 1182system.cpu.dcache.WriteReq_misses::total 1943975 # number of WriteReq misses 1183system.cpu.dcache.LoadLockedReq_misses::cpu.data 22707 # number of LoadLockedReq misses 1184system.cpu.dcache.LoadLockedReq_misses::total 22707 # number of LoadLockedReq misses 1185system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses 1186system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses 1187system.cpu.dcache.demand_misses::cpu.data 3750803 # number of demand (read+write) misses 1188system.cpu.dcache.demand_misses::total 3750803 # number of demand (read+write) misses 1189system.cpu.dcache.overall_misses::cpu.data 3750803 # number of overall misses 1190system.cpu.dcache.overall_misses::total 3750803 # number of overall misses 1191system.cpu.dcache.ReadReq_miss_latency::cpu.data 39803546178 # number of ReadReq miss cycles 1192system.cpu.dcache.ReadReq_miss_latency::total 39803546178 # number of ReadReq miss cycles 1193system.cpu.dcache.WriteReq_miss_latency::cpu.data 76325479834 # number of WriteReq miss cycles 1194system.cpu.dcache.WriteReq_miss_latency::total 76325479834 # number of WriteReq miss cycles 1195system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 321955499 # number of LoadLockedReq miss cycles 1196system.cpu.dcache.LoadLockedReq_miss_latency::total 321955499 # number of LoadLockedReq miss cycles 1197system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles 1198system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles 1199system.cpu.dcache.demand_miss_latency::cpu.data 116129026012 # number of demand (read+write) miss cycles 1200system.cpu.dcache.demand_miss_latency::total 116129026012 # number of demand (read+write) miss cycles 1201system.cpu.dcache.overall_miss_latency::cpu.data 116129026012 # number of overall miss cycles 1202system.cpu.dcache.overall_miss_latency::total 116129026012 # number of overall miss cycles 1203system.cpu.dcache.ReadReq_accesses::cpu.data 9009292 # number of ReadReq accesses(hits+misses) 1204system.cpu.dcache.ReadReq_accesses::total 9009292 # number of ReadReq accesses(hits+misses) 1205system.cpu.dcache.WriteReq_accesses::cpu.data 6147688 # number of WriteReq accesses(hits+misses) 1206system.cpu.dcache.WriteReq_accesses::total 6147688 # number of WriteReq accesses(hits+misses) 1207system.cpu.dcache.LoadLockedReq_accesses::cpu.data 208876 # number of LoadLockedReq accesses(hits+misses) 1208system.cpu.dcache.LoadLockedReq_accesses::total 208876 # number of LoadLockedReq accesses(hits+misses) 1209system.cpu.dcache.StoreCondReq_accesses::cpu.data 215522 # number of StoreCondReq accesses(hits+misses) 1210system.cpu.dcache.StoreCondReq_accesses::total 215522 # number of StoreCondReq accesses(hits+misses) 1211system.cpu.dcache.demand_accesses::cpu.data 15156980 # number of demand (read+write) accesses 1212system.cpu.dcache.demand_accesses::total 15156980 # number of demand (read+write) accesses 1213system.cpu.dcache.overall_accesses::cpu.data 15156980 # number of overall (read+write) accesses 1214system.cpu.dcache.overall_accesses::total 15156980 # number of overall (read+write) accesses 1215system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.200552 # miss rate for ReadReq accesses 1216system.cpu.dcache.ReadReq_miss_rate::total 0.200552 # miss rate for ReadReq accesses 1217system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.316212 # miss rate for WriteReq accesses 1218system.cpu.dcache.WriteReq_miss_rate::total 0.316212 # miss rate for WriteReq accesses 1219system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.108710 # miss rate for LoadLockedReq accesses 1220system.cpu.dcache.LoadLockedReq_miss_rate::total 0.108710 # miss rate for LoadLockedReq accesses 1221system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses 1222system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses 1223system.cpu.dcache.demand_miss_rate::cpu.data 0.247464 # miss rate for demand accesses 1224system.cpu.dcache.demand_miss_rate::total 0.247464 # miss rate for demand accesses 1225system.cpu.dcache.overall_miss_rate::cpu.data 0.247464 # miss rate for overall accesses 1226system.cpu.dcache.overall_miss_rate::total 0.247464 # miss rate for overall accesses 1227system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22029.515913 # average ReadReq miss latency 1228system.cpu.dcache.ReadReq_avg_miss_latency::total 22029.515913 # average ReadReq miss latency 1229system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39262.583024 # average WriteReq miss latency 1230system.cpu.dcache.WriteReq_avg_miss_latency::total 39262.583024 # average WriteReq miss latency 1231system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14178.689347 # average LoadLockedReq miss latency 1232system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14178.689347 # average LoadLockedReq miss latency 1233system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency 1234system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency 1235system.cpu.dcache.demand_avg_miss_latency::cpu.data 30961.110464 # average overall miss latency 1236system.cpu.dcache.demand_avg_miss_latency::total 30961.110464 # average overall miss latency 1237system.cpu.dcache.overall_avg_miss_latency::cpu.data 30961.110464 # average overall miss latency 1238system.cpu.dcache.overall_avg_miss_latency::total 30961.110464 # average overall miss latency 1239system.cpu.dcache.blocked_cycles::no_mshrs 2958985 # number of cycles access was blocked 1240system.cpu.dcache.blocked_cycles::no_targets 733 # number of cycles access was blocked 1241system.cpu.dcache.blocked::no_mshrs 97398 # number of cycles access was blocked 1242system.cpu.dcache.blocked::no_targets 7 # number of cycles access was blocked 1243system.cpu.dcache.avg_blocked_cycles::no_mshrs 30.380347 # average number of cycles each access was blocked 1244system.cpu.dcache.avg_blocked_cycles::no_targets 104.714286 # average number of cycles each access was blocked 1245system.cpu.dcache.fast_writes 0 # number of fast writes performed 1246system.cpu.dcache.cache_copies 0 # number of cache copies performed 1247system.cpu.dcache.writebacks::writebacks 840831 # number of writebacks 1248system.cpu.dcache.writebacks::total 840831 # number of writebacks 1249system.cpu.dcache.ReadReq_mshr_hits::cpu.data 723109 # number of ReadReq MSHR hits 1250system.cpu.dcache.ReadReq_mshr_hits::total 723109 # number of ReadReq MSHR hits 1251system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1643505 # number of WriteReq MSHR hits 1252system.cpu.dcache.WriteReq_mshr_hits::total 1643505 # number of WriteReq MSHR hits 1253system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5191 # number of LoadLockedReq MSHR hits 1254system.cpu.dcache.LoadLockedReq_mshr_hits::total 5191 # number of LoadLockedReq MSHR hits 1255system.cpu.dcache.demand_mshr_hits::cpu.data 2366614 # number of demand (read+write) MSHR hits 1256system.cpu.dcache.demand_mshr_hits::total 2366614 # number of demand (read+write) MSHR hits 1257system.cpu.dcache.overall_mshr_hits::cpu.data 2366614 # number of overall MSHR hits 1258system.cpu.dcache.overall_mshr_hits::total 2366614 # number of overall MSHR hits 1259system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1083719 # number of ReadReq MSHR misses 1260system.cpu.dcache.ReadReq_mshr_misses::total 1083719 # number of ReadReq MSHR misses 1261system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300470 # number of WriteReq MSHR misses 1262system.cpu.dcache.WriteReq_mshr_misses::total 300470 # number of WriteReq MSHR misses 1263system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17516 # number of LoadLockedReq MSHR misses 1264system.cpu.dcache.LoadLockedReq_mshr_misses::total 17516 # number of LoadLockedReq MSHR misses 1265system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses 1266system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses 1267system.cpu.dcache.demand_mshr_misses::cpu.data 1384189 # number of demand (read+write) MSHR misses 1268system.cpu.dcache.demand_mshr_misses::total 1384189 # number of demand (read+write) MSHR misses 1269system.cpu.dcache.overall_mshr_misses::cpu.data 1384189 # number of overall MSHR misses 1270system.cpu.dcache.overall_mshr_misses::total 1384189 # number of overall MSHR misses 1271system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26582228002 # number of ReadReq MSHR miss cycles 1272system.cpu.dcache.ReadReq_mshr_miss_latency::total 26582228002 # number of ReadReq MSHR miss cycles 1273system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11613303338 # number of WriteReq MSHR miss cycles 1274system.cpu.dcache.WriteReq_mshr_miss_latency::total 11613303338 # number of WriteReq MSHR miss cycles 1275system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 201814751 # number of LoadLockedReq MSHR miss cycles 1276system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 201814751 # number of LoadLockedReq MSHR miss cycles 1277system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles 1278system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles 1279system.cpu.dcache.demand_mshr_miss_latency::cpu.data 38195531340 # number of demand (read+write) MSHR miss cycles 1280system.cpu.dcache.demand_mshr_miss_latency::total 38195531340 # number of demand (read+write) MSHR miss cycles 1281system.cpu.dcache.overall_mshr_miss_latency::cpu.data 38195531340 # number of overall MSHR miss cycles 1282system.cpu.dcache.overall_mshr_miss_latency::total 38195531340 # number of overall MSHR miss cycles 1283system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424015000 # number of ReadReq MSHR uncacheable cycles 1284system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424015000 # number of ReadReq MSHR uncacheable cycles 1285system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997805998 # number of WriteReq MSHR uncacheable cycles 1286system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997805998 # number of WriteReq MSHR uncacheable cycles 1287system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421820998 # number of overall MSHR uncacheable cycles 1288system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421820998 # number of overall MSHR uncacheable cycles 1289system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120289 # mshr miss rate for ReadReq accesses 1290system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120289 # mshr miss rate for ReadReq accesses 1291system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048875 # mshr miss rate for WriteReq accesses 1292system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.048875 # mshr miss rate for WriteReq accesses 1293system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.083858 # mshr miss rate for LoadLockedReq accesses 1294system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.083858 # mshr miss rate for LoadLockedReq accesses 1295system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses 1296system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses 1297system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091324 # mshr miss rate for demand accesses 1298system.cpu.dcache.demand_mshr_miss_rate::total 0.091324 # mshr miss rate for demand accesses 1299system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091324 # mshr miss rate for overall accesses 1300system.cpu.dcache.overall_mshr_miss_rate::total 0.091324 # mshr miss rate for overall accesses 1301system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24528.709012 # average ReadReq mshr miss latency 1302system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24528.709012 # average ReadReq mshr miss latency 1303system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38650.458741 # average WriteReq mshr miss latency 1304system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38650.458741 # average WriteReq mshr miss latency 1305system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11521.737326 # average LoadLockedReq mshr miss latency 1306system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11521.737326 # average LoadLockedReq mshr miss latency 1307system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency 1308system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency 1309system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27594.158991 # average overall mshr miss latency 1310system.cpu.dcache.demand_avg_mshr_miss_latency::total 27594.158991 # average overall mshr miss latency 1311system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27594.158991 # average overall mshr miss latency 1312system.cpu.dcache.overall_avg_mshr_miss_latency::total 27594.158991 # average overall mshr miss latency 1313system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency 1314system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency 1315system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency 1316system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency 1317system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency 1318system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 1319system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1320system.cpu.kern.inst.arm 0 # number of arm instructions executed 1321system.cpu.kern.inst.quiesce 6440 # number of quiesce instructions executed 1322system.cpu.kern.inst.hwrei 211017 # number of hwrei instructions executed 1323system.cpu.kern.ipl_count::0 74663 40.97% 40.97% # number of times we switched to this ipl 1324system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl 1325system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl 1326system.cpu.kern.ipl_count::31 105573 57.93% 100.00% # number of times we switched to this ipl 1327system.cpu.kern.ipl_count::total 182247 # number of times we switched to this ipl 1328system.cpu.kern.ipl_good::0 73296 49.32% 49.32% # number of times we switched to this ipl from a different ipl 1329system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl 1330system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl 1331system.cpu.kern.ipl_good::31 73296 49.32% 100.00% # number of times we switched to this ipl from a different ipl 1332system.cpu.kern.ipl_good::total 148603 # number of times we switched to this ipl from a different ipl 1333system.cpu.kern.ipl_ticks::0 1818706968000 97.77% 97.77% # number of cycles we spent at this ipl 1334system.cpu.kern.ipl_ticks::21 64176500 0.00% 97.77% # number of cycles we spent at this ipl 1335system.cpu.kern.ipl_ticks::22 554827000 0.03% 97.80% # number of cycles we spent at this ipl 1336system.cpu.kern.ipl_ticks::31 40873882000 2.20% 100.00% # number of cycles we spent at this ipl 1337system.cpu.kern.ipl_ticks::total 1860199853500 # number of cycles we spent at this ipl 1338system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl 1339system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 1340system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 1341system.cpu.kern.ipl_used::31 0.694268 # fraction of swpipl calls that actually changed the ipl 1342system.cpu.kern.ipl_used::total 0.815393 # fraction of swpipl calls that actually changed the ipl 1343system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 1344system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 1345system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 1346system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 1347system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 1348system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 1349system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 1350system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed 1351system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed 1352system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed 1353system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed 1354system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed 1355system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed 1356system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed 1357system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed 1358system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed 1359system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed 1360system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed 1361system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed 1362system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed 1363system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed 1364system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed 1365system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed 1366system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed 1367system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed 1368system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed 1369system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed 1370system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed 1371system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed 1372system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed 1373system.cpu.kern.syscall::total 326 # number of syscalls executed 1374system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 1375system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 1376system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 1377system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 1378system.cpu.kern.callpal::swpctx 4176 2.18% 2.18% # number of callpals executed 1379system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed 1380system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed 1381system.cpu.kern.callpal::swpipl 175130 91.22% 93.43% # number of callpals executed 1382system.cpu.kern.callpal::rdps 6785 3.53% 96.97% # number of callpals executed 1383system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed 1384system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed 1385system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed 1386system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed 1387system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed 1388system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 1389system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed 1390system.cpu.kern.callpal::total 191976 # number of callpals executed 1391system.cpu.kern.mode_switch::kernel 5853 # number of protection mode switches 1392system.cpu.kern.mode_switch::user 1739 # number of protection mode switches 1393system.cpu.kern.mode_switch::idle 2094 # number of protection mode switches 1394system.cpu.kern.mode_good::kernel 1909 1395system.cpu.kern.mode_good::user 1739 1396system.cpu.kern.mode_good::idle 170 1397system.cpu.kern.mode_switch_good::kernel 0.326158 # fraction of useful protection mode switches 1398system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 1399system.cpu.kern.mode_switch_good::idle 0.081184 # fraction of useful protection mode switches 1400system.cpu.kern.mode_switch_good::total 0.394177 # fraction of useful protection mode switches 1401system.cpu.kern.mode_ticks::kernel 29671097000 1.60% 1.60% # number of ticks spent at the given mode 1402system.cpu.kern.mode_ticks::user 2774842500 0.15% 1.74% # number of ticks spent at the given mode 1403system.cpu.kern.mode_ticks::idle 1827753906000 98.26% 100.00% # number of ticks spent at the given mode 1404system.cpu.kern.swap_context 4177 # number of times the context was actually changed 1405 1406---------- End Simulation Statistics ---------- 1407