simple-run.py revision 13676:831fc4270d4c 
1# Copyright (c) 2012 ARM Limited
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35#
36# Authors: Andreas Hansson
37
38import m5
39from m5.objects import *
40
41import argparse
42
43parser = argparse.ArgumentParser(description='Simple memory tester')
44parser.add_argument('--bandwidth', default=None)
45parser.add_argument('--latency', default=None)
46parser.add_argument('--latency_var', default=None)
47
48args = parser.parse_args()
49
50# both traffic generator and communication monitor are only available
51# if we have protobuf support, so potentially skip this test
52# require_sim_object("TrafficGen")
53# require_sim_object("CommMonitor")
54# This needs to be fixed in the new infrastructure
55
56# even if this is only a traffic generator, call it cpu to make sure
57# the scripts are happy
58cpu = TrafficGen(
59    config_file=os.path.join(os.path.dirname(os.path.abspath(__file__)),
60                             "tgen-simple-mem.cfg"))
61
62class MyMem(SimpleMemory):
63    if args.bandwidth:
64        bandwidth = args.bandwidth
65    if args.latency:
66        latency = args.latency
67    if args.latency_var:
68        latency_var = args.latency_var
69
70# system simulated
71system = System(cpu = cpu, physmem = MyMem(),
72                membus = IOXBar(width = 16),
73                clk_domain = SrcClockDomain(clock = '1GHz',
74                                            voltage_domain =
75                                            VoltageDomain()))
76
77# add a communication monitor, and also trace all the packets and
78# calculate and verify stack distance
79system.monitor = CommMonitor()
80system.monitor.trace = MemTraceProbe(trace_file = "monitor.ptrc.gz")
81system.monitor.stackdist = StackDistProbe(verify = True)
82
83# connect the traffic generator to the bus via a communication monitor
84system.cpu.port = system.monitor.slave
85system.monitor.master = system.membus.slave
86
87# connect the system port even if it is not used in this example
88system.system_port = system.membus.slave
89
90# connect memory to the membus
91system.physmem.port = system.membus.master
92
93# -----------------------
94# run simulation
95# -----------------------
96
97root = Root(full_system = False, system = system)
98root.system.mem_mode = 'timing'
99
100m5.instantiate()
101exit_event = m5.simulate(100000000000)
102
103print(exit_event.getCause())
104