memtest-run.py revision 13677
16657Snate@binkert.org# Copyright (c) 2006-2007 The Regents of The University of Michigan 26657Snate@binkert.org# All rights reserved. 36657Snate@binkert.org# 46657Snate@binkert.org# Redistribution and use in source and binary forms, with or without 56657Snate@binkert.org# modification, are permitted provided that the following conditions are 66657Snate@binkert.org# met: redistributions of source code must retain the above copyright 76657Snate@binkert.org# notice, this list of conditions and the following disclaimer; 86657Snate@binkert.org# redistributions in binary form must reproduce the above copyright 96657Snate@binkert.org# notice, this list of conditions and the following disclaimer in the 106657Snate@binkert.org# documentation and/or other materials provided with the distribution; 116657Snate@binkert.org# neither the name of the copyright holders nor the names of its 126657Snate@binkert.org# contributors may be used to endorse or promote products derived from 136657Snate@binkert.org# this software without specific prior written permission. 146657Snate@binkert.org# 156657Snate@binkert.org# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 166657Snate@binkert.org# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 176657Snate@binkert.org# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 186657Snate@binkert.org# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 196657Snate@binkert.org# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 206657Snate@binkert.org# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 216657Snate@binkert.org# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 226657Snate@binkert.org# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 236657Snate@binkert.org# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 246657Snate@binkert.org# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 256657Snate@binkert.org# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 266657Snate@binkert.org# 276657Snate@binkert.org# Authors: Ron Dreslinski 286657Snate@binkert.org 296657Snate@binkert.orgimport m5 306657Snate@binkert.orgfrom m5.objects import * 316657Snate@binkert.orgm5.util.addToPath('../../../configs/') 326657Snate@binkert.orgfrom common.Caches import * 336999Snate@binkert.org 348452Snate@binkert.org#MAX CORES IS 8 with the fals sharing method 356657Snate@binkert.orgnb_cores = 8 366657Snate@binkert.orgcpus = [MemTest(max_loads = 1e5, progress_interval = 1e4) 376657Snate@binkert.org for i in xrange(nb_cores) ] 386657Snate@binkert.org 396657Snate@binkert.org# system simulated 406657Snate@binkert.orgsystem = System(cpu = cpus, 419219Spower.jg@gmail.com physmem = SimpleMemory(), 428454Snate@binkert.org membus = SystemXBar()) 438454Snate@binkert.org# Dummy voltage domain for all our clock domains 448453Snate@binkert.orgsystem.voltage_domain = VoltageDomain() 456999Snate@binkert.orgsystem.clk_domain = SrcClockDomain(clock = '1GHz', 469219Spower.jg@gmail.com voltage_domain = system.voltage_domain) 476999Snate@binkert.org 488454Snate@binkert.org# Create a seperate clock domain for components that should run at 498454Snate@binkert.org# CPUs frequency 508454Snate@binkert.orgsystem.cpu_clk_domain = SrcClockDomain(clock = '2GHz', 518454Snate@binkert.org voltage_domain = system.voltage_domain) 528454Snate@binkert.org 538454Snate@binkert.orgsystem.toL2Bus = L2XBar(clk_domain = system.cpu_clk_domain) 548454Snate@binkert.orgsystem.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8) 558453Snate@binkert.orgsystem.l2c.cpu_side = system.toL2Bus.master 568453Snate@binkert.org 578453Snate@binkert.org# connect l2c to membus 588453Snate@binkert.orgsystem.l2c.mem_side = system.membus.slave 596999Snate@binkert.org 606999Snate@binkert.org# add L1 caches 616999Snate@binkert.orgfor cpu in cpus: 626999Snate@binkert.org # All cpus are associated with cpu_clk_domain 636657Snate@binkert.org cpu.clk_domain = system.cpu_clk_domain 648453Snate@binkert.org cpu.l1c = L1Cache(size = '32kB', assoc = 4) 658454Snate@binkert.org cpu.l1c.cpu_side = cpu.port 668454Snate@binkert.org cpu.l1c.mem_side = system.toL2Bus.slave 676657Snate@binkert.org 689219Spower.jg@gmail.comsystem.system_port = system.membus.slave 699219Spower.jg@gmail.com 706657Snate@binkert.org# connect memory to membus 718453Snate@binkert.orgsystem.physmem.port = system.membus.master 728453Snate@binkert.org 736657Snate@binkert.org 746657Snate@binkert.org# ----------------------- 756714Ssteve.reinhardt@amd.com# run simulation 766714Ssteve.reinhardt@amd.com# ----------------------- 776657Snate@binkert.org 786657Snate@binkert.orgroot = Root( full_system = False, system = system ) 796657Snate@binkert.orgroot.system.mem_mode = 'timing' 808454Snate@binkert.org 816657Snate@binkert.orgm5.instantiate() 826714Ssteve.reinhardt@amd.comexit_event = m5.simulate() 836657Snate@binkert.orgif exit_event.getCause() != "maximum number of loads reached": 846657Snate@binkert.org exit(1) 856657Snate@binkert.org 866657Snate@binkert.org