tsunami-o3.py revision 5703
15703Ssaidi@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 25703Ssaidi@eecs.umich.edu# All rights reserved. 35703Ssaidi@eecs.umich.edu# 45703Ssaidi@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 55703Ssaidi@eecs.umich.edu# modification, are permitted provided that the following conditions are 65703Ssaidi@eecs.umich.edu# met: redistributions of source code must retain the above copyright 75703Ssaidi@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 85703Ssaidi@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 95703Ssaidi@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 105703Ssaidi@eecs.umich.edu# documentation and/or other materials provided with the distribution; 115703Ssaidi@eecs.umich.edu# neither the name of the copyright holders nor the names of its 125703Ssaidi@eecs.umich.edu# contributors may be used to endorse or promote products derived from 135703Ssaidi@eecs.umich.edu# this software without specific prior written permission. 145703Ssaidi@eecs.umich.edu# 155703Ssaidi@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 165703Ssaidi@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 175703Ssaidi@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 185703Ssaidi@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 195703Ssaidi@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 205703Ssaidi@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 215703Ssaidi@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 225703Ssaidi@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 235703Ssaidi@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 245703Ssaidi@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 255703Ssaidi@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 265703Ssaidi@eecs.umich.edu# 275703Ssaidi@eecs.umich.edu# Authors: Steve Reinhardt 285703Ssaidi@eecs.umich.edu 295703Ssaidi@eecs.umich.eduimport m5 305703Ssaidi@eecs.umich.edufrom m5.objects import * 315703Ssaidi@eecs.umich.edum5.AddToPath('../configs/common') 325703Ssaidi@eecs.umich.eduimport FSConfig 335703Ssaidi@eecs.umich.edu 345703Ssaidi@eecs.umich.edu 355703Ssaidi@eecs.umich.edu# -------------------- 365703Ssaidi@eecs.umich.edu# Base L1 Cache 375703Ssaidi@eecs.umich.edu# ==================== 385703Ssaidi@eecs.umich.edu 395703Ssaidi@eecs.umich.educlass L1(BaseCache): 405703Ssaidi@eecs.umich.edu latency = '1ns' 415703Ssaidi@eecs.umich.edu block_size = 64 425703Ssaidi@eecs.umich.edu mshrs = 4 435703Ssaidi@eecs.umich.edu tgts_per_mshr = 8 445703Ssaidi@eecs.umich.edu 455703Ssaidi@eecs.umich.edu# ---------------------- 465703Ssaidi@eecs.umich.edu# Base L2 Cache 475703Ssaidi@eecs.umich.edu# ---------------------- 485703Ssaidi@eecs.umich.edu 495703Ssaidi@eecs.umich.educlass L2(BaseCache): 505703Ssaidi@eecs.umich.edu block_size = 64 515703Ssaidi@eecs.umich.edu latency = '10ns' 525703Ssaidi@eecs.umich.edu mshrs = 92 535703Ssaidi@eecs.umich.edu tgts_per_mshr = 16 545703Ssaidi@eecs.umich.edu write_buffers = 8 555703Ssaidi@eecs.umich.edu 565703Ssaidi@eecs.umich.edu# --------------------- 575703Ssaidi@eecs.umich.edu# I/O Cache 585703Ssaidi@eecs.umich.edu# --------------------- 595703Ssaidi@eecs.umich.educlass IOCache(BaseCache): 605703Ssaidi@eecs.umich.edu assoc = 8 615703Ssaidi@eecs.umich.edu block_size = 64 625703Ssaidi@eecs.umich.edu latency = '50ns' 635703Ssaidi@eecs.umich.edu mshrs = 20 645703Ssaidi@eecs.umich.edu size = '1kB' 655703Ssaidi@eecs.umich.edu tgts_per_mshr = 12 665703Ssaidi@eecs.umich.edu mem_side_filter_ranges=[AddrRange(0, Addr.max)] 675703Ssaidi@eecs.umich.edu cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)] 685703Ssaidi@eecs.umich.edu 695703Ssaidi@eecs.umich.edu#cpu 705703Ssaidi@eecs.umich.educpu = DerivO3CPU(cpu_id=0) 715703Ssaidi@eecs.umich.edu#the system 725703Ssaidi@eecs.umich.edusystem = FSConfig.makeLinuxAlphaSystem('timing') 735703Ssaidi@eecs.umich.edu 745703Ssaidi@eecs.umich.edusystem.cpu = cpu 755703Ssaidi@eecs.umich.edu#create the l1/l2 bus 765703Ssaidi@eecs.umich.edusystem.toL2Bus = Bus() 775703Ssaidi@eecs.umich.edusystem.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] 785703Ssaidi@eecs.umich.edusystem.bridge.filter_ranges_b=[AddrRange(0, size='8GB')] 795703Ssaidi@eecs.umich.edusystem.iocache = IOCache() 805703Ssaidi@eecs.umich.edusystem.iocache.cpu_side = system.iobus.port 815703Ssaidi@eecs.umich.edusystem.iocache.mem_side = system.membus.port 825703Ssaidi@eecs.umich.edu 835703Ssaidi@eecs.umich.edu 845703Ssaidi@eecs.umich.edu#connect up the l2 cache 855703Ssaidi@eecs.umich.edusystem.l2c = L2(size='4MB', assoc=8) 865703Ssaidi@eecs.umich.edusystem.l2c.cpu_side = system.toL2Bus.port 875703Ssaidi@eecs.umich.edusystem.l2c.mem_side = system.membus.port 885703Ssaidi@eecs.umich.edu 895703Ssaidi@eecs.umich.edu#connect up the cpu and l1s 905703Ssaidi@eecs.umich.educpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 915703Ssaidi@eecs.umich.edu L1(size = '32kB', assoc = 4)) 925703Ssaidi@eecs.umich.edu# connect cpu level-1 caches to shared level-2 cache 935703Ssaidi@eecs.umich.educpu.connectMemPorts(system.toL2Bus) 945703Ssaidi@eecs.umich.educpu.clock = '2GHz' 955703Ssaidi@eecs.umich.edu 965703Ssaidi@eecs.umich.eduroot = Root(system=system) 975703Ssaidi@eecs.umich.edum5.ticks.setGlobalFrequency('1THz') 985703Ssaidi@eecs.umich.edu 99