tsunami-o3.py revision 5703 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.AddToPath('../configs/common')
32import FSConfig
33
34
35# --------------------
36# Base L1 Cache
37# ====================
38
39class L1(BaseCache):
40    latency = '1ns'
41    block_size = 64
42    mshrs = 4
43    tgts_per_mshr = 8
44
45# ----------------------
46# Base L2 Cache
47# ----------------------
48
49class L2(BaseCache):
50    block_size = 64
51    latency = '10ns'
52    mshrs = 92
53    tgts_per_mshr = 16
54    write_buffers = 8
55
56# ---------------------
57# I/O Cache
58# ---------------------
59class IOCache(BaseCache):
60    assoc = 8
61    block_size = 64
62    latency = '50ns'
63    mshrs = 20
64    size = '1kB'
65    tgts_per_mshr = 12
66    mem_side_filter_ranges=[AddrRange(0, Addr.max)]
67    cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
68
69#cpu
70cpu = DerivO3CPU(cpu_id=0)
71#the system
72system = FSConfig.makeLinuxAlphaSystem('timing')
73
74system.cpu = cpu
75#create the l1/l2 bus
76system.toL2Bus = Bus()
77system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
78system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
79system.iocache = IOCache()
80system.iocache.cpu_side = system.iobus.port
81system.iocache.mem_side = system.membus.port
82
83
84#connect up the l2 cache
85system.l2c = L2(size='4MB', assoc=8)
86system.l2c.cpu_side = system.toL2Bus.port
87system.l2c.mem_side = system.membus.port
88
89#connect up the cpu and l1s
90cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
91                            L1(size = '32kB', assoc = 4))
92# connect cpu level-1 caches to shared level-2 cache
93cpu.connectMemPorts(system.toL2Bus)
94cpu.clock = '2GHz'
95
96root = Root(system=system)
97m5.ticks.setGlobalFrequency('1THz')
98
99