t1000-simple-atomic.py revision 9826
14130Ssaidi@eecs.umich.edu# Copyright (c) 2007 The Regents of The University of Michigan 24130Ssaidi@eecs.umich.edu# All rights reserved. 34130Ssaidi@eecs.umich.edu# 44130Ssaidi@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 54130Ssaidi@eecs.umich.edu# modification, are permitted provided that the following conditions are 64130Ssaidi@eecs.umich.edu# met: redistributions of source code must retain the above copyright 74130Ssaidi@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 84130Ssaidi@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 94130Ssaidi@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 104130Ssaidi@eecs.umich.edu# documentation and/or other materials provided with the distribution; 114130Ssaidi@eecs.umich.edu# neither the name of the copyright holders nor the names of its 124130Ssaidi@eecs.umich.edu# contributors may be used to endorse or promote products derived from 134130Ssaidi@eecs.umich.edu# this software without specific prior written permission. 144130Ssaidi@eecs.umich.edu# 154130Ssaidi@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 164130Ssaidi@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 174130Ssaidi@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 184130Ssaidi@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 194130Ssaidi@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 204130Ssaidi@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 214130Ssaidi@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 224130Ssaidi@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 234130Ssaidi@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 244130Ssaidi@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 254130Ssaidi@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 264130Ssaidi@eecs.umich.edu# 274130Ssaidi@eecs.umich.edu# Authors: Ali Saidi 284130Ssaidi@eecs.umich.edu 294130Ssaidi@eecs.umich.eduimport m5 304130Ssaidi@eecs.umich.edufrom m5.objects import * 316654Snate@binkert.orgm5.util.addToPath('../configs/common') 324130Ssaidi@eecs.umich.eduimport FSConfig 334130Ssaidi@eecs.umich.edu 349826Sandreas.hansson@arm.comsystem = FSConfig.makeSparcSystem('atomic') 359802Snilay@cs.wisc.edusystem.clk_domain = SrcClockDomain(clock = '1GHz') 369802Snilay@cs.wisc.edusystem.cpu_clk_domain = SrcClockDomain(clock = '1GHz') 379802Snilay@cs.wisc.educpu = AtomicSimpleCPU(cpu_id=0, clk_domain = system.cpu_clk_domain) 384130Ssaidi@eecs.umich.edusystem.cpu = cpu 398882Sgblack@eecs.umich.edu# create the interrupt controller 408882Sgblack@eecs.umich.educpu.createInterruptController() 417876Sgblack@eecs.umich.educpu.connectAllPorts(system.membus) 424130Ssaidi@eecs.umich.edu 439826Sandreas.hansson@arm.com# create the memory controllers and connect them, stick with 449826Sandreas.hansson@arm.com# the physmem name to avoid bumping all the reference stats 459826Sandreas.hansson@arm.comsystem.physmem = [SimpleMemory(range = r, 469826Sandreas.hansson@arm.com conf_table_reported = True) 479826Sandreas.hansson@arm.com for r in system.mem_ranges] 489826Sandreas.hansson@arm.comfor i in xrange(len(system.physmem)): 499826Sandreas.hansson@arm.com system.physmem[i].port = system.membus.master 509826Sandreas.hansson@arm.com 518801Sgblack@eecs.umich.eduroot = Root(full_system=True, system=system) 524167Sbinkertn@umich.edu 534167Sbinkertn@umich.edum5.ticks.setGlobalFrequency('2GHz') 54