simple-timing.py revision 2997 
1import m5
2from m5.objects import *
3m5.AddToPath('../configs/common')
4from SEConfig import *
5
6class MyCache(BaseCache):
7    assoc = 2
8    block_size = 64
9    latency = 1
10    mshrs = 10
11    tgts_per_mshr = 5
12
13cpu = TimingSimpleCPU()
14cpu.icache = MyCache(size = '128kB')
15cpu.dcache = MyCache(size = '256kB')
16cpu.l2cache = MyCache(size = '2MB')
17
18cpu.icache_port = cpu.icache.cpu_side
19cpu.dcache_port = cpu.dcache.cpu_side
20
21root = makeSESystem(cpu)
22