simple-timing-mp-ruby.py revision 9790:ccc428657233 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
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8# redistributions in binary form must reproduce the above copyright
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13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31from m5.defines import buildEnv
32from m5.util import addToPath
33import os, optparse, sys
34
35# Get paths we might need
36config_path = os.path.dirname(os.path.abspath(__file__))
37config_root = os.path.dirname(config_path)
38m5_root = os.path.dirname(config_root)
39addToPath(config_root+'/configs/common')
40addToPath(config_root+'/configs/ruby')
41addToPath(config_root+'/configs/topologies')
42
43import Options
44import Ruby
45
46parser = optparse.OptionParser()
47Options.addCommonOptions(parser)
48
49# Add the ruby specific and protocol specific options
50Ruby.define_options(parser)
51
52(options, args) = parser.parse_args()
53
54#
55# Set the default cache size and associativity to be very small to encourage
56# races between requests and writebacks.
57#
58options.l1d_size="256B"
59options.l1i_size="256B"
60options.l2_size="512B"
61options.l3_size="1kB"
62options.l1d_assoc=2
63options.l1i_assoc=2
64options.l2_assoc=2
65options.l3_assoc=2
66
67nb_cores = 4
68cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
69
70# overwrite the num_cpus to equal nb_cores
71options.num_cpus = nb_cores
72
73# system simulated
74system = System(cpu = cpus, physmem = SimpleMemory())
75system.clock = options.sys_clock
76
77Ruby.create_system(options, system)
78
79assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
80
81for (i, cpu) in enumerate(system.cpu):
82    # create the interrupt controller
83    cpu.createInterruptController()
84
85    #
86    # Tie the cpu ports to the ruby cpu ports
87    #
88    cpu.connectAllPorts(system.ruby._cpu_ruby_ports[i])
89
90# -----------------------
91# run simulation
92# -----------------------
93
94root = Root( full_system=False, system = system )
95root.system.mem_mode = 'timing'
96
97# Not much point in this being higher than the L1 latency
98m5.ticks.setGlobalFrequency('1ns')
99