simple-timing-mp-ruby.py revision 9113:9a72589ce4fd
12391SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 28931Sandreas.hansson@arm.com# All rights reserved. 37733SN/A# 47733SN/A# Redistribution and use in source and binary forms, with or without 57733SN/A# modification, are permitted provided that the following conditions are 67733SN/A# met: redistributions of source code must retain the above copyright 77733SN/A# notice, this list of conditions and the following disclaimer; 87733SN/A# redistributions in binary form must reproduce the above copyright 97733SN/A# notice, this list of conditions and the following disclaimer in the 107733SN/A# documentation and/or other materials provided with the distribution; 117733SN/A# neither the name of the copyright holders nor the names of its 127733SN/A# contributors may be used to endorse or promote products derived from 137733SN/A# this software without specific prior written permission. 142391SN/A# 152391SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162391SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172391SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182391SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192391SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202391SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212391SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222391SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232391SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242391SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252391SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262391SN/A# 272391SN/A# Authors: Ron Dreslinski 282391SN/A 292391SN/Aimport m5 302391SN/Afrom m5.objects import * 312391SN/Afrom m5.defines import buildEnv 322391SN/Afrom m5.util import addToPath 332391SN/Aimport os, optparse, sys 342391SN/A 352391SN/A# Get paths we might need 362391SN/Aconfig_path = os.path.dirname(os.path.abspath(__file__)) 372391SN/Aconfig_root = os.path.dirname(config_path) 382391SN/Am5_root = os.path.dirname(config_root) 392665SN/AaddToPath(config_root+'/configs/common') 402665SN/AaddToPath(config_root+'/configs/ruby') 412914SN/AaddToPath(config_root+'/configs/topologies') 428931Sandreas.hansson@arm.com 432391SN/Aimport Options 442391SN/Aimport Ruby 458229SN/A 462391SN/Aparser = optparse.OptionParser() 477730SN/AOptions.addCommonOptions(parser) 482391SN/A 492391SN/A# Add the ruby specific and protocol specific options 502391SN/ARuby.define_options(parser) 512391SN/A 528229SN/A(options, args) = parser.parse_args() 536712SN/A 542391SN/A# 552391SN/A# Set the default cache size and associativity to be very small to encourage 562391SN/A# races between requests and writebacks. 576329SN/A# 586658SN/Aoptions.l1d_size="256B" 598232SN/Aoptions.l1i_size="256B" 608232SN/Aoptions.l2_size="512B" 618931Sandreas.hansson@arm.comoptions.l3_size="1kB" 623879SN/Aoptions.l1d_assoc=2 639053Sdam.sunwoo@arm.comoptions.l1i_assoc=2 642394SN/Aoptions.l2_assoc=2 652391SN/Aoptions.l3_assoc=2 662391SN/A 678931Sandreas.hansson@arm.comnb_cores = 4 688931Sandreas.hansson@arm.comcpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 699053Sdam.sunwoo@arm.com 709053Sdam.sunwoo@arm.com# overwrite the num_cpus to equal nb_cores 712391SN/Aoptions.num_cpus = nb_cores 727730SN/A 732391SN/A# system simulated 742391SN/Asystem = System(cpu = cpus, physmem = SimpleMemory()) 755477SN/A 765477SN/ARuby.create_system(options, system) 775477SN/A 787730SN/Aassert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 797730SN/A 807730SN/Afor (i, cpu) in enumerate(system.cpu): 817730SN/A # create the interrupt controller 827730SN/A cpu.createInterruptController() 837730SN/A 847730SN/A # 858931Sandreas.hansson@arm.com # Tie the cpu ports to the ruby cpu ports 868931Sandreas.hansson@arm.com # 878931Sandreas.hansson@arm.com cpu.connectAllPorts(system.ruby._cpu_ruby_ports[i]) 888931Sandreas.hansson@arm.com 898931Sandreas.hansson@arm.com# ----------------------- 908931Sandreas.hansson@arm.com# run simulation 917730SN/A# ----------------------- 928931Sandreas.hansson@arm.com 937730SN/Aroot = Root( full_system=False, system = system ) 947730SN/Aroot.system.mem_mode = 'timing' 952391SN/A 963012SN/A# Not much point in this being higher than the L1 latency 972391SN/Am5.ticks.setGlobalFrequency('1ns') 987730SN/A