simple-timing-mp-ruby.py revision 9113:9a72589ce4fd
110259SAndrew.Bardsley@arm.com# Copyright (c) 2006-2007 The Regents of The University of Michigan 210259SAndrew.Bardsley@arm.com# All rights reserved. 310259SAndrew.Bardsley@arm.com# 410259SAndrew.Bardsley@arm.com# Redistribution and use in source and binary forms, with or without 510259SAndrew.Bardsley@arm.com# modification, are permitted provided that the following conditions are 610259SAndrew.Bardsley@arm.com# met: redistributions of source code must retain the above copyright 710259SAndrew.Bardsley@arm.com# notice, this list of conditions and the following disclaimer; 810259SAndrew.Bardsley@arm.com# redistributions in binary form must reproduce the above copyright 910259SAndrew.Bardsley@arm.com# notice, this list of conditions and the following disclaimer in the 1010259SAndrew.Bardsley@arm.com# documentation and/or other materials provided with the distribution; 1110259SAndrew.Bardsley@arm.com# neither the name of the copyright holders nor the names of its 1210259SAndrew.Bardsley@arm.com# contributors may be used to endorse or promote products derived from 1310259SAndrew.Bardsley@arm.com# this software without specific prior written permission. 1410259SAndrew.Bardsley@arm.com# 1510259SAndrew.Bardsley@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1610259SAndrew.Bardsley@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1710259SAndrew.Bardsley@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1810259SAndrew.Bardsley@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 1910259SAndrew.Bardsley@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2010259SAndrew.Bardsley@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2110259SAndrew.Bardsley@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2210259SAndrew.Bardsley@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2310259SAndrew.Bardsley@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2410259SAndrew.Bardsley@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2510259SAndrew.Bardsley@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2610259SAndrew.Bardsley@arm.com# 2710259SAndrew.Bardsley@arm.com# Authors: Ron Dreslinski 2810259SAndrew.Bardsley@arm.com 2910259SAndrew.Bardsley@arm.comimport m5 3010259SAndrew.Bardsley@arm.comfrom m5.objects import * 3110259SAndrew.Bardsley@arm.comfrom m5.defines import buildEnv 3210259SAndrew.Bardsley@arm.comfrom m5.util import addToPath 3310259SAndrew.Bardsley@arm.comimport os, optparse, sys 3410259SAndrew.Bardsley@arm.com 3510259SAndrew.Bardsley@arm.com# Get paths we might need 3610259SAndrew.Bardsley@arm.comconfig_path = os.path.dirname(os.path.abspath(__file__)) 3710259SAndrew.Bardsley@arm.comconfig_root = os.path.dirname(config_path) 3810259SAndrew.Bardsley@arm.comm5_root = os.path.dirname(config_root) 3910259SAndrew.Bardsley@arm.comaddToPath(config_root+'/configs/common') 4010259SAndrew.Bardsley@arm.comaddToPath(config_root+'/configs/ruby') 4110259SAndrew.Bardsley@arm.comaddToPath(config_root+'/configs/topologies') 4210259SAndrew.Bardsley@arm.com 4310259SAndrew.Bardsley@arm.comimport Options 4410259SAndrew.Bardsley@arm.comimport Ruby 4510259SAndrew.Bardsley@arm.com 4610259SAndrew.Bardsley@arm.comparser = optparse.OptionParser() 4710259SAndrew.Bardsley@arm.comOptions.addCommonOptions(parser) 4810259SAndrew.Bardsley@arm.com 4910259SAndrew.Bardsley@arm.com# Add the ruby specific and protocol specific options 5010913Sandreas.sandberg@arm.comRuby.define_options(parser) 5110259SAndrew.Bardsley@arm.com 5210259SAndrew.Bardsley@arm.com(options, args) = parser.parse_args() 5310259SAndrew.Bardsley@arm.com 5410259SAndrew.Bardsley@arm.com# 5510259SAndrew.Bardsley@arm.com# Set the default cache size and associativity to be very small to encourage 5610259SAndrew.Bardsley@arm.com# races between requests and writebacks. 5710259SAndrew.Bardsley@arm.com# 5810259SAndrew.Bardsley@arm.comoptions.l1d_size="256B" 5910259SAndrew.Bardsley@arm.comoptions.l1i_size="256B" 6010259SAndrew.Bardsley@arm.comoptions.l2_size="512B" 6110259SAndrew.Bardsley@arm.comoptions.l3_size="1kB" 6210259SAndrew.Bardsley@arm.comoptions.l1d_assoc=2 6310259SAndrew.Bardsley@arm.comoptions.l1i_assoc=2 6410259SAndrew.Bardsley@arm.comoptions.l2_assoc=2 6510259SAndrew.Bardsley@arm.comoptions.l3_assoc=2 6610259SAndrew.Bardsley@arm.com 6710259SAndrew.Bardsley@arm.comnb_cores = 4 6810259SAndrew.Bardsley@arm.comcpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 6910259SAndrew.Bardsley@arm.com 7010259SAndrew.Bardsley@arm.com# overwrite the num_cpus to equal nb_cores 7110259SAndrew.Bardsley@arm.comoptions.num_cpus = nb_cores 7210259SAndrew.Bardsley@arm.com 7310259SAndrew.Bardsley@arm.com# system simulated 7410259SAndrew.Bardsley@arm.comsystem = System(cpu = cpus, physmem = SimpleMemory()) 7510259SAndrew.Bardsley@arm.com 7610259SAndrew.Bardsley@arm.comRuby.create_system(options, system) 7710259SAndrew.Bardsley@arm.com 7810259SAndrew.Bardsley@arm.comassert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 7910259SAndrew.Bardsley@arm.com 8010259SAndrew.Bardsley@arm.comfor (i, cpu) in enumerate(system.cpu): 8110259SAndrew.Bardsley@arm.com # create the interrupt controller 8210259SAndrew.Bardsley@arm.com cpu.createInterruptController() 8310259SAndrew.Bardsley@arm.com 8410259SAndrew.Bardsley@arm.com # 8510259SAndrew.Bardsley@arm.com # Tie the cpu ports to the ruby cpu ports 8610259SAndrew.Bardsley@arm.com # 8710259SAndrew.Bardsley@arm.com cpu.connectAllPorts(system.ruby._cpu_ruby_ports[i]) 8810259SAndrew.Bardsley@arm.com 8910259SAndrew.Bardsley@arm.com# ----------------------- 9010259SAndrew.Bardsley@arm.com# run simulation 9110259SAndrew.Bardsley@arm.com# ----------------------- 9210259SAndrew.Bardsley@arm.com 9310259SAndrew.Bardsley@arm.comroot = Root( full_system=False, system = system ) 9410259SAndrew.Bardsley@arm.comroot.system.mem_mode = 'timing' 9510259SAndrew.Bardsley@arm.com 9610259SAndrew.Bardsley@arm.com# Not much point in this being higher than the L1 latency 9710259SAndrew.Bardsley@arm.comm5.ticks.setGlobalFrequency('1ns') 9810259SAndrew.Bardsley@arm.com