simple-timing-mp-ruby.py revision 8920:99083b5b7ed4 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
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15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31from m5.defines import buildEnv
32from m5.util import addToPath
33import os, optparse, sys
34
35# Get paths we might need
36config_path = os.path.dirname(os.path.abspath(__file__))
37config_root = os.path.dirname(config_path)
38m5_root = os.path.dirname(config_root)
39addToPath(config_root+'/configs/common')
40addToPath(config_root+'/configs/ruby')
41
42import Options
43import Ruby
44
45parser = optparse.OptionParser()
46Options.addCommonOptions(parser)
47
48# Add the ruby specific and protocol specific options
49Ruby.define_options(parser)
50
51(options, args) = parser.parse_args()
52
53#
54# Set the default cache size and associativity to be very small to encourage
55# races between requests and writebacks.
56#
57options.l1d_size="256B"
58options.l1i_size="256B"
59options.l2_size="512B"
60options.l3_size="1kB"
61options.l1d_assoc=2
62options.l1i_assoc=2
63options.l2_assoc=2
64options.l3_assoc=2
65
66nb_cores = 4
67cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
68
69# overwrite the num_cpus to equal nb_cores
70options.num_cpus = nb_cores
71
72# system simulated
73system = System(cpu = cpus, physmem = PhysicalMemory())
74
75Ruby.create_system(options, system)
76
77assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
78
79for (i, cpu) in enumerate(system.cpu):
80    #
81    # Tie the cpu ports to the ruby cpu ports
82    #
83    cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
84    cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
85
86# -----------------------
87# run simulation
88# -----------------------
89
90root = Root( full_system=False, system = system )
91root.system.mem_mode = 'timing'
92
93# Not much point in this being higher than the L1 latency
94m5.ticks.setGlobalFrequency('1ns')
95