simple-timing-mp-ruby.py revision 8802:ef66a9083bc4 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
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14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31from m5.defines import buildEnv
32from m5.util import addToPath
33import os, optparse, sys
34
35# Get paths we might need
36config_path = os.path.dirname(os.path.abspath(__file__))
37config_root = os.path.dirname(config_path)
38m5_root = os.path.dirname(config_root)
39addToPath(config_root+'/configs/common')
40addToPath(config_root+'/configs/ruby')
41
42import Ruby
43
44parser = optparse.OptionParser()
45
46#
47# Add the ruby specific and protocol specific options
48#
49Ruby.define_options(parser)
50
51execfile(os.path.join(config_root, "configs/common", "Options.py"))
52
53(options, args) = parser.parse_args()
54
55#
56# Set the default cache size and associativity to be very small to encourage
57# races between requests and writebacks.
58#
59options.l1d_size="256B"
60options.l1i_size="256B"
61options.l2_size="512B"
62options.l3_size="1kB"
63options.l1d_assoc=2
64options.l1i_assoc=2
65options.l2_assoc=2
66options.l3_assoc=2
67
68nb_cores = 4
69cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
70
71# overwrite the num_cpus to equal nb_cores
72options.num_cpus = nb_cores
73
74# system simulated
75system = System(cpu = cpus, physmem = PhysicalMemory())
76
77Ruby.create_system(options, system)
78
79assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
80
81for (i, cpu) in enumerate(system.cpu):
82    #
83    # Tie the cpu ports to the ruby cpu ports
84    #
85    cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
86    cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
87
88# Connect the system port for loading of binaries etc
89system.system_port = system.ruby._sys_port_proxy.port
90
91# -----------------------
92# run simulation
93# -----------------------
94
95root = Root( full_system=False, system = system )
96root.system.mem_mode = 'timing'
97
98# Not much point in this being higher than the L1 latency
99m5.ticks.setGlobalFrequency('1ns')
100