simple-timing-mp-ruby.py revision 10524:fff17530cef6
111986Sandreas.sandberg@arm.com# Copyright (c) 2006-2007 The Regents of The University of Michigan
211986Sandreas.sandberg@arm.com# All rights reserved.
311986Sandreas.sandberg@arm.com#
411986Sandreas.sandberg@arm.com# Redistribution and use in source and binary forms, with or without
511986Sandreas.sandberg@arm.com# modification, are permitted provided that the following conditions are
611986Sandreas.sandberg@arm.com# met: redistributions of source code must retain the above copyright
714299Sbbruce@ucdavis.edu# notice, this list of conditions and the following disclaimer;
814299Sbbruce@ucdavis.edu# redistributions in binary form must reproduce the above copyright
914299Sbbruce@ucdavis.edu# notice, this list of conditions and the following disclaimer in the
1014299Sbbruce@ucdavis.edu# documentation and/or other materials provided with the distribution;
1114299Sbbruce@ucdavis.edu# neither the name of the copyright holders nor the names of its
1214299Sbbruce@ucdavis.edu# contributors may be used to endorse or promote products derived from
1314299Sbbruce@ucdavis.edu# this software without specific prior written permission.
1411986Sandreas.sandberg@arm.com#
1511986Sandreas.sandberg@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
1611986Sandreas.sandberg@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
1711986Sandreas.sandberg@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
1812391Sjason@lowepower.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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2411986Sandreas.sandberg@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
2511986Sandreas.sandberg@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2611986Sandreas.sandberg@arm.com#
2711986Sandreas.sandberg@arm.com# Authors: Ron Dreslinski
2812391Sjason@lowepower.com
2911986Sandreas.sandberg@arm.comimport m5
3011986Sandreas.sandberg@arm.comfrom m5.objects import *
3111986Sandreas.sandberg@arm.comfrom m5.defines import buildEnv
3211986Sandreas.sandberg@arm.comfrom m5.util import addToPath
3311986Sandreas.sandberg@arm.comimport os, optparse, sys
3411986Sandreas.sandberg@arm.com
3511986Sandreas.sandberg@arm.com# Get paths we might need
3611986Sandreas.sandberg@arm.comconfig_path = os.path.dirname(os.path.abspath(__file__))
3711986Sandreas.sandberg@arm.comconfig_root = os.path.dirname(config_path)
3811986Sandreas.sandberg@arm.comm5_root = os.path.dirname(config_root)
3911986Sandreas.sandberg@arm.comaddToPath(config_root+'/configs/common')
4011986Sandreas.sandberg@arm.comaddToPath(config_root+'/configs/ruby')
4111986Sandreas.sandberg@arm.comaddToPath(config_root+'/configs/topologies')
4214299Sbbruce@ucdavis.edu
4314299Sbbruce@ucdavis.eduimport Options
4411986Sandreas.sandberg@arm.comimport Ruby
4511986Sandreas.sandberg@arm.com
4611986Sandreas.sandberg@arm.comparser = optparse.OptionParser()
4711986Sandreas.sandberg@arm.comOptions.addCommonOptions(parser)
4811986Sandreas.sandberg@arm.com
4911986Sandreas.sandberg@arm.com# Add the ruby specific and protocol specific options
5011986Sandreas.sandberg@arm.comRuby.define_options(parser)
5111986Sandreas.sandberg@arm.com
5211986Sandreas.sandberg@arm.com(options, args) = parser.parse_args()
5311986Sandreas.sandberg@arm.com
5411986Sandreas.sandberg@arm.com#
5511986Sandreas.sandberg@arm.com# Set the default cache size and associativity to be very small to encourage
5611986Sandreas.sandberg@arm.com# races between requests and writebacks.
5711986Sandreas.sandberg@arm.com#
5811986Sandreas.sandberg@arm.comoptions.l1d_size="256B"
5911986Sandreas.sandberg@arm.comoptions.l1i_size="256B"
6011986Sandreas.sandberg@arm.comoptions.l2_size="512B"
6111986Sandreas.sandberg@arm.comoptions.l3_size="1kB"
6211986Sandreas.sandberg@arm.comoptions.l1d_assoc=2
6311986Sandreas.sandberg@arm.comoptions.l1i_assoc=2
6411986Sandreas.sandberg@arm.comoptions.l2_assoc=2
6511986Sandreas.sandberg@arm.comoptions.l3_assoc=2
6611986Sandreas.sandberg@arm.com
6711986Sandreas.sandberg@arm.comnb_cores = 4
6811986Sandreas.sandberg@arm.comcpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
6911986Sandreas.sandberg@arm.com
7011986Sandreas.sandberg@arm.com# overwrite the num_cpus to equal nb_cores
7111986Sandreas.sandberg@arm.comoptions.num_cpus = nb_cores
7211986Sandreas.sandberg@arm.com
7311986Sandreas.sandberg@arm.com# system simulated
7411986Sandreas.sandberg@arm.comsystem = System(cpu = cpus, clk_domain = SrcClockDomain(clock = '1GHz'))
7511986Sandreas.sandberg@arm.com
7611986Sandreas.sandberg@arm.com# Create a seperate clock domain for components that should run at
7711986Sandreas.sandberg@arm.com# CPUs frequency
7811986Sandreas.sandberg@arm.comsystem.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
7911986Sandreas.sandberg@arm.com
8011986Sandreas.sandberg@arm.comRuby.create_system(options, False, system)
8111986Sandreas.sandberg@arm.com
8211986Sandreas.sandberg@arm.com# Create a separate clock domain for Ruby
8311986Sandreas.sandberg@arm.comsystem.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
8411986Sandreas.sandberg@arm.com
8511986Sandreas.sandberg@arm.comassert(options.num_cpus == len(system.ruby._cpu_ports))
8611986Sandreas.sandberg@arm.com
8711986Sandreas.sandberg@arm.comfor (i, cpu) in enumerate(system.cpu):
8811986Sandreas.sandberg@arm.com    # create the interrupt controller
8911986Sandreas.sandberg@arm.com    cpu.createInterruptController()
9011986Sandreas.sandberg@arm.com
9111986Sandreas.sandberg@arm.com    #
9211986Sandreas.sandberg@arm.com    # Tie the cpu ports to the ruby cpu ports
9311986Sandreas.sandberg@arm.com    #
9411986Sandreas.sandberg@arm.com    cpu.connectAllPorts(system.ruby._cpu_ports[i])
9511986Sandreas.sandberg@arm.com
9611986Sandreas.sandberg@arm.com# -----------------------
9711986Sandreas.sandberg@arm.com# run simulation
9811986Sandreas.sandberg@arm.com# -----------------------
9911986Sandreas.sandberg@arm.com
10011986Sandreas.sandberg@arm.comroot = Root( full_system=False, system = system )
10111986Sandreas.sandberg@arm.comroot.system.mem_mode = 'timing'
10211986Sandreas.sandberg@arm.com
10311986Sandreas.sandberg@arm.com# Not much point in this being higher than the L1 latency
10411986Sandreas.sandberg@arm.comm5.ticks.setGlobalFrequency('1ns')
10511986Sandreas.sandberg@arm.com