simple-timing-mp-ruby.py revision 10519:7a3ad4b09ce4
12292SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 22689Sktlim@umich.edu# All rights reserved. 39916Ssteve.reinhardt@amd.com# 42292SN/A# Redistribution and use in source and binary forms, with or without 52292SN/A# modification, are permitted provided that the following conditions are 62292SN/A# met: redistributions of source code must retain the above copyright 72292SN/A# notice, this list of conditions and the following disclaimer; 82292SN/A# redistributions in binary form must reproduce the above copyright 92292SN/A# notice, this list of conditions and the following disclaimer in the 102292SN/A# documentation and/or other materials provided with the distribution; 112292SN/A# neither the name of the copyright holders nor the names of its 122292SN/A# contributors may be used to endorse or promote products derived from 132292SN/A# this software without specific prior written permission. 142292SN/A# 152292SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162292SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172292SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182292SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192292SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202292SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212292SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222292SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232292SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242292SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252292SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262292SN/A# 272292SN/A# Authors: Ron Dreslinski 282689Sktlim@umich.edu 292689Sktlim@umich.eduimport m5 302689Sktlim@umich.edufrom m5.objects import * 319916Ssteve.reinhardt@amd.comfrom m5.defines import buildEnv 322292SN/Afrom m5.util import addToPath 332292SN/Aimport os, optparse, sys 342292SN/A 352292SN/A# Get paths we might need 362292SN/Aconfig_path = os.path.dirname(os.path.abspath(__file__)) 372292SN/Aconfig_root = os.path.dirname(config_path) 382292SN/Am5_root = os.path.dirname(config_root) 392292SN/AaddToPath(config_root+'/configs/common') 408229Snate@binkert.orgaddToPath(config_root+'/configs/ruby') 412292SN/AaddToPath(config_root+'/configs/topologies') 429916Ssteve.reinhardt@amd.com 432292SN/Aimport Options 449916Ssteve.reinhardt@amd.comimport Ruby 452292SN/A 462292SN/Aparser = optparse.OptionParser() 479916Ssteve.reinhardt@amd.comOptions.addCommonOptions(parser) 489916Ssteve.reinhardt@amd.com 4912105Snathanael.premillieu@arm.com# Add the ruby specific and protocol specific options 5012105Snathanael.premillieu@arm.comRuby.define_options(parser) 512292SN/A 522292SN/A(options, args) = parser.parse_args() 532292SN/A 549916Ssteve.reinhardt@amd.com# 559916Ssteve.reinhardt@amd.com# Set the default cache size and associativity to be very small to encourage 569916Ssteve.reinhardt@amd.com# races between requests and writebacks. 579916Ssteve.reinhardt@amd.com# 589916Ssteve.reinhardt@amd.comoptions.l1d_size="256B" 599916Ssteve.reinhardt@amd.comoptions.l1i_size="256B" 609916Ssteve.reinhardt@amd.comoptions.l2_size="512B" 619916Ssteve.reinhardt@amd.comoptions.l3_size="1kB" 629916Ssteve.reinhardt@amd.comoptions.l1d_assoc=2 639916Ssteve.reinhardt@amd.comoptions.l1i_assoc=2 649916Ssteve.reinhardt@amd.comoptions.l2_assoc=2 659916Ssteve.reinhardt@amd.comoptions.l3_assoc=2 662292SN/A 672292SN/Anb_cores = 4 689916Ssteve.reinhardt@amd.comcpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 692292SN/A 702292SN/A# overwrite the num_cpus to equal nb_cores 719916Ssteve.reinhardt@amd.comoptions.num_cpus = nb_cores 7212105Snathanael.premillieu@arm.com 732292SN/A# system simulated 742292SN/Asystem = System(cpu = cpus, physmem = SimpleMemory(), 752292SN/A clk_domain = SrcClockDomain(clock = '1GHz')) 762292SN/A 772292SN/A# Create a seperate clock domain for components that should run at 789916Ssteve.reinhardt@amd.com# CPUs frequency 792292SN/Asystem.cpu.clk_domain = SrcClockDomain(clock = '2GHz') 802292SN/A 8112105Snathanael.premillieu@arm.comRuby.create_system(options, False, system) 829916Ssteve.reinhardt@amd.com 8312106SRekai.GonzalezAlberquilla@arm.com# Create a separate clock domain for Ruby 849916Ssteve.reinhardt@amd.comsystem.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock) 8512105Snathanael.premillieu@arm.com 8612105Snathanael.premillieu@arm.comassert(options.num_cpus == len(system.ruby._cpu_ports)) 879916Ssteve.reinhardt@amd.com 889916Ssteve.reinhardt@amd.comfor (i, cpu) in enumerate(system.cpu): 899916Ssteve.reinhardt@amd.com # create the interrupt controller 9012106SRekai.GonzalezAlberquilla@arm.com cpu.createInterruptController() 919916Ssteve.reinhardt@amd.com 9212105Snathanael.premillieu@arm.com # 939916Ssteve.reinhardt@amd.com # Tie the cpu ports to the ruby cpu ports 949916Ssteve.reinhardt@amd.com # 959916Ssteve.reinhardt@amd.com cpu.connectAllPorts(system.ruby._cpu_ports[i]) 969916Ssteve.reinhardt@amd.com 972292SN/A# ----------------------- 982292SN/A# run simulation 9912105Snathanael.premillieu@arm.com# ----------------------- 1009916Ssteve.reinhardt@amd.com 10112106SRekai.GonzalezAlberquilla@arm.comroot = Root( full_system=False, system = system ) 1029916Ssteve.reinhardt@amd.comroot.system.mem_mode = 'timing' 10312105Snathanael.premillieu@arm.com 10412105Snathanael.premillieu@arm.com# Not much point in this being higher than the L1 latency 10512105Snathanael.premillieu@arm.comm5.ticks.setGlobalFrequency('1ns') 1069916Ssteve.reinhardt@amd.com