simple-atomic-mp-ruby.py revision 9790:ccc428657233 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
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27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/topologies')
32
33
34nb_cores = 4
35cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
36
37import ruby_config
38ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
39
40# system simulated
41system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus())
42system.clock = '1GHz'
43
44# add L1 caches
45for cpu in cpus:
46    cpu.connectAllPorts(system.membus)
47    cpu.clock = '2GHz'
48
49# connect memory to membus
50system.physmem.port = system.membus.master
51
52# Connect the system port for loading of binaries etc
53system.system_port = system.membus.slave
54
55# -----------------------
56# run simulation
57# -----------------------
58
59root = Root(full_system = False, system = system)
60root.system.mem_mode = 'atomic'
61