simple-atomic-mp-ruby.py revision 9793
16166Ssteve.reinhardt@amd.com# Copyright (c) 2006-2007 The Regents of The University of Michigan
26166Ssteve.reinhardt@amd.com# All rights reserved.
36166Ssteve.reinhardt@amd.com#
46166Ssteve.reinhardt@amd.com# Redistribution and use in source and binary forms, with or without
56166Ssteve.reinhardt@amd.com# modification, are permitted provided that the following conditions are
66166Ssteve.reinhardt@amd.com# met: redistributions of source code must retain the above copyright
76166Ssteve.reinhardt@amd.com# notice, this list of conditions and the following disclaimer;
86166Ssteve.reinhardt@amd.com# redistributions in binary form must reproduce the above copyright
96166Ssteve.reinhardt@amd.com# notice, this list of conditions and the following disclaimer in the
106166Ssteve.reinhardt@amd.com# documentation and/or other materials provided with the distribution;
116166Ssteve.reinhardt@amd.com# neither the name of the copyright holders nor the names of its
126166Ssteve.reinhardt@amd.com# contributors may be used to endorse or promote products derived from
136166Ssteve.reinhardt@amd.com# this software without specific prior written permission.
146166Ssteve.reinhardt@amd.com#
156166Ssteve.reinhardt@amd.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
166166Ssteve.reinhardt@amd.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
176166Ssteve.reinhardt@amd.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
186166Ssteve.reinhardt@amd.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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246166Ssteve.reinhardt@amd.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
256166Ssteve.reinhardt@amd.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
266166Ssteve.reinhardt@amd.com#
276166Ssteve.reinhardt@amd.com# Authors: Ron Dreslinski
286166Ssteve.reinhardt@amd.com
296166Ssteve.reinhardt@amd.comimport m5
306166Ssteve.reinhardt@amd.comfrom m5.objects import *
319113SBrad.Beckmann@amd.comm5.util.addToPath('../configs/topologies')
326166Ssteve.reinhardt@amd.com
336166Ssteve.reinhardt@amd.com
346166Ssteve.reinhardt@amd.comnb_cores = 4
356166Ssteve.reinhardt@amd.comcpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
366166Ssteve.reinhardt@amd.com
376289Snate@binkert.orgimport ruby_config
386870Sdrh5@cs.wisc.eduruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
396289Snate@binkert.org
406166Ssteve.reinhardt@amd.com# system simulated
419793Sakash.bagdia@arm.comsystem = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus(),
429793Sakash.bagdia@arm.com                clk_domain = SrcClockDomain(clock = '1GHz'))
439793Sakash.bagdia@arm.com
449793Sakash.bagdia@arm.com# Create a seperate clock domain for components that should run at
459793Sakash.bagdia@arm.com# CPUs frequency
469793Sakash.bagdia@arm.comsystem.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
476166Ssteve.reinhardt@amd.com
486166Ssteve.reinhardt@amd.com# add L1 caches
496166Ssteve.reinhardt@amd.comfor cpu in cpus:
507876Sgblack@eecs.umich.edu    cpu.connectAllPorts(system.membus)
519793Sakash.bagdia@arm.com    # All cpus are associated with cpu_clk_domain
529793Sakash.bagdia@arm.com    cpu.clk_domain = system.cpu_clk_domain
536166Ssteve.reinhardt@amd.com
546166Ssteve.reinhardt@amd.com# connect memory to membus
558839Sandreas.hansson@arm.comsystem.physmem.port = system.membus.master
566166Ssteve.reinhardt@amd.com
578732Sandreas.hansson@arm.com# Connect the system port for loading of binaries etc
588839Sandreas.hansson@arm.comsystem.system_port = system.membus.slave
596166Ssteve.reinhardt@amd.com
606166Ssteve.reinhardt@amd.com# -----------------------
616166Ssteve.reinhardt@amd.com# run simulation
626166Ssteve.reinhardt@amd.com# -----------------------
636166Ssteve.reinhardt@amd.com
648801Sgblack@eecs.umich.eduroot = Root(full_system = False, system = system)
656166Ssteve.reinhardt@amd.comroot.system.mem_mode = 'atomic'
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